1 // SPDX-License-Identifier: GPL-2.0
3 * Generic EP93xx GPIO handling
5 * Copyright (c) 2008 Ryan Mallon
6 * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
8 * Based on code originally from:
9 * linux/arch/arm/mach-ep93xx/core.c
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
16 #include <linux/irq.h>
17 #include <linux/slab.h>
18 #include <linux/gpio/driver.h>
19 /* FIXME: this is here for gpio_to_irq() - get rid of this! */
20 #include <linux/gpio.h>
22 #define irq_to_gpio(irq) ((irq) - gpio_to_irq(0))
24 void __iomem *ep93xx_gpio_base; /* FIXME: put this into irq_data */
25 #define EP93XX_GPIO_REG(x) (ep93xx_gpio_base + (x))
26 #define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c)
27 #define EP93XX_GPIO_A_INT_STATUS EP93XX_GPIO_REG(0xa0)
28 #define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc)
30 /* Maximum value for gpio line identifiers */
31 #define EP93XX_GPIO_LINE_MAX 63
33 /* Maximum value for irq capable line identifiers */
34 #define EP93XX_GPIO_LINE_MAX_IRQ 23
38 struct gpio_chip gc[8];
41 /*************************************************************************
42 * Interrupt handling for EP93xx on-chip GPIOs
43 *************************************************************************/
44 static unsigned char gpio_int_unmasked[3];
45 static unsigned char gpio_int_enabled[3];
46 static unsigned char gpio_int_type1[3];
47 static unsigned char gpio_int_type2[3];
48 static unsigned char gpio_int_debounce[3];
50 /* Port ordering is: A B F */
51 static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
52 static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
53 static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
54 static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
55 static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
57 static void ep93xx_gpio_update_int_params(unsigned port)
61 writeb_relaxed(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
63 writeb_relaxed(gpio_int_type2[port],
64 EP93XX_GPIO_REG(int_type2_register_offset[port]));
66 writeb_relaxed(gpio_int_type1[port],
67 EP93XX_GPIO_REG(int_type1_register_offset[port]));
69 writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
70 EP93XX_GPIO_REG(int_en_register_offset[port]));
73 static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
75 int line = irq_to_gpio(irq);
77 int port_mask = 1 << (line & 7);
80 gpio_int_debounce[port] |= port_mask;
82 gpio_int_debounce[port] &= ~port_mask;
84 writeb(gpio_int_debounce[port],
85 EP93XX_GPIO_REG(int_debounce_register_offset[port]));
88 static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
93 status = readb(EP93XX_GPIO_A_INT_STATUS);
94 for (i = 0; i < 8; i++) {
95 if (status & (1 << i)) {
96 int gpio_irq = gpio_to_irq(0) + i;
97 generic_handle_irq(gpio_irq);
101 status = readb(EP93XX_GPIO_B_INT_STATUS);
102 for (i = 0; i < 8; i++) {
103 if (status & (1 << i)) {
104 int gpio_irq = gpio_to_irq(8) + i;
105 generic_handle_irq(gpio_irq);
110 static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
113 * map discontiguous hw irq range to continuous sw irq range:
115 * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
117 unsigned int irq = irq_desc_get_irq(desc);
118 int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
119 int gpio_irq = gpio_to_irq(16) + port_f_idx;
121 generic_handle_irq(gpio_irq);
124 static void ep93xx_gpio_irq_ack(struct irq_data *d)
126 int line = irq_to_gpio(d->irq);
127 int port = line >> 3;
128 int port_mask = 1 << (line & 7);
130 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
131 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
132 ep93xx_gpio_update_int_params(port);
135 writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
138 static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
140 int line = irq_to_gpio(d->irq);
141 int port = line >> 3;
142 int port_mask = 1 << (line & 7);
144 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
145 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
147 gpio_int_unmasked[port] &= ~port_mask;
148 ep93xx_gpio_update_int_params(port);
150 writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
153 static void ep93xx_gpio_irq_mask(struct irq_data *d)
155 int line = irq_to_gpio(d->irq);
156 int port = line >> 3;
158 gpio_int_unmasked[port] &= ~(1 << (line & 7));
159 ep93xx_gpio_update_int_params(port);
162 static void ep93xx_gpio_irq_unmask(struct irq_data *d)
164 int line = irq_to_gpio(d->irq);
165 int port = line >> 3;
167 gpio_int_unmasked[port] |= 1 << (line & 7);
168 ep93xx_gpio_update_int_params(port);
172 * gpio_int_type1 controls whether the interrupt is level (0) or
173 * edge (1) triggered, while gpio_int_type2 controls whether it
174 * triggers on low/falling (0) or high/rising (1).
176 static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
178 const int gpio = irq_to_gpio(d->irq);
179 const int port = gpio >> 3;
180 const int port_mask = 1 << (gpio & 7);
181 irq_flow_handler_t handler;
183 gpio_direction_input(gpio);
186 case IRQ_TYPE_EDGE_RISING:
187 gpio_int_type1[port] |= port_mask;
188 gpio_int_type2[port] |= port_mask;
189 handler = handle_edge_irq;
191 case IRQ_TYPE_EDGE_FALLING:
192 gpio_int_type1[port] |= port_mask;
193 gpio_int_type2[port] &= ~port_mask;
194 handler = handle_edge_irq;
196 case IRQ_TYPE_LEVEL_HIGH:
197 gpio_int_type1[port] &= ~port_mask;
198 gpio_int_type2[port] |= port_mask;
199 handler = handle_level_irq;
201 case IRQ_TYPE_LEVEL_LOW:
202 gpio_int_type1[port] &= ~port_mask;
203 gpio_int_type2[port] &= ~port_mask;
204 handler = handle_level_irq;
206 case IRQ_TYPE_EDGE_BOTH:
207 gpio_int_type1[port] |= port_mask;
208 /* set initial polarity based on current input level */
209 if (gpio_get_value(gpio))
210 gpio_int_type2[port] &= ~port_mask; /* falling */
212 gpio_int_type2[port] |= port_mask; /* rising */
213 handler = handle_edge_irq;
219 irq_set_handler_locked(d, handler);
221 gpio_int_enabled[port] |= port_mask;
223 ep93xx_gpio_update_int_params(port);
228 static struct irq_chip ep93xx_gpio_irq_chip = {
230 .irq_ack = ep93xx_gpio_irq_ack,
231 .irq_mask_ack = ep93xx_gpio_irq_mask_ack,
232 .irq_mask = ep93xx_gpio_irq_mask,
233 .irq_unmask = ep93xx_gpio_irq_unmask,
234 .irq_set_type = ep93xx_gpio_irq_type,
237 static void ep93xx_gpio_init_irq(struct platform_device *pdev)
242 for (gpio_irq = gpio_to_irq(0);
243 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
244 irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
246 irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
249 irq_set_chained_handler(platform_get_irq(pdev, 0),
250 ep93xx_gpio_ab_irq_handler);
251 for (i = 1; i <= 8; i++)
252 irq_set_chained_handler(platform_get_irq(pdev, i),
253 ep93xx_gpio_f_irq_handler);
257 /*************************************************************************
258 * gpiolib interface for EP93xx on-chip GPIOs
259 *************************************************************************/
260 struct ep93xx_gpio_bank {
268 #define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _debounce) \
274 .has_debounce = _debounce, \
277 static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
278 EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true),
279 EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true),
280 EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false),
281 EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false),
282 EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false),
283 EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true),
284 EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false),
285 EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false),
288 static int ep93xx_gpio_set_config(struct gpio_chip *chip, unsigned offset,
289 unsigned long config)
291 int gpio = chip->base + offset;
292 int irq = gpio_to_irq(gpio);
295 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
301 debounce = pinconf_to_config_argument(config);
302 ep93xx_gpio_int_debounce(irq, debounce ? true : false);
308 * Map GPIO A0..A7 (0..7) to irq 64..71,
309 * B0..B7 (7..15) to irq 72..79, and
310 * F0..F7 (16..24) to irq 80..87.
312 static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
314 int gpio = chip->base + offset;
316 if (gpio > EP93XX_GPIO_LINE_MAX_IRQ)
322 static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev,
323 void __iomem *base, struct ep93xx_gpio_bank *bank)
325 void __iomem *data = base + bank->data;
326 void __iomem *dir = base + bank->dir;
329 err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
333 gc->label = bank->label;
334 gc->base = bank->base;
336 if (bank->has_debounce) {
337 gc->set_config = ep93xx_gpio_set_config;
338 gc->to_irq = ep93xx_gpio_to_irq;
341 return devm_gpiochip_add_data(dev, gc, NULL);
344 static int ep93xx_gpio_probe(struct platform_device *pdev)
346 struct ep93xx_gpio *epg;
347 struct resource *res;
349 struct device *dev = &pdev->dev;
351 epg = devm_kzalloc(dev, sizeof(*epg), GFP_KERNEL);
355 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
356 epg->base = devm_ioremap_resource(dev, res);
357 if (IS_ERR(epg->base))
358 return PTR_ERR(epg->base);
359 ep93xx_gpio_base = epg->base;
361 for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
362 struct gpio_chip *gc = &epg->gc[i];
363 struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
365 if (ep93xx_gpio_add_bank(gc, &pdev->dev,
367 dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
371 ep93xx_gpio_init_irq(pdev);
376 static struct platform_driver ep93xx_gpio_driver = {
378 .name = "gpio-ep93xx",
380 .probe = ep93xx_gpio_probe,
383 static int __init ep93xx_gpio_init(void)
385 return platform_driver_register(&ep93xx_gpio_driver);
387 postcore_initcall(ep93xx_gpio_init);
389 MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
390 "H Hartley Sweeten <hsweeten@visionengravers.com>");
391 MODULE_DESCRIPTION("EP93XX GPIO driver");
392 MODULE_LICENSE("GPL");