1 // SPDX-License-Identifier: GPL-2.0
3 * Generic EP93xx GPIO handling
5 * Copyright (c) 2008 Ryan Mallon
6 * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
8 * Based on code originally from:
9 * linux/arch/arm/mach-ep93xx/core.c
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
16 #include <linux/irq.h>
17 #include <linux/slab.h>
18 #include <linux/gpio/driver.h>
19 /* FIXME: this is here for gpio_to_irq() - get rid of this! */
20 #include <linux/gpio.h>
22 #define irq_to_gpio(irq) ((irq) - gpio_to_irq(0))
24 #define EP93XX_GPIO_F_INT_STATUS 0x5c
25 #define EP93XX_GPIO_A_INT_STATUS 0xa0
26 #define EP93XX_GPIO_B_INT_STATUS 0xbc
28 /* Maximum value for gpio line identifiers */
29 #define EP93XX_GPIO_LINE_MAX 63
31 /* Maximum value for irq capable line identifiers */
32 #define EP93XX_GPIO_LINE_MAX_IRQ 23
36 struct gpio_chip gc[8];
39 /*************************************************************************
40 * Interrupt handling for EP93xx on-chip GPIOs
41 *************************************************************************/
42 static unsigned char gpio_int_unmasked[3];
43 static unsigned char gpio_int_enabled[3];
44 static unsigned char gpio_int_type1[3];
45 static unsigned char gpio_int_type2[3];
46 static unsigned char gpio_int_debounce[3];
48 /* Port ordering is: A B F */
49 static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
50 static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
51 static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
52 static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
53 static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
55 static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, unsigned port)
59 writeb_relaxed(0, epg->base + int_en_register_offset[port]);
61 writeb_relaxed(gpio_int_type2[port],
62 epg->base + int_type2_register_offset[port]);
64 writeb_relaxed(gpio_int_type1[port],
65 epg->base + int_type1_register_offset[port]);
67 writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
68 epg->base + int_en_register_offset[port]);
71 static void ep93xx_gpio_int_debounce(struct ep93xx_gpio *epg,
72 unsigned int irq, bool enable)
74 int line = irq_to_gpio(irq);
76 int port_mask = 1 << (line & 7);
79 gpio_int_debounce[port] |= port_mask;
81 gpio_int_debounce[port] &= ~port_mask;
83 writeb(gpio_int_debounce[port],
84 epg->base + int_debounce_register_offset[port]);
87 static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
89 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
90 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
91 struct irq_chip *irqchip = irq_desc_get_chip(desc);
95 chained_irq_enter(irqchip, desc);
97 status = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);
98 for (i = 0; i < 8; i++) {
99 if (status & (1 << i)) {
100 int gpio_irq = gpio_to_irq(0) + i;
101 generic_handle_irq(gpio_irq);
105 status = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);
106 for (i = 0; i < 8; i++) {
107 if (status & (1 << i)) {
108 int gpio_irq = gpio_to_irq(8) + i;
109 generic_handle_irq(gpio_irq);
113 chained_irq_exit(irqchip, desc);
116 static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
119 * map discontiguous hw irq range to continuous sw irq range:
121 * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
123 struct irq_chip *irqchip = irq_desc_get_chip(desc);
124 unsigned int irq = irq_desc_get_irq(desc);
125 int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
126 int gpio_irq = gpio_to_irq(16) + port_f_idx;
128 chained_irq_enter(irqchip, desc);
129 generic_handle_irq(gpio_irq);
130 chained_irq_exit(irqchip, desc);
133 static void ep93xx_gpio_irq_ack(struct irq_data *d)
135 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
136 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
137 int line = irq_to_gpio(d->irq);
138 int port = line >> 3;
139 int port_mask = 1 << (line & 7);
141 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
142 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
143 ep93xx_gpio_update_int_params(epg, port);
146 writeb(port_mask, epg->base + eoi_register_offset[port]);
149 static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
151 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
152 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
153 int line = irq_to_gpio(d->irq);
154 int port = line >> 3;
155 int port_mask = 1 << (line & 7);
157 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
158 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
160 gpio_int_unmasked[port] &= ~port_mask;
161 ep93xx_gpio_update_int_params(epg, port);
163 writeb(port_mask, epg->base + eoi_register_offset[port]);
166 static void ep93xx_gpio_irq_mask(struct irq_data *d)
168 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
169 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
170 int line = irq_to_gpio(d->irq);
171 int port = line >> 3;
173 gpio_int_unmasked[port] &= ~(1 << (line & 7));
174 ep93xx_gpio_update_int_params(epg, port);
177 static void ep93xx_gpio_irq_unmask(struct irq_data *d)
179 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
180 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
181 int line = irq_to_gpio(d->irq);
182 int port = line >> 3;
184 gpio_int_unmasked[port] |= 1 << (line & 7);
185 ep93xx_gpio_update_int_params(epg, port);
189 * gpio_int_type1 controls whether the interrupt is level (0) or
190 * edge (1) triggered, while gpio_int_type2 controls whether it
191 * triggers on low/falling (0) or high/rising (1).
193 static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
195 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
196 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
197 const int gpio = irq_to_gpio(d->irq);
198 const int port = gpio >> 3;
199 const int port_mask = 1 << (gpio & 7);
200 irq_flow_handler_t handler;
202 gpio_direction_input(gpio);
205 case IRQ_TYPE_EDGE_RISING:
206 gpio_int_type1[port] |= port_mask;
207 gpio_int_type2[port] |= port_mask;
208 handler = handle_edge_irq;
210 case IRQ_TYPE_EDGE_FALLING:
211 gpio_int_type1[port] |= port_mask;
212 gpio_int_type2[port] &= ~port_mask;
213 handler = handle_edge_irq;
215 case IRQ_TYPE_LEVEL_HIGH:
216 gpio_int_type1[port] &= ~port_mask;
217 gpio_int_type2[port] |= port_mask;
218 handler = handle_level_irq;
220 case IRQ_TYPE_LEVEL_LOW:
221 gpio_int_type1[port] &= ~port_mask;
222 gpio_int_type2[port] &= ~port_mask;
223 handler = handle_level_irq;
225 case IRQ_TYPE_EDGE_BOTH:
226 gpio_int_type1[port] |= port_mask;
227 /* set initial polarity based on current input level */
228 if (gpio_get_value(gpio))
229 gpio_int_type2[port] &= ~port_mask; /* falling */
231 gpio_int_type2[port] |= port_mask; /* rising */
232 handler = handle_edge_irq;
238 irq_set_handler_locked(d, handler);
240 gpio_int_enabled[port] |= port_mask;
242 ep93xx_gpio_update_int_params(epg, port);
247 static struct irq_chip ep93xx_gpio_irq_chip = {
249 .irq_ack = ep93xx_gpio_irq_ack,
250 .irq_mask_ack = ep93xx_gpio_irq_mask_ack,
251 .irq_mask = ep93xx_gpio_irq_mask,
252 .irq_unmask = ep93xx_gpio_irq_unmask,
253 .irq_set_type = ep93xx_gpio_irq_type,
256 static void ep93xx_gpio_init_irq(struct platform_device *pdev,
257 struct ep93xx_gpio *epg)
263 for (gpio_irq = gpio_to_irq(0);
264 gpio_irq < gpio_to_irq(8);
266 irq_set_chip_data(gpio_irq, &epg->gc[0]);
267 irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
269 irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
272 for (gpio_irq = gpio_to_irq(8);
273 gpio_irq < gpio_to_irq(16);
275 irq_set_chip_data(gpio_irq, &epg->gc[1]);
276 irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
278 irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
281 for (gpio_irq = gpio_to_irq(16);
282 gpio_irq < gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ);
284 irq_set_chip_data(gpio_irq, &epg->gc[5]);
285 irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
287 irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
290 irq_set_chained_handler_and_data(platform_get_irq(pdev, 0),
291 ep93xx_gpio_ab_irq_handler,
293 for (i = 1; i <= 8; i++)
294 irq_set_chained_handler_and_data(platform_get_irq(pdev, i),
295 ep93xx_gpio_f_irq_handler,
300 /*************************************************************************
301 * gpiolib interface for EP93xx on-chip GPIOs
302 *************************************************************************/
303 struct ep93xx_gpio_bank {
311 #define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _has_irq) \
317 .has_irq = _has_irq, \
320 static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
321 EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true), /* Bank A has 8 IRQs */
322 EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true), /* Bank B has 8 IRQs */
323 EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false),
324 EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false),
325 EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false),
326 EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true), /* Bank F has 8 IRQs */
327 EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false),
328 EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false),
331 static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset,
332 unsigned long config)
334 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
335 int gpio = gc->base + offset;
336 int irq = gpio_to_irq(gpio);
339 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
345 debounce = pinconf_to_config_argument(config);
346 ep93xx_gpio_int_debounce(epg, irq, debounce ? true : false);
352 * Map GPIO A0..A7 (0..7) to irq 64..71,
353 * B0..B7 (7..15) to irq 72..79, and
354 * F0..F7 (16..24) to irq 80..87.
356 static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
358 int gpio = chip->base + offset;
360 if (gpio > EP93XX_GPIO_LINE_MAX_IRQ)
366 static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev,
367 struct ep93xx_gpio *epg,
368 struct ep93xx_gpio_bank *bank)
370 void __iomem *data = epg->base + bank->data;
371 void __iomem *dir = epg->base + bank->dir;
374 err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
378 gc->label = bank->label;
379 gc->base = bank->base;
382 gc->set_config = ep93xx_gpio_set_config;
383 gc->to_irq = ep93xx_gpio_to_irq;
386 return devm_gpiochip_add_data(dev, gc, epg);
389 static int ep93xx_gpio_probe(struct platform_device *pdev)
391 struct ep93xx_gpio *epg;
392 struct resource *res;
394 struct device *dev = &pdev->dev;
396 epg = devm_kzalloc(dev, sizeof(*epg), GFP_KERNEL);
400 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
401 epg->base = devm_ioremap_resource(dev, res);
402 if (IS_ERR(epg->base))
403 return PTR_ERR(epg->base);
405 for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
406 struct gpio_chip *gc = &epg->gc[i];
407 struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
409 if (ep93xx_gpio_add_bank(gc, &pdev->dev, epg, bank))
410 dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
414 ep93xx_gpio_init_irq(pdev, epg);
419 static struct platform_driver ep93xx_gpio_driver = {
421 .name = "gpio-ep93xx",
423 .probe = ep93xx_gpio_probe,
426 static int __init ep93xx_gpio_init(void)
428 return platform_driver_register(&ep93xx_gpio_driver);
430 postcore_initcall(ep93xx_gpio_init);
432 MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
433 "H Hartley Sweeten <hsweeten@visionengravers.com>");
434 MODULE_DESCRIPTION("EP93XX GPIO driver");
435 MODULE_LICENSE("GPL");