1 // SPDX-License-Identifier: GPL-2.0
3 * Intel MID GPIO driver
5 * Copyright (c) 2008-2014,2016 Intel Corporation.
9 * Moorestown platform Langwell chip.
10 * Medfield platform Penwell chip.
11 * Clovertrail platform Cloverview chip.
14 #include <linux/delay.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/slab.h>
24 #include <linux/stddef.h>
26 #define INTEL_MID_IRQ_TYPE_EDGE (1 << 0)
27 #define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1)
30 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
31 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
32 * registers to control them, so we only define the order here instead of a
33 * structure, to get a bit offset for a pin (use GPDR as an example):
38 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
40 * so the bit of reg_addr is to control pin offset's GPDR feature
44 GPLR = 0, /* pin level read-only */
45 GPDR, /* pin direction */
48 GRER, /* rising edge detect */
49 GFER, /* falling edge detect */
50 GEDR, /* edge detect result */
51 GAFR, /* alt function */
54 /* intel_mid gpio driver data */
55 struct intel_mid_gpio_ddata {
56 u16 ngpio; /* number of gpio pins */
57 u32 chip_irq_type; /* chip interrupt type */
60 struct intel_mid_gpio {
61 struct gpio_chip chip;
62 void __iomem *reg_base;
67 static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
68 enum GPIO_REG reg_type)
70 struct intel_mid_gpio *priv = gpiochip_get_data(chip);
71 unsigned nreg = chip->ngpio / 32;
74 return priv->reg_base + reg_type * nreg * 4 + reg * 4;
77 static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
78 enum GPIO_REG reg_type)
80 struct intel_mid_gpio *priv = gpiochip_get_data(chip);
81 unsigned nreg = chip->ngpio / 32;
84 return priv->reg_base + reg_type * nreg * 4 + reg * 4;
87 static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
89 void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
90 u32 value = readl(gafr);
91 int shift = (offset % 16) << 1, af = (value >> shift) & 3;
94 value &= ~(3 << shift);
100 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
102 void __iomem *gplr = gpio_reg(chip, offset, GPLR);
104 return !!(readl(gplr) & BIT(offset % 32));
107 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
109 void __iomem *gpsr, *gpcr;
112 gpsr = gpio_reg(chip, offset, GPSR);
113 writel(BIT(offset % 32), gpsr);
115 gpcr = gpio_reg(chip, offset, GPCR);
116 writel(BIT(offset % 32), gpcr);
120 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
122 struct intel_mid_gpio *priv = gpiochip_get_data(chip);
123 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
128 pm_runtime_get(&priv->pdev->dev);
130 spin_lock_irqsave(&priv->lock, flags);
132 value &= ~BIT(offset % 32);
134 spin_unlock_irqrestore(&priv->lock, flags);
137 pm_runtime_put(&priv->pdev->dev);
142 static int intel_gpio_direction_output(struct gpio_chip *chip,
143 unsigned offset, int value)
145 struct intel_mid_gpio *priv = gpiochip_get_data(chip);
146 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
149 intel_gpio_set(chip, offset, value);
152 pm_runtime_get(&priv->pdev->dev);
154 spin_lock_irqsave(&priv->lock, flags);
156 value |= BIT(offset % 32);
158 spin_unlock_irqrestore(&priv->lock, flags);
161 pm_runtime_put(&priv->pdev->dev);
166 static int intel_mid_irq_type(struct irq_data *d, unsigned type)
168 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
169 struct intel_mid_gpio *priv = gpiochip_get_data(gc);
170 u32 gpio = irqd_to_hwirq(d);
173 void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
174 void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
176 if (gpio >= priv->chip.ngpio)
180 pm_runtime_get(&priv->pdev->dev);
182 spin_lock_irqsave(&priv->lock, flags);
183 if (type & IRQ_TYPE_EDGE_RISING)
184 value = readl(grer) | BIT(gpio % 32);
186 value = readl(grer) & (~BIT(gpio % 32));
189 if (type & IRQ_TYPE_EDGE_FALLING)
190 value = readl(gfer) | BIT(gpio % 32);
192 value = readl(gfer) & (~BIT(gpio % 32));
194 spin_unlock_irqrestore(&priv->lock, flags);
197 pm_runtime_put(&priv->pdev->dev);
202 static void intel_mid_irq_unmask(struct irq_data *d)
206 static void intel_mid_irq_mask(struct irq_data *d)
210 static struct irq_chip intel_mid_irqchip = {
211 .name = "INTEL_MID-GPIO",
212 .irq_mask = intel_mid_irq_mask,
213 .irq_unmask = intel_mid_irq_unmask,
214 .irq_set_type = intel_mid_irq_type,
217 static const struct intel_mid_gpio_ddata gpio_lincroft = {
221 static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
223 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
226 static const struct intel_mid_gpio_ddata gpio_penwell_core = {
228 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
231 static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
233 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL,
236 static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
238 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
241 static const struct pci_device_id intel_gpio_ids[] = {
244 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
245 .driver_data = (kernel_ulong_t)&gpio_lincroft,
249 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
250 .driver_data = (kernel_ulong_t)&gpio_penwell_aon,
254 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
255 .driver_data = (kernel_ulong_t)&gpio_penwell_core,
259 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
260 .driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
263 /* Cloverview Core */
264 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
265 .driver_data = (kernel_ulong_t)&gpio_cloverview_core,
270 static void intel_mid_irq_handler(struct irq_desc *desc)
272 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
273 struct intel_mid_gpio *priv = gpiochip_get_data(gc);
274 struct irq_data *data = irq_desc_get_irq_data(desc);
275 struct irq_chip *chip = irq_data_get_irq_chip(data);
276 u32 base, gpio, mask;
277 unsigned long pending;
280 /* check GPIO controller to check which pin triggered the interrupt */
281 for (base = 0; base < priv->chip.ngpio; base += 32) {
282 gedr = gpio_reg(&priv->chip, base, GEDR);
283 while ((pending = readl(gedr))) {
284 gpio = __ffs(pending);
286 /* Clear before handling so we can't lose an edge */
288 generic_handle_irq(irq_find_mapping(gc->irq.domain,
296 static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv)
301 for (base = 0; base < priv->chip.ngpio; base += 32) {
302 /* Clear the rising-edge detect register */
303 reg = gpio_reg(&priv->chip, base, GRER);
305 /* Clear the falling-edge detect register */
306 reg = gpio_reg(&priv->chip, base, GFER);
308 /* Clear the edge detect status register */
309 reg = gpio_reg(&priv->chip, base, GEDR);
314 static int __maybe_unused intel_gpio_runtime_idle(struct device *dev)
316 int err = pm_schedule_suspend(dev, 500);
317 return err ?: -EBUSY;
320 static const struct dev_pm_ops intel_gpio_pm_ops = {
321 SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
324 static int intel_gpio_probe(struct pci_dev *pdev,
325 const struct pci_device_id *id)
328 struct intel_mid_gpio *priv;
332 struct gpio_irq_chip *girq;
333 struct intel_mid_gpio_ddata *ddata =
334 (struct intel_mid_gpio_ddata *)id->driver_data;
336 retval = pcim_enable_device(pdev);
340 retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
342 dev_err(&pdev->dev, "I/O memory mapping error\n");
346 base = pcim_iomap_table(pdev)[1];
348 irq_base = readl(base);
349 gpio_base = readl(sizeof(u32) + base);
351 /* release the IO mapping, since we already get the info from bar1 */
352 pcim_iounmap_regions(pdev, 1 << 1);
354 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
358 priv->reg_base = pcim_iomap_table(pdev)[0];
359 priv->chip.label = dev_name(&pdev->dev);
360 priv->chip.parent = &pdev->dev;
361 priv->chip.request = intel_gpio_request;
362 priv->chip.direction_input = intel_gpio_direction_input;
363 priv->chip.direction_output = intel_gpio_direction_output;
364 priv->chip.get = intel_gpio_get;
365 priv->chip.set = intel_gpio_set;
366 priv->chip.base = gpio_base;
367 priv->chip.ngpio = ddata->ngpio;
368 priv->chip.can_sleep = false;
371 spin_lock_init(&priv->lock);
373 girq = &priv->chip.irq;
374 girq->chip = &intel_mid_irqchip;
375 girq->parent_handler = intel_mid_irq_handler;
376 girq->num_parents = 1;
377 girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
378 sizeof(*girq->parents),
382 girq->parents[0] = pdev->irq;
383 girq->first = irq_base;
384 girq->default_type = IRQ_TYPE_NONE;
385 girq->handler = handle_simple_irq;
387 intel_mid_irq_init_hw(priv);
389 pci_set_drvdata(pdev, priv);
390 retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
392 dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
396 pm_runtime_put_noidle(&pdev->dev);
397 pm_runtime_allow(&pdev->dev);
402 static struct pci_driver intel_gpio_driver = {
403 .name = "intel_mid_gpio",
404 .id_table = intel_gpio_ids,
405 .probe = intel_gpio_probe,
407 .pm = &intel_gpio_pm_ops,
411 builtin_pci_driver(intel_gpio_driver);