2 * GPIO driver for Marvell SoCs
4 * Copyright (C) 2012 Marvell
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * Andrew Lunn <andrew@lunn.ch>
8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
14 * This driver is a fairly straightforward GPIO driver for the
15 * complete family of Marvell EBU SoC platforms (Orion, Dove,
16 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
17 * driver is the different register layout that exists between the
18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
19 * platforms (MV78200 from the Discovery family and the Armada
20 * XP). Therefore, this driver handles three variants of the GPIO
22 * - the basic variant, called "orion-gpio", with the simplest
23 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
24 * non-SMP Discovery systems
25 * - the mv78200 variant for MV78200 Discovery systems. This variant
26 * turns the edge mask and level mask registers into CPU0 edge
27 * mask/level mask registers, and adds CPU1 edge mask/level mask
29 * - the armadaxp variant for Armada XP systems. This variant keeps
30 * the normal cause/edge mask/level mask registers when the global
31 * interrupts are used, but adds per-CPU cause/edge mask/level mask
32 * registers n a separate memory area for the per-CPU GPIO
36 #include <linux/bitops.h>
37 #include <linux/clk.h>
38 #include <linux/err.h>
39 #include <linux/gpio/driver.h>
40 #include <linux/gpio/consumer.h>
41 #include <linux/gpio/machine.h>
42 #include <linux/init.h>
44 #include <linux/irq.h>
45 #include <linux/irqchip/chained_irq.h>
46 #include <linux/irqdomain.h>
47 #include <linux/mfd/syscon.h>
48 #include <linux/of_device.h>
49 #include <linux/of_irq.h>
50 #include <linux/pinctrl/consumer.h>
51 #include <linux/platform_device.h>
52 #include <linux/pwm.h>
53 #include <linux/regmap.h>
54 #include <linux/slab.h>
57 * GPIO unit register offsets.
59 #define GPIO_OUT_OFF 0x0000
60 #define GPIO_IO_CONF_OFF 0x0004
61 #define GPIO_BLINK_EN_OFF 0x0008
62 #define GPIO_IN_POL_OFF 0x000c
63 #define GPIO_DATA_IN_OFF 0x0010
64 #define GPIO_EDGE_CAUSE_OFF 0x0014
65 #define GPIO_EDGE_MASK_OFF 0x0018
66 #define GPIO_LEVEL_MASK_OFF 0x001c
67 #define GPIO_BLINK_CNT_SELECT_OFF 0x0020
70 * PWM register offsets.
72 #define PWM_BLINK_ON_DURATION_OFF 0x0
73 #define PWM_BLINK_OFF_DURATION_OFF 0x4
76 /* The MV78200 has per-CPU registers for edge mask and level mask */
77 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
78 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
81 * The Armada XP has per-CPU registers for interrupt cause, interrupt
82 * mask and interrupt level mask. Those are relative to the
85 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
86 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
87 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
89 #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
90 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
91 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
92 #define MVEBU_GPIO_SOC_VARIANT_A8K 0x4
94 #define MVEBU_MAX_GPIO_PER_BANK 32
97 void __iomem *membase;
98 unsigned long clk_rate;
99 struct gpio_desc *gpiod;
100 struct pwm_chip chip;
102 struct mvebu_gpio_chip *mvchip;
104 /* Used to preserve GPIO/PWM registers across suspend/resume */
106 u32 blink_on_duration;
107 u32 blink_off_duration;
110 struct mvebu_gpio_chip {
111 struct gpio_chip chip;
114 struct regmap *percpu_regs;
116 struct irq_domain *domain;
119 /* Used for PWM support */
121 struct mvebu_pwm *mvpwm;
123 /* Used to preserve GPIO registers across suspend/resume */
128 u32 edge_mask_regs[4];
129 u32 level_mask_regs[4];
133 * Functions returning addresses of individual registers for a given
137 static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip,
138 struct regmap **map, unsigned int *offset)
142 switch (mvchip->soc_variant) {
143 case MVEBU_GPIO_SOC_VARIANT_ORION:
144 case MVEBU_GPIO_SOC_VARIANT_MV78200:
145 case MVEBU_GPIO_SOC_VARIANT_A8K:
147 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset;
149 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
150 cpu = smp_processor_id();
151 *map = mvchip->percpu_regs;
152 *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
160 mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip)
166 mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
167 regmap_read(map, offset, &val);
173 mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val)
178 mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
179 regmap_write(map, offset, val);
183 mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip,
184 struct regmap **map, unsigned int *offset)
188 switch (mvchip->soc_variant) {
189 case MVEBU_GPIO_SOC_VARIANT_ORION:
190 case MVEBU_GPIO_SOC_VARIANT_A8K:
192 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset;
194 case MVEBU_GPIO_SOC_VARIANT_MV78200:
195 cpu = smp_processor_id();
197 *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu);
199 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
200 cpu = smp_processor_id();
201 *map = mvchip->percpu_regs;
202 *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
210 mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip)
216 mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
217 regmap_read(map, offset, &val);
223 mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val)
228 mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
229 regmap_write(map, offset, val);
233 mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip,
234 struct regmap **map, unsigned int *offset)
238 switch (mvchip->soc_variant) {
239 case MVEBU_GPIO_SOC_VARIANT_ORION:
240 case MVEBU_GPIO_SOC_VARIANT_A8K:
242 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset;
244 case MVEBU_GPIO_SOC_VARIANT_MV78200:
245 cpu = smp_processor_id();
247 *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu);
249 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
250 cpu = smp_processor_id();
251 *map = mvchip->percpu_regs;
252 *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
260 mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip)
266 mvebu_gpioreg_level_mask(mvchip, &map, &offset);
267 regmap_read(map, offset, &val);
273 mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val)
278 mvebu_gpioreg_level_mask(mvchip, &map, &offset);
279 regmap_write(map, offset, val);
283 * Functions returning addresses of individual registers for a given
286 static void __iomem *mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
288 return mvpwm->membase + PWM_BLINK_ON_DURATION_OFF;
291 static void __iomem *mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
293 return mvpwm->membase + PWM_BLINK_OFF_DURATION_OFF;
297 * Functions implementing the gpio_chip methods
299 static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
301 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
303 regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
304 BIT(pin), value ? BIT(pin) : 0);
307 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin)
309 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
312 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
317 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset,
319 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
321 u = data_in ^ in_pol;
323 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u);
326 return (u >> pin) & 1;
329 static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin,
332 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
334 regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
335 BIT(pin), value ? BIT(pin) : 0);
338 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
340 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
344 * Check with the pinctrl driver whether this pin is usable as
347 ret = pinctrl_gpio_direction_input(chip->base + pin);
351 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
357 static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
360 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
364 * Check with the pinctrl driver whether this pin is usable as
367 ret = pinctrl_gpio_direction_output(chip->base + pin);
371 mvebu_gpio_blink(chip, pin, 0);
372 mvebu_gpio_set(chip, pin, value);
374 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
380 static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
382 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
385 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
387 return !!(u & BIT(pin));
390 static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin)
392 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
394 return irq_create_mapping(mvchip->domain, pin);
398 * Functions implementing the irq_chip methods
400 static void mvebu_gpio_irq_ack(struct irq_data *d)
402 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
403 struct mvebu_gpio_chip *mvchip = gc->private;
407 mvebu_gpio_write_edge_cause(mvchip, ~mask);
411 static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
413 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
414 struct mvebu_gpio_chip *mvchip = gc->private;
415 struct irq_chip_type *ct = irq_data_get_chip_type(d);
419 ct->mask_cache_priv &= ~mask;
420 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
424 static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
426 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
427 struct mvebu_gpio_chip *mvchip = gc->private;
428 struct irq_chip_type *ct = irq_data_get_chip_type(d);
432 ct->mask_cache_priv |= mask;
433 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
437 static void mvebu_gpio_level_irq_mask(struct irq_data *d)
439 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
440 struct mvebu_gpio_chip *mvchip = gc->private;
441 struct irq_chip_type *ct = irq_data_get_chip_type(d);
445 ct->mask_cache_priv &= ~mask;
446 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
450 static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
452 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
453 struct mvebu_gpio_chip *mvchip = gc->private;
454 struct irq_chip_type *ct = irq_data_get_chip_type(d);
458 ct->mask_cache_priv |= mask;
459 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
463 /*****************************************************************************
466 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
467 * value of the line or the opposite value.
469 * Level IRQ handlers: DATA_IN is used directly as cause register.
470 * Interrupt are masked by LEVEL_MASK registers.
471 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
472 * Interrupt are masked by EDGE_MASK registers.
473 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
474 * the polarity to catch the next line transaction.
475 * This is a race condition that might not perfectly
476 * work on some use cases.
478 * Every eight GPIO lines are grouped (OR'ed) before going up to main
482 * data-in /--------| |-----| |----\
483 * -----| |----- ---- to main cause reg
484 * X \----------------| |----/
485 * polarity LEVEL mask
487 ****************************************************************************/
489 static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
491 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
492 struct irq_chip_type *ct = irq_data_get_chip_type(d);
493 struct mvebu_gpio_chip *mvchip = gc->private;
499 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
500 if ((u & BIT(pin)) == 0)
503 type &= IRQ_TYPE_SENSE_MASK;
504 if (type == IRQ_TYPE_NONE)
507 /* Check if we need to change chip and handler */
508 if (!(ct->type & type))
509 if (irq_setup_alt_chip(d, type))
513 * Configure interrupt polarity.
516 case IRQ_TYPE_EDGE_RISING:
517 case IRQ_TYPE_LEVEL_HIGH:
518 regmap_update_bits(mvchip->regs,
519 GPIO_IN_POL_OFF + mvchip->offset,
522 case IRQ_TYPE_EDGE_FALLING:
523 case IRQ_TYPE_LEVEL_LOW:
524 regmap_update_bits(mvchip->regs,
525 GPIO_IN_POL_OFF + mvchip->offset,
528 case IRQ_TYPE_EDGE_BOTH: {
529 u32 data_in, in_pol, val;
531 regmap_read(mvchip->regs,
532 GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
533 regmap_read(mvchip->regs,
534 GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
537 * set initial polarity based on current input level
539 if ((data_in ^ in_pol) & BIT(pin))
540 val = BIT(pin); /* falling */
542 val = 0; /* raising */
544 regmap_update_bits(mvchip->regs,
545 GPIO_IN_POL_OFF + mvchip->offset,
553 static void mvebu_gpio_irq_handler(struct irq_desc *desc)
555 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
556 struct irq_chip *chip = irq_desc_get_chip(desc);
557 u32 cause, type, data_in, level_mask, edge_cause, edge_mask;
563 chained_irq_enter(chip, desc);
565 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
566 level_mask = mvebu_gpio_read_level_mask(mvchip);
567 edge_cause = mvebu_gpio_read_edge_cause(mvchip);
568 edge_mask = mvebu_gpio_read_edge_mask(mvchip);
570 cause = (data_in & level_mask) | (edge_cause & edge_mask);
572 for (i = 0; i < mvchip->chip.ngpio; i++) {
575 irq = irq_find_mapping(mvchip->domain, i);
577 if (!(cause & BIT(i)))
580 type = irq_get_trigger_type(irq);
581 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
582 /* Swap polarity (race with GPIO line) */
585 regmap_read(mvchip->regs,
586 GPIO_IN_POL_OFF + mvchip->offset,
589 regmap_write(mvchip->regs,
590 GPIO_IN_POL_OFF + mvchip->offset,
594 generic_handle_irq(irq);
597 chained_irq_exit(chip, desc);
601 * Functions implementing the pwm_chip methods
603 static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip)
605 return container_of(chip, struct mvebu_pwm, chip);
608 static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
610 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
611 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
612 struct gpio_desc *desc;
616 spin_lock_irqsave(&mvpwm->lock, flags);
621 desc = gpiochip_request_own_desc(&mvchip->chip,
622 pwm->hwpwm, "mvebu-pwm",
633 spin_unlock_irqrestore(&mvpwm->lock, flags);
637 static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
639 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
642 spin_lock_irqsave(&mvpwm->lock, flags);
643 gpiochip_free_own_desc(mvpwm->gpiod);
645 spin_unlock_irqrestore(&mvpwm->lock, flags);
648 static void mvebu_pwm_get_state(struct pwm_chip *chip,
649 struct pwm_device *pwm,
650 struct pwm_state *state) {
652 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
653 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
654 unsigned long long val;
658 spin_lock_irqsave(&mvpwm->lock, flags);
660 val = (unsigned long long)
661 readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
663 do_div(val, mvpwm->clk_rate);
665 state->duty_cycle = UINT_MAX;
667 state->duty_cycle = val;
669 state->duty_cycle = 1;
671 val = (unsigned long long)
672 readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
674 do_div(val, mvpwm->clk_rate);
675 if (val < state->duty_cycle) {
678 val -= state->duty_cycle;
680 state->period = UINT_MAX;
687 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u);
689 state->enabled = true;
691 state->enabled = false;
693 spin_unlock_irqrestore(&mvpwm->lock, flags);
696 static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
697 struct pwm_state *state)
699 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
700 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
701 unsigned long long val;
703 unsigned int on, off;
705 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle;
706 do_div(val, NSEC_PER_SEC);
714 val = (unsigned long long) mvpwm->clk_rate *
715 (state->period - state->duty_cycle);
716 do_div(val, NSEC_PER_SEC);
724 spin_lock_irqsave(&mvpwm->lock, flags);
726 writel_relaxed(on, mvebu_pwmreg_blink_on_duration(mvpwm));
727 writel_relaxed(off, mvebu_pwmreg_blink_off_duration(mvpwm));
729 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
731 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
733 spin_unlock_irqrestore(&mvpwm->lock, flags);
738 static const struct pwm_ops mvebu_pwm_ops = {
739 .request = mvebu_pwm_request,
740 .free = mvebu_pwm_free,
741 .get_state = mvebu_pwm_get_state,
742 .apply = mvebu_pwm_apply,
743 .owner = THIS_MODULE,
746 static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
748 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
750 regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
751 &mvpwm->blink_select);
752 mvpwm->blink_on_duration =
753 readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
754 mvpwm->blink_off_duration =
755 readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
758 static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
760 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
762 regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
763 mvpwm->blink_select);
764 writel_relaxed(mvpwm->blink_on_duration,
765 mvebu_pwmreg_blink_on_duration(mvpwm));
766 writel_relaxed(mvpwm->blink_off_duration,
767 mvebu_pwmreg_blink_off_duration(mvpwm));
770 static int mvebu_pwm_probe(struct platform_device *pdev,
771 struct mvebu_gpio_chip *mvchip,
774 struct device *dev = &pdev->dev;
775 struct mvebu_pwm *mvpwm;
776 struct resource *res;
779 if (!of_device_is_compatible(mvchip->chip.of_node,
780 "marvell,armada-370-gpio"))
784 * There are only two sets of PWM configuration registers for
785 * all the GPIO lines on those SoCs which this driver reserves
786 * for the first two GPIO chips. So if the resource is missing
787 * we can't treat it as an error.
789 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm");
793 if (IS_ERR(mvchip->clk))
794 return PTR_ERR(mvchip->clk);
797 * Use set A for lines of GPIO chip with id 0, B for GPIO chip
798 * with id 1. Don't allow further GPIO chips to be used for PWM.
806 regmap_write(mvchip->regs,
807 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
809 mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL);
812 mvchip->mvpwm = mvpwm;
813 mvpwm->mvchip = mvchip;
815 mvpwm->membase = devm_ioremap_resource(dev, res);
816 if (IS_ERR(mvpwm->membase))
817 return PTR_ERR(mvpwm->membase);
819 mvpwm->clk_rate = clk_get_rate(mvchip->clk);
820 if (!mvpwm->clk_rate) {
821 dev_err(dev, "failed to get clock rate\n");
825 mvpwm->chip.dev = dev;
826 mvpwm->chip.ops = &mvebu_pwm_ops;
827 mvpwm->chip.npwm = mvchip->chip.ngpio;
829 * There may already be some PWM allocated, so we can't force
830 * mvpwm->chip.base to a fixed point like mvchip->chip.base.
831 * So, we let pwmchip_add() do the numbering and take the next free
834 mvpwm->chip.base = -1;
836 spin_lock_init(&mvpwm->lock);
838 return pwmchip_add(&mvpwm->chip);
841 #ifdef CONFIG_DEBUG_FS
842 #include <linux/seq_file.h>
844 static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
846 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
847 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
850 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out);
851 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf);
852 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink);
853 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
854 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
855 cause = mvebu_gpio_read_edge_cause(mvchip);
856 edg_msk = mvebu_gpio_read_edge_mask(mvchip);
857 lvl_msk = mvebu_gpio_read_level_mask(mvchip);
859 for (i = 0; i < chip->ngpio; i++) {
864 label = gpiochip_is_requested(chip, i);
869 is_out = !(io_conf & msk);
871 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
874 seq_printf(s, " out %s %s\n",
875 out & msk ? "hi" : "lo",
876 blink & msk ? "(blink )" : "");
880 seq_printf(s, " in %s (act %s) - IRQ",
881 (data_in ^ in_pol) & msk ? "hi" : "lo",
882 in_pol & msk ? "lo" : "hi");
883 if (!((edg_msk | lvl_msk) & msk)) {
884 seq_puts(s, " disabled\n");
888 seq_puts(s, " edge ");
890 seq_puts(s, " level");
891 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
895 #define mvebu_gpio_dbg_show NULL
898 static const struct of_device_id mvebu_gpio_of_match[] = {
900 .compatible = "marvell,orion-gpio",
901 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
904 .compatible = "marvell,mv78200-gpio",
905 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
908 .compatible = "marvell,armadaxp-gpio",
909 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
912 .compatible = "marvell,armada-370-gpio",
913 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
916 .compatible = "marvell,armada-8k-gpio",
917 .data = (void *) MVEBU_GPIO_SOC_VARIANT_A8K,
924 static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
926 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
929 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
931 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
932 &mvchip->io_conf_reg);
933 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
934 &mvchip->blink_en_reg);
935 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
936 &mvchip->in_pol_reg);
938 switch (mvchip->soc_variant) {
939 case MVEBU_GPIO_SOC_VARIANT_ORION:
940 case MVEBU_GPIO_SOC_VARIANT_A8K:
941 regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
942 &mvchip->edge_mask_regs[0]);
943 regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
944 &mvchip->level_mask_regs[0]);
946 case MVEBU_GPIO_SOC_VARIANT_MV78200:
947 for (i = 0; i < 2; i++) {
948 regmap_read(mvchip->regs,
949 GPIO_EDGE_MASK_MV78200_OFF(i),
950 &mvchip->edge_mask_regs[i]);
951 regmap_read(mvchip->regs,
952 GPIO_LEVEL_MASK_MV78200_OFF(i),
953 &mvchip->level_mask_regs[i]);
956 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
957 for (i = 0; i < 4; i++) {
958 regmap_read(mvchip->regs,
959 GPIO_EDGE_MASK_ARMADAXP_OFF(i),
960 &mvchip->edge_mask_regs[i]);
961 regmap_read(mvchip->regs,
962 GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
963 &mvchip->level_mask_regs[i]);
970 if (IS_ENABLED(CONFIG_PWM))
971 mvebu_pwm_suspend(mvchip);
976 static int mvebu_gpio_resume(struct platform_device *pdev)
978 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
981 regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
983 regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
984 mvchip->io_conf_reg);
985 regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
986 mvchip->blink_en_reg);
987 regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
990 switch (mvchip->soc_variant) {
991 case MVEBU_GPIO_SOC_VARIANT_ORION:
992 case MVEBU_GPIO_SOC_VARIANT_A8K:
993 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
994 mvchip->edge_mask_regs[0]);
995 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
996 mvchip->level_mask_regs[0]);
998 case MVEBU_GPIO_SOC_VARIANT_MV78200:
999 for (i = 0; i < 2; i++) {
1000 regmap_write(mvchip->regs,
1001 GPIO_EDGE_MASK_MV78200_OFF(i),
1002 mvchip->edge_mask_regs[i]);
1003 regmap_write(mvchip->regs,
1004 GPIO_LEVEL_MASK_MV78200_OFF(i),
1005 mvchip->level_mask_regs[i]);
1008 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1009 for (i = 0; i < 4; i++) {
1010 regmap_write(mvchip->regs,
1011 GPIO_EDGE_MASK_ARMADAXP_OFF(i),
1012 mvchip->edge_mask_regs[i]);
1013 regmap_write(mvchip->regs,
1014 GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
1015 mvchip->level_mask_regs[i]);
1022 if (IS_ENABLED(CONFIG_PWM))
1023 mvebu_pwm_resume(mvchip);
1028 static const struct regmap_config mvebu_gpio_regmap_config = {
1035 static int mvebu_gpio_probe_raw(struct platform_device *pdev,
1036 struct mvebu_gpio_chip *mvchip)
1040 base = devm_platform_ioremap_resource(pdev, 0);
1042 return PTR_ERR(base);
1044 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base,
1045 &mvebu_gpio_regmap_config);
1046 if (IS_ERR(mvchip->regs))
1047 return PTR_ERR(mvchip->regs);
1050 * For the legacy SoCs, the regmap directly maps to the GPIO
1051 * registers, so no offset is needed.
1056 * The Armada XP has a second range of registers for the
1059 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
1060 base = devm_platform_ioremap_resource(pdev, 1);
1062 return PTR_ERR(base);
1064 mvchip->percpu_regs =
1065 devm_regmap_init_mmio(&pdev->dev, base,
1066 &mvebu_gpio_regmap_config);
1067 if (IS_ERR(mvchip->percpu_regs))
1068 return PTR_ERR(mvchip->percpu_regs);
1074 static int mvebu_gpio_probe_syscon(struct platform_device *pdev,
1075 struct mvebu_gpio_chip *mvchip)
1077 mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node);
1078 if (IS_ERR(mvchip->regs))
1079 return PTR_ERR(mvchip->regs);
1081 if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset))
1087 static int mvebu_gpio_probe(struct platform_device *pdev)
1089 struct mvebu_gpio_chip *mvchip;
1090 const struct of_device_id *match;
1091 struct device_node *np = pdev->dev.of_node;
1092 struct irq_chip_generic *gc;
1093 struct irq_chip_type *ct;
1094 unsigned int ngpios;
1100 match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
1102 soc_variant = (unsigned long) match->data;
1104 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
1106 /* Some gpio controllers do not provide irq support */
1107 have_irqs = of_irq_count(np) != 0;
1109 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
1114 platform_set_drvdata(pdev, mvchip);
1116 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
1117 dev_err(&pdev->dev, "Missing ngpios OF property\n");
1121 id = of_alias_get_id(pdev->dev.of_node, "gpio");
1123 dev_err(&pdev->dev, "Couldn't get OF id\n");
1127 mvchip->clk = devm_clk_get(&pdev->dev, NULL);
1128 /* Not all SoCs require a clock.*/
1129 if (!IS_ERR(mvchip->clk))
1130 clk_prepare_enable(mvchip->clk);
1132 mvchip->soc_variant = soc_variant;
1133 mvchip->chip.label = dev_name(&pdev->dev);
1134 mvchip->chip.parent = &pdev->dev;
1135 mvchip->chip.request = gpiochip_generic_request;
1136 mvchip->chip.free = gpiochip_generic_free;
1137 mvchip->chip.get_direction = mvebu_gpio_get_direction;
1138 mvchip->chip.direction_input = mvebu_gpio_direction_input;
1139 mvchip->chip.get = mvebu_gpio_get;
1140 mvchip->chip.direction_output = mvebu_gpio_direction_output;
1141 mvchip->chip.set = mvebu_gpio_set;
1143 mvchip->chip.to_irq = mvebu_gpio_to_irq;
1144 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
1145 mvchip->chip.ngpio = ngpios;
1146 mvchip->chip.can_sleep = false;
1147 mvchip->chip.of_node = np;
1148 mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
1150 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K)
1151 err = mvebu_gpio_probe_syscon(pdev, mvchip);
1153 err = mvebu_gpio_probe_raw(pdev, mvchip);
1159 * Mask and clear GPIO interrupts.
1161 switch (soc_variant) {
1162 case MVEBU_GPIO_SOC_VARIANT_ORION:
1163 case MVEBU_GPIO_SOC_VARIANT_A8K:
1164 regmap_write(mvchip->regs,
1165 GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0);
1166 regmap_write(mvchip->regs,
1167 GPIO_EDGE_MASK_OFF + mvchip->offset, 0);
1168 regmap_write(mvchip->regs,
1169 GPIO_LEVEL_MASK_OFF + mvchip->offset, 0);
1171 case MVEBU_GPIO_SOC_VARIANT_MV78200:
1172 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1173 for (cpu = 0; cpu < 2; cpu++) {
1174 regmap_write(mvchip->regs,
1175 GPIO_EDGE_MASK_MV78200_OFF(cpu), 0);
1176 regmap_write(mvchip->regs,
1177 GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0);
1180 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1181 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1182 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0);
1183 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0);
1184 for (cpu = 0; cpu < 4; cpu++) {
1185 regmap_write(mvchip->percpu_regs,
1186 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0);
1187 regmap_write(mvchip->percpu_regs,
1188 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0);
1189 regmap_write(mvchip->percpu_regs,
1190 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0);
1197 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
1199 /* Some gpio controllers do not provide irq support */
1204 irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL);
1205 if (!mvchip->domain) {
1206 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
1207 mvchip->chip.label);
1211 err = irq_alloc_domain_generic_chips(
1212 mvchip->domain, ngpios, 2, np->name, handle_level_irq,
1213 IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0);
1215 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
1216 mvchip->chip.label);
1221 * NOTE: The common accessors cannot be used because of the percpu
1222 * access to the mask registers
1224 gc = irq_get_domain_generic_chip(mvchip->domain, 0);
1225 gc->private = mvchip;
1226 ct = &gc->chip_types[0];
1227 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
1228 ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
1229 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
1230 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1231 ct->chip.name = mvchip->chip.label;
1233 ct = &gc->chip_types[1];
1234 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
1235 ct->chip.irq_ack = mvebu_gpio_irq_ack;
1236 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
1237 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
1238 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1239 ct->handler = handle_edge_irq;
1240 ct->chip.name = mvchip->chip.label;
1243 * Setup the interrupt handlers. Each chip can have up to 4
1244 * interrupt handlers, with each handler dealing with 8 GPIO
1247 for (i = 0; i < 4; i++) {
1248 int irq = platform_get_irq(pdev, i);
1252 irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
1256 /* Some MVEBU SoCs have simple PWM support for GPIO lines */
1257 if (IS_ENABLED(CONFIG_PWM))
1258 return mvebu_pwm_probe(pdev, mvchip, id);
1263 irq_domain_remove(mvchip->domain);
1268 static struct platform_driver mvebu_gpio_driver = {
1270 .name = "mvebu-gpio",
1271 .of_match_table = mvebu_gpio_of_match,
1273 .probe = mvebu_gpio_probe,
1274 .suspend = mvebu_gpio_suspend,
1275 .resume = mvebu_gpio_resume,
1277 builtin_platform_driver(mvebu_gpio_driver);