1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support functions for OMAP GPIO
5 * Copyright (C) 2003-2005 Nokia Corporation
6 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/syscore_ops.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/device.h>
21 #include <linux/pm_runtime.h>
24 #include <linux/of_device.h>
25 #include <linux/gpio/driver.h>
26 #include <linux/bitops.h>
27 #include <linux/platform_data/gpio-omap.h>
29 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
47 struct list_head node;
51 u32 enabled_non_wakeup_gpios;
52 struct gpio_regs context;
57 raw_spinlock_t wa_lock;
58 struct gpio_chip chip;
60 struct notifier_block nb;
61 unsigned int is_suspended:1;
72 int context_loss_count;
74 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
75 void (*set_dataout_multiple)(struct gpio_bank *bank,
76 unsigned long *mask, unsigned long *bits);
77 int (*get_context_loss_count)(struct device *dev);
79 struct omap_gpio_reg_offs *regs;
82 #define GPIO_MOD_CTRL_BIT BIT(0)
84 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
85 #define LINE_USED(line, offset) (line & (BIT(offset)))
87 static void omap_gpio_unmask_irq(struct irq_data *d);
89 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
91 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
92 return gpiochip_get_data(chip);
95 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
98 void __iomem *reg = bank->base;
101 reg += bank->regs->direction;
102 l = readl_relaxed(reg);
107 writel_relaxed(l, reg);
108 bank->context.oe = l;
112 /* set data out value using dedicate set/clear register */
113 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
116 void __iomem *reg = bank->base;
120 reg += bank->regs->set_dataout;
121 bank->context.dataout |= l;
123 reg += bank->regs->clr_dataout;
124 bank->context.dataout &= ~l;
127 writel_relaxed(l, reg);
130 /* set data out value using mask register */
131 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
134 void __iomem *reg = bank->base + bank->regs->dataout;
135 u32 gpio_bit = BIT(offset);
138 l = readl_relaxed(reg);
143 writel_relaxed(l, reg);
144 bank->context.dataout = l;
147 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
149 void __iomem *reg = bank->base + bank->regs->datain;
151 return (readl_relaxed(reg) & (BIT(offset))) != 0;
154 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
156 void __iomem *reg = bank->base + bank->regs->dataout;
158 return (readl_relaxed(reg) & (BIT(offset))) != 0;
161 /* set multiple data out values using dedicate set/clear register */
162 static void omap_set_gpio_dataout_reg_multiple(struct gpio_bank *bank,
166 void __iomem *reg = bank->base;
170 writel_relaxed(l, reg + bank->regs->set_dataout);
171 bank->context.dataout |= l;
174 writel_relaxed(l, reg + bank->regs->clr_dataout);
175 bank->context.dataout &= ~l;
178 /* set multiple data out values using mask register */
179 static void omap_set_gpio_dataout_mask_multiple(struct gpio_bank *bank,
183 void __iomem *reg = bank->base + bank->regs->dataout;
184 u32 l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask);
186 writel_relaxed(l, reg);
187 bank->context.dataout = l;
190 static unsigned long omap_get_gpio_datain_multiple(struct gpio_bank *bank,
193 void __iomem *reg = bank->base + bank->regs->datain;
195 return readl_relaxed(reg) & *mask;
198 static unsigned long omap_get_gpio_dataout_multiple(struct gpio_bank *bank,
201 void __iomem *reg = bank->base + bank->regs->dataout;
203 return readl_relaxed(reg) & *mask;
206 static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
208 int l = readl_relaxed(base + reg);
215 writel_relaxed(l, base + reg);
218 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
220 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
221 clk_enable(bank->dbck);
222 bank->dbck_enabled = true;
224 writel_relaxed(bank->dbck_enable_mask,
225 bank->base + bank->regs->debounce_en);
229 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
231 if (bank->dbck_enable_mask && bank->dbck_enabled) {
233 * Disable debounce before cutting it's clock. If debounce is
234 * enabled but the clock is not, GPIO module seems to be unable
235 * to detect events and generate interrupts at least on OMAP3.
237 writel_relaxed(0, bank->base + bank->regs->debounce_en);
239 clk_disable(bank->dbck);
240 bank->dbck_enabled = false;
245 * omap2_set_gpio_debounce - low level gpio debounce time
246 * @bank: the gpio bank we're acting upon
247 * @offset: the gpio number on this @bank
248 * @debounce: debounce time to use
250 * OMAP's debounce time is in 31us steps
251 * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
252 * so we need to convert and round up to the closest unit.
254 * Return: 0 on success, negative error otherwise.
256 static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
262 bool enable = !!debounce;
264 if (!bank->dbck_flag)
268 debounce = DIV_ROUND_UP(debounce, 31) - 1;
269 if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce)
275 clk_enable(bank->dbck);
276 reg = bank->base + bank->regs->debounce;
277 writel_relaxed(debounce, reg);
279 reg = bank->base + bank->regs->debounce_en;
280 val = readl_relaxed(reg);
286 bank->dbck_enable_mask = val;
288 writel_relaxed(val, reg);
289 clk_disable(bank->dbck);
291 * Enable debounce clock per module.
292 * This call is mandatory because in omap_gpio_request() when
293 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
294 * runtime callbck fails to turn on dbck because dbck_enable_mask
295 * used within _gpio_dbck_enable() is still not initialized at
296 * that point. Therefore we have to enable dbck here.
298 omap_gpio_dbck_enable(bank);
299 if (bank->dbck_enable_mask) {
300 bank->context.debounce = debounce;
301 bank->context.debounce_en = val;
308 * omap_clear_gpio_debounce - clear debounce settings for a gpio
309 * @bank: the gpio bank we're acting upon
310 * @offset: the gpio number on this @bank
312 * If a gpio is using debounce, then clear the debounce enable bit and if
313 * this is the only gpio in this bank using debounce, then clear the debounce
314 * time too. The debounce clock will also be disabled when calling this function
315 * if this is the only gpio in the bank using debounce.
317 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
319 u32 gpio_bit = BIT(offset);
321 if (!bank->dbck_flag)
324 if (!(bank->dbck_enable_mask & gpio_bit))
327 bank->dbck_enable_mask &= ~gpio_bit;
328 bank->context.debounce_en &= ~gpio_bit;
329 writel_relaxed(bank->context.debounce_en,
330 bank->base + bank->regs->debounce_en);
332 if (!bank->dbck_enable_mask) {
333 bank->context.debounce = 0;
334 writel_relaxed(bank->context.debounce, bank->base +
335 bank->regs->debounce);
336 clk_disable(bank->dbck);
337 bank->dbck_enabled = false;
342 * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain.
343 * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs
344 * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none
345 * are capable waking up the system from off mode.
347 static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask)
349 u32 no_wake = bank->non_wakeup_gpios;
352 return !!(~no_wake & gpio_mask);
357 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
360 void __iomem *base = bank->base;
361 u32 gpio_bit = BIT(gpio);
363 omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
364 trigger & IRQ_TYPE_LEVEL_LOW);
365 omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
366 trigger & IRQ_TYPE_LEVEL_HIGH);
369 * We need the edge detection enabled for to allow the GPIO block
370 * to be woken from idle state. Set the appropriate edge detection
371 * in addition to the level detection.
373 omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
374 trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH));
375 omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
376 trigger & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW));
378 bank->context.leveldetect0 =
379 readl_relaxed(bank->base + bank->regs->leveldetect0);
380 bank->context.leveldetect1 =
381 readl_relaxed(bank->base + bank->regs->leveldetect1);
382 bank->context.risingdetect =
383 readl_relaxed(bank->base + bank->regs->risingdetect);
384 bank->context.fallingdetect =
385 readl_relaxed(bank->base + bank->regs->fallingdetect);
387 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
388 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
389 bank->context.wake_en =
390 readl_relaxed(bank->base + bank->regs->wkup_en);
393 /* This part needs to be executed always for OMAP{34xx, 44xx} */
394 if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) {
396 * Log the edge gpio and manually trigger the IRQ
397 * after resume if the input level changes
398 * to avoid irq lost during PER RET/OFF mode
399 * Applies for omap2 non-wakeup gpio and all omap3 gpios
401 if (trigger & IRQ_TYPE_EDGE_BOTH)
402 bank->enabled_non_wakeup_gpios |= gpio_bit;
404 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
408 readl_relaxed(bank->base + bank->regs->leveldetect0) |
409 readl_relaxed(bank->base + bank->regs->leveldetect1);
412 #ifdef CONFIG_ARCH_OMAP1
414 * This only applies to chips that can't do both rising and falling edge
415 * detection at once. For all other chips, this function is a noop.
417 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
419 void __iomem *reg = bank->base;
422 if (!bank->regs->irqctrl)
425 reg += bank->regs->irqctrl;
427 l = readl_relaxed(reg);
433 writel_relaxed(l, reg);
436 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
439 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
442 void __iomem *reg = bank->base;
443 void __iomem *base = bank->base;
446 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
447 omap_set_gpio_trigger(bank, gpio, trigger);
448 } else if (bank->regs->irqctrl) {
449 reg += bank->regs->irqctrl;
451 l = readl_relaxed(reg);
452 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
453 bank->toggle_mask |= BIT(gpio);
454 if (trigger & IRQ_TYPE_EDGE_RISING)
456 else if (trigger & IRQ_TYPE_EDGE_FALLING)
461 writel_relaxed(l, reg);
462 } else if (bank->regs->edgectrl1) {
464 reg += bank->regs->edgectrl2;
466 reg += bank->regs->edgectrl1;
469 l = readl_relaxed(reg);
470 l &= ~(3 << (gpio << 1));
471 if (trigger & IRQ_TYPE_EDGE_RISING)
472 l |= 2 << (gpio << 1);
473 if (trigger & IRQ_TYPE_EDGE_FALLING)
476 /* Enable wake-up during idle for dynamic tick */
477 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
478 bank->context.wake_en =
479 readl_relaxed(bank->base + bank->regs->wkup_en);
480 writel_relaxed(l, reg);
485 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
487 if (bank->regs->pinctrl) {
488 void __iomem *reg = bank->base + bank->regs->pinctrl;
490 /* Claim the pin for MPU */
491 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
494 if (bank->regs->ctrl && !BANK_USED(bank)) {
495 void __iomem *reg = bank->base + bank->regs->ctrl;
498 ctrl = readl_relaxed(reg);
499 /* Module is enabled, clocks are not gated */
500 ctrl &= ~GPIO_MOD_CTRL_BIT;
501 writel_relaxed(ctrl, reg);
502 bank->context.ctrl = ctrl;
506 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
508 void __iomem *base = bank->base;
510 if (bank->regs->wkup_en &&
511 !LINE_USED(bank->mod_usage, offset) &&
512 !LINE_USED(bank->irq_usage, offset)) {
513 /* Disable wake-up during idle for dynamic tick */
514 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
515 bank->context.wake_en =
516 readl_relaxed(bank->base + bank->regs->wkup_en);
519 if (bank->regs->ctrl && !BANK_USED(bank)) {
520 void __iomem *reg = bank->base + bank->regs->ctrl;
523 ctrl = readl_relaxed(reg);
524 /* Module is disabled, clocks are gated */
525 ctrl |= GPIO_MOD_CTRL_BIT;
526 writel_relaxed(ctrl, reg);
527 bank->context.ctrl = ctrl;
531 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
533 void __iomem *reg = bank->base + bank->regs->direction;
535 return readl_relaxed(reg) & BIT(offset);
538 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
540 if (!LINE_USED(bank->mod_usage, offset)) {
541 omap_enable_gpio_module(bank, offset);
542 omap_set_gpio_direction(bank, offset, 1);
544 bank->irq_usage |= BIT(offset);
547 static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
549 struct gpio_bank *bank = omap_irq_data_get_bank(d);
552 unsigned offset = d->hwirq;
554 if (type & ~IRQ_TYPE_SENSE_MASK)
557 if (!bank->regs->leveldetect0 &&
558 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
561 raw_spin_lock_irqsave(&bank->lock, flags);
562 retval = omap_set_gpio_triggering(bank, offset, type);
564 raw_spin_unlock_irqrestore(&bank->lock, flags);
567 omap_gpio_init_irq(bank, offset);
568 if (!omap_gpio_is_input(bank, offset)) {
569 raw_spin_unlock_irqrestore(&bank->lock, flags);
573 raw_spin_unlock_irqrestore(&bank->lock, flags);
575 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
576 irq_set_handler_locked(d, handle_level_irq);
577 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
579 * Edge IRQs are already cleared/acked in irq_handler and
580 * not need to be masked, as result handle_edge_irq()
581 * logic is excessed here and may cause lose of interrupts.
582 * So just use handle_simple_irq.
584 irq_set_handler_locked(d, handle_simple_irq);
592 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
594 void __iomem *reg = bank->base;
596 reg += bank->regs->irqstatus;
597 writel_relaxed(gpio_mask, reg);
599 /* Workaround for clearing DSP GPIO interrupts to allow retention */
600 if (bank->regs->irqstatus2) {
601 reg = bank->base + bank->regs->irqstatus2;
602 writel_relaxed(gpio_mask, reg);
605 /* Flush posted write for the irq status to avoid spurious interrupts */
609 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
612 omap_clear_gpio_irqbank(bank, BIT(offset));
615 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
617 void __iomem *reg = bank->base;
619 u32 mask = (BIT(bank->width)) - 1;
621 reg += bank->regs->irqenable;
622 l = readl_relaxed(reg);
623 if (bank->regs->irqenable_inv)
629 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
631 void __iomem *reg = bank->base;
634 if (bank->regs->set_irqenable) {
635 reg += bank->regs->set_irqenable;
637 bank->context.irqenable1 |= gpio_mask;
639 reg += bank->regs->irqenable;
640 l = readl_relaxed(reg);
641 if (bank->regs->irqenable_inv)
645 bank->context.irqenable1 = l;
648 writel_relaxed(l, reg);
651 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
653 void __iomem *reg = bank->base;
656 if (bank->regs->clr_irqenable) {
657 reg += bank->regs->clr_irqenable;
659 bank->context.irqenable1 &= ~gpio_mask;
661 reg += bank->regs->irqenable;
662 l = readl_relaxed(reg);
663 if (bank->regs->irqenable_inv)
667 bank->context.irqenable1 = l;
670 writel_relaxed(l, reg);
673 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
674 unsigned offset, int enable)
677 omap_enable_gpio_irqbank(bank, BIT(offset));
679 omap_disable_gpio_irqbank(bank, BIT(offset));
682 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
683 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
685 struct gpio_bank *bank = omap_irq_data_get_bank(d);
687 return irq_set_irq_wake(bank->irq, enable);
690 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
692 struct gpio_bank *bank = gpiochip_get_data(chip);
695 pm_runtime_get_sync(chip->parent);
697 raw_spin_lock_irqsave(&bank->lock, flags);
698 omap_enable_gpio_module(bank, offset);
699 bank->mod_usage |= BIT(offset);
700 raw_spin_unlock_irqrestore(&bank->lock, flags);
705 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
707 struct gpio_bank *bank = gpiochip_get_data(chip);
710 raw_spin_lock_irqsave(&bank->lock, flags);
711 bank->mod_usage &= ~(BIT(offset));
712 if (!LINE_USED(bank->irq_usage, offset)) {
713 omap_set_gpio_direction(bank, offset, 1);
714 omap_clear_gpio_debounce(bank, offset);
716 omap_disable_gpio_module(bank, offset);
717 raw_spin_unlock_irqrestore(&bank->lock, flags);
719 pm_runtime_put(chip->parent);
723 * We need to unmask the GPIO bank interrupt as soon as possible to
724 * avoid missing GPIO interrupts for other lines in the bank.
725 * Then we need to mask-read-clear-unmask the triggered GPIO lines
726 * in the bank to avoid missing nested interrupts for a GPIO line.
727 * If we wait to unmask individual GPIO lines in the bank after the
728 * line's interrupt handler has been run, we may miss some nested
731 static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
733 void __iomem *isr_reg = NULL;
734 u32 enabled, isr, level_mask;
736 struct gpio_bank *bank = gpiobank;
737 unsigned long wa_lock_flags;
738 unsigned long lock_flags;
740 isr_reg = bank->base + bank->regs->irqstatus;
741 if (WARN_ON(!isr_reg))
744 if (WARN_ONCE(!pm_runtime_active(bank->chip.parent),
745 "gpio irq%i while runtime suspended?\n", irq))
749 raw_spin_lock_irqsave(&bank->lock, lock_flags);
751 enabled = omap_get_gpio_irqbank_mask(bank);
752 isr = readl_relaxed(isr_reg) & enabled;
754 if (bank->level_mask)
755 level_mask = bank->level_mask & enabled;
759 /* clear edge sensitive interrupts before handler(s) are
760 called so that we don't miss any interrupt occurred while
762 if (isr & ~level_mask)
763 omap_clear_gpio_irqbank(bank, isr & ~level_mask);
765 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
774 raw_spin_lock_irqsave(&bank->lock, lock_flags);
776 * Some chips can't respond to both rising and falling
777 * at the same time. If this irq was requested with
778 * both flags, we need to flip the ICR data for the IRQ
779 * to respond to the IRQ for the opposite direction.
780 * This will be indicated in the bank toggle_mask.
782 if (bank->toggle_mask & (BIT(bit)))
783 omap_toggle_gpio_edge_triggering(bank, bit);
785 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
787 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
789 generic_handle_irq(irq_find_mapping(bank->chip.irq.domain,
792 raw_spin_unlock_irqrestore(&bank->wa_lock,
800 static unsigned int omap_gpio_irq_startup(struct irq_data *d)
802 struct gpio_bank *bank = omap_irq_data_get_bank(d);
804 unsigned offset = d->hwirq;
806 raw_spin_lock_irqsave(&bank->lock, flags);
808 if (!LINE_USED(bank->mod_usage, offset))
809 omap_set_gpio_direction(bank, offset, 1);
810 else if (!omap_gpio_is_input(bank, offset))
812 omap_enable_gpio_module(bank, offset);
813 bank->irq_usage |= BIT(offset);
815 raw_spin_unlock_irqrestore(&bank->lock, flags);
816 omap_gpio_unmask_irq(d);
820 raw_spin_unlock_irqrestore(&bank->lock, flags);
824 static void omap_gpio_irq_shutdown(struct irq_data *d)
826 struct gpio_bank *bank = omap_irq_data_get_bank(d);
828 unsigned offset = d->hwirq;
830 raw_spin_lock_irqsave(&bank->lock, flags);
831 bank->irq_usage &= ~(BIT(offset));
832 omap_set_gpio_irqenable(bank, offset, 0);
833 omap_clear_gpio_irqstatus(bank, offset);
834 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
835 if (!LINE_USED(bank->mod_usage, offset))
836 omap_clear_gpio_debounce(bank, offset);
837 omap_disable_gpio_module(bank, offset);
838 raw_spin_unlock_irqrestore(&bank->lock, flags);
841 static void omap_gpio_irq_bus_lock(struct irq_data *data)
843 struct gpio_bank *bank = omap_irq_data_get_bank(data);
845 pm_runtime_get_sync(bank->chip.parent);
848 static void gpio_irq_bus_sync_unlock(struct irq_data *data)
850 struct gpio_bank *bank = omap_irq_data_get_bank(data);
852 pm_runtime_put(bank->chip.parent);
855 static void omap_gpio_ack_irq(struct irq_data *d)
857 struct gpio_bank *bank = omap_irq_data_get_bank(d);
858 unsigned offset = d->hwirq;
860 omap_clear_gpio_irqstatus(bank, offset);
863 static void omap_gpio_mask_irq(struct irq_data *d)
865 struct gpio_bank *bank = omap_irq_data_get_bank(d);
866 unsigned offset = d->hwirq;
869 raw_spin_lock_irqsave(&bank->lock, flags);
870 omap_set_gpio_irqenable(bank, offset, 0);
871 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
872 raw_spin_unlock_irqrestore(&bank->lock, flags);
875 static void omap_gpio_unmask_irq(struct irq_data *d)
877 struct gpio_bank *bank = omap_irq_data_get_bank(d);
878 unsigned offset = d->hwirq;
879 u32 trigger = irqd_get_trigger_type(d);
882 raw_spin_lock_irqsave(&bank->lock, flags);
884 omap_set_gpio_triggering(bank, offset, trigger);
886 omap_set_gpio_irqenable(bank, offset, 1);
889 * For level-triggered GPIOs, clearing must be done after the source
890 * is cleared, thus after the handler has run. OMAP4 needs this done
891 * after enabing the interrupt to clear the wakeup status.
893 if (bank->level_mask & BIT(offset))
894 omap_clear_gpio_irqstatus(bank, offset);
896 raw_spin_unlock_irqrestore(&bank->lock, flags);
899 /*---------------------------------------------------------------------*/
901 static int omap_mpuio_suspend_noirq(struct device *dev)
903 struct gpio_bank *bank = dev_get_drvdata(dev);
904 void __iomem *mask_reg = bank->base +
905 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
908 raw_spin_lock_irqsave(&bank->lock, flags);
909 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
910 raw_spin_unlock_irqrestore(&bank->lock, flags);
915 static int omap_mpuio_resume_noirq(struct device *dev)
917 struct gpio_bank *bank = dev_get_drvdata(dev);
918 void __iomem *mask_reg = bank->base +
919 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
922 raw_spin_lock_irqsave(&bank->lock, flags);
923 writel_relaxed(bank->context.wake_en, mask_reg);
924 raw_spin_unlock_irqrestore(&bank->lock, flags);
929 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
930 .suspend_noirq = omap_mpuio_suspend_noirq,
931 .resume_noirq = omap_mpuio_resume_noirq,
934 /* use platform_driver for this. */
935 static struct platform_driver omap_mpuio_driver = {
938 .pm = &omap_mpuio_dev_pm_ops,
942 static struct platform_device omap_mpuio_device = {
946 .driver = &omap_mpuio_driver.driver,
948 /* could list the /proc/iomem resources */
951 static inline void omap_mpuio_init(struct gpio_bank *bank)
953 platform_set_drvdata(&omap_mpuio_device, bank);
955 if (platform_driver_register(&omap_mpuio_driver) == 0)
956 (void) platform_device_register(&omap_mpuio_device);
959 /*---------------------------------------------------------------------*/
961 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
963 struct gpio_bank *bank;
968 bank = gpiochip_get_data(chip);
969 reg = bank->base + bank->regs->direction;
970 raw_spin_lock_irqsave(&bank->lock, flags);
971 dir = !!(readl_relaxed(reg) & BIT(offset));
972 raw_spin_unlock_irqrestore(&bank->lock, flags);
976 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
978 struct gpio_bank *bank;
981 bank = gpiochip_get_data(chip);
982 raw_spin_lock_irqsave(&bank->lock, flags);
983 omap_set_gpio_direction(bank, offset, 1);
984 raw_spin_unlock_irqrestore(&bank->lock, flags);
988 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
990 struct gpio_bank *bank;
992 bank = gpiochip_get_data(chip);
994 if (omap_gpio_is_input(bank, offset))
995 return omap_get_gpio_datain(bank, offset);
997 return omap_get_gpio_dataout(bank, offset);
1000 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1002 struct gpio_bank *bank;
1003 unsigned long flags;
1005 bank = gpiochip_get_data(chip);
1006 raw_spin_lock_irqsave(&bank->lock, flags);
1007 bank->set_dataout(bank, offset, value);
1008 omap_set_gpio_direction(bank, offset, 0);
1009 raw_spin_unlock_irqrestore(&bank->lock, flags);
1013 static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
1014 unsigned long *bits)
1016 struct gpio_bank *bank = gpiochip_get_data(chip);
1017 void __iomem *reg = bank->base + bank->regs->direction;
1018 unsigned long in = readl_relaxed(reg), l;
1024 *bits |= omap_get_gpio_datain_multiple(bank, &l);
1028 *bits |= omap_get_gpio_dataout_multiple(bank, &l);
1033 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
1036 struct gpio_bank *bank;
1037 unsigned long flags;
1040 bank = gpiochip_get_data(chip);
1042 raw_spin_lock_irqsave(&bank->lock, flags);
1043 ret = omap2_set_gpio_debounce(bank, offset, debounce);
1044 raw_spin_unlock_irqrestore(&bank->lock, flags);
1047 dev_info(chip->parent,
1048 "Could not set line %u debounce to %u microseconds (%d)",
1049 offset, debounce, ret);
1054 static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,
1055 unsigned long config)
1059 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
1062 debounce = pinconf_to_config_argument(config);
1063 return omap_gpio_debounce(chip, offset, debounce);
1066 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1068 struct gpio_bank *bank;
1069 unsigned long flags;
1071 bank = gpiochip_get_data(chip);
1072 raw_spin_lock_irqsave(&bank->lock, flags);
1073 bank->set_dataout(bank, offset, value);
1074 raw_spin_unlock_irqrestore(&bank->lock, flags);
1077 static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
1078 unsigned long *bits)
1080 struct gpio_bank *bank = gpiochip_get_data(chip);
1081 unsigned long flags;
1083 raw_spin_lock_irqsave(&bank->lock, flags);
1084 bank->set_dataout_multiple(bank, mask, bits);
1085 raw_spin_unlock_irqrestore(&bank->lock, flags);
1088 /*---------------------------------------------------------------------*/
1090 static void omap_gpio_show_rev(struct gpio_bank *bank)
1095 if (called || bank->regs->revision == USHRT_MAX)
1098 rev = readw_relaxed(bank->base + bank->regs->revision);
1099 pr_info("OMAP GPIO hardware version %d.%d\n",
1100 (rev >> 4) & 0x0f, rev & 0x0f);
1105 static void omap_gpio_mod_init(struct gpio_bank *bank)
1107 void __iomem *base = bank->base;
1110 if (bank->width == 16)
1113 if (bank->is_mpuio) {
1114 writel_relaxed(l, bank->base + bank->regs->irqenable);
1118 omap_gpio_rmw(base, bank->regs->irqenable, l,
1119 bank->regs->irqenable_inv);
1120 omap_gpio_rmw(base, bank->regs->irqstatus, l,
1121 !bank->regs->irqenable_inv);
1122 if (bank->regs->debounce_en)
1123 writel_relaxed(0, base + bank->regs->debounce_en);
1125 /* Save OE default value (0xffffffff) in the context */
1126 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1127 /* Initialize interface clk ungated, module enabled */
1128 if (bank->regs->ctrl)
1129 writel_relaxed(0, base + bank->regs->ctrl);
1132 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1134 struct gpio_irq_chip *irq;
1141 * REVISIT eventually switch from OMAP-specific gpio structs
1142 * over to the generic ones
1144 bank->chip.request = omap_gpio_request;
1145 bank->chip.free = omap_gpio_free;
1146 bank->chip.get_direction = omap_gpio_get_direction;
1147 bank->chip.direction_input = omap_gpio_input;
1148 bank->chip.get = omap_gpio_get;
1149 bank->chip.get_multiple = omap_gpio_get_multiple;
1150 bank->chip.direction_output = omap_gpio_output;
1151 bank->chip.set_config = omap_gpio_set_config;
1152 bank->chip.set = omap_gpio_set;
1153 bank->chip.set_multiple = omap_gpio_set_multiple;
1154 if (bank->is_mpuio) {
1155 bank->chip.label = "mpuio";
1156 if (bank->regs->wkup_en)
1157 bank->chip.parent = &omap_mpuio_device.dev;
1158 bank->chip.base = OMAP_MPUIO(0);
1160 label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d",
1161 gpio, gpio + bank->width - 1);
1164 bank->chip.label = label;
1165 bank->chip.base = gpio;
1167 bank->chip.ngpio = bank->width;
1169 #ifdef CONFIG_ARCH_OMAP1
1171 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1172 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1174 irq_base = devm_irq_alloc_descs(bank->chip.parent,
1175 -1, 0, bank->width, 0);
1177 dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n");
1182 /* MPUIO is a bit different, reading IRQ status clears it */
1183 if (bank->is_mpuio) {
1184 irqc->irq_ack = dummy_irq_chip.irq_ack;
1185 if (!bank->regs->wkup_en)
1186 irqc->irq_set_wake = NULL;
1189 irq = &bank->chip.irq;
1191 irq->handler = handle_bad_irq;
1192 irq->default_type = IRQ_TYPE_NONE;
1193 irq->num_parents = 1;
1194 irq->parents = &bank->irq;
1195 irq->first = irq_base;
1197 ret = gpiochip_add_data(&bank->chip, bank);
1199 dev_err(bank->chip.parent,
1200 "Could not register gpio chip %d\n", ret);
1204 ret = devm_request_irq(bank->chip.parent, bank->irq,
1205 omap_gpio_irq_handler,
1206 0, dev_name(bank->chip.parent), bank);
1208 gpiochip_remove(&bank->chip);
1210 if (!bank->is_mpuio)
1211 gpio += bank->width;
1216 static void omap_gpio_init_context(struct gpio_bank *p)
1218 struct omap_gpio_reg_offs *regs = p->regs;
1219 void __iomem *base = p->base;
1221 p->context.ctrl = readl_relaxed(base + regs->ctrl);
1222 p->context.oe = readl_relaxed(base + regs->direction);
1223 p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1224 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1225 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1226 p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1227 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1228 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1229 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
1231 if (regs->set_dataout && p->regs->clr_dataout)
1232 p->context.dataout = readl_relaxed(base + regs->set_dataout);
1234 p->context.dataout = readl_relaxed(base + regs->dataout);
1236 p->context_valid = true;
1239 static void omap_gpio_restore_context(struct gpio_bank *bank)
1241 writel_relaxed(bank->context.wake_en,
1242 bank->base + bank->regs->wkup_en);
1243 writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1244 writel_relaxed(bank->context.leveldetect0,
1245 bank->base + bank->regs->leveldetect0);
1246 writel_relaxed(bank->context.leveldetect1,
1247 bank->base + bank->regs->leveldetect1);
1248 writel_relaxed(bank->context.risingdetect,
1249 bank->base + bank->regs->risingdetect);
1250 writel_relaxed(bank->context.fallingdetect,
1251 bank->base + bank->regs->fallingdetect);
1252 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1253 writel_relaxed(bank->context.dataout,
1254 bank->base + bank->regs->set_dataout);
1256 writel_relaxed(bank->context.dataout,
1257 bank->base + bank->regs->dataout);
1258 writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1260 if (bank->dbck_enable_mask) {
1261 writel_relaxed(bank->context.debounce, bank->base +
1262 bank->regs->debounce);
1263 writel_relaxed(bank->context.debounce_en,
1264 bank->base + bank->regs->debounce_en);
1267 writel_relaxed(bank->context.irqenable1,
1268 bank->base + bank->regs->irqenable);
1269 writel_relaxed(bank->context.irqenable2,
1270 bank->base + bank->regs->irqenable2);
1273 static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context)
1275 struct device *dev = bank->chip.parent;
1276 void __iomem *base = bank->base;
1279 bank->saved_datain = readl_relaxed(base + bank->regs->datain);
1281 if (!bank->enabled_non_wakeup_gpios)
1282 goto update_gpio_context_count;
1284 if (!may_lose_context)
1285 goto update_gpio_context_count;
1288 * If going to OFF, remove triggering for all wkup domain
1289 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1290 * generated. See OMAP2420 Errata item 1.101.
1292 if (!bank->loses_context && bank->enabled_non_wakeup_gpios) {
1293 nowake = bank->enabled_non_wakeup_gpios;
1294 omap_gpio_rmw(base, bank->regs->fallingdetect, nowake, ~nowake);
1295 omap_gpio_rmw(base, bank->regs->risingdetect, nowake, ~nowake);
1298 update_gpio_context_count:
1299 if (bank->get_context_loss_count)
1300 bank->context_loss_count =
1301 bank->get_context_loss_count(dev);
1303 omap_gpio_dbck_disable(bank);
1306 static void omap_gpio_unidle(struct gpio_bank *bank)
1308 struct device *dev = bank->chip.parent;
1309 u32 l = 0, gen, gen0, gen1;
1313 * On the first resume during the probe, the context has not
1314 * been initialised and so initialise it now. Also initialise
1315 * the context loss count.
1317 if (bank->loses_context && !bank->context_valid) {
1318 omap_gpio_init_context(bank);
1320 if (bank->get_context_loss_count)
1321 bank->context_loss_count =
1322 bank->get_context_loss_count(dev);
1325 omap_gpio_dbck_enable(bank);
1327 if (bank->loses_context) {
1328 if (!bank->get_context_loss_count) {
1329 omap_gpio_restore_context(bank);
1331 c = bank->get_context_loss_count(dev);
1332 if (c != bank->context_loss_count) {
1333 omap_gpio_restore_context(bank);
1339 /* Restore changes done for OMAP2420 errata 1.101 */
1340 writel_relaxed(bank->context.fallingdetect,
1341 bank->base + bank->regs->fallingdetect);
1342 writel_relaxed(bank->context.risingdetect,
1343 bank->base + bank->regs->risingdetect);
1346 l = readl_relaxed(bank->base + bank->regs->datain);
1349 * Check if any of the non-wakeup interrupt GPIOs have changed
1350 * state. If so, generate an IRQ by software. This is
1351 * horribly racy, but it's the best we can do to work around
1354 l ^= bank->saved_datain;
1355 l &= bank->enabled_non_wakeup_gpios;
1358 * No need to generate IRQs for the rising edge for gpio IRQs
1359 * configured with falling edge only; and vice versa.
1361 gen0 = l & bank->context.fallingdetect;
1362 gen0 &= bank->saved_datain;
1364 gen1 = l & bank->context.risingdetect;
1365 gen1 &= ~(bank->saved_datain);
1367 /* FIXME: Consider GPIO IRQs with level detections properly! */
1368 gen = l & (~(bank->context.fallingdetect) &
1369 ~(bank->context.risingdetect));
1370 /* Consider all GPIO IRQs needed to be updated */
1376 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1377 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1379 if (!bank->regs->irqstatus_raw0) {
1380 writel_relaxed(old0 | gen, bank->base +
1381 bank->regs->leveldetect0);
1382 writel_relaxed(old1 | gen, bank->base +
1383 bank->regs->leveldetect1);
1386 if (bank->regs->irqstatus_raw0) {
1387 writel_relaxed(old0 | l, bank->base +
1388 bank->regs->leveldetect0);
1389 writel_relaxed(old1 | l, bank->base +
1390 bank->regs->leveldetect1);
1392 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1393 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1397 static int gpio_omap_cpu_notifier(struct notifier_block *nb,
1398 unsigned long cmd, void *v)
1400 struct gpio_bank *bank;
1401 unsigned long flags;
1403 bank = container_of(nb, struct gpio_bank, nb);
1405 raw_spin_lock_irqsave(&bank->lock, flags);
1407 case CPU_CLUSTER_PM_ENTER:
1408 if (bank->is_suspended)
1410 omap_gpio_idle(bank, true);
1412 case CPU_CLUSTER_PM_ENTER_FAILED:
1413 case CPU_CLUSTER_PM_EXIT:
1414 if (bank->is_suspended)
1416 omap_gpio_unidle(bank);
1419 raw_spin_unlock_irqrestore(&bank->lock, flags);
1424 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1425 .revision = OMAP24XX_GPIO_REVISION,
1426 .direction = OMAP24XX_GPIO_OE,
1427 .datain = OMAP24XX_GPIO_DATAIN,
1428 .dataout = OMAP24XX_GPIO_DATAOUT,
1429 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1430 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1431 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1432 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1433 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1434 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1435 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1436 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1437 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1438 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1439 .ctrl = OMAP24XX_GPIO_CTRL,
1440 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1441 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1442 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1443 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1444 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1447 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1448 .revision = OMAP4_GPIO_REVISION,
1449 .direction = OMAP4_GPIO_OE,
1450 .datain = OMAP4_GPIO_DATAIN,
1451 .dataout = OMAP4_GPIO_DATAOUT,
1452 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1453 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1454 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1455 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1456 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1457 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1458 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1459 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1460 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1461 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1462 .ctrl = OMAP4_GPIO_CTRL,
1463 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1464 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1465 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1466 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1467 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1470 static const struct omap_gpio_platform_data omap2_pdata = {
1471 .regs = &omap2_gpio_regs,
1476 static const struct omap_gpio_platform_data omap3_pdata = {
1477 .regs = &omap2_gpio_regs,
1482 static const struct omap_gpio_platform_data omap4_pdata = {
1483 .regs = &omap4_gpio_regs,
1488 static const struct of_device_id omap_gpio_match[] = {
1490 .compatible = "ti,omap4-gpio",
1491 .data = &omap4_pdata,
1494 .compatible = "ti,omap3-gpio",
1495 .data = &omap3_pdata,
1498 .compatible = "ti,omap2-gpio",
1499 .data = &omap2_pdata,
1503 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1505 static int omap_gpio_probe(struct platform_device *pdev)
1507 struct device *dev = &pdev->dev;
1508 struct device_node *node = dev->of_node;
1509 const struct of_device_id *match;
1510 const struct omap_gpio_platform_data *pdata;
1511 struct gpio_bank *bank;
1512 struct irq_chip *irqc;
1515 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1517 pdata = match ? match->data : dev_get_platdata(dev);
1521 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
1525 irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1529 irqc->irq_startup = omap_gpio_irq_startup,
1530 irqc->irq_shutdown = omap_gpio_irq_shutdown,
1531 irqc->irq_ack = omap_gpio_ack_irq,
1532 irqc->irq_mask = omap_gpio_mask_irq,
1533 irqc->irq_unmask = omap_gpio_unmask_irq,
1534 irqc->irq_set_type = omap_gpio_irq_type,
1535 irqc->irq_set_wake = omap_gpio_wake_enable,
1536 irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
1537 irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
1538 irqc->name = dev_name(&pdev->dev);
1539 irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
1540 irqc->parent_device = dev;
1542 bank->irq = platform_get_irq(pdev, 0);
1543 if (bank->irq <= 0) {
1546 if (bank->irq != -EPROBE_DEFER)
1548 "can't get irq resource ret=%d\n", bank->irq);
1552 bank->chip.parent = dev;
1553 bank->chip.owner = THIS_MODULE;
1554 bank->dbck_flag = pdata->dbck_flag;
1555 bank->stride = pdata->bank_stride;
1556 bank->width = pdata->bank_width;
1557 bank->is_mpuio = pdata->is_mpuio;
1558 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1559 bank->regs = pdata->regs;
1560 #ifdef CONFIG_OF_GPIO
1561 bank->chip.of_node = of_node_get(node);
1565 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1566 bank->loses_context = true;
1568 bank->loses_context = pdata->loses_context;
1570 if (bank->loses_context)
1571 bank->get_context_loss_count =
1572 pdata->get_context_loss_count;
1575 if (bank->regs->set_dataout && bank->regs->clr_dataout) {
1576 bank->set_dataout = omap_set_gpio_dataout_reg;
1577 bank->set_dataout_multiple = omap_set_gpio_dataout_reg_multiple;
1579 bank->set_dataout = omap_set_gpio_dataout_mask;
1580 bank->set_dataout_multiple =
1581 omap_set_gpio_dataout_mask_multiple;
1584 raw_spin_lock_init(&bank->lock);
1585 raw_spin_lock_init(&bank->wa_lock);
1587 /* Static mapping, never released */
1588 bank->base = devm_platform_ioremap_resource(pdev, 0);
1589 if (IS_ERR(bank->base)) {
1590 return PTR_ERR(bank->base);
1593 if (bank->dbck_flag) {
1594 bank->dbck = devm_clk_get(dev, "dbclk");
1595 if (IS_ERR(bank->dbck)) {
1597 "Could not get gpio dbck. Disable debounce\n");
1598 bank->dbck_flag = false;
1600 clk_prepare(bank->dbck);
1604 platform_set_drvdata(pdev, bank);
1606 pm_runtime_enable(dev);
1607 pm_runtime_get_sync(dev);
1610 omap_mpuio_init(bank);
1612 omap_gpio_mod_init(bank);
1614 ret = omap_gpio_chip_init(bank, irqc);
1616 pm_runtime_put_sync(dev);
1617 pm_runtime_disable(dev);
1618 if (bank->dbck_flag)
1619 clk_unprepare(bank->dbck);
1623 omap_gpio_show_rev(bank);
1625 bank->nb.notifier_call = gpio_omap_cpu_notifier;
1626 cpu_pm_register_notifier(&bank->nb);
1628 pm_runtime_put(dev);
1633 static int omap_gpio_remove(struct platform_device *pdev)
1635 struct gpio_bank *bank = platform_get_drvdata(pdev);
1637 cpu_pm_unregister_notifier(&bank->nb);
1638 list_del(&bank->node);
1639 gpiochip_remove(&bank->chip);
1640 pm_runtime_disable(&pdev->dev);
1641 if (bank->dbck_flag)
1642 clk_unprepare(bank->dbck);
1647 static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev)
1649 struct gpio_bank *bank = dev_get_drvdata(dev);
1650 unsigned long flags;
1652 raw_spin_lock_irqsave(&bank->lock, flags);
1653 omap_gpio_idle(bank, true);
1654 bank->is_suspended = true;
1655 raw_spin_unlock_irqrestore(&bank->lock, flags);
1660 static int __maybe_unused omap_gpio_runtime_resume(struct device *dev)
1662 struct gpio_bank *bank = dev_get_drvdata(dev);
1663 unsigned long flags;
1665 raw_spin_lock_irqsave(&bank->lock, flags);
1666 omap_gpio_unidle(bank);
1667 bank->is_suspended = false;
1668 raw_spin_unlock_irqrestore(&bank->lock, flags);
1673 static const struct dev_pm_ops gpio_pm_ops = {
1674 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1678 static struct platform_driver omap_gpio_driver = {
1679 .probe = omap_gpio_probe,
1680 .remove = omap_gpio_remove,
1682 .name = "omap_gpio",
1684 .of_match_table = omap_gpio_match,
1689 * gpio driver register needs to be done before
1690 * machine_init functions access gpio APIs.
1691 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1693 static int __init omap_gpio_drv_reg(void)
1695 return platform_driver_register(&omap_gpio_driver);
1697 postcore_initcall(omap_gpio_drv_reg);
1699 static void __exit omap_gpio_exit(void)
1701 platform_driver_unregister(&omap_gpio_driver);
1703 module_exit(omap_gpio_exit);
1705 MODULE_DESCRIPTION("omap gpio driver");
1706 MODULE_ALIAS("platform:gpio-omap");
1707 MODULE_LICENSE("GPL v2");