1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas R-Car GPIO Support
5 * Copyright (C) 2014 Renesas Electronics Corporation
6 * Copyright (C) 2013 Magnus Damm
10 #include <linux/gpio/driver.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
14 #include <linux/ioport.h>
15 #include <linux/irq.h>
16 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/pinctrl/consumer.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/spinlock.h>
23 #include <linux/slab.h>
25 struct gpio_rcar_bank_info {
35 struct gpio_rcar_priv {
39 struct gpio_chip gpio_chip;
40 struct irq_chip irq_chip;
41 unsigned int irq_parent;
44 bool has_both_edge_trigger;
45 struct gpio_rcar_bank_info bank_info;
48 #define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
49 #define INOUTSEL 0x04 /* General Input/Output Switching Register */
50 #define OUTDT 0x08 /* General Output Register */
51 #define INDT 0x0c /* General Input Register */
52 #define INTDT 0x10 /* Interrupt Display Register */
53 #define INTCLR 0x14 /* Interrupt Clear Register */
54 #define INTMSK 0x18 /* Interrupt Mask Register */
55 #define MSKCLR 0x1c /* Interrupt Mask Clear Register */
56 #define POSNEG 0x20 /* Positive/Negative Logic Select Register */
57 #define EDGLEVEL 0x24 /* Edge/level Select Register */
58 #define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
59 #define OUTDTSEL 0x40 /* Output Data Select Register */
60 #define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
62 #define RCAR_MAX_GPIO_PER_BANK 32
64 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
66 return ioread32(p->base + offs);
69 static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
72 iowrite32(value, p->base + offs);
75 static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
78 u32 tmp = gpio_rcar_read(p, offs);
85 gpio_rcar_write(p, offs, tmp);
88 static void gpio_rcar_irq_disable(struct irq_data *d)
90 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
91 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
93 gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
96 static void gpio_rcar_irq_enable(struct irq_data *d)
98 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
99 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
101 gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
104 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
106 bool active_high_rising_edge,
112 /* follow steps in the GPIO documentation for
113 * "Setting Edge-Sensitive Interrupt Input Mode" and
114 * "Setting Level-Sensitive Interrupt Input Mode"
117 spin_lock_irqsave(&p->lock, flags);
119 /* Configure postive or negative logic in POSNEG */
120 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
122 /* Configure edge or level trigger in EDGLEVEL */
123 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
125 /* Select one edge or both edges in BOTHEDGE */
126 if (p->has_both_edge_trigger)
127 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
129 /* Select "Interrupt Input Mode" in IOINTSEL */
130 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
132 /* Write INTCLR in case of edge trigger */
134 gpio_rcar_write(p, INTCLR, BIT(hwirq));
136 spin_unlock_irqrestore(&p->lock, flags);
139 static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
141 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
142 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
143 unsigned int hwirq = irqd_to_hwirq(d);
145 dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type);
147 switch (type & IRQ_TYPE_SENSE_MASK) {
148 case IRQ_TYPE_LEVEL_HIGH:
149 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
152 case IRQ_TYPE_LEVEL_LOW:
153 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
156 case IRQ_TYPE_EDGE_RISING:
157 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
160 case IRQ_TYPE_EDGE_FALLING:
161 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
164 case IRQ_TYPE_EDGE_BOTH:
165 if (!p->has_both_edge_trigger)
167 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
176 static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
178 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
179 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
183 error = irq_set_irq_wake(p->irq_parent, on);
185 dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n",
192 atomic_inc(&p->wakeup_path);
194 atomic_dec(&p->wakeup_path);
199 static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
201 struct gpio_rcar_priv *p = dev_id;
203 unsigned int offset, irqs_handled = 0;
205 while ((pending = gpio_rcar_read(p, INTDT) &
206 gpio_rcar_read(p, INTMSK))) {
207 offset = __ffs(pending);
208 gpio_rcar_write(p, INTCLR, BIT(offset));
209 generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
214 return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
217 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
221 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
224 /* follow steps in the GPIO documentation for
225 * "Setting General Output Mode" and
226 * "Setting General Input Mode"
229 spin_lock_irqsave(&p->lock, flags);
231 /* Configure postive logic in POSNEG */
232 gpio_rcar_modify_bit(p, POSNEG, gpio, false);
234 /* Select "General Input/Output Mode" in IOINTSEL */
235 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
237 /* Select Input Mode or Output Mode in INOUTSEL */
238 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
240 /* Select General Output Register to output data in OUTDTSEL */
241 if (p->has_outdtsel && output)
242 gpio_rcar_modify_bit(p, OUTDTSEL, gpio, false);
244 spin_unlock_irqrestore(&p->lock, flags);
247 static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
249 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
252 error = pm_runtime_get_sync(p->dev);
256 error = pinctrl_gpio_request(chip->base + offset);
258 pm_runtime_put(p->dev);
263 static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
265 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
267 pinctrl_gpio_free(chip->base + offset);
270 * Set the GPIO as an input to ensure that the next GPIO request won't
271 * drive the GPIO pin as an output.
273 gpio_rcar_config_general_input_output_mode(chip, offset, false);
275 pm_runtime_put(p->dev);
278 static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
280 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
282 if (gpio_rcar_read(p, INOUTSEL) & BIT(offset))
283 return GPIO_LINE_DIRECTION_OUT;
285 return GPIO_LINE_DIRECTION_IN;
288 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
290 gpio_rcar_config_general_input_output_mode(chip, offset, false);
294 static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
296 u32 bit = BIT(offset);
298 /* testing on r8a7790 shows that INDT does not show correct pin state
299 * when configured as output, so use OUTDT in case of output pins */
300 if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
301 return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
303 return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
306 static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
308 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
311 spin_lock_irqsave(&p->lock, flags);
312 gpio_rcar_modify_bit(p, OUTDT, offset, value);
313 spin_unlock_irqrestore(&p->lock, flags);
316 static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
319 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
323 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
324 if (chip->valid_mask)
325 bankmask &= chip->valid_mask[0];
330 spin_lock_irqsave(&p->lock, flags);
331 val = gpio_rcar_read(p, OUTDT);
333 val |= (bankmask & bits[0]);
334 gpio_rcar_write(p, OUTDT, val);
335 spin_unlock_irqrestore(&p->lock, flags);
338 static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
341 /* write GPIO value to output before selecting output mode of pin */
342 gpio_rcar_set(chip, offset, value);
343 gpio_rcar_config_general_input_output_mode(chip, offset, true);
347 struct gpio_rcar_info {
349 bool has_both_edge_trigger;
352 static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
353 .has_outdtsel = false,
354 .has_both_edge_trigger = false,
357 static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
358 .has_outdtsel = true,
359 .has_both_edge_trigger = true,
362 static const struct of_device_id gpio_rcar_of_table[] = {
364 .compatible = "renesas,gpio-r8a7743",
365 /* RZ/G1 GPIO is identical to R-Car Gen2. */
366 .data = &gpio_rcar_info_gen2,
368 .compatible = "renesas,gpio-r8a7790",
369 .data = &gpio_rcar_info_gen2,
371 .compatible = "renesas,gpio-r8a7791",
372 .data = &gpio_rcar_info_gen2,
374 .compatible = "renesas,gpio-r8a7792",
375 .data = &gpio_rcar_info_gen2,
377 .compatible = "renesas,gpio-r8a7793",
378 .data = &gpio_rcar_info_gen2,
380 .compatible = "renesas,gpio-r8a7794",
381 .data = &gpio_rcar_info_gen2,
383 .compatible = "renesas,gpio-r8a7795",
384 /* Gen3 GPIO is identical to Gen2. */
385 .data = &gpio_rcar_info_gen2,
387 .compatible = "renesas,gpio-r8a7796",
388 /* Gen3 GPIO is identical to Gen2. */
389 .data = &gpio_rcar_info_gen2,
391 .compatible = "renesas,rcar-gen1-gpio",
392 .data = &gpio_rcar_info_gen1,
394 .compatible = "renesas,rcar-gen2-gpio",
395 .data = &gpio_rcar_info_gen2,
397 .compatible = "renesas,rcar-gen3-gpio",
398 /* Gen3 GPIO is identical to Gen2. */
399 .data = &gpio_rcar_info_gen2,
401 .compatible = "renesas,gpio-rcar",
402 .data = &gpio_rcar_info_gen1,
408 MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
410 static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
412 struct device_node *np = p->dev->of_node;
413 const struct gpio_rcar_info *info;
414 struct of_phandle_args args;
417 info = of_device_get_match_data(p->dev);
418 p->has_outdtsel = info->has_outdtsel;
419 p->has_both_edge_trigger = info->has_both_edge_trigger;
421 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
422 *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
424 if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
425 dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n",
426 *npins, RCAR_MAX_GPIO_PER_BANK);
427 *npins = RCAR_MAX_GPIO_PER_BANK;
433 static int gpio_rcar_probe(struct platform_device *pdev)
435 struct gpio_rcar_priv *p;
436 struct resource *irq;
437 struct gpio_chip *gpio_chip;
438 struct irq_chip *irq_chip;
439 struct device *dev = &pdev->dev;
440 const char *name = dev_name(dev);
444 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
449 spin_lock_init(&p->lock);
451 /* Get device configuration from DT node */
452 ret = gpio_rcar_parse_dt(p, &npins);
456 platform_set_drvdata(pdev, p);
458 pm_runtime_enable(dev);
460 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
462 dev_err(dev, "missing IRQ\n");
467 p->base = devm_platform_ioremap_resource(pdev, 0);
468 if (IS_ERR(p->base)) {
469 ret = PTR_ERR(p->base);
473 gpio_chip = &p->gpio_chip;
474 gpio_chip->request = gpio_rcar_request;
475 gpio_chip->free = gpio_rcar_free;
476 gpio_chip->get_direction = gpio_rcar_get_direction;
477 gpio_chip->direction_input = gpio_rcar_direction_input;
478 gpio_chip->get = gpio_rcar_get;
479 gpio_chip->direction_output = gpio_rcar_direction_output;
480 gpio_chip->set = gpio_rcar_set;
481 gpio_chip->set_multiple = gpio_rcar_set_multiple;
482 gpio_chip->label = name;
483 gpio_chip->parent = dev;
484 gpio_chip->owner = THIS_MODULE;
485 gpio_chip->base = -1;
486 gpio_chip->ngpio = npins;
488 irq_chip = &p->irq_chip;
489 irq_chip->name = "gpio-rcar";
490 irq_chip->parent_device = dev;
491 irq_chip->irq_mask = gpio_rcar_irq_disable;
492 irq_chip->irq_unmask = gpio_rcar_irq_enable;
493 irq_chip->irq_set_type = gpio_rcar_irq_set_type;
494 irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
495 irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
497 ret = gpiochip_add_data(gpio_chip, p);
499 dev_err(dev, "failed to add GPIO controller\n");
503 ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
506 dev_err(dev, "cannot add irqchip\n");
510 p->irq_parent = irq->start;
511 if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
512 IRQF_SHARED, name, p)) {
513 dev_err(dev, "failed to request IRQ\n");
518 dev_info(dev, "driving %d GPIOs\n", npins);
523 gpiochip_remove(gpio_chip);
525 pm_runtime_disable(dev);
529 static int gpio_rcar_remove(struct platform_device *pdev)
531 struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
533 gpiochip_remove(&p->gpio_chip);
535 pm_runtime_disable(&pdev->dev);
539 #ifdef CONFIG_PM_SLEEP
540 static int gpio_rcar_suspend(struct device *dev)
542 struct gpio_rcar_priv *p = dev_get_drvdata(dev);
544 p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
545 p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
546 p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
547 p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
548 p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
549 p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
550 if (p->has_both_edge_trigger)
551 p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);
553 if (atomic_read(&p->wakeup_path))
554 device_set_wakeup_path(dev);
559 static int gpio_rcar_resume(struct device *dev)
561 struct gpio_rcar_priv *p = dev_get_drvdata(dev);
565 for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
566 if (!gpiochip_line_is_valid(&p->gpio_chip, offset))
571 if (!(p->bank_info.iointsel & mask)) {
572 if (p->bank_info.inoutsel & mask)
573 gpio_rcar_direction_output(
574 &p->gpio_chip, offset,
575 !!(p->bank_info.outdt & mask));
577 gpio_rcar_direction_input(&p->gpio_chip,
581 gpio_rcar_config_interrupt_input_mode(
584 !(p->bank_info.posneg & mask),
585 !(p->bank_info.edglevel & mask),
586 !!(p->bank_info.bothedge & mask));
588 if (p->bank_info.intmsk & mask)
589 gpio_rcar_write(p, MSKCLR, mask);
595 #endif /* CONFIG_PM_SLEEP*/
597 static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);
599 static struct platform_driver gpio_rcar_device_driver = {
600 .probe = gpio_rcar_probe,
601 .remove = gpio_rcar_remove,
604 .pm = &gpio_rcar_pm_ops,
605 .of_match_table = of_match_ptr(gpio_rcar_of_table),
609 module_platform_driver(gpio_rcar_device_driver);
611 MODULE_AUTHOR("Magnus Damm");
612 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
613 MODULE_LICENSE("GPL v2");