1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-sa1100/gpio.c
5 * Generic SA-1100 GPIO handling
7 #include <linux/gpio/driver.h>
8 #include <linux/init.h>
9 #include <linux/module.h>
11 #include <linux/syscore_ops.h>
12 #include <soc/sa1100/pwer.h>
13 #include <mach/hardware.h>
14 #include <mach/irqs.h>
16 struct sa1100_gpio_chip {
17 struct gpio_chip chip;
18 void __iomem *membase;
26 #define sa1100_gpio_chip(x) container_of(x, struct sa1100_gpio_chip, chip)
39 static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset)
41 return readl_relaxed(sa1100_gpio_chip(chip)->membase + R_GPLR) &
45 static void sa1100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
47 int reg = value ? R_GPSR : R_GPCR;
49 writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg);
52 static int sa1100_get_direction(struct gpio_chip *chip, unsigned offset)
54 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR;
56 return !(readl_relaxed(gpdr) & BIT(offset));
59 static int sa1100_direction_input(struct gpio_chip *chip, unsigned offset)
61 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR;
64 local_irq_save(flags);
65 writel_relaxed(readl_relaxed(gpdr) & ~BIT(offset), gpdr);
66 local_irq_restore(flags);
71 static int sa1100_direction_output(struct gpio_chip *chip, unsigned offset, int value)
73 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR;
76 local_irq_save(flags);
77 sa1100_gpio_set(chip, offset, value);
78 writel_relaxed(readl_relaxed(gpdr) | BIT(offset), gpdr);
79 local_irq_restore(flags);
84 static int sa1100_to_irq(struct gpio_chip *chip, unsigned offset)
86 return sa1100_gpio_chip(chip)->irqbase + offset;
89 static struct sa1100_gpio_chip sa1100_gpio_chip = {
92 .get_direction = sa1100_get_direction,
93 .direction_input = sa1100_direction_input,
94 .direction_output = sa1100_direction_output,
95 .set = sa1100_gpio_set,
96 .get = sa1100_gpio_get,
97 .to_irq = sa1100_to_irq,
99 .ngpio = GPIO_MAX + 1,
101 .membase = (void *)&GPLR,
102 .irqbase = IRQ_GPIO0,
106 * SA1100 GPIO edge detection for IRQs:
107 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
108 * Use this instead of directly setting GRER/GFER.
110 static void sa1100_update_edge_regs(struct sa1100_gpio_chip *sgc)
112 void *base = sgc->membase;
115 grer = sgc->irqrising & sgc->irqmask;
116 gfer = sgc->irqfalling & sgc->irqmask;
118 writel_relaxed(grer, base + R_GRER);
119 writel_relaxed(gfer, base + R_GFER);
122 static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
124 struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
125 unsigned int mask = BIT(d->hwirq);
127 if (type == IRQ_TYPE_PROBE) {
128 if ((sgc->irqrising | sgc->irqfalling) & mask)
130 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
133 if (type & IRQ_TYPE_EDGE_RISING)
134 sgc->irqrising |= mask;
136 sgc->irqrising &= ~mask;
137 if (type & IRQ_TYPE_EDGE_FALLING)
138 sgc->irqfalling |= mask;
140 sgc->irqfalling &= ~mask;
142 sa1100_update_edge_regs(sgc);
148 * GPIO IRQs must be acknowledged.
150 static void sa1100_gpio_ack(struct irq_data *d)
152 struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
154 writel_relaxed(BIT(d->hwirq), sgc->membase + R_GEDR);
157 static void sa1100_gpio_mask(struct irq_data *d)
159 struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
160 unsigned int mask = BIT(d->hwirq);
162 sgc->irqmask &= ~mask;
164 sa1100_update_edge_regs(sgc);
167 static void sa1100_gpio_unmask(struct irq_data *d)
169 struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
170 unsigned int mask = BIT(d->hwirq);
172 sgc->irqmask |= mask;
174 sa1100_update_edge_regs(sgc);
177 static int sa1100_gpio_wake(struct irq_data *d, unsigned int on)
179 struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
180 int ret = sa11x0_gpio_set_wake(d->hwirq, on);
183 sgc->irqwake |= BIT(d->hwirq);
185 sgc->irqwake &= ~BIT(d->hwirq);
191 * This is for GPIO IRQs
193 static struct irq_chip sa1100_gpio_irq_chip = {
195 .irq_ack = sa1100_gpio_ack,
196 .irq_mask = sa1100_gpio_mask,
197 .irq_unmask = sa1100_gpio_unmask,
198 .irq_set_type = sa1100_gpio_type,
199 .irq_set_wake = sa1100_gpio_wake,
202 static int sa1100_gpio_irqdomain_map(struct irq_domain *d,
203 unsigned int irq, irq_hw_number_t hwirq)
205 struct sa1100_gpio_chip *sgc = d->host_data;
207 irq_set_chip_data(irq, sgc);
208 irq_set_chip_and_handler(irq, &sa1100_gpio_irq_chip, handle_edge_irq);
214 static const struct irq_domain_ops sa1100_gpio_irqdomain_ops = {
215 .map = sa1100_gpio_irqdomain_map,
216 .xlate = irq_domain_xlate_onetwocell,
219 static struct irq_domain *sa1100_gpio_irqdomain;
222 * IRQ 0-11 (GPIO) handler. We enter here with the
223 * irq_controller_lock held, and IRQs disabled. Decode the IRQ
224 * and call the handler.
226 static void sa1100_gpio_handler(struct irq_desc *desc)
228 struct sa1100_gpio_chip *sgc = irq_desc_get_handler_data(desc);
229 unsigned int irq, mask;
230 void __iomem *gedr = sgc->membase + R_GEDR;
232 mask = readl_relaxed(gedr);
235 * clear down all currently active IRQ sources.
236 * We will be processing them all.
238 writel_relaxed(mask, gedr);
243 generic_handle_irq(irq);
248 mask = readl_relaxed(gedr);
252 static int sa1100_gpio_suspend(void)
254 struct sa1100_gpio_chip *sgc = &sa1100_gpio_chip;
257 * Set the appropriate edges for wakeup.
259 writel_relaxed(sgc->irqwake & sgc->irqrising, sgc->membase + R_GRER);
260 writel_relaxed(sgc->irqwake & sgc->irqfalling, sgc->membase + R_GFER);
263 * Clear any pending GPIO interrupts.
265 writel_relaxed(readl_relaxed(sgc->membase + R_GEDR),
266 sgc->membase + R_GEDR);
271 static void sa1100_gpio_resume(void)
273 sa1100_update_edge_regs(&sa1100_gpio_chip);
276 static struct syscore_ops sa1100_gpio_syscore_ops = {
277 .suspend = sa1100_gpio_suspend,
278 .resume = sa1100_gpio_resume,
281 static int __init sa1100_gpio_init_devicefs(void)
283 register_syscore_ops(&sa1100_gpio_syscore_ops);
287 device_initcall(sa1100_gpio_init_devicefs);
289 static const int sa1100_gpio_irqs[] __initconst = {
290 /* Install handlers for GPIO 0-10 edge detect interrupts */
302 /* Install handler for GPIO 11-27 edge detect interrupts */
306 void __init sa1100_init_gpio(void)
308 struct sa1100_gpio_chip *sgc = &sa1100_gpio_chip;
311 /* clear all GPIO edge detects */
312 writel_relaxed(0, sgc->membase + R_GFER);
313 writel_relaxed(0, sgc->membase + R_GRER);
314 writel_relaxed(-1, sgc->membase + R_GEDR);
316 gpiochip_add_data(&sa1100_gpio_chip.chip, NULL);
318 sa1100_gpio_irqdomain = irq_domain_add_simple(NULL,
320 &sa1100_gpio_irqdomain_ops, sgc);
322 for (i = 0; i < ARRAY_SIZE(sa1100_gpio_irqs); i++)
323 irq_set_chained_handler_and_data(sa1100_gpio_irqs[i],
324 sa1100_gpio_handler, sgc);