1 // SPDX-License-Identifier: GPL-2.0
3 * GPIO interface for Intel Poulsbo SCH
5 * Copyright (c) 2010 CompuLab Ltd
6 * Author: Denis Turischev <denis@compulab.co.il>
9 #include <linux/acpi.h>
10 #include <linux/errno.h>
11 #include <linux/gpio/driver.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/pci_ids.h>
16 #include <linux/platform_device.h>
23 struct gpio_chip chip;
25 unsigned short iobase;
26 unsigned short core_base;
27 unsigned short resume_base;
30 static unsigned sch_gpio_offset(struct sch_gpio *sch, unsigned gpio,
35 if (gpio >= sch->resume_base) {
36 gpio -= sch->resume_base;
40 return base + reg + gpio / 8;
43 static unsigned sch_gpio_bit(struct sch_gpio *sch, unsigned gpio)
45 if (gpio >= sch->resume_base)
46 gpio -= sch->resume_base;
50 static int sch_gpio_reg_get(struct sch_gpio *sch, unsigned gpio, unsigned reg)
52 unsigned short offset, bit;
55 offset = sch_gpio_offset(sch, gpio, reg);
56 bit = sch_gpio_bit(sch, gpio);
58 reg_val = !!(inb(sch->iobase + offset) & BIT(bit));
63 static void sch_gpio_reg_set(struct sch_gpio *sch, unsigned gpio, unsigned reg,
66 unsigned short offset, bit;
69 offset = sch_gpio_offset(sch, gpio, reg);
70 bit = sch_gpio_bit(sch, gpio);
72 reg_val = inb(sch->iobase + offset);
75 outb(reg_val | BIT(bit), sch->iobase + offset);
77 outb((reg_val & ~BIT(bit)), sch->iobase + offset);
80 static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned gpio_num)
82 struct sch_gpio *sch = gpiochip_get_data(gc);
84 spin_lock(&sch->lock);
85 sch_gpio_reg_set(sch, gpio_num, GIO, 1);
86 spin_unlock(&sch->lock);
90 static int sch_gpio_get(struct gpio_chip *gc, unsigned gpio_num)
92 struct sch_gpio *sch = gpiochip_get_data(gc);
93 return sch_gpio_reg_get(sch, gpio_num, GLV);
96 static void sch_gpio_set(struct gpio_chip *gc, unsigned gpio_num, int val)
98 struct sch_gpio *sch = gpiochip_get_data(gc);
100 spin_lock(&sch->lock);
101 sch_gpio_reg_set(sch, gpio_num, GLV, val);
102 spin_unlock(&sch->lock);
105 static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned gpio_num,
108 struct sch_gpio *sch = gpiochip_get_data(gc);
110 spin_lock(&sch->lock);
111 sch_gpio_reg_set(sch, gpio_num, GIO, 0);
112 spin_unlock(&sch->lock);
115 * according to the datasheet, writing to the level register has no
116 * effect when GPIO is programmed as input.
117 * Actually the the level register is read-only when configured as input.
118 * Thus presetting the output level before switching to output is _NOT_ possible.
119 * Hence we set the level after configuring the GPIO as output.
120 * But we cannot prevent a short low pulse if direction is set to high
121 * and an external pull-up is connected.
123 sch_gpio_set(gc, gpio_num, val);
127 static int sch_gpio_get_direction(struct gpio_chip *gc, unsigned gpio_num)
129 struct sch_gpio *sch = gpiochip_get_data(gc);
131 return sch_gpio_reg_get(sch, gpio_num, GIO);
134 static const struct gpio_chip sch_gpio_chip = {
136 .owner = THIS_MODULE,
137 .direction_input = sch_gpio_direction_in,
139 .direction_output = sch_gpio_direction_out,
141 .get_direction = sch_gpio_get_direction,
144 static int sch_gpio_probe(struct platform_device *pdev)
146 struct sch_gpio *sch;
147 struct resource *res;
149 sch = devm_kzalloc(&pdev->dev, sizeof(*sch), GFP_KERNEL);
153 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
157 if (!devm_request_region(&pdev->dev, res->start, resource_size(res),
161 spin_lock_init(&sch->lock);
162 sch->iobase = res->start;
163 sch->chip = sch_gpio_chip;
164 sch->chip.label = dev_name(&pdev->dev);
165 sch->chip.parent = &pdev->dev;
168 case PCI_DEVICE_ID_INTEL_SCH_LPC:
170 sch->resume_base = 10;
171 sch->chip.ngpio = 14;
174 * GPIO[6:0] enabled by default
175 * GPIO7 is configured by the CMC as SLPIOVR
176 * Enable GPIO[9:8] core powered gpios explicitly
178 sch_gpio_reg_set(sch, 8, GEN, 1);
179 sch_gpio_reg_set(sch, 9, GEN, 1);
181 * SUS_GPIO[2:0] enabled by default
182 * Enable SUS_GPIO3 resume powered gpio explicitly
184 sch_gpio_reg_set(sch, 13, GEN, 1);
187 case PCI_DEVICE_ID_INTEL_ITC_LPC:
189 sch->resume_base = 5;
190 sch->chip.ngpio = 14;
193 case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
195 sch->resume_base = 21;
196 sch->chip.ngpio = 30;
199 case PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB:
201 sch->resume_base = 2;
209 platform_set_drvdata(pdev, sch);
211 return devm_gpiochip_add_data(&pdev->dev, &sch->chip, sch);
214 static struct platform_driver sch_gpio_driver = {
218 .probe = sch_gpio_probe,
221 module_platform_driver(sch_gpio_driver);
223 MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>");
224 MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH");
225 MODULE_LICENSE("GPL v2");
226 MODULE_ALIAS("platform:sch_gpio");