1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2017 NVIDIA Corporation
5 * Author: Thierry Reding <treding@nvidia.com>
8 #include <linux/gpio/driver.h>
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
15 #include <dt-bindings/gpio/tegra186-gpio.h>
16 #include <dt-bindings/gpio/tegra194-gpio.h>
18 /* security registers */
19 #define TEGRA186_GPIO_CTL_SCR 0x0c
20 #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28)
21 #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27)
23 #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4)
25 /* control registers */
26 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00
27 #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
28 #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
29 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
30 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
31 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
32 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
33 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
34 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
35 #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5)
36 #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
38 #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
39 #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
41 #define TEGRA186_GPIO_INPUT 0x08
42 #define TEGRA186_GPIO_INPUT_HIGH BIT(0)
44 #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
45 #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
47 #define TEGRA186_GPIO_OUTPUT_VALUE 0x10
48 #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
50 #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
52 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
54 struct tegra_gpio_port {
61 struct tegra_gpio_soc {
62 const struct tegra_gpio_port *ports;
63 unsigned int num_ports;
65 unsigned int instance;
69 struct gpio_chip gpio;
74 const struct tegra_gpio_soc *soc;
80 static const struct tegra_gpio_port *
81 tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
83 unsigned int start = 0, i;
85 for (i = 0; i < gpio->soc->num_ports; i++) {
86 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
88 if (*pin >= start && *pin < start + port->pins) {
99 static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
102 const struct tegra_gpio_port *port;
105 port = tegra186_gpio_get_port(gpio, &pin);
109 offset = port->bank * 0x1000 + port->port * 0x200;
111 return gpio->base + offset + pin * 0x20;
114 static int tegra186_gpio_get_direction(struct gpio_chip *chip,
117 struct tegra_gpio *gpio = gpiochip_get_data(chip);
121 base = tegra186_gpio_get_base(gpio, offset);
122 if (WARN_ON(base == NULL))
125 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
126 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
127 return GPIO_LINE_DIRECTION_OUT;
129 return GPIO_LINE_DIRECTION_IN;
132 static int tegra186_gpio_direction_input(struct gpio_chip *chip,
135 struct tegra_gpio *gpio = gpiochip_get_data(chip);
139 base = tegra186_gpio_get_base(gpio, offset);
140 if (WARN_ON(base == NULL))
143 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
144 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
145 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
147 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
148 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
149 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
150 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
155 static int tegra186_gpio_direction_output(struct gpio_chip *chip,
156 unsigned int offset, int level)
158 struct tegra_gpio *gpio = gpiochip_get_data(chip);
162 /* configure output level first */
163 chip->set(chip, offset, level);
165 base = tegra186_gpio_get_base(gpio, offset);
166 if (WARN_ON(base == NULL))
169 /* set the direction */
170 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
171 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
172 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
174 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
175 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
176 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
177 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
182 static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
184 struct tegra_gpio *gpio = gpiochip_get_data(chip);
188 base = tegra186_gpio_get_base(gpio, offset);
189 if (WARN_ON(base == NULL))
192 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
193 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
194 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
196 value = readl(base + TEGRA186_GPIO_INPUT);
198 return value & BIT(0);
201 static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
204 struct tegra_gpio *gpio = gpiochip_get_data(chip);
208 base = tegra186_gpio_get_base(gpio, offset);
209 if (WARN_ON(base == NULL))
212 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
214 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
216 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
218 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
221 static int tegra186_gpio_set_config(struct gpio_chip *chip,
223 unsigned long config)
225 struct tegra_gpio *gpio = gpiochip_get_data(chip);
229 base = tegra186_gpio_get_base(gpio, offset);
233 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
236 debounce = pinconf_to_config_argument(config);
239 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce
242 if (debounce > 255000)
245 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC);
247 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce);
248 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL);
250 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
251 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE;
252 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
257 static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
258 const struct of_phandle_args *spec,
261 struct tegra_gpio *gpio = gpiochip_get_data(chip);
262 unsigned int port, pin, i, offset = 0;
264 if (WARN_ON(chip->of_gpio_n_cells < 2))
267 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
270 port = spec->args[0] / 8;
271 pin = spec->args[0] % 8;
273 if (port >= gpio->soc->num_ports) {
274 dev_err(chip->parent, "invalid port number: %u\n", port);
278 for (i = 0; i < port; i++)
279 offset += gpio->soc->ports[i].pins;
282 *flags = spec->args[1];
287 static void tegra186_irq_ack(struct irq_data *data)
289 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
292 base = tegra186_gpio_get_base(gpio, data->hwirq);
293 if (WARN_ON(base == NULL))
296 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
299 static void tegra186_irq_mask(struct irq_data *data)
301 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
305 base = tegra186_gpio_get_base(gpio, data->hwirq);
306 if (WARN_ON(base == NULL))
309 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
310 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
311 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
314 static void tegra186_irq_unmask(struct irq_data *data)
316 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
320 base = tegra186_gpio_get_base(gpio, data->hwirq);
321 if (WARN_ON(base == NULL))
324 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
325 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
326 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
329 static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)
331 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
335 base = tegra186_gpio_get_base(gpio, data->hwirq);
336 if (WARN_ON(base == NULL))
339 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
340 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
341 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
343 switch (type & IRQ_TYPE_SENSE_MASK) {
347 case IRQ_TYPE_EDGE_RISING:
348 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
349 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
352 case IRQ_TYPE_EDGE_FALLING:
353 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
356 case IRQ_TYPE_EDGE_BOTH:
357 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
360 case IRQ_TYPE_LEVEL_HIGH:
361 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
362 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
365 case IRQ_TYPE_LEVEL_LOW:
366 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
373 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
375 if ((type & IRQ_TYPE_EDGE_BOTH) == 0)
376 irq_set_handler_locked(data, handle_level_irq);
378 irq_set_handler_locked(data, handle_edge_irq);
380 return irq_chip_set_type_parent(data, type);
383 static void tegra186_gpio_irq(struct irq_desc *desc)
385 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
386 struct irq_domain *domain = gpio->gpio.irq.domain;
387 struct irq_chip *chip = irq_desc_get_chip(desc);
388 unsigned int parent = irq_desc_get_irq(desc);
389 unsigned int i, offset = 0;
391 chained_irq_enter(chip, desc);
393 for (i = 0; i < gpio->soc->num_ports; i++) {
394 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
395 unsigned int pin, irq;
399 base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
401 /* skip ports that are not associated with this bank */
402 if (parent != gpio->irq[port->bank])
405 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
407 for_each_set_bit(pin, &value, port->pins) {
408 irq = irq_find_mapping(domain, offset + pin);
409 if (WARN_ON(irq == 0))
412 generic_handle_irq(irq);
416 offset += port->pins;
419 chained_irq_exit(chip, desc);
422 static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain,
423 struct irq_fwspec *fwspec,
424 unsigned long *hwirq,
427 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
428 unsigned int port, pin, i, offset = 0;
430 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2))
433 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells))
436 port = fwspec->param[0] / 8;
437 pin = fwspec->param[0] % 8;
439 if (port >= gpio->soc->num_ports)
442 for (i = 0; i < port; i++)
443 offset += gpio->soc->ports[i].pins;
445 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
446 *hwirq = offset + pin;
451 static void *tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,
452 unsigned int parent_hwirq,
453 unsigned int parent_type)
455 struct tegra_gpio *gpio = gpiochip_get_data(chip);
456 struct irq_fwspec *fwspec;
458 fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL);
462 fwspec->fwnode = chip->irq.parent_domain->fwnode;
463 fwspec->param_count = 3;
464 fwspec->param[0] = gpio->soc->instance;
465 fwspec->param[1] = parent_hwirq;
466 fwspec->param[2] = parent_type;
471 static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
474 unsigned int *parent_hwirq,
475 unsigned int *parent_type)
477 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
483 static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip,
486 struct tegra_gpio *gpio = gpiochip_get_data(chip);
489 for (i = 0; i < gpio->soc->num_ports; i++) {
490 if (offset < gpio->soc->ports[i].pins)
493 offset -= gpio->soc->ports[i].pins;
496 return offset + i * 8;
499 static const struct of_device_id tegra186_pmc_of_match[] = {
500 { .compatible = "nvidia,tegra186-pmc" },
501 { .compatible = "nvidia,tegra194-pmc" },
505 static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
510 for (i = 0; i < gpio->soc->num_ports; i++) {
511 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
512 unsigned int offset, p = port->port;
515 base = gpio->secure + port->bank * 0x1000 + 0x800;
517 value = readl(base + TEGRA186_GPIO_CTL_SCR);
520 * For controllers that haven't been locked down yet, make
521 * sure to program the default interrupt route mapping.
523 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&
524 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {
525 for (j = 0; j < 8; j++) {
526 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j);
528 value = readl(base + offset);
529 value = BIT(port->pins) - 1;
530 writel(value, base + offset);
536 static int tegra186_gpio_probe(struct platform_device *pdev)
538 unsigned int i, j, offset;
539 struct gpio_irq_chip *irq;
540 struct tegra_gpio *gpio;
541 struct device_node *np;
545 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
549 gpio->soc = of_device_get_match_data(&pdev->dev);
551 gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security");
552 if (IS_ERR(gpio->secure))
553 return PTR_ERR(gpio->secure);
555 gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
556 if (IS_ERR(gpio->base))
557 return PTR_ERR(gpio->base);
559 err = platform_irq_count(pdev);
565 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
570 for (i = 0; i < gpio->num_irq; i++) {
571 err = platform_get_irq(pdev, i);
578 gpio->gpio.label = gpio->soc->name;
579 gpio->gpio.parent = &pdev->dev;
581 gpio->gpio.get_direction = tegra186_gpio_get_direction;
582 gpio->gpio.direction_input = tegra186_gpio_direction_input;
583 gpio->gpio.direction_output = tegra186_gpio_direction_output;
584 gpio->gpio.get = tegra186_gpio_get,
585 gpio->gpio.set = tegra186_gpio_set;
586 gpio->gpio.set_config = tegra186_gpio_set_config;
588 gpio->gpio.base = -1;
590 for (i = 0; i < gpio->soc->num_ports; i++)
591 gpio->gpio.ngpio += gpio->soc->ports[i].pins;
593 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
594 sizeof(*names), GFP_KERNEL);
598 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
599 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
602 for (j = 0; j < port->pins; j++) {
603 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
604 "P%s.%02x", port->name, j);
608 names[offset + j] = name;
611 offset += port->pins;
614 gpio->gpio.names = (const char * const *)names;
616 gpio->gpio.of_node = pdev->dev.of_node;
617 gpio->gpio.of_gpio_n_cells = 2;
618 gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
620 gpio->intc.name = pdev->dev.of_node->name;
621 gpio->intc.irq_ack = tegra186_irq_ack;
622 gpio->intc.irq_mask = tegra186_irq_mask;
623 gpio->intc.irq_unmask = tegra186_irq_unmask;
624 gpio->intc.irq_set_type = tegra186_irq_set_type;
625 gpio->intc.irq_set_wake = irq_chip_set_wake_parent;
627 irq = &gpio->gpio.irq;
628 irq->chip = &gpio->intc;
629 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
630 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq;
631 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec;
632 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq;
633 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate;
634 irq->handler = handle_simple_irq;
635 irq->default_type = IRQ_TYPE_NONE;
636 irq->parent_handler = tegra186_gpio_irq;
637 irq->parent_handler_data = gpio;
638 irq->num_parents = gpio->num_irq;
639 irq->parents = gpio->irq;
641 np = of_find_matching_node(NULL, tegra186_pmc_of_match);
643 irq->parent_domain = irq_find_host(np);
646 if (!irq->parent_domain)
647 return -EPROBE_DEFER;
650 tegra186_gpio_init_route_mapping(gpio);
652 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
653 sizeof(*irq->map), GFP_KERNEL);
657 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
658 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
660 for (j = 0; j < port->pins; j++)
661 irq->map[offset + j] = irq->parents[port->bank];
663 offset += port->pins;
666 platform_set_drvdata(pdev, gpio);
668 err = devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
675 static int tegra186_gpio_remove(struct platform_device *pdev)
680 #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
681 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \
688 static const struct tegra_gpio_port tegra186_main_ports[] = {
689 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),
690 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),
691 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7),
692 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6),
693 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8),
694 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6),
695 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6),
696 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7),
697 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8),
698 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8),
699 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1),
700 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8),
701 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6),
702 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7),
703 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4),
704 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7),
705 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6),
706 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6),
707 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4),
708 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8),
709 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7),
710 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2),
711 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4),
714 static const struct tegra_gpio_soc tegra186_main_soc = {
715 .num_ports = ARRAY_SIZE(tegra186_main_ports),
716 .ports = tegra186_main_ports,
717 .name = "tegra186-gpio",
721 #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
722 [TEGRA186_AON_GPIO_PORT_##_name] = { \
729 static const struct tegra_gpio_port tegra186_aon_ports[] = {
730 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),
731 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6),
732 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8),
733 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8),
734 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4),
735 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8),
736 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3),
737 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5),
740 static const struct tegra_gpio_soc tegra186_aon_soc = {
741 .num_ports = ARRAY_SIZE(tegra186_aon_ports),
742 .ports = tegra186_aon_ports,
743 .name = "tegra186-gpio-aon",
747 #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
748 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \
755 static const struct tegra_gpio_port tegra194_main_ports[] = {
756 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),
757 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2),
758 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8),
759 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4),
760 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8),
761 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6),
762 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8),
763 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8),
764 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5),
765 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6),
766 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8),
767 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4),
768 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8),
769 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3),
770 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6),
771 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8),
772 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8),
773 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6),
774 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8),
775 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8),
776 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1),
777 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8),
778 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2),
779 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8),
780 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8),
781 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8),
782 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2),
783 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)
786 static const struct tegra_gpio_soc tegra194_main_soc = {
787 .num_ports = ARRAY_SIZE(tegra194_main_ports),
788 .ports = tegra194_main_ports,
789 .name = "tegra194-gpio",
793 #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \
794 [TEGRA194_AON_GPIO_PORT_##_name] = { \
801 static const struct tegra_gpio_port tegra194_aon_ports[] = {
802 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),
803 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4),
804 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8),
805 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3),
806 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7)
809 static const struct tegra_gpio_soc tegra194_aon_soc = {
810 .num_ports = ARRAY_SIZE(tegra194_aon_ports),
811 .ports = tegra194_aon_ports,
812 .name = "tegra194-gpio-aon",
816 static const struct of_device_id tegra186_gpio_of_match[] = {
818 .compatible = "nvidia,tegra186-gpio",
819 .data = &tegra186_main_soc
821 .compatible = "nvidia,tegra186-gpio-aon",
822 .data = &tegra186_aon_soc
824 .compatible = "nvidia,tegra194-gpio",
825 .data = &tegra194_main_soc
827 .compatible = "nvidia,tegra194-gpio-aon",
828 .data = &tegra194_aon_soc
834 static struct platform_driver tegra186_gpio_driver = {
836 .name = "tegra186-gpio",
837 .of_match_table = tegra186_gpio_of_match,
839 .probe = tegra186_gpio_probe,
840 .remove = tegra186_gpio_remove,
842 module_platform_driver(tegra186_gpio_driver);
844 MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
845 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
846 MODULE_LICENSE("GPL v2");