2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2016, 2017 Cavium Inc.
9 #include <linux/bitops.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17 #include <linux/spinlock.h>
20 #define GPIO_RX_DAT 0x0
21 #define GPIO_TX_SET 0x8
22 #define GPIO_TX_CLR 0x10
23 #define GPIO_CONST 0x90
24 #define GPIO_CONST_GPIOS_MASK 0xff
25 #define GPIO_BIT_CFG 0x400
26 #define GPIO_BIT_CFG_TX_OE BIT(0)
27 #define GPIO_BIT_CFG_PIN_XOR BIT(1)
28 #define GPIO_BIT_CFG_INT_EN BIT(2)
29 #define GPIO_BIT_CFG_INT_TYPE BIT(3)
30 #define GPIO_BIT_CFG_FIL_MASK GENMASK(11, 4)
31 #define GPIO_BIT_CFG_FIL_CNT_SHIFT 4
32 #define GPIO_BIT_CFG_FIL_SEL_SHIFT 8
33 #define GPIO_BIT_CFG_TX_OD BIT(12)
34 #define GPIO_BIT_CFG_PIN_SEL_MASK GENMASK(25, 16)
35 #define GPIO_INTR 0x800
36 #define GPIO_INTR_INTR BIT(0)
37 #define GPIO_INTR_INTR_W1S BIT(1)
38 #define GPIO_INTR_ENA_W1C BIT(2)
39 #define GPIO_INTR_ENA_W1S BIT(3)
40 #define GPIO_2ND_BANK 0x1400
42 #define GLITCH_FILTER_400NS ((4u << GPIO_BIT_CFG_FIL_SEL_SHIFT) | \
43 (9u << GPIO_BIT_CFG_FIL_CNT_SHIFT))
47 struct thunderx_line {
48 struct thunderx_gpio *txgpio;
50 unsigned int fil_bits;
53 struct thunderx_gpio {
54 struct gpio_chip chip;
55 u8 __iomem *register_base;
56 struct irq_domain *irqd;
57 struct msix_entry *msix_entries; /* per line MSI-X */
58 struct thunderx_line *line_entries; /* per line irq info */
60 unsigned long invert_mask[2];
61 unsigned long od_mask[2];
65 static unsigned int bit_cfg_reg(unsigned int line)
67 return 8 * line + GPIO_BIT_CFG;
70 static unsigned int intr_reg(unsigned int line)
72 return 8 * line + GPIO_INTR;
75 static bool thunderx_gpio_is_gpio_nowarn(struct thunderx_gpio *txgpio,
78 u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
80 return (bit_cfg & GPIO_BIT_CFG_PIN_SEL_MASK) == 0;
84 * Check (and WARN) that the pin is available for GPIO. We will not
85 * allow modification of the state of non-GPIO pins from this driver.
87 static bool thunderx_gpio_is_gpio(struct thunderx_gpio *txgpio,
90 bool rv = thunderx_gpio_is_gpio_nowarn(txgpio, line);
92 WARN_RATELIMIT(!rv, "Pin %d not available for GPIO\n", line);
97 static int thunderx_gpio_request(struct gpio_chip *chip, unsigned int line)
99 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
101 return thunderx_gpio_is_gpio(txgpio, line) ? 0 : -EIO;
104 static int thunderx_gpio_dir_in(struct gpio_chip *chip, unsigned int line)
106 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
108 if (!thunderx_gpio_is_gpio(txgpio, line))
111 raw_spin_lock(&txgpio->lock);
112 clear_bit(line, txgpio->invert_mask);
113 clear_bit(line, txgpio->od_mask);
114 writeq(txgpio->line_entries[line].fil_bits,
115 txgpio->register_base + bit_cfg_reg(line));
116 raw_spin_unlock(&txgpio->lock);
120 static void thunderx_gpio_set(struct gpio_chip *chip, unsigned int line,
123 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
124 int bank = line / 64;
125 int bank_bit = line % 64;
127 void __iomem *reg = txgpio->register_base +
128 (bank * GPIO_2ND_BANK) + (value ? GPIO_TX_SET : GPIO_TX_CLR);
130 writeq(BIT_ULL(bank_bit), reg);
133 static int thunderx_gpio_dir_out(struct gpio_chip *chip, unsigned int line,
136 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
137 u64 bit_cfg = txgpio->line_entries[line].fil_bits | GPIO_BIT_CFG_TX_OE;
139 if (!thunderx_gpio_is_gpio(txgpio, line))
142 raw_spin_lock(&txgpio->lock);
144 thunderx_gpio_set(chip, line, value);
146 if (test_bit(line, txgpio->invert_mask))
147 bit_cfg |= GPIO_BIT_CFG_PIN_XOR;
149 if (test_bit(line, txgpio->od_mask))
150 bit_cfg |= GPIO_BIT_CFG_TX_OD;
152 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
154 raw_spin_unlock(&txgpio->lock);
158 static int thunderx_gpio_get_direction(struct gpio_chip *chip, unsigned int line)
160 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
163 if (!thunderx_gpio_is_gpio_nowarn(txgpio, line))
165 * Say it is input for now to avoid WARNing on
166 * gpiochip_add_data(). We will WARN if someone
167 * requests it or tries to use it.
171 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
173 if (bit_cfg & GPIO_BIT_CFG_TX_OE)
174 return GPIO_LINE_DIRECTION_OUT;
176 return GPIO_LINE_DIRECTION_IN;
179 static int thunderx_gpio_set_config(struct gpio_chip *chip,
183 bool orig_invert, orig_od, orig_dat, new_invert, new_od;
186 int bank = line / 64;
187 int bank_bit = line % 64;
189 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
190 void __iomem *reg = txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET;
192 if (!thunderx_gpio_is_gpio(txgpio, line))
195 raw_spin_lock(&txgpio->lock);
196 orig_invert = test_bit(line, txgpio->invert_mask);
197 new_invert = orig_invert;
198 orig_od = test_bit(line, txgpio->od_mask);
200 orig_dat = ((readq(reg) >> bank_bit) & 1) ^ orig_invert;
201 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
202 switch (pinconf_to_config_param(cfg)) {
203 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
205 * Weird, setting open-drain mode causes signal
206 * inversion. Note this so we can compensate in the
209 set_bit(line, txgpio->invert_mask);
211 set_bit(line, txgpio->od_mask);
215 case PIN_CONFIG_DRIVE_PUSH_PULL:
216 clear_bit(line, txgpio->invert_mask);
218 clear_bit(line, txgpio->od_mask);
222 case PIN_CONFIG_INPUT_DEBOUNCE:
223 arg = pinconf_to_config_argument(cfg);
224 if (arg > 1228) { /* 15 * 2^15 * 2.5nS maximum */
228 arg *= 400; /* scale to 2.5nS clocks. */
232 arg++; /* always round up */
235 txgpio->line_entries[line].fil_bits =
236 (sel << GPIO_BIT_CFG_FIL_SEL_SHIFT) |
237 (arg << GPIO_BIT_CFG_FIL_CNT_SHIFT);
238 bit_cfg &= ~GPIO_BIT_CFG_FIL_MASK;
239 bit_cfg |= txgpio->line_entries[line].fil_bits;
240 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
246 raw_spin_unlock(&txgpio->lock);
249 * If currently output and OPEN_DRAIN changed, install the new
252 if ((new_invert != orig_invert || new_od != orig_od) &&
253 (bit_cfg & GPIO_BIT_CFG_TX_OE))
254 ret = thunderx_gpio_dir_out(chip, line, orig_dat ^ new_invert);
259 static int thunderx_gpio_get(struct gpio_chip *chip, unsigned int line)
261 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
262 int bank = line / 64;
263 int bank_bit = line % 64;
264 u64 read_bits = readq(txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_RX_DAT);
265 u64 masked_bits = read_bits & BIT_ULL(bank_bit);
267 if (test_bit(line, txgpio->invert_mask))
268 return masked_bits == 0;
270 return masked_bits != 0;
273 static void thunderx_gpio_set_multiple(struct gpio_chip *chip,
278 u64 set_bits, clear_bits;
279 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
281 for (bank = 0; bank <= chip->ngpio / 64; bank++) {
282 set_bits = bits[bank] & mask[bank];
283 clear_bits = ~bits[bank] & mask[bank];
284 writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET);
285 writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR);
289 static void thunderx_gpio_irq_ack(struct irq_data *data)
291 struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
293 writeq(GPIO_INTR_INTR,
294 txline->txgpio->register_base + intr_reg(txline->line));
297 static void thunderx_gpio_irq_mask(struct irq_data *data)
299 struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
301 writeq(GPIO_INTR_ENA_W1C,
302 txline->txgpio->register_base + intr_reg(txline->line));
305 static void thunderx_gpio_irq_mask_ack(struct irq_data *data)
307 struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
309 writeq(GPIO_INTR_ENA_W1C | GPIO_INTR_INTR,
310 txline->txgpio->register_base + intr_reg(txline->line));
313 static void thunderx_gpio_irq_unmask(struct irq_data *data)
315 struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
317 writeq(GPIO_INTR_ENA_W1S,
318 txline->txgpio->register_base + intr_reg(txline->line));
321 static int thunderx_gpio_irq_set_type(struct irq_data *data,
322 unsigned int flow_type)
324 struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
325 struct thunderx_gpio *txgpio = txline->txgpio;
328 irqd_set_trigger_type(data, flow_type);
330 bit_cfg = txline->fil_bits | GPIO_BIT_CFG_INT_EN;
332 if (flow_type & IRQ_TYPE_EDGE_BOTH) {
333 irq_set_handler_locked(data, handle_fasteoi_ack_irq);
334 bit_cfg |= GPIO_BIT_CFG_INT_TYPE;
336 irq_set_handler_locked(data, handle_fasteoi_mask_irq);
339 raw_spin_lock(&txgpio->lock);
340 if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)) {
341 bit_cfg |= GPIO_BIT_CFG_PIN_XOR;
342 set_bit(txline->line, txgpio->invert_mask);
344 clear_bit(txline->line, txgpio->invert_mask);
346 clear_bit(txline->line, txgpio->od_mask);
347 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(txline->line));
348 raw_spin_unlock(&txgpio->lock);
350 return IRQ_SET_MASK_OK;
353 static void thunderx_gpio_irq_enable(struct irq_data *data)
355 irq_chip_enable_parent(data);
356 thunderx_gpio_irq_unmask(data);
359 static void thunderx_gpio_irq_disable(struct irq_data *data)
361 thunderx_gpio_irq_mask(data);
362 irq_chip_disable_parent(data);
365 static int thunderx_gpio_irq_request_resources(struct irq_data *data)
367 struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
368 struct thunderx_gpio *txgpio = txline->txgpio;
371 r = gpiochip_lock_as_irq(&txgpio->chip, txline->line);
375 r = irq_chip_request_resources_parent(data);
377 gpiochip_unlock_as_irq(&txgpio->chip, txline->line);
382 static void thunderx_gpio_irq_release_resources(struct irq_data *data)
384 struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
385 struct thunderx_gpio *txgpio = txline->txgpio;
387 irq_chip_release_resources_parent(data);
389 gpiochip_unlock_as_irq(&txgpio->chip, txline->line);
393 * Interrupts are chained from underlying MSI-X vectors. We have
394 * these irq_chip functions to be able to handle level triggering
395 * semantics and other acknowledgment tasks associated with the GPIO
398 static struct irq_chip thunderx_gpio_irq_chip = {
400 .irq_enable = thunderx_gpio_irq_enable,
401 .irq_disable = thunderx_gpio_irq_disable,
402 .irq_ack = thunderx_gpio_irq_ack,
403 .irq_mask = thunderx_gpio_irq_mask,
404 .irq_mask_ack = thunderx_gpio_irq_mask_ack,
405 .irq_unmask = thunderx_gpio_irq_unmask,
406 .irq_eoi = irq_chip_eoi_parent,
407 .irq_set_affinity = irq_chip_set_affinity_parent,
408 .irq_request_resources = thunderx_gpio_irq_request_resources,
409 .irq_release_resources = thunderx_gpio_irq_release_resources,
410 .irq_set_type = thunderx_gpio_irq_set_type,
412 .flags = IRQCHIP_SET_TYPE_MASKED
415 static int thunderx_gpio_irq_translate(struct irq_domain *d,
416 struct irq_fwspec *fwspec,
417 irq_hw_number_t *hwirq,
420 struct thunderx_gpio *txgpio = d->host_data;
422 if (WARN_ON(fwspec->param_count < 2))
424 if (fwspec->param[0] >= txgpio->chip.ngpio)
426 *hwirq = fwspec->param[0];
427 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
431 static int thunderx_gpio_irq_alloc(struct irq_domain *d, unsigned int virq,
432 unsigned int nr_irqs, void *arg)
434 struct thunderx_line *txline = arg;
436 return irq_domain_set_hwirq_and_chip(d, virq, txline->line,
437 &thunderx_gpio_irq_chip, txline);
440 static const struct irq_domain_ops thunderx_gpio_irqd_ops = {
441 .alloc = thunderx_gpio_irq_alloc,
442 .translate = thunderx_gpio_irq_translate
445 static int thunderx_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
447 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
449 return irq_find_mapping(txgpio->irqd, offset);
452 static int thunderx_gpio_probe(struct pci_dev *pdev,
453 const struct pci_device_id *id)
455 void __iomem * const *tbl;
456 struct device *dev = &pdev->dev;
457 struct thunderx_gpio *txgpio;
458 struct gpio_chip *chip;
462 txgpio = devm_kzalloc(dev, sizeof(*txgpio), GFP_KERNEL);
466 raw_spin_lock_init(&txgpio->lock);
467 chip = &txgpio->chip;
469 pci_set_drvdata(pdev, txgpio);
471 err = pcim_enable_device(pdev);
473 dev_err(dev, "Failed to enable PCI device: err %d\n", err);
477 err = pcim_iomap_regions(pdev, 1 << 0, KBUILD_MODNAME);
479 dev_err(dev, "Failed to iomap PCI device: err %d\n", err);
483 tbl = pcim_iomap_table(pdev);
484 txgpio->register_base = tbl[0];
485 if (!txgpio->register_base) {
486 dev_err(dev, "Cannot map PCI resource\n");
491 if (pdev->subsystem_device == 0xa10a) {
492 /* CN88XX has no GPIO_CONST register*/
494 txgpio->base_msi = 48;
496 u64 c = readq(txgpio->register_base + GPIO_CONST);
498 ngpio = c & GPIO_CONST_GPIOS_MASK;
499 txgpio->base_msi = (c >> 8) & 0xff;
502 txgpio->msix_entries = devm_kcalloc(dev,
503 ngpio, sizeof(struct msix_entry),
505 if (!txgpio->msix_entries) {
510 txgpio->line_entries = devm_kcalloc(dev,
512 sizeof(struct thunderx_line),
514 if (!txgpio->line_entries) {
519 for (i = 0; i < ngpio; i++) {
520 u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(i));
522 txgpio->msix_entries[i].entry = txgpio->base_msi + (2 * i);
523 txgpio->line_entries[i].line = i;
524 txgpio->line_entries[i].txgpio = txgpio;
526 * If something has already programmed the pin, use
527 * the existing glitch filter settings, otherwise go
530 txgpio->line_entries[i].fil_bits = bit_cfg ?
531 (bit_cfg & GPIO_BIT_CFG_FIL_MASK) : GLITCH_FILTER_400NS;
533 if ((bit_cfg & GPIO_BIT_CFG_TX_OE) && (bit_cfg & GPIO_BIT_CFG_TX_OD))
534 set_bit(i, txgpio->od_mask);
535 if (bit_cfg & GPIO_BIT_CFG_PIN_XOR)
536 set_bit(i, txgpio->invert_mask);
540 /* Enable all MSI-X for interrupts on all possible lines. */
541 err = pci_enable_msix_range(pdev, txgpio->msix_entries, ngpio, ngpio);
546 * Push GPIO specific irqdomain on hierarchy created as a side
547 * effect of the pci_enable_msix()
549 txgpio->irqd = irq_domain_create_hierarchy(irq_get_irq_data(txgpio->msix_entries[0].vector)->domain,
550 0, 0, of_node_to_fwnode(dev->of_node),
551 &thunderx_gpio_irqd_ops, txgpio);
557 /* Push on irq_data and the domain for each line. */
558 for (i = 0; i < ngpio; i++) {
559 err = irq_domain_push_irq(txgpio->irqd,
560 txgpio->msix_entries[i].vector,
561 &txgpio->line_entries[i]);
563 dev_err(dev, "irq_domain_push_irq: %d\n", err);
566 chip->label = KBUILD_MODNAME;
568 chip->owner = THIS_MODULE;
569 chip->request = thunderx_gpio_request;
570 chip->base = -1; /* System allocated */
571 chip->can_sleep = false;
573 chip->get_direction = thunderx_gpio_get_direction;
574 chip->direction_input = thunderx_gpio_dir_in;
575 chip->get = thunderx_gpio_get;
576 chip->direction_output = thunderx_gpio_dir_out;
577 chip->set = thunderx_gpio_set;
578 chip->set_multiple = thunderx_gpio_set_multiple;
579 chip->set_config = thunderx_gpio_set_config;
580 chip->to_irq = thunderx_gpio_to_irq;
581 err = devm_gpiochip_add_data(dev, chip, txgpio);
585 dev_info(dev, "ThunderX GPIO: %d lines with base %d.\n",
589 pci_set_drvdata(pdev, NULL);
593 static void thunderx_gpio_remove(struct pci_dev *pdev)
596 struct thunderx_gpio *txgpio = pci_get_drvdata(pdev);
598 for (i = 0; i < txgpio->chip.ngpio; i++)
599 irq_domain_pop_irq(txgpio->irqd,
600 txgpio->msix_entries[i].vector);
602 irq_domain_remove(txgpio->irqd);
604 pci_set_drvdata(pdev, NULL);
607 static const struct pci_device_id thunderx_gpio_id_table[] = {
608 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xA00A) },
609 { 0, } /* end of table */
612 MODULE_DEVICE_TABLE(pci, thunderx_gpio_id_table);
614 static struct pci_driver thunderx_gpio_driver = {
615 .name = KBUILD_MODNAME,
616 .id_table = thunderx_gpio_id_table,
617 .probe = thunderx_gpio_probe,
618 .remove = thunderx_gpio_remove,
621 module_pci_driver(thunderx_gpio_driver);
623 MODULE_DESCRIPTION("Cavium Inc. ThunderX/OCTEON-TX GPIO Driver");
624 MODULE_LICENSE("GPL");