2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2016, 2017 Cavium Inc.
9 #include <linux/bitops.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17 #include <linux/spinlock.h>
20 #define GPIO_RX_DAT 0x0
21 #define GPIO_TX_SET 0x8
22 #define GPIO_TX_CLR 0x10
23 #define GPIO_CONST 0x90
24 #define GPIO_CONST_GPIOS_MASK 0xff
25 #define GPIO_BIT_CFG 0x400
26 #define GPIO_BIT_CFG_TX_OE BIT(0)
27 #define GPIO_BIT_CFG_PIN_XOR BIT(1)
28 #define GPIO_BIT_CFG_INT_EN BIT(2)
29 #define GPIO_BIT_CFG_INT_TYPE BIT(3)
30 #define GPIO_BIT_CFG_FIL_MASK GENMASK(11, 4)
31 #define GPIO_BIT_CFG_FIL_CNT_SHIFT 4
32 #define GPIO_BIT_CFG_FIL_SEL_SHIFT 8
33 #define GPIO_BIT_CFG_TX_OD BIT(12)
34 #define GPIO_BIT_CFG_PIN_SEL_MASK GENMASK(25, 16)
35 #define GPIO_INTR 0x800
36 #define GPIO_INTR_INTR BIT(0)
37 #define GPIO_INTR_INTR_W1S BIT(1)
38 #define GPIO_INTR_ENA_W1C BIT(2)
39 #define GPIO_INTR_ENA_W1S BIT(3)
40 #define GPIO_2ND_BANK 0x1400
42 #define GLITCH_FILTER_400NS ((4u << GPIO_BIT_CFG_FIL_SEL_SHIFT) | \
43 (9u << GPIO_BIT_CFG_FIL_CNT_SHIFT))
47 struct thunderx_line {
48 struct thunderx_gpio *txgpio;
50 unsigned int fil_bits;
53 struct thunderx_gpio {
54 struct gpio_chip chip;
55 u8 __iomem *register_base;
56 struct msix_entry *msix_entries; /* per line MSI-X */
57 struct thunderx_line *line_entries; /* per line irq info */
59 unsigned long invert_mask[2];
60 unsigned long od_mask[2];
64 static unsigned int bit_cfg_reg(unsigned int line)
66 return 8 * line + GPIO_BIT_CFG;
69 static unsigned int intr_reg(unsigned int line)
71 return 8 * line + GPIO_INTR;
74 static bool thunderx_gpio_is_gpio_nowarn(struct thunderx_gpio *txgpio,
77 u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
79 return (bit_cfg & GPIO_BIT_CFG_PIN_SEL_MASK) == 0;
83 * Check (and WARN) that the pin is available for GPIO. We will not
84 * allow modification of the state of non-GPIO pins from this driver.
86 static bool thunderx_gpio_is_gpio(struct thunderx_gpio *txgpio,
89 bool rv = thunderx_gpio_is_gpio_nowarn(txgpio, line);
91 WARN_RATELIMIT(!rv, "Pin %d not available for GPIO\n", line);
96 static int thunderx_gpio_request(struct gpio_chip *chip, unsigned int line)
98 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
100 return thunderx_gpio_is_gpio(txgpio, line) ? 0 : -EIO;
103 static int thunderx_gpio_dir_in(struct gpio_chip *chip, unsigned int line)
105 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
107 if (!thunderx_gpio_is_gpio(txgpio, line))
110 raw_spin_lock(&txgpio->lock);
111 clear_bit(line, txgpio->invert_mask);
112 clear_bit(line, txgpio->od_mask);
113 writeq(txgpio->line_entries[line].fil_bits,
114 txgpio->register_base + bit_cfg_reg(line));
115 raw_spin_unlock(&txgpio->lock);
119 static void thunderx_gpio_set(struct gpio_chip *chip, unsigned int line,
122 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
123 int bank = line / 64;
124 int bank_bit = line % 64;
126 void __iomem *reg = txgpio->register_base +
127 (bank * GPIO_2ND_BANK) + (value ? GPIO_TX_SET : GPIO_TX_CLR);
129 writeq(BIT_ULL(bank_bit), reg);
132 static int thunderx_gpio_dir_out(struct gpio_chip *chip, unsigned int line,
135 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
136 u64 bit_cfg = txgpio->line_entries[line].fil_bits | GPIO_BIT_CFG_TX_OE;
138 if (!thunderx_gpio_is_gpio(txgpio, line))
141 raw_spin_lock(&txgpio->lock);
143 thunderx_gpio_set(chip, line, value);
145 if (test_bit(line, txgpio->invert_mask))
146 bit_cfg |= GPIO_BIT_CFG_PIN_XOR;
148 if (test_bit(line, txgpio->od_mask))
149 bit_cfg |= GPIO_BIT_CFG_TX_OD;
151 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
153 raw_spin_unlock(&txgpio->lock);
157 static int thunderx_gpio_get_direction(struct gpio_chip *chip, unsigned int line)
159 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
162 if (!thunderx_gpio_is_gpio_nowarn(txgpio, line))
164 * Say it is input for now to avoid WARNing on
165 * gpiochip_add_data(). We will WARN if someone
166 * requests it or tries to use it.
170 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
172 if (bit_cfg & GPIO_BIT_CFG_TX_OE)
173 return GPIO_LINE_DIRECTION_OUT;
175 return GPIO_LINE_DIRECTION_IN;
178 static int thunderx_gpio_set_config(struct gpio_chip *chip,
182 bool orig_invert, orig_od, orig_dat, new_invert, new_od;
185 int bank = line / 64;
186 int bank_bit = line % 64;
188 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
189 void __iomem *reg = txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET;
191 if (!thunderx_gpio_is_gpio(txgpio, line))
194 raw_spin_lock(&txgpio->lock);
195 orig_invert = test_bit(line, txgpio->invert_mask);
196 new_invert = orig_invert;
197 orig_od = test_bit(line, txgpio->od_mask);
199 orig_dat = ((readq(reg) >> bank_bit) & 1) ^ orig_invert;
200 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
201 switch (pinconf_to_config_param(cfg)) {
202 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
204 * Weird, setting open-drain mode causes signal
205 * inversion. Note this so we can compensate in the
208 set_bit(line, txgpio->invert_mask);
210 set_bit(line, txgpio->od_mask);
214 case PIN_CONFIG_DRIVE_PUSH_PULL:
215 clear_bit(line, txgpio->invert_mask);
217 clear_bit(line, txgpio->od_mask);
221 case PIN_CONFIG_INPUT_DEBOUNCE:
222 arg = pinconf_to_config_argument(cfg);
223 if (arg > 1228) { /* 15 * 2^15 * 2.5nS maximum */
227 arg *= 400; /* scale to 2.5nS clocks. */
231 arg++; /* always round up */
234 txgpio->line_entries[line].fil_bits =
235 (sel << GPIO_BIT_CFG_FIL_SEL_SHIFT) |
236 (arg << GPIO_BIT_CFG_FIL_CNT_SHIFT);
237 bit_cfg &= ~GPIO_BIT_CFG_FIL_MASK;
238 bit_cfg |= txgpio->line_entries[line].fil_bits;
239 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
245 raw_spin_unlock(&txgpio->lock);
248 * If currently output and OPEN_DRAIN changed, install the new
251 if ((new_invert != orig_invert || new_od != orig_od) &&
252 (bit_cfg & GPIO_BIT_CFG_TX_OE))
253 ret = thunderx_gpio_dir_out(chip, line, orig_dat ^ new_invert);
258 static int thunderx_gpio_get(struct gpio_chip *chip, unsigned int line)
260 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
261 int bank = line / 64;
262 int bank_bit = line % 64;
263 u64 read_bits = readq(txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_RX_DAT);
264 u64 masked_bits = read_bits & BIT_ULL(bank_bit);
266 if (test_bit(line, txgpio->invert_mask))
267 return masked_bits == 0;
269 return masked_bits != 0;
272 static void thunderx_gpio_set_multiple(struct gpio_chip *chip,
277 u64 set_bits, clear_bits;
278 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
280 for (bank = 0; bank <= chip->ngpio / 64; bank++) {
281 set_bits = bits[bank] & mask[bank];
282 clear_bits = ~bits[bank] & mask[bank];
283 writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET);
284 writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR);
288 static void thunderx_gpio_irq_ack(struct irq_data *d)
290 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
291 struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
293 writeq(GPIO_INTR_INTR,
294 txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
297 static void thunderx_gpio_irq_mask(struct irq_data *d)
299 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
300 struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
302 writeq(GPIO_INTR_ENA_W1C,
303 txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
306 static void thunderx_gpio_irq_mask_ack(struct irq_data *d)
308 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
309 struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
311 writeq(GPIO_INTR_ENA_W1C | GPIO_INTR_INTR,
312 txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
315 static void thunderx_gpio_irq_unmask(struct irq_data *d)
317 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
318 struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
320 writeq(GPIO_INTR_ENA_W1S,
321 txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
324 static int thunderx_gpio_irq_set_type(struct irq_data *d,
325 unsigned int flow_type)
327 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
328 struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
329 struct thunderx_line *txline =
330 &txgpio->line_entries[irqd_to_hwirq(d)];
333 irqd_set_trigger_type(d, flow_type);
335 bit_cfg = txline->fil_bits | GPIO_BIT_CFG_INT_EN;
337 if (flow_type & IRQ_TYPE_EDGE_BOTH) {
338 irq_set_handler_locked(d, handle_fasteoi_ack_irq);
339 bit_cfg |= GPIO_BIT_CFG_INT_TYPE;
341 irq_set_handler_locked(d, handle_fasteoi_mask_irq);
344 raw_spin_lock(&txgpio->lock);
345 if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)) {
346 bit_cfg |= GPIO_BIT_CFG_PIN_XOR;
347 set_bit(txline->line, txgpio->invert_mask);
349 clear_bit(txline->line, txgpio->invert_mask);
351 clear_bit(txline->line, txgpio->od_mask);
352 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(txline->line));
353 raw_spin_unlock(&txgpio->lock);
355 return IRQ_SET_MASK_OK;
358 static void thunderx_gpio_irq_enable(struct irq_data *data)
360 irq_chip_enable_parent(data);
361 thunderx_gpio_irq_unmask(data);
364 static void thunderx_gpio_irq_disable(struct irq_data *data)
366 thunderx_gpio_irq_mask(data);
367 irq_chip_disable_parent(data);
371 * Interrupts are chained from underlying MSI-X vectors. We have
372 * these irq_chip functions to be able to handle level triggering
373 * semantics and other acknowledgment tasks associated with the GPIO
376 static struct irq_chip thunderx_gpio_irq_chip = {
378 .irq_enable = thunderx_gpio_irq_enable,
379 .irq_disable = thunderx_gpio_irq_disable,
380 .irq_ack = thunderx_gpio_irq_ack,
381 .irq_mask = thunderx_gpio_irq_mask,
382 .irq_mask_ack = thunderx_gpio_irq_mask_ack,
383 .irq_unmask = thunderx_gpio_irq_unmask,
384 .irq_eoi = irq_chip_eoi_parent,
385 .irq_set_affinity = irq_chip_set_affinity_parent,
386 .irq_set_type = thunderx_gpio_irq_set_type,
388 .flags = IRQCHIP_SET_TYPE_MASKED
391 static int thunderx_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
393 unsigned int child_type,
394 unsigned int *parent,
395 unsigned int *parent_type)
397 struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
399 *parent = txgpio->base_msi + (2 * child);
400 *parent_type = IRQ_TYPE_LEVEL_HIGH;
404 static int thunderx_gpio_probe(struct pci_dev *pdev,
405 const struct pci_device_id *id)
407 void __iomem * const *tbl;
408 struct device *dev = &pdev->dev;
409 struct thunderx_gpio *txgpio;
410 struct gpio_chip *chip;
411 struct gpio_irq_chip *girq;
415 txgpio = devm_kzalloc(dev, sizeof(*txgpio), GFP_KERNEL);
419 raw_spin_lock_init(&txgpio->lock);
420 chip = &txgpio->chip;
422 pci_set_drvdata(pdev, txgpio);
424 err = pcim_enable_device(pdev);
426 dev_err(dev, "Failed to enable PCI device: err %d\n", err);
430 err = pcim_iomap_regions(pdev, 1 << 0, KBUILD_MODNAME);
432 dev_err(dev, "Failed to iomap PCI device: err %d\n", err);
436 tbl = pcim_iomap_table(pdev);
437 txgpio->register_base = tbl[0];
438 if (!txgpio->register_base) {
439 dev_err(dev, "Cannot map PCI resource\n");
444 if (pdev->subsystem_device == 0xa10a) {
445 /* CN88XX has no GPIO_CONST register*/
447 txgpio->base_msi = 48;
449 u64 c = readq(txgpio->register_base + GPIO_CONST);
451 ngpio = c & GPIO_CONST_GPIOS_MASK;
452 txgpio->base_msi = (c >> 8) & 0xff;
455 txgpio->msix_entries = devm_kcalloc(dev,
456 ngpio, sizeof(struct msix_entry),
458 if (!txgpio->msix_entries) {
463 txgpio->line_entries = devm_kcalloc(dev,
465 sizeof(struct thunderx_line),
467 if (!txgpio->line_entries) {
472 for (i = 0; i < ngpio; i++) {
473 u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(i));
475 txgpio->msix_entries[i].entry = txgpio->base_msi + (2 * i);
476 txgpio->line_entries[i].line = i;
477 txgpio->line_entries[i].txgpio = txgpio;
479 * If something has already programmed the pin, use
480 * the existing glitch filter settings, otherwise go
483 txgpio->line_entries[i].fil_bits = bit_cfg ?
484 (bit_cfg & GPIO_BIT_CFG_FIL_MASK) : GLITCH_FILTER_400NS;
486 if ((bit_cfg & GPIO_BIT_CFG_TX_OE) && (bit_cfg & GPIO_BIT_CFG_TX_OD))
487 set_bit(i, txgpio->od_mask);
488 if (bit_cfg & GPIO_BIT_CFG_PIN_XOR)
489 set_bit(i, txgpio->invert_mask);
493 /* Enable all MSI-X for interrupts on all possible lines. */
494 err = pci_enable_msix_range(pdev, txgpio->msix_entries, ngpio, ngpio);
498 chip->label = KBUILD_MODNAME;
500 chip->owner = THIS_MODULE;
501 chip->request = thunderx_gpio_request;
502 chip->base = -1; /* System allocated */
503 chip->can_sleep = false;
505 chip->get_direction = thunderx_gpio_get_direction;
506 chip->direction_input = thunderx_gpio_dir_in;
507 chip->get = thunderx_gpio_get;
508 chip->direction_output = thunderx_gpio_dir_out;
509 chip->set = thunderx_gpio_set;
510 chip->set_multiple = thunderx_gpio_set_multiple;
511 chip->set_config = thunderx_gpio_set_config;
513 girq->chip = &thunderx_gpio_irq_chip;
514 girq->fwnode = of_node_to_fwnode(dev->of_node);
515 girq->parent_domain =
516 irq_get_irq_data(txgpio->msix_entries[0].vector)->domain;
517 girq->child_to_parent_hwirq = thunderx_gpio_child_to_parent_hwirq;
518 girq->handler = handle_bad_irq;
519 girq->default_type = IRQ_TYPE_NONE;
521 err = devm_gpiochip_add_data(dev, chip, txgpio);
525 /* Push on irq_data and the domain for each line. */
526 for (i = 0; i < ngpio; i++) {
527 err = irq_domain_push_irq(chip->irq.domain,
528 txgpio->msix_entries[i].vector,
531 dev_err(dev, "irq_domain_push_irq: %d\n", err);
534 dev_info(dev, "ThunderX GPIO: %d lines with base %d.\n",
538 pci_set_drvdata(pdev, NULL);
542 static void thunderx_gpio_remove(struct pci_dev *pdev)
545 struct thunderx_gpio *txgpio = pci_get_drvdata(pdev);
547 for (i = 0; i < txgpio->chip.ngpio; i++)
548 irq_domain_pop_irq(txgpio->chip.irq.domain,
549 txgpio->msix_entries[i].vector);
551 irq_domain_remove(txgpio->chip.irq.domain);
553 pci_set_drvdata(pdev, NULL);
556 static const struct pci_device_id thunderx_gpio_id_table[] = {
557 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xA00A) },
558 { 0, } /* end of table */
561 MODULE_DEVICE_TABLE(pci, thunderx_gpio_id_table);
563 static struct pci_driver thunderx_gpio_driver = {
564 .name = KBUILD_MODNAME,
565 .id_table = thunderx_gpio_id_table,
566 .probe = thunderx_gpio_probe,
567 .remove = thunderx_gpio_remove,
570 module_pci_driver(thunderx_gpio_driver);
572 MODULE_DESCRIPTION("Cavium Inc. ThunderX/OCTEON-TX GPIO Driver");
573 MODULE_LICENSE("GPL");