drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "amdgpu_amdkfd.h"
  24 #include "amd_shared.h"
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_gfx.h"
  28 #include <linux/module.h>
  29
  30 const struct kgd2kfd_calls *kgd2kfd;
  31 bool (*kgd2kfd_init_p)(unsigned int, const struct kgd2kfd_calls**);
  32
  33 static const unsigned int compute_vmid_bitmap = 0xFF00;
  34
  35 int amdgpu_amdkfd_init(void)
  36 {
  37         int ret;
  38
  39 #if defined(CONFIG_HSA_AMD_MODULE)
  40         int (*kgd2kfd_init_p)(unsigned int, const struct kgd2kfd_calls**);
  41
  42         kgd2kfd_init_p = symbol_request(kgd2kfd_init);
  43
  44         if (kgd2kfd_init_p == NULL)
  45                 return -ENOENT;
  46
  47         ret = kgd2kfd_init_p(KFD_INTERFACE_VERSION, &kgd2kfd);
  48         if (ret) {
  49                 symbol_put(kgd2kfd_init);
  50                 kgd2kfd = NULL;
  51         }
  52
  53
  54 #elif defined(CONFIG_HSA_AMD)
  55
  56         ret = kgd2kfd_init(KFD_INTERFACE_VERSION, &kgd2kfd);
  57         if (ret)
  58                 kgd2kfd = NULL;
  59
  60 #else
  61         kgd2kfd = NULL;
  62         ret = -ENOENT;
  63 #endif
  64
  65 #if defined(CONFIG_HSA_AMD_MODULE) || defined(CONFIG_HSA_AMD)
  66         amdgpu_amdkfd_gpuvm_init_mem_limits();
  67 #endif
  68
  69         return ret;
  70 }
  71
  72 void amdgpu_amdkfd_fini(void)
  73 {
  74         if (kgd2kfd) {
  75                 kgd2kfd->exit();
  76                 symbol_put(kgd2kfd_init);
  77         }
  78 }
  79
  80 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
  81 {
  82         const struct kfd2kgd_calls *kfd2kgd;
  83
  84         if (!kgd2kfd)
  85                 return;
  86
  87         switch (adev->asic_type) {
  88 #ifdef CONFIG_DRM_AMDGPU_CIK
  89         case CHIP_KAVERI:
  90         case CHIP_HAWAII:
  91                 kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions();
  92                 break;
  93 #endif
  94         case CHIP_CARRIZO:
  95         case CHIP_TONGA:
  96         case CHIP_FIJI:
  97         case CHIP_POLARIS10:
  98         case CHIP_POLARIS11:
  99                 kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
 100                 break;
 101         case CHIP_VEGA10:
 102         case CHIP_RAVEN:
 103                 kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions();
 104                 break;
 105         default:
 106                 dev_info(adev->dev, "kfd not supported on this ASIC\n");
 107                 return;
 108         }
 109
 110         adev->kfd = kgd2kfd->probe((struct kgd_dev *)adev,
 111                                    adev->pdev, kfd2kgd);
 112 }
 113
 114 /**
 115  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
 116  *                                setup amdkfd
 117  *
 118  * @adev: amdgpu_device pointer
 119  * @aperture_base: output returning doorbell aperture base physical address
 120  * @aperture_size: output returning doorbell aperture size in bytes
 121  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
 122  *
 123  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
 124  * takes doorbells required for its own rings and reports the setup to amdkfd.
 125  * amdgpu reserved doorbells are at the start of the doorbell aperture.
 126  */
 127 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
 128                                          phys_addr_t *aperture_base,
 129                                          size_t *aperture_size,
 130                                          size_t *start_offset)
 131 {
 132         /*
 133          * The first num_doorbells are used by amdgpu.
 134          * amdkfd takes whatever's left in the aperture.
 135          */
 136         if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
 137                 *aperture_base = adev->doorbell.base;
 138                 *aperture_size = adev->doorbell.size;
 139                 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
 140         } else {
 141                 *aperture_base = 0;
 142                 *aperture_size = 0;
 143                 *start_offset = 0;
 144         }
 145 }
 146
 147 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
 148 {
 149         int i;
 150         int last_valid_bit;
 151         if (adev->kfd) {
 152                 struct kgd2kfd_shared_resources gpu_resources = {
 153                         .compute_vmid_bitmap = compute_vmid_bitmap,
 154                         .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
 155                         .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
 156                         .gpuvm_size = min(adev->vm_manager.max_pfn
 157                                           << AMDGPU_GPU_PAGE_SHIFT,
 158                                           AMDGPU_VA_HOLE_START),
 159                         .drm_render_minor = adev->ddev->render->index
 160                 };
 161
 162                 /* this is going to have a few of the MSBs set that we need to
 163                  * clear */
 164                 bitmap_complement(gpu_resources.queue_bitmap,
 165                                   adev->gfx.mec.queue_bitmap,
 166                                   KGD_MAX_QUEUES);
 167
 168                 /* remove the KIQ bit as well */
 169                 if (adev->gfx.kiq.ring.ready)
 170                         clear_bit(amdgpu_gfx_queue_to_bit(adev,
 171                                                           adev->gfx.kiq.ring.me - 1,
 172                                                           adev->gfx.kiq.ring.pipe,
 173                                                           adev->gfx.kiq.ring.queue),
 174                                   gpu_resources.queue_bitmap);
 175
 176                 /* According to linux/bitmap.h we shouldn't use bitmap_clear if
 177                  * nbits is not compile time constant */
 178                 last_valid_bit = 1 /* only first MEC can have compute queues */
 179                                 * adev->gfx.mec.num_pipe_per_mec
 180                                 * adev->gfx.mec.num_queue_per_pipe;
 181                 for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
 182                         clear_bit(i, gpu_resources.queue_bitmap);
 183
 184                 amdgpu_doorbell_get_kfd_info(adev,
 185                                 &gpu_resources.doorbell_physical_address,
 186                                 &gpu_resources.doorbell_aperture_size,
 187                                 &gpu_resources.doorbell_start_offset);
 188                 if (adev->asic_type >= CHIP_VEGA10) {
 189                         /* On SOC15 the BIF is involved in routing
 190                          * doorbells using the low 12 bits of the
 191                          * address. Communicate the assignments to
 192                          * KFD. KFD uses two doorbell pages per
 193                          * process in case of 64-bit doorbells so we
 194                          * can use each doorbell assignment twice.
 195                          */
 196                         gpu_resources.sdma_doorbell[0][0] =
 197                                 AMDGPU_DOORBELL64_sDMA_ENGINE0;
 198                         gpu_resources.sdma_doorbell[0][1] =
 199                                 AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200;
 200                         gpu_resources.sdma_doorbell[1][0] =
 201                                 AMDGPU_DOORBELL64_sDMA_ENGINE1;
 202                         gpu_resources.sdma_doorbell[1][1] =
 203                                 AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200;
 204                         /* Doorbells 0x0f0-0ff and 0x2f0-2ff are reserved for
 205                          * SDMA, IH and VCN. So don't use them for the CP.
 206                          */
 207                         gpu_resources.reserved_doorbell_mask = 0x1f0;
 208                         gpu_resources.reserved_doorbell_val  = 0x0f0;
 209                 }
 210
 211                 kgd2kfd->device_init(adev->kfd, &gpu_resources);
 212         }
 213 }
 214
 215 void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)
 216 {
 217         if (adev->kfd) {
 218                 kgd2kfd->device_exit(adev->kfd);
 219                 adev->kfd = NULL;
 220         }
 221 }
 222
 223 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
 224                 const void *ih_ring_entry)
 225 {
 226         if (adev->kfd)
 227                 kgd2kfd->interrupt(adev->kfd, ih_ring_entry);
 228 }
 229
 230 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev)
 231 {
 232         if (adev->kfd)
 233                 kgd2kfd->suspend(adev->kfd);
 234 }
 235
 236 int amdgpu_amdkfd_resume(struct amdgpu_device *adev)
 237 {
 238         int r = 0;
 239
 240         if (adev->kfd)
 241                 r = kgd2kfd->resume(adev->kfd);
 242
 243         return r;
 244 }
 245
 246 int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
 247                         void **mem_obj, uint64_t *gpu_addr,
 248                         void **cpu_ptr)
 249 {
 250         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 251         struct amdgpu_bo *bo = NULL;
 252         struct amdgpu_bo_param bp;
 253         int r;
 254         uint64_t gpu_addr_tmp = 0;
 255         void *cpu_ptr_tmp = NULL;
 256
 257         memset(&bp, 0, sizeof(bp));
 258         bp.size = size;
 259         bp.byte_align = PAGE_SIZE;
 260         bp.domain = AMDGPU_GEM_DOMAIN_GTT;
 261         bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 262         bp.type = ttm_bo_type_kernel;
 263         bp.resv = NULL;
 264         r = amdgpu_bo_create(adev, &bp, &bo);
 265         if (r) {
 266                 dev_err(adev->dev,
 267                         "failed to allocate BO for amdkfd (%d)\n", r);
 268                 return r;
 269         }
 270
 271         /* map the buffer */
 272         r = amdgpu_bo_reserve(bo, true);
 273         if (r) {
 274                 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
 275                 goto allocate_mem_reserve_bo_failed;
 276         }
 277
 278         r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT,
 279                                 &gpu_addr_tmp);
 280         if (r) {
 281                 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
 282                 goto allocate_mem_pin_bo_failed;
 283         }
 284
 285         r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
 286         if (r) {
 287                 dev_err(adev->dev,
 288                         "(%d) failed to map bo to kernel for amdkfd\n", r);
 289                 goto allocate_mem_kmap_bo_failed;
 290         }
 291
 292         *mem_obj = bo;
 293         *gpu_addr = gpu_addr_tmp;
 294         *cpu_ptr = cpu_ptr_tmp;
 295
 296         amdgpu_bo_unreserve(bo);
 297
 298         return 0;
 299
 300 allocate_mem_kmap_bo_failed:
 301         amdgpu_bo_unpin(bo);
 302 allocate_mem_pin_bo_failed:
 303         amdgpu_bo_unreserve(bo);
 304 allocate_mem_reserve_bo_failed:
 305         amdgpu_bo_unref(&bo);
 306
 307         return r;
 308 }
 309
 310 void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
 311 {
 312         struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj;
 313
 314         amdgpu_bo_reserve(bo, true);
 315         amdgpu_bo_kunmap(bo);
 316         amdgpu_bo_unpin(bo);
 317         amdgpu_bo_unreserve(bo);
 318         amdgpu_bo_unref(&(bo));
 319 }
 320
 321 void get_local_mem_info(struct kgd_dev *kgd,
 322                         struct kfd_local_mem_info *mem_info)
 323 {
 324         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 325         uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask :
 326                                              ~((1ULL << 32) - 1);
 327         resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size;
 328
 329         memset(mem_info, 0, sizeof(*mem_info));
 330         if (!(adev->gmc.aper_base & address_mask || aper_limit & address_mask)) {
 331                 mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
 332                 mem_info->local_mem_size_private = adev->gmc.real_vram_size -
 333                                 adev->gmc.visible_vram_size;
 334         } else {
 335                 mem_info->local_mem_size_public = 0;
 336                 mem_info->local_mem_size_private = adev->gmc.real_vram_size;
 337         }
 338         mem_info->vram_width = adev->gmc.vram_width;
 339
 340         pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n",
 341                         &adev->gmc.aper_base, &aper_limit,
 342                         mem_info->local_mem_size_public,
 343                         mem_info->local_mem_size_private);
 344
 345         if (amdgpu_sriov_vf(adev))
 346                 mem_info->mem_clk_max = adev->clock.default_mclk / 100;
 347         else if (adev->powerplay.pp_funcs)
 348                 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
 349         else
 350                 mem_info->mem_clk_max = 100;
 351 }
 352
 353 uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
 354 {
 355         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 356
 357         if (adev->gfx.funcs->get_gpu_clock_counter)
 358                 return adev->gfx.funcs->get_gpu_clock_counter(adev);
 359         return 0;
 360 }
 361
 362 uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
 363 {
 364         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 365
 366         /* the sclk is in quantas of 10kHz */
 367         if (amdgpu_sriov_vf(adev))
 368                 return adev->clock.default_sclk / 100;
 369         else if (adev->powerplay.pp_funcs)
 370                 return amdgpu_dpm_get_sclk(adev, false) / 100;
 371         else
 372                 return 100;
 373 }
 374
 375 void get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info)
 376 {
 377         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 378         struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
 379
 380         memset(cu_info, 0, sizeof(*cu_info));
 381         if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
 382                 return;
 383
 384         cu_info->cu_active_number = acu_info.number;
 385         cu_info->cu_ao_mask = acu_info.ao_cu_mask;
 386         memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
 387                sizeof(acu_info.bitmap));
 388         cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 389         cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 390         cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 391         cu_info->simd_per_cu = acu_info.simd_per_cu;
 392         cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
 393         cu_info->wave_front_size = acu_info.wave_front_size;
 394         cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
 395         cu_info->lds_size = acu_info.lds_size;
 396 }
 397
 398 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd)
 399 {
 400         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 401
 402         return amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 403 }
 404
 405 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
 406                                 uint32_t vmid, uint64_t gpu_addr,
 407                                 uint32_t *ib_cmd, uint32_t ib_len)
 408 {
 409         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 410         struct amdgpu_job *job;
 411         struct amdgpu_ib *ib;
 412         struct amdgpu_ring *ring;
 413         struct dma_fence *f = NULL;
 414         int ret;
 415
 416         switch (engine) {
 417         case KGD_ENGINE_MEC1:
 418                 ring = &adev->gfx.compute_ring[0];
 419                 break;
 420         case KGD_ENGINE_SDMA1:
 421                 ring = &adev->sdma.instance[0].ring;
 422                 break;
 423         case KGD_ENGINE_SDMA2:
 424                 ring = &adev->sdma.instance[1].ring;
 425                 break;
 426         default:
 427                 pr_err("Invalid engine in IB submission: %d\n", engine);
 428                 ret = -EINVAL;
 429                 goto err;
 430         }
 431
 432         ret = amdgpu_job_alloc(adev, 1, &job, NULL);
 433         if (ret)
 434                 goto err;
 435
 436         ib = &job->ibs[0];
 437         memset(ib, 0, sizeof(struct amdgpu_ib));
 438
 439         ib->gpu_addr = gpu_addr;
 440         ib->ptr = ib_cmd;
 441         ib->length_dw = ib_len;
 442         /* This works for NO_HWS. TODO: need to handle without knowing VMID */
 443         job->vmid = vmid;
 444
 445         ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
 446         if (ret) {
 447                 DRM_ERROR("amdgpu: failed to schedule IB.\n");
 448                 goto err_ib_sched;
 449         }
 450
 451         ret = dma_fence_wait(f, false);
 452
 453 err_ib_sched:
 454         dma_fence_put(f);
 455         amdgpu_job_free(job);
 456 err:
 457         return ret;
 458 }
 459
 460 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
 461 {
 462         if (adev->kfd) {
 463                 if ((1 << vmid) & compute_vmid_bitmap)
 464                         return true;
 465         }
 466
 467         return false;
 468 }
 469
 470 #if !defined(CONFIG_HSA_AMD_MODULE) && !defined(CONFIG_HSA_AMD)
 471 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
 472 {
 473         return false;
 474 }
 475
 476 void amdgpu_amdkfd_unreserve_system_memory_limit(struct amdgpu_bo *bo)
 477 {
 478 }
 479
 480 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
 481                                         struct amdgpu_vm *vm)
 482 {
 483 }
 484
 485 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
 486 {
 487         return NULL;
 488 }
 489
 490 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm)
 491 {
 492         return 0;
 493 }
 494
 495 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
 496 {
 497         return NULL;
 498 }
 499
 500 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
 501 {
 502         return NULL;
 503 }
 504
 505 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)
 506 {
 507         return NULL;
 508 }
 509 #endif