drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/fdtable.h>
  25 #include <linux/uaccess.h>
  26 #include <linux/firmware.h>
  27 #include <drm/drmP.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_amdkfd.h"
  30 #include "amdgpu_ucode.h"
  31 #include "gfx_v8_0.h"
  32 #include "gca/gfx_8_0_sh_mask.h"
  33 #include "gca/gfx_8_0_d.h"
  34 #include "gca/gfx_8_0_enum.h"
  35 #include "oss/oss_3_0_sh_mask.h"
  36 #include "oss/oss_3_0_d.h"
  37 #include "gmc/gmc_8_1_sh_mask.h"
  38 #include "gmc/gmc_8_1_d.h"
  39 #include "vi_structs.h"
  40 #include "vid.h"
  41
  42 enum hqd_dequeue_request_type {
  43         NO_ACTION = 0,
  44         DRAIN_PIPE,
  45         RESET_WAVES
  46 };
  47
  48 struct vi_sdma_mqd;
  49
  50 /*
  51  * Register access functions
  52  */
  53
  54 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
  55                 uint32_t sh_mem_config,
  56                 uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,
  57                 uint32_t sh_mem_bases);
  58 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
  59                 unsigned int vmid);
  60 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
  61                 uint32_t hpd_size, uint64_t hpd_gpu_addr);
  62 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
  63 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
  64                         uint32_t queue_id, uint32_t __user *wptr,
  65                         uint32_t wptr_shift, uint32_t wptr_mask,
  66                         struct mm_struct *mm);
  67 static int kgd_hqd_dump(struct kgd_dev *kgd,
  68                         uint32_t pipe_id, uint32_t queue_id,
  69                         uint32_t (**dump)[2], uint32_t *n_regs);
  70 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
  71                              uint32_t __user *wptr, struct mm_struct *mm);
  72 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
  73                              uint32_t engine_id, uint32_t queue_id,
  74                              uint32_t (**dump)[2], uint32_t *n_regs);
  75 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
  76                 uint32_t pipe_id, uint32_t queue_id);
  77 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
  78 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
  79                                 enum kfd_preempt_type reset_type,
  80                                 unsigned int utimeout, uint32_t pipe_id,
  81                                 uint32_t queue_id);
  82 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
  83                                 unsigned int utimeout);
  84 static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid);
  85 static int kgd_address_watch_disable(struct kgd_dev *kgd);
  86 static int kgd_address_watch_execute(struct kgd_dev *kgd,
  87                                         unsigned int watch_point_id,
  88                                         uint32_t cntl_val,
  89                                         uint32_t addr_hi,
  90                                         uint32_t addr_lo);
  91 static int kgd_wave_control_execute(struct kgd_dev *kgd,
  92                                         uint32_t gfx_index_val,
  93                                         uint32_t sq_cmd);
  94 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
  95                                         unsigned int watch_point_id,
  96                                         unsigned int reg_offset);
  97
  98 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
  99                 uint8_t vmid);
 100 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
 101                 uint8_t vmid);
 102 static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid);
 103 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
 104 static void set_scratch_backing_va(struct kgd_dev *kgd,
 105                                         uint64_t va, uint32_t vmid);
 106
 107 /* Because of REG_GET_FIELD() being used, we put this function in the
 108  * asic specific file.
 109  */
 110 static int get_tile_config(struct kgd_dev *kgd,
 111                 struct tile_config *config)
 112 {
 113         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 114
 115         config->gb_addr_config = adev->gfx.config.gb_addr_config;
 116         config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
 117                                 MC_ARB_RAMCFG, NOOFBANK);
 118         config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
 119                                 MC_ARB_RAMCFG, NOOFRANKS);
 120
 121         config->tile_config_ptr = adev->gfx.config.tile_mode_array;
 122         config->num_tile_configs =
 123                         ARRAY_SIZE(adev->gfx.config.tile_mode_array);
 124         config->macro_tile_config_ptr =
 125                         adev->gfx.config.macrotile_mode_array;
 126         config->num_macro_tile_configs =
 127                         ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
 128
 129         return 0;
 130 }
 131
 132 static const struct kfd2kgd_calls kfd2kgd = {
 133         .init_gtt_mem_allocation = alloc_gtt_mem,
 134         .free_gtt_mem = free_gtt_mem,
 135         .get_local_mem_info = get_local_mem_info,
 136         .get_gpu_clock_counter = get_gpu_clock_counter,
 137         .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
 138         .alloc_pasid = amdgpu_vm_alloc_pasid,
 139         .free_pasid = amdgpu_vm_free_pasid,
 140         .program_sh_mem_settings = kgd_program_sh_mem_settings,
 141         .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
 142         .init_pipeline = kgd_init_pipeline,
 143         .init_interrupts = kgd_init_interrupts,
 144         .hqd_load = kgd_hqd_load,
 145         .hqd_sdma_load = kgd_hqd_sdma_load,
 146         .hqd_dump = kgd_hqd_dump,
 147         .hqd_sdma_dump = kgd_hqd_sdma_dump,
 148         .hqd_is_occupied = kgd_hqd_is_occupied,
 149         .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
 150         .hqd_destroy = kgd_hqd_destroy,
 151         .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
 152         .address_watch_disable = kgd_address_watch_disable,
 153         .address_watch_execute = kgd_address_watch_execute,
 154         .wave_control_execute = kgd_wave_control_execute,
 155         .address_watch_get_offset = kgd_address_watch_get_offset,
 156         .get_atc_vmid_pasid_mapping_pasid =
 157                         get_atc_vmid_pasid_mapping_pasid,
 158         .get_atc_vmid_pasid_mapping_valid =
 159                         get_atc_vmid_pasid_mapping_valid,
 160         .write_vmid_invalidate_request = write_vmid_invalidate_request,
 161         .get_fw_version = get_fw_version,
 162         .set_scratch_backing_va = set_scratch_backing_va,
 163         .get_tile_config = get_tile_config,
 164         .get_cu_info = get_cu_info
 165 };
 166
 167 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
 168 {
 169         return (struct kfd2kgd_calls *)&kfd2kgd;
 170 }
 171
 172 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
 173 {
 174         return (struct amdgpu_device *)kgd;
 175 }
 176
 177 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
 178                         uint32_t queue, uint32_t vmid)
 179 {
 180         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 181         uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
 182
 183         mutex_lock(&adev->srbm_mutex);
 184         WREG32(mmSRBM_GFX_CNTL, value);
 185 }
 186
 187 static void unlock_srbm(struct kgd_dev *kgd)
 188 {
 189         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 190
 191         WREG32(mmSRBM_GFX_CNTL, 0);
 192         mutex_unlock(&adev->srbm_mutex);
 193 }
 194
 195 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
 196                                 uint32_t queue_id)
 197 {
 198         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 199
 200         uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
 201         uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 202
 203         lock_srbm(kgd, mec, pipe, queue_id, 0);
 204 }
 205
 206 static void release_queue(struct kgd_dev *kgd)
 207 {
 208         unlock_srbm(kgd);
 209 }
 210
 211 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
 212                                         uint32_t sh_mem_config,
 213                                         uint32_t sh_mem_ape1_base,
 214                                         uint32_t sh_mem_ape1_limit,
 215                                         uint32_t sh_mem_bases)
 216 {
 217         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 218
 219         lock_srbm(kgd, 0, 0, 0, vmid);
 220
 221         WREG32(mmSH_MEM_CONFIG, sh_mem_config);
 222         WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
 223         WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
 224         WREG32(mmSH_MEM_BASES, sh_mem_bases);
 225
 226         unlock_srbm(kgd);
 227 }
 228
 229 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
 230                                         unsigned int vmid)
 231 {
 232         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 233
 234         /*
 235          * We have to assume that there is no outstanding mapping.
 236          * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
 237          * a mapping is in progress or because a mapping finished
 238          * and the SW cleared it.
 239          * So the protocol is to always wait & clear.
 240          */
 241         uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
 242                         ATC_VMID0_PASID_MAPPING__VALID_MASK;
 243
 244         WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
 245
 246         while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
 247                 cpu_relax();
 248         WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
 249
 250         /* Mapping vmid to pasid also for IH block */
 251         WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
 252
 253         return 0;
 254 }
 255
 256 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
 257                                 uint32_t hpd_size, uint64_t hpd_gpu_addr)
 258 {
 259         /* amdgpu owns the per-pipe state */
 260         return 0;
 261 }
 262
 263 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
 264 {
 265         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 266         uint32_t mec;
 267         uint32_t pipe;
 268
 269         mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
 270         pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 271
 272         lock_srbm(kgd, mec, pipe, 0, 0);
 273
 274         WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK);
 275
 276         unlock_srbm(kgd);
 277
 278         return 0;
 279 }
 280
 281 static inline uint32_t get_sdma_base_addr(struct vi_sdma_mqd *m)
 282 {
 283         uint32_t retval;
 284
 285         retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
 286                 m->sdma_queue_id * KFD_VI_SDMA_QUEUE_OFFSET;
 287         pr_debug("kfd: sdma base address: 0x%x\n", retval);
 288
 289         return retval;
 290 }
 291
 292 static inline struct vi_mqd *get_mqd(void *mqd)
 293 {
 294         return (struct vi_mqd *)mqd;
 295 }
 296
 297 static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd)
 298 {
 299         return (struct vi_sdma_mqd *)mqd;
 300 }
 301
 302 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 303                         uint32_t queue_id, uint32_t __user *wptr,
 304                         uint32_t wptr_shift, uint32_t wptr_mask,
 305                         struct mm_struct *mm)
 306 {
 307         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 308         struct vi_mqd *m;
 309         uint32_t *mqd_hqd;
 310         uint32_t reg, wptr_val, data;
 311         bool valid_wptr = false;
 312
 313         m = get_mqd(mqd);
 314
 315         acquire_queue(kgd, pipe_id, queue_id);
 316
 317         /* HIQ is set during driver init period with vmid set to 0*/
 318         if (m->cp_hqd_vmid == 0) {
 319                 uint32_t value, mec, pipe;
 320
 321                 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
 322                 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 323
 324                 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
 325                         mec, pipe, queue_id);
 326                 value = RREG32(mmRLC_CP_SCHEDULERS);
 327                 value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,
 328                         ((mec << 5) | (pipe << 3) | queue_id | 0x80));
 329                 WREG32(mmRLC_CP_SCHEDULERS, value);
 330         }
 331
 332         /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */
 333         mqd_hqd = &m->cp_mqd_base_addr_lo;
 334
 335         for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++)
 336                 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
 337
 338         /* Tonga errata: EOP RPTR/WPTR should be left unmodified.
 339          * This is safe since EOP RPTR==WPTR for any inactive HQD
 340          * on ASICs that do not support context-save.
 341          * EOP writes/reads can start anywhere in the ring.
 342          */
 343         if (get_amdgpu_device(kgd)->asic_type != CHIP_TONGA) {
 344                 WREG32(mmCP_HQD_EOP_RPTR, m->cp_hqd_eop_rptr);
 345                 WREG32(mmCP_HQD_EOP_WPTR, m->cp_hqd_eop_wptr);
 346                 WREG32(mmCP_HQD_EOP_WPTR_MEM, m->cp_hqd_eop_wptr_mem);
 347         }
 348
 349         for (reg = mmCP_HQD_EOP_EVENTS; reg <= mmCP_HQD_ERROR; reg++)
 350                 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
 351
 352         /* Copy userspace write pointer value to register.
 353          * Activate doorbell logic to monitor subsequent changes.
 354          */
 355         data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
 356                              CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
 357         WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);
 358
 359         /* read_user_ptr may take the mm->mmap_sem.
 360          * release srbm_mutex to avoid circular dependency between
 361          * srbm_mutex->mm_sem->reservation_ww_class_mutex->srbm_mutex.
 362          */
 363         release_queue(kgd);
 364         valid_wptr = read_user_wptr(mm, wptr, wptr_val);
 365         acquire_queue(kgd, pipe_id, queue_id);
 366         if (valid_wptr)
 367                 WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask);
 368
 369         data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
 370         WREG32(mmCP_HQD_ACTIVE, data);
 371
 372         release_queue(kgd);
 373
 374         return 0;
 375 }
 376
 377 static int kgd_hqd_dump(struct kgd_dev *kgd,
 378                         uint32_t pipe_id, uint32_t queue_id,
 379                         uint32_t (**dump)[2], uint32_t *n_regs)
 380 {
 381         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 382         uint32_t i = 0, reg;
 383 #define HQD_N_REGS (54+4)
 384 #define DUMP_REG(addr) do {                             \
 385                 if (WARN_ON_ONCE(i >= HQD_N_REGS))      \
 386                         break;                          \
 387                 (*dump)[i][0] = (addr) << 2;            \
 388                 (*dump)[i++][1] = RREG32(addr);         \
 389         } while (0)
 390
 391         *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
 392         if (*dump == NULL)
 393                 return -ENOMEM;
 394
 395         acquire_queue(kgd, pipe_id, queue_id);
 396
 397         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0);
 398         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1);
 399         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2);
 400         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3);
 401
 402         for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_DONES; reg++)
 403                 DUMP_REG(reg);
 404
 405         release_queue(kgd);
 406
 407         WARN_ON_ONCE(i != HQD_N_REGS);
 408         *n_regs = i;
 409
 410         return 0;
 411 }
 412
 413 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
 414                              uint32_t __user *wptr, struct mm_struct *mm)
 415 {
 416         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 417         struct vi_sdma_mqd *m;
 418         unsigned long end_jiffies;
 419         uint32_t sdma_base_addr;
 420         uint32_t data;
 421
 422         m = get_sdma_mqd(mqd);
 423         sdma_base_addr = get_sdma_base_addr(m);
 424         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
 425                 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
 426
 427         end_jiffies = msecs_to_jiffies(2000) + jiffies;
 428         while (true) {
 429                 data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
 430                 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
 431                         break;
 432                 if (time_after(jiffies, end_jiffies))
 433                         return -ETIME;
 434                 usleep_range(500, 1000);
 435         }
 436         if (m->sdma_engine_id) {
 437                 data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
 438                 data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
 439                                 RESUME_CTX, 0);
 440                 WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);
 441         } else {
 442                 data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
 443                 data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
 444                                 RESUME_CTX, 0);
 445                 WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
 446         }
 447
 448         data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
 449                              ENABLE, 1);
 450         WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
 451         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
 452
 453         if (read_user_wptr(mm, wptr, data))
 454                 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data);
 455         else
 456                 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
 457                        m->sdmax_rlcx_rb_rptr);
 458
 459         WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
 460                                 m->sdmax_rlcx_virtual_addr);
 461         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
 462         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
 463                         m->sdmax_rlcx_rb_base_hi);
 464         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
 465                         m->sdmax_rlcx_rb_rptr_addr_lo);
 466         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
 467                         m->sdmax_rlcx_rb_rptr_addr_hi);
 468
 469         data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
 470                              RB_ENABLE, 1);
 471         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
 472
 473         return 0;
 474 }
 475
 476 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
 477                              uint32_t engine_id, uint32_t queue_id,
 478                              uint32_t (**dump)[2], uint32_t *n_regs)
 479 {
 480         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 481         uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET +
 482                 queue_id * KFD_VI_SDMA_QUEUE_OFFSET;
 483         uint32_t i = 0, reg;
 484 #undef HQD_N_REGS
 485 #define HQD_N_REGS (19+4+2+3+7)
 486
 487         *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
 488         if (*dump == NULL)
 489                 return -ENOMEM;
 490
 491         for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
 492                 DUMP_REG(sdma_offset + reg);
 493         for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK;
 494              reg++)
 495                 DUMP_REG(sdma_offset + reg);
 496         for (reg = mmSDMA0_RLC0_CSA_ADDR_LO; reg <= mmSDMA0_RLC0_CSA_ADDR_HI;
 497              reg++)
 498                 DUMP_REG(sdma_offset + reg);
 499         for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; reg <= mmSDMA0_RLC0_DUMMY_REG;
 500              reg++)
 501                 DUMP_REG(sdma_offset + reg);
 502         for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; reg <= mmSDMA0_RLC0_MIDCMD_CNTL;
 503              reg++)
 504                 DUMP_REG(sdma_offset + reg);
 505
 506         WARN_ON_ONCE(i != HQD_N_REGS);
 507         *n_regs = i;
 508
 509         return 0;
 510 }
 511
 512 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
 513                                 uint32_t pipe_id, uint32_t queue_id)
 514 {
 515         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 516         uint32_t act;
 517         bool retval = false;
 518         uint32_t low, high;
 519
 520         acquire_queue(kgd, pipe_id, queue_id);
 521         act = RREG32(mmCP_HQD_ACTIVE);
 522         if (act) {
 523                 low = lower_32_bits(queue_address >> 8);
 524                 high = upper_32_bits(queue_address >> 8);
 525
 526                 if (low == RREG32(mmCP_HQD_PQ_BASE) &&
 527                                 high == RREG32(mmCP_HQD_PQ_BASE_HI))
 528                         retval = true;
 529         }
 530         release_queue(kgd);
 531         return retval;
 532 }
 533
 534 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
 535 {
 536         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 537         struct vi_sdma_mqd *m;
 538         uint32_t sdma_base_addr;
 539         uint32_t sdma_rlc_rb_cntl;
 540
 541         m = get_sdma_mqd(mqd);
 542         sdma_base_addr = get_sdma_base_addr(m);
 543
 544         sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
 545
 546         if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
 547                 return true;
 548
 549         return false;
 550 }
 551
 552 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
 553                                 enum kfd_preempt_type reset_type,
 554                                 unsigned int utimeout, uint32_t pipe_id,
 555                                 uint32_t queue_id)
 556 {
 557         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 558         uint32_t temp;
 559         enum hqd_dequeue_request_type type;
 560         unsigned long flags, end_jiffies;
 561         int retry;
 562         struct vi_mqd *m = get_mqd(mqd);
 563
 564         acquire_queue(kgd, pipe_id, queue_id);
 565
 566         if (m->cp_hqd_vmid == 0)
 567                 WREG32_FIELD(RLC_CP_SCHEDULERS, scheduler1, 0);
 568
 569         switch (reset_type) {
 570         case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN:
 571                 type = DRAIN_PIPE;
 572                 break;
 573         case KFD_PREEMPT_TYPE_WAVEFRONT_RESET:
 574                 type = RESET_WAVES;
 575                 break;
 576         default:
 577                 type = DRAIN_PIPE;
 578                 break;
 579         }
 580
 581         /* Workaround: If IQ timer is active and the wait time is close to or
 582          * equal to 0, dequeueing is not safe. Wait until either the wait time
 583          * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is
 584          * cleared before continuing. Also, ensure wait times are set to at
 585          * least 0x3.
 586          */
 587         local_irq_save(flags);
 588         preempt_disable();
 589         retry = 5000; /* wait for 500 usecs at maximum */
 590         while (true) {
 591                 temp = RREG32(mmCP_HQD_IQ_TIMER);
 592                 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
 593                         pr_debug("HW is processing IQ\n");
 594                         goto loop;
 595                 }
 596                 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
 597                         if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE)
 598                                         == 3) /* SEM-rearm is safe */
 599                                 break;
 600                         /* Wait time 3 is safe for CP, but our MMIO read/write
 601                          * time is close to 1 microsecond, so check for 10 to
 602                          * leave more buffer room
 603                          */
 604                         if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
 605                                         >= 10)
 606                                 break;
 607                         pr_debug("IQ timer is active\n");
 608                 } else
 609                         break;
 610 loop:
 611                 if (!retry) {
 612                         pr_err("CP HQD IQ timer status time out\n");
 613                         break;
 614                 }
 615                 ndelay(100);
 616                 --retry;
 617         }
 618         retry = 1000;
 619         while (true) {
 620                 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);
 621                 if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK))
 622                         break;
 623                 pr_debug("Dequeue request is pending\n");
 624
 625                 if (!retry) {
 626                         pr_err("CP HQD dequeue request time out\n");
 627                         break;
 628                 }
 629                 ndelay(100);
 630                 --retry;
 631         }
 632         local_irq_restore(flags);
 633         preempt_enable();
 634
 635         WREG32(mmCP_HQD_DEQUEUE_REQUEST, type);
 636
 637         end_jiffies = (utimeout * HZ / 1000) + jiffies;
 638         while (true) {
 639                 temp = RREG32(mmCP_HQD_ACTIVE);
 640                 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
 641                         break;
 642                 if (time_after(jiffies, end_jiffies)) {
 643                         pr_err("cp queue preemption time out.\n");
 644                         release_queue(kgd);
 645                         return -ETIME;
 646                 }
 647                 usleep_range(500, 1000);
 648         }
 649
 650         release_queue(kgd);
 651         return 0;
 652 }
 653
 654 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 655                                 unsigned int utimeout)
 656 {
 657         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 658         struct vi_sdma_mqd *m;
 659         uint32_t sdma_base_addr;
 660         uint32_t temp;
 661         unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
 662
 663         m = get_sdma_mqd(mqd);
 664         sdma_base_addr = get_sdma_base_addr(m);
 665
 666         temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
 667         temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
 668         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
 669
 670         while (true) {
 671                 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
 672                 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
 673                         break;
 674                 if (time_after(jiffies, end_jiffies))
 675                         return -ETIME;
 676                 usleep_range(500, 1000);
 677         }
 678
 679         WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
 680         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
 681                 RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
 682                 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
 683
 684         m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
 685
 686         return 0;
 687 }
 688
 689 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
 690                                                         uint8_t vmid)
 691 {
 692         uint32_t reg;
 693         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 694
 695         reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 696         return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
 697 }
 698
 699 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
 700                                                                 uint8_t vmid)
 701 {
 702         uint32_t reg;
 703         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 704
 705         reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 706         return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
 707 }
 708
 709 static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid)
 710 {
 711         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 712
 713         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 714 }
 715
 716 static int kgd_address_watch_disable(struct kgd_dev *kgd)
 717 {
 718         return 0;
 719 }
 720
 721 static int kgd_address_watch_execute(struct kgd_dev *kgd,
 722                                         unsigned int watch_point_id,
 723                                         uint32_t cntl_val,
 724                                         uint32_t addr_hi,
 725                                         uint32_t addr_lo)
 726 {
 727         return 0;
 728 }
 729
 730 static int kgd_wave_control_execute(struct kgd_dev *kgd,
 731                                         uint32_t gfx_index_val,
 732                                         uint32_t sq_cmd)
 733 {
 734         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 735         uint32_t data = 0;
 736
 737         mutex_lock(&adev->grbm_idx_mutex);
 738
 739         WREG32(mmGRBM_GFX_INDEX, gfx_index_val);
 740         WREG32(mmSQ_CMD, sq_cmd);
 741
 742         data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 743                 INSTANCE_BROADCAST_WRITES, 1);
 744         data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 745                 SH_BROADCAST_WRITES, 1);
 746         data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 747                 SE_BROADCAST_WRITES, 1);
 748
 749         WREG32(mmGRBM_GFX_INDEX, data);
 750         mutex_unlock(&adev->grbm_idx_mutex);
 751
 752         return 0;
 753 }
 754
 755 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
 756                                         unsigned int watch_point_id,
 757                                         unsigned int reg_offset)
 758 {
 759         return 0;
 760 }
 761
 762 static void set_scratch_backing_va(struct kgd_dev *kgd,
 763                                         uint64_t va, uint32_t vmid)
 764 {
 765         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 766
 767         lock_srbm(kgd, 0, 0, 0, vmid);
 768         WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va);
 769         unlock_srbm(kgd);
 770 }
 771
 772 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
 773 {
 774         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 775         const union amdgpu_firmware_header *hdr;
 776
 777         BUG_ON(kgd == NULL);
 778
 779         switch (type) {
 780         case KGD_ENGINE_PFP:
 781                 hdr = (const union amdgpu_firmware_header *)
 782                                                 adev->gfx.pfp_fw->data;
 783                 break;
 784
 785         case KGD_ENGINE_ME:
 786                 hdr = (const union amdgpu_firmware_header *)
 787                                                 adev->gfx.me_fw->data;
 788                 break;
 789
 790         case KGD_ENGINE_CE:
 791                 hdr = (const union amdgpu_firmware_header *)
 792                                                 adev->gfx.ce_fw->data;
 793                 break;
 794
 795         case KGD_ENGINE_MEC1:
 796                 hdr = (const union amdgpu_firmware_header *)
 797                                                 adev->gfx.mec_fw->data;
 798                 break;
 799
 800         case KGD_ENGINE_MEC2:
 801                 hdr = (const union amdgpu_firmware_header *)
 802                                                 adev->gfx.mec2_fw->data;
 803                 break;
 804
 805         case KGD_ENGINE_RLC:
 806                 hdr = (const union amdgpu_firmware_header *)
 807                                                 adev->gfx.rlc_fw->data;
 808                 break;
 809
 810         case KGD_ENGINE_SDMA1:
 811                 hdr = (const union amdgpu_firmware_header *)
 812                                                 adev->sdma.instance[0].fw->data;
 813                 break;
 814
 815         case KGD_ENGINE_SDMA2:
 816                 hdr = (const union amdgpu_firmware_header *)
 817                                                 adev->sdma.instance[1].fw->data;
 818                 break;
 819
 820         default:
 821                 return 0;
 822         }
 823
 824         if (hdr == NULL)
 825                 return 0;
 826
 827         /* Only 12 bit in use*/
 828         return hdr->common.ucode_version;
 829 }