drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <glisse@freedesktop.org>
  26  */
  27 #include <linux/pagemap.h>
  28 #include <linux/sync_file.h>
  29 #include <drm/drmP.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include <drm/drm_syncobj.h>
  32 #include "amdgpu.h"
  33 #include "amdgpu_trace.h"
  34 #include "amdgpu_gmc.h"
  35 #include "amdgpu_gem.h"
  36
  37 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
  38                                       struct drm_amdgpu_cs_chunk_fence *data,
  39                                       uint32_t *offset)
  40 {
  41         struct drm_gem_object *gobj;
  42         unsigned long size;
  43
  44         gobj = drm_gem_object_lookup(p->filp, data->handle);
  45         if (gobj == NULL)
  46                 return -EINVAL;
  47
  48         p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
  49         p->uf_entry.priority = 0;
  50         p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
  51         p->uf_entry.tv.shared = true;
  52         p->uf_entry.user_pages = NULL;
  53
  54         size = amdgpu_bo_size(p->uf_entry.robj);
  55         if (size != PAGE_SIZE || (data->offset + 8) > size)
  56                 return -EINVAL;
  57
  58         *offset = data->offset;
  59
  60         drm_gem_object_put_unlocked(gobj);
  61
  62         if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) {
  63                 amdgpu_bo_unref(&p->uf_entry.robj);
  64                 return -EINVAL;
  65         }
  66
  67         return 0;
  68 }
  69
  70 static int amdgpu_cs_bo_handles_chunk(struct amdgpu_cs_parser *p,
  71                                       struct drm_amdgpu_bo_list_in *data)
  72 {
  73         int r;
  74         struct drm_amdgpu_bo_list_entry *info = NULL;
  75
  76         r = amdgpu_bo_create_list_entry_array(data, &info);
  77         if (r)
  78                 return r;
  79
  80         r = amdgpu_bo_list_create(p->adev, p->filp, info, data->bo_number,
  81                                   &p->bo_list);
  82         if (r)
  83                 goto error_free;
  84
  85         kvfree(info);
  86         return 0;
  87
  88 error_free:
  89         if (info)
  90                 kvfree(info);
  91
  92         return r;
  93 }
  94
  95 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs *cs)
  96 {
  97         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
  98         struct amdgpu_vm *vm = &fpriv->vm;
  99         uint64_t *chunk_array_user;
 100         uint64_t *chunk_array;
 101         unsigned size, num_ibs = 0;
 102         uint32_t uf_offset = 0;
 103         int i;
 104         int ret;
 105
 106         if (cs->in.num_chunks == 0)
 107                 return 0;
 108
 109         chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
 110         if (!chunk_array)
 111                 return -ENOMEM;
 112
 113         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
 114         if (!p->ctx) {
 115                 ret = -EINVAL;
 116                 goto free_chunk;
 117         }
 118
 119         /* skip guilty context job */
 120         if (atomic_read(&p->ctx->guilty) == 1) {
 121                 ret = -ECANCELED;
 122                 goto free_chunk;
 123         }
 124
 125         mutex_lock(&p->ctx->lock);
 126
 127         /* get chunks */
 128         chunk_array_user = u64_to_user_ptr(cs->in.chunks);
 129         if (copy_from_user(chunk_array, chunk_array_user,
 130                            sizeof(uint64_t)*cs->in.num_chunks)) {
 131                 ret = -EFAULT;
 132                 goto free_chunk;
 133         }
 134
 135         p->nchunks = cs->in.num_chunks;
 136         p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 137                             GFP_KERNEL);
 138         if (!p->chunks) {
 139                 ret = -ENOMEM;
 140                 goto free_chunk;
 141         }
 142
 143         for (i = 0; i < p->nchunks; i++) {
 144                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 145                 struct drm_amdgpu_cs_chunk user_chunk;
 146                 uint32_t __user *cdata;
 147
 148                 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
 149                 if (copy_from_user(&user_chunk, chunk_ptr,
 150                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 151                         ret = -EFAULT;
 152                         i--;
 153                         goto free_partial_kdata;
 154                 }
 155                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 156                 p->chunks[i].length_dw = user_chunk.length_dw;
 157
 158                 size = p->chunks[i].length_dw;
 159                 cdata = u64_to_user_ptr(user_chunk.chunk_data);
 160
 161                 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
 162                 if (p->chunks[i].kdata == NULL) {
 163                         ret = -ENOMEM;
 164                         i--;
 165                         goto free_partial_kdata;
 166                 }
 167                 size *= sizeof(uint32_t);
 168                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 169                         ret = -EFAULT;
 170                         goto free_partial_kdata;
 171                 }
 172
 173                 switch (p->chunks[i].chunk_id) {
 174                 case AMDGPU_CHUNK_ID_IB:
 175                         ++num_ibs;
 176                         break;
 177
 178                 case AMDGPU_CHUNK_ID_FENCE:
 179                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 180                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 181                                 ret = -EINVAL;
 182                                 goto free_partial_kdata;
 183                         }
 184
 185                         ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
 186                                                          &uf_offset);
 187                         if (ret)
 188                                 goto free_partial_kdata;
 189
 190                         break;
 191
 192                 case AMDGPU_CHUNK_ID_BO_HANDLES:
 193                         size = sizeof(struct drm_amdgpu_bo_list_in);
 194                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 195                                 ret = -EINVAL;
 196                                 goto free_partial_kdata;
 197                         }
 198
 199                         ret = amdgpu_cs_bo_handles_chunk(p, p->chunks[i].kdata);
 200                         if (ret)
 201                                 goto free_partial_kdata;
 202
 203                         break;
 204
 205                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 206                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
 207                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
 208                         break;
 209
 210                 default:
 211                         ret = -EINVAL;
 212                         goto free_partial_kdata;
 213                 }
 214         }
 215
 216         ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
 217         if (ret)
 218                 goto free_all_kdata;
 219
 220         if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
 221                 ret = -ECANCELED;
 222                 goto free_all_kdata;
 223         }
 224
 225         if (p->uf_entry.robj)
 226                 p->job->uf_addr = uf_offset;
 227         kfree(chunk_array);
 228
 229         /* Use this opportunity to fill in task info for the vm */
 230         amdgpu_vm_set_task_info(vm);
 231
 232         return 0;
 233
 234 free_all_kdata:
 235         i = p->nchunks - 1;
 236 free_partial_kdata:
 237         for (; i >= 0; i--)
 238                 kvfree(p->chunks[i].kdata);
 239         kfree(p->chunks);
 240         p->chunks = NULL;
 241         p->nchunks = 0;
 242 free_chunk:
 243         kfree(chunk_array);
 244
 245         return ret;
 246 }
 247
 248 /* Convert microseconds to bytes. */
 249 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
 250 {
 251         if (us <= 0 || !adev->mm_stats.log2_max_MBps)
 252                 return 0;
 253
 254         /* Since accum_us is incremented by a million per second, just
 255          * multiply it by the number of MB/s to get the number of bytes.
 256          */
 257         return us << adev->mm_stats.log2_max_MBps;
 258 }
 259
 260 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
 261 {
 262         if (!adev->mm_stats.log2_max_MBps)
 263                 return 0;
 264
 265         return bytes >> adev->mm_stats.log2_max_MBps;
 266 }
 267
 268 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
 269  * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
 270  * which means it can go over the threshold once. If that happens, the driver
 271  * will be in debt and no other buffer migrations can be done until that debt
 272  * is repaid.
 273  *
 274  * This approach allows moving a buffer of any size (it's important to allow
 275  * that).
 276  *
 277  * The currency is simply time in microseconds and it increases as the clock
 278  * ticks. The accumulated microseconds (us) are converted to bytes and
 279  * returned.
 280  */
 281 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
 282                                               u64 *max_bytes,
 283                                               u64 *max_vis_bytes)
 284 {
 285         s64 time_us, increment_us;
 286         u64 free_vram, total_vram, used_vram;
 287
 288         /* Allow a maximum of 200 accumulated ms. This is basically per-IB
 289          * throttling.
 290          *
 291          * It means that in order to get full max MBps, at least 5 IBs per
 292          * second must be submitted and not more than 200ms apart from each
 293          * other.
 294          */
 295         const s64 us_upper_bound = 200000;
 296
 297         if (!adev->mm_stats.log2_max_MBps) {
 298                 *max_bytes = 0;
 299                 *max_vis_bytes = 0;
 300                 return;
 301         }
 302
 303         total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size);
 304         used_vram = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 305         free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
 306
 307         spin_lock(&adev->mm_stats.lock);
 308
 309         /* Increase the amount of accumulated us. */
 310         time_us = ktime_to_us(ktime_get());
 311         increment_us = time_us - adev->mm_stats.last_update_us;
 312         adev->mm_stats.last_update_us = time_us;
 313         adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
 314                                       us_upper_bound);
 315
 316         /* This prevents the short period of low performance when the VRAM
 317          * usage is low and the driver is in debt or doesn't have enough
 318          * accumulated us to fill VRAM quickly.
 319          *
 320          * The situation can occur in these cases:
 321          * - a lot of VRAM is freed by userspace
 322          * - the presence of a big buffer causes a lot of evictions
 323          *   (solution: split buffers into smaller ones)
 324          *
 325          * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
 326          * accum_us to a positive number.
 327          */
 328         if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
 329                 s64 min_us;
 330
 331                 /* Be more aggresive on dGPUs. Try to fill a portion of free
 332                  * VRAM now.
 333                  */
 334                 if (!(adev->flags & AMD_IS_APU))
 335                         min_us = bytes_to_us(adev, free_vram / 4);
 336                 else
 337                         min_us = 0; /* Reset accum_us on APUs. */
 338
 339                 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
 340         }
 341
 342         /* This is set to 0 if the driver is in debt to disallow (optional)
 343          * buffer moves.
 344          */
 345         *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
 346
 347         /* Do the same for visible VRAM if half of it is free */
 348         if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) {
 349                 u64 total_vis_vram = adev->gmc.visible_vram_size;
 350                 u64 used_vis_vram =
 351                         amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 352
 353                 if (used_vis_vram < total_vis_vram) {
 354                         u64 free_vis_vram = total_vis_vram - used_vis_vram;
 355                         adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
 356                                                           increment_us, us_upper_bound);
 357
 358                         if (free_vis_vram >= total_vis_vram / 2)
 359                                 adev->mm_stats.accum_us_vis =
 360                                         max(bytes_to_us(adev, free_vis_vram / 2),
 361                                             adev->mm_stats.accum_us_vis);
 362                 }
 363
 364                 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
 365         } else {
 366                 *max_vis_bytes = 0;
 367         }
 368
 369         spin_unlock(&adev->mm_stats.lock);
 370 }
 371
 372 /* Report how many bytes have really been moved for the last command
 373  * submission. This can result in a debt that can stop buffer migrations
 374  * temporarily.
 375  */
 376 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
 377                                   u64 num_vis_bytes)
 378 {
 379         spin_lock(&adev->mm_stats.lock);
 380         adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
 381         adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
 382         spin_unlock(&adev->mm_stats.lock);
 383 }
 384
 385 static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
 386                                  struct amdgpu_bo *bo)
 387 {
 388         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 389         struct ttm_operation_ctx ctx = {
 390                 .interruptible = true,
 391                 .no_wait_gpu = false,
 392                 .resv = bo->tbo.resv,
 393                 .flags = 0
 394         };
 395         uint32_t domain;
 396         int r;
 397
 398         if (bo->pin_count)
 399                 return 0;
 400
 401         /* Don't move this buffer if we have depleted our allowance
 402          * to move it. Don't move anything if the threshold is zero.
 403          */
 404         if (p->bytes_moved < p->bytes_moved_threshold) {
 405                 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 406                     (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 407                         /* And don't move a CPU_ACCESS_REQUIRED BO to limited
 408                          * visible VRAM if we've depleted our allowance to do
 409                          * that.
 410                          */
 411                         if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
 412                                 domain = bo->preferred_domains;
 413                         else
 414                                 domain = bo->allowed_domains;
 415                 } else {
 416                         domain = bo->preferred_domains;
 417                 }
 418         } else {
 419                 domain = bo->allowed_domains;
 420         }
 421
 422 retry:
 423         amdgpu_bo_placement_from_domain(bo, domain);
 424         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 425
 426         p->bytes_moved += ctx.bytes_moved;
 427         if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 428             amdgpu_bo_in_cpu_visible_vram(bo))
 429                 p->bytes_moved_vis += ctx.bytes_moved;
 430
 431         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 432                 domain = bo->allowed_domains;
 433                 goto retry;
 434         }
 435
 436         return r;
 437 }
 438
 439 /* Last resort, try to evict something from the current working set */
 440 static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
 441                                 struct amdgpu_bo *validated)
 442 {
 443         uint32_t domain = validated->allowed_domains;
 444         struct ttm_operation_ctx ctx = { true, false };
 445         int r;
 446
 447         if (!p->evictable)
 448                 return false;
 449
 450         for (;&p->evictable->tv.head != &p->validated;
 451              p->evictable = list_prev_entry(p->evictable, tv.head)) {
 452
 453                 struct amdgpu_bo_list_entry *candidate = p->evictable;
 454                 struct amdgpu_bo *bo = candidate->robj;
 455                 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 456                 bool update_bytes_moved_vis;
 457                 uint32_t other;
 458
 459                 /* If we reached our current BO we can forget it */
 460                 if (candidate->robj == validated)
 461                         break;
 462
 463                 /* We can't move pinned BOs here */
 464                 if (bo->pin_count)
 465                         continue;
 466
 467                 other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 468
 469                 /* Check if this BO is in one of the domains we need space for */
 470                 if (!(other & domain))
 471                         continue;
 472
 473                 /* Check if we can move this BO somewhere else */
 474                 other = bo->allowed_domains & ~domain;
 475                 if (!other)
 476                         continue;
 477
 478                 /* Good we can try to move this BO somewhere else */
 479                 update_bytes_moved_vis =
 480                                 !amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 481                                 amdgpu_bo_in_cpu_visible_vram(bo);
 482                 amdgpu_bo_placement_from_domain(bo, other);
 483                 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 484                 p->bytes_moved += ctx.bytes_moved;
 485                 if (update_bytes_moved_vis)
 486                         p->bytes_moved_vis += ctx.bytes_moved;
 487
 488                 if (unlikely(r))
 489                         break;
 490
 491                 p->evictable = list_prev_entry(p->evictable, tv.head);
 492                 list_move(&candidate->tv.head, &p->validated);
 493
 494                 return true;
 495         }
 496
 497         return false;
 498 }
 499
 500 static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
 501 {
 502         struct amdgpu_cs_parser *p = param;
 503         int r;
 504
 505         do {
 506                 r = amdgpu_cs_bo_validate(p, bo);
 507         } while (r == -ENOMEM && amdgpu_cs_try_evict(p, bo));
 508         if (r)
 509                 return r;
 510
 511         if (bo->shadow)
 512                 r = amdgpu_cs_bo_validate(p, bo->shadow);
 513
 514         return r;
 515 }
 516
 517 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 518                             struct list_head *validated)
 519 {
 520         struct ttm_operation_ctx ctx = { true, false };
 521         struct amdgpu_bo_list_entry *lobj;
 522         int r;
 523
 524         list_for_each_entry(lobj, validated, tv.head) {
 525                 struct amdgpu_bo *bo = lobj->robj;
 526                 bool binding_userptr = false;
 527                 struct mm_struct *usermm;
 528
 529                 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
 530                 if (usermm && usermm != current->mm)
 531                         return -EPERM;
 532
 533                 /* Check if we have user pages and nobody bound the BO already */
 534                 if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
 535                     lobj->user_pages) {
 536                         amdgpu_bo_placement_from_domain(bo,
 537                                                         AMDGPU_GEM_DOMAIN_CPU);
 538                         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 539                         if (r)
 540                                 return r;
 541                         amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
 542                                                      lobj->user_pages);
 543                         binding_userptr = true;
 544                 }
 545
 546                 if (p->evictable == lobj)
 547                         p->evictable = NULL;
 548
 549                 r = amdgpu_cs_validate(p, bo);
 550                 if (r)
 551                         return r;
 552
 553                 if (binding_userptr) {
 554                         kvfree(lobj->user_pages);
 555                         lobj->user_pages = NULL;
 556                 }
 557         }
 558         return 0;
 559 }
 560
 561 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 562                                 union drm_amdgpu_cs *cs)
 563 {
 564         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 565         struct amdgpu_vm *vm = &fpriv->vm;
 566         struct amdgpu_bo_list_entry *e;
 567         struct list_head duplicates;
 568         struct amdgpu_bo *gds;
 569         struct amdgpu_bo *gws;
 570         struct amdgpu_bo *oa;
 571         unsigned tries = 10;
 572         int r;
 573
 574         INIT_LIST_HEAD(&p->validated);
 575
 576         /* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES is present */
 577         if (cs->in.bo_list_handle) {
 578                 if (p->bo_list)
 579                         return -EINVAL;
 580
 581                 r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle,
 582                                        &p->bo_list);
 583                 if (r)
 584                         return r;
 585         } else if (!p->bo_list) {
 586                 /* Create a empty bo_list when no handle is provided */
 587                 r = amdgpu_bo_list_create(p->adev, p->filp, NULL, 0,
 588                                           &p->bo_list);
 589                 if (r)
 590                         return r;
 591         }
 592
 593         amdgpu_bo_list_get_list(p->bo_list, &p->validated);
 594         if (p->bo_list->first_userptr != p->bo_list->num_entries)
 595                 p->mn = amdgpu_mn_get(p->adev, AMDGPU_MN_TYPE_GFX);
 596
 597         INIT_LIST_HEAD(&duplicates);
 598         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
 599
 600         if (p->uf_entry.robj && !p->uf_entry.robj->parent)
 601                 list_add(&p->uf_entry.tv.head, &p->validated);
 602
 603         while (1) {
 604                 struct list_head need_pages;
 605
 606                 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
 607                                            &duplicates);
 608                 if (unlikely(r != 0)) {
 609                         if (r != -ERESTARTSYS)
 610                                 DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
 611                         goto error_free_pages;
 612                 }
 613
 614                 INIT_LIST_HEAD(&need_pages);
 615                 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
 616                         struct amdgpu_bo *bo = e->robj;
 617
 618                         if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm,
 619                                  &e->user_invalidated) && e->user_pages) {
 620
 621                                 /* We acquired a page array, but somebody
 622                                  * invalidated it. Free it and try again
 623                                  */
 624                                 release_pages(e->user_pages,
 625                                               bo->tbo.ttm->num_pages);
 626                                 kvfree(e->user_pages);
 627                                 e->user_pages = NULL;
 628                         }
 629
 630                         if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
 631                             !e->user_pages) {
 632                                 list_del(&e->tv.head);
 633                                 list_add(&e->tv.head, &need_pages);
 634
 635                                 amdgpu_bo_unreserve(e->robj);
 636                         }
 637                 }
 638
 639                 if (list_empty(&need_pages))
 640                         break;
 641
 642                 /* Unreserve everything again. */
 643                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 644
 645                 /* We tried too many times, just abort */
 646                 if (!--tries) {
 647                         r = -EDEADLK;
 648                         DRM_ERROR("deadlock in %s\n", __func__);
 649                         goto error_free_pages;
 650                 }
 651
 652                 /* Fill the page arrays for all userptrs. */
 653                 list_for_each_entry(e, &need_pages, tv.head) {
 654                         struct ttm_tt *ttm = e->robj->tbo.ttm;
 655
 656                         e->user_pages = kvmalloc_array(ttm->num_pages,
 657                                                          sizeof(struct page*),
 658                                                          GFP_KERNEL | __GFP_ZERO);
 659                         if (!e->user_pages) {
 660                                 r = -ENOMEM;
 661                                 DRM_ERROR("calloc failure in %s\n", __func__);
 662                                 goto error_free_pages;
 663                         }
 664
 665                         r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages);
 666                         if (r) {
 667                                 DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n");
 668                                 kvfree(e->user_pages);
 669                                 e->user_pages = NULL;
 670                                 goto error_free_pages;
 671                         }
 672                 }
 673
 674                 /* And try again. */
 675                 list_splice(&need_pages, &p->validated);
 676         }
 677
 678         amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
 679                                           &p->bytes_moved_vis_threshold);
 680         p->bytes_moved = 0;
 681         p->bytes_moved_vis = 0;
 682         p->evictable = list_last_entry(&p->validated,
 683                                        struct amdgpu_bo_list_entry,
 684                                        tv.head);
 685
 686         r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
 687                                       amdgpu_cs_validate, p);
 688         if (r) {
 689                 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
 690                 goto error_validate;
 691         }
 692
 693         r = amdgpu_cs_list_validate(p, &duplicates);
 694         if (r) {
 695                 DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n");
 696                 goto error_validate;
 697         }
 698
 699         r = amdgpu_cs_list_validate(p, &p->validated);
 700         if (r) {
 701                 DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n");
 702                 goto error_validate;
 703         }
 704
 705         amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
 706                                      p->bytes_moved_vis);
 707
 708         gds = p->bo_list->gds_obj;
 709         gws = p->bo_list->gws_obj;
 710         oa = p->bo_list->oa_obj;
 711
 712         amdgpu_bo_list_for_each_entry(e, p->bo_list)
 713                 e->bo_va = amdgpu_vm_bo_find(vm, e->robj);
 714
 715         if (gds) {
 716                 p->job->gds_base = amdgpu_bo_gpu_offset(gds);
 717                 p->job->gds_size = amdgpu_bo_size(gds);
 718         }
 719         if (gws) {
 720                 p->job->gws_base = amdgpu_bo_gpu_offset(gws);
 721                 p->job->gws_size = amdgpu_bo_size(gws);
 722         }
 723         if (oa) {
 724                 p->job->oa_base = amdgpu_bo_gpu_offset(oa);
 725                 p->job->oa_size = amdgpu_bo_size(oa);
 726         }
 727
 728         if (!r && p->uf_entry.robj) {
 729                 struct amdgpu_bo *uf = p->uf_entry.robj;
 730
 731                 r = amdgpu_ttm_alloc_gart(&uf->tbo);
 732                 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
 733         }
 734
 735 error_validate:
 736         if (r)
 737                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 738
 739 error_free_pages:
 740
 741         amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
 742                 if (!e->user_pages)
 743                         continue;
 744
 745                 release_pages(e->user_pages,
 746                               e->robj->tbo.ttm->num_pages);
 747                 kvfree(e->user_pages);
 748         }
 749
 750         return r;
 751 }
 752
 753 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 754 {
 755         struct amdgpu_bo_list_entry *e;
 756         int r;
 757
 758         list_for_each_entry(e, &p->validated, tv.head) {
 759                 struct reservation_object *resv = e->robj->tbo.resv;
 760                 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
 761                                      amdgpu_bo_explicit_sync(e->robj));
 762
 763                 if (r)
 764                         return r;
 765         }
 766         return 0;
 767 }
 768
 769 /**
 770  * cs_parser_fini() - clean parser states
 771  * @parser:     parser structure holding parsing context.
 772  * @error:      error number
 773  *
 774  * If error is set than unvalidate buffer, otherwise just free memory
 775  * used by parsing context.
 776  **/
 777 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
 778                                   bool backoff)
 779 {
 780         unsigned i;
 781
 782         if (error && backoff)
 783                 ttm_eu_backoff_reservation(&parser->ticket,
 784                                            &parser->validated);
 785
 786         for (i = 0; i < parser->num_post_dep_syncobjs; i++)
 787                 drm_syncobj_put(parser->post_dep_syncobjs[i]);
 788         kfree(parser->post_dep_syncobjs);
 789
 790         dma_fence_put(parser->fence);
 791
 792         if (parser->ctx) {
 793                 mutex_unlock(&parser->ctx->lock);
 794                 amdgpu_ctx_put(parser->ctx);
 795         }
 796         if (parser->bo_list)
 797                 amdgpu_bo_list_put(parser->bo_list);
 798
 799         for (i = 0; i < parser->nchunks; i++)
 800                 kvfree(parser->chunks[i].kdata);
 801         kfree(parser->chunks);
 802         if (parser->job)
 803                 amdgpu_job_free(parser->job);
 804         amdgpu_bo_unref(&parser->uf_entry.robj);
 805 }
 806
 807 static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
 808 {
 809         struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
 810         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 811         struct amdgpu_device *adev = p->adev;
 812         struct amdgpu_vm *vm = &fpriv->vm;
 813         struct amdgpu_bo_list_entry *e;
 814         struct amdgpu_bo_va *bo_va;
 815         struct amdgpu_bo *bo;
 816         int r;
 817
 818         /* Only for UVD/VCE VM emulation */
 819         if (ring->funcs->parse_cs || ring->funcs->patch_cs_in_place) {
 820                 unsigned i, j;
 821
 822                 for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
 823                         struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 824                         struct amdgpu_bo_va_mapping *m;
 825                         struct amdgpu_bo *aobj = NULL;
 826                         struct amdgpu_cs_chunk *chunk;
 827                         uint64_t offset, va_start;
 828                         struct amdgpu_ib *ib;
 829                         uint8_t *kptr;
 830
 831                         chunk = &p->chunks[i];
 832                         ib = &p->job->ibs[j];
 833                         chunk_ib = chunk->kdata;
 834
 835                         if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 836                                 continue;
 837
 838                         va_start = chunk_ib->va_start & AMDGPU_VA_HOLE_MASK;
 839                         r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
 840                         if (r) {
 841                                 DRM_ERROR("IB va_start is invalid\n");
 842                                 return r;
 843                         }
 844
 845                         if ((va_start + chunk_ib->ib_bytes) >
 846                             (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 847                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 848                                 return -EINVAL;
 849                         }
 850
 851                         /* the IB should be reserved at this point */
 852                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 853                         if (r) {
 854                                 return r;
 855                         }
 856
 857                         offset = m->start * AMDGPU_GPU_PAGE_SIZE;
 858                         kptr += va_start - offset;
 859
 860                         if (ring->funcs->parse_cs) {
 861                                 memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 862                                 amdgpu_bo_kunmap(aobj);
 863
 864                                 r = amdgpu_ring_parse_cs(ring, p, j);
 865                                 if (r)
 866                                         return r;
 867                         } else {
 868                                 ib->ptr = (uint32_t *)kptr;
 869                                 r = amdgpu_ring_patch_cs_in_place(ring, p, j);
 870                                 amdgpu_bo_kunmap(aobj);
 871                                 if (r)
 872                                         return r;
 873                         }
 874
 875                         j++;
 876                 }
 877         }
 878
 879         if (!p->job->vm)
 880                 return amdgpu_cs_sync_rings(p);
 881
 882
 883         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 884         if (r)
 885                 return r;
 886
 887         r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
 888         if (r)
 889                 return r;
 890
 891         r = amdgpu_sync_fence(adev, &p->job->sync,
 892                               fpriv->prt_va->last_pt_update, false);
 893         if (r)
 894                 return r;
 895
 896         if (amdgpu_sriov_vf(adev)) {
 897                 struct dma_fence *f;
 898
 899                 bo_va = fpriv->csa_va;
 900                 BUG_ON(!bo_va);
 901                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 902                 if (r)
 903                         return r;
 904
 905                 f = bo_va->last_pt_update;
 906                 r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
 907                 if (r)
 908                         return r;
 909         }
 910
 911         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 912                 struct dma_fence *f;
 913
 914                 /* ignore duplicates */
 915                 bo = e->robj;
 916                 if (!bo)
 917                         continue;
 918
 919                 bo_va = e->bo_va;
 920                 if (bo_va == NULL)
 921                         continue;
 922
 923                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 924                 if (r)
 925                         return r;
 926
 927                 f = bo_va->last_pt_update;
 928                 r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
 929                 if (r)
 930                         return r;
 931         }
 932
 933         r = amdgpu_vm_handle_moved(adev, vm);
 934         if (r)
 935                 return r;
 936
 937         r = amdgpu_vm_update_directories(adev, vm);
 938         if (r)
 939                 return r;
 940
 941         r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update, false);
 942         if (r)
 943                 return r;
 944
 945         r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv);
 946         if (r)
 947                 return r;
 948
 949         p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
 950
 951         if (amdgpu_vm_debug) {
 952                 /* Invalidate all BOs to test for userspace bugs */
 953                 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 954                         /* ignore duplicates */
 955                         if (!e->robj)
 956                                 continue;
 957
 958                         amdgpu_vm_bo_invalidate(adev, e->robj, false);
 959                 }
 960         }
 961
 962         return amdgpu_cs_sync_rings(p);
 963 }
 964
 965 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 966                              struct amdgpu_cs_parser *parser)
 967 {
 968         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 969         struct amdgpu_vm *vm = &fpriv->vm;
 970         int r, ce_preempt = 0, de_preempt = 0;
 971         struct amdgpu_ring *ring;
 972         int i, j;
 973
 974         for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
 975                 struct amdgpu_cs_chunk *chunk;
 976                 struct amdgpu_ib *ib;
 977                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 978                 struct drm_sched_entity *entity;
 979
 980                 chunk = &parser->chunks[i];
 981                 ib = &parser->job->ibs[j];
 982                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 983
 984                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 985                         continue;
 986
 987                 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX && amdgpu_sriov_vf(adev)) {
 988                         if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
 989                                 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
 990                                         ce_preempt++;
 991                                 else
 992                                         de_preempt++;
 993                         }
 994
 995                         /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
 996                         if (ce_preempt > 1 || de_preempt > 1)
 997                                 return -EINVAL;
 998                 }
 999
1000                 r = amdgpu_ctx_get_entity(parser->ctx, chunk_ib->ip_type,
1001                                           chunk_ib->ip_instance, chunk_ib->ring,
1002                                           &entity);
1003                 if (r)
1004                         return r;
1005
1006                 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE)
1007                         parser->job->preamble_status |=
1008                                 AMDGPU_PREAMBLE_IB_PRESENT;
1009
1010                 if (parser->entity && parser->entity != entity)
1011                         return -EINVAL;
1012
1013                 parser->entity = entity;
1014
1015                 ring = to_amdgpu_ring(entity->rq->sched);
1016                 r =  amdgpu_ib_get(adev, vm, ring->funcs->parse_cs ?
1017                                    chunk_ib->ib_bytes : 0, ib);
1018                 if (r) {
1019                         DRM_ERROR("Failed to get ib !\n");
1020                         return r;
1021                 }
1022
1023                 ib->gpu_addr = chunk_ib->va_start;
1024                 ib->length_dw = chunk_ib->ib_bytes / 4;
1025                 ib->flags = chunk_ib->flags;
1026
1027                 j++;
1028         }
1029
1030         /* UVD & VCE fw doesn't support user fences */
1031         ring = to_amdgpu_ring(parser->entity->rq->sched);
1032         if (parser->job->uf_addr && (
1033             ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
1034             ring->funcs->type == AMDGPU_RING_TYPE_VCE))
1035                 return -EINVAL;
1036
1037         return amdgpu_ctx_wait_prev_fence(parser->ctx, parser->entity);
1038 }
1039
1040 static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
1041                                        struct amdgpu_cs_chunk *chunk)
1042 {
1043         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1044         unsigned num_deps;
1045         int i, r;
1046         struct drm_amdgpu_cs_chunk_dep *deps;
1047
1048         deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
1049         num_deps = chunk->length_dw * 4 /
1050                 sizeof(struct drm_amdgpu_cs_chunk_dep);
1051
1052         for (i = 0; i < num_deps; ++i) {
1053                 struct amdgpu_ctx *ctx;
1054                 struct drm_sched_entity *entity;
1055                 struct dma_fence *fence;
1056
1057                 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
1058                 if (ctx == NULL)
1059                         return -EINVAL;
1060
1061                 r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type,
1062                                           deps[i].ip_instance,
1063                                           deps[i].ring, &entity);
1064                 if (r) {
1065                         amdgpu_ctx_put(ctx);
1066                         return r;
1067                 }
1068
1069                 fence = amdgpu_ctx_get_fence(ctx, entity,
1070                                              deps[i].handle);
1071                 if (IS_ERR(fence)) {
1072                         r = PTR_ERR(fence);
1073                         amdgpu_ctx_put(ctx);
1074                         return r;
1075                 } else if (fence) {
1076                         r = amdgpu_sync_fence(p->adev, &p->job->sync, fence,
1077                                         true);
1078                         dma_fence_put(fence);
1079                         amdgpu_ctx_put(ctx);
1080                         if (r)
1081                                 return r;
1082                 }
1083         }
1084         return 0;
1085 }
1086
1087 static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
1088                                                  uint32_t handle)
1089 {
1090         int r;
1091         struct dma_fence *fence;
1092         r = drm_syncobj_find_fence(p->filp, handle, &fence);
1093         if (r)
1094                 return r;
1095
1096         r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true);
1097         dma_fence_put(fence);
1098
1099         return r;
1100 }
1101
1102 static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
1103                                             struct amdgpu_cs_chunk *chunk)
1104 {
1105         unsigned num_deps;
1106         int i, r;
1107         struct drm_amdgpu_cs_chunk_sem *deps;
1108
1109         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1110         num_deps = chunk->length_dw * 4 /
1111                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1112
1113         for (i = 0; i < num_deps; ++i) {
1114                 r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle);
1115                 if (r)
1116                         return r;
1117         }
1118         return 0;
1119 }
1120
1121 static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
1122                                              struct amdgpu_cs_chunk *chunk)
1123 {
1124         unsigned num_deps;
1125         int i;
1126         struct drm_amdgpu_cs_chunk_sem *deps;
1127         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1128         num_deps = chunk->length_dw * 4 /
1129                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1130
1131         p->post_dep_syncobjs = kmalloc_array(num_deps,
1132                                              sizeof(struct drm_syncobj *),
1133                                              GFP_KERNEL);
1134         p->num_post_dep_syncobjs = 0;
1135
1136         if (!p->post_dep_syncobjs)
1137                 return -ENOMEM;
1138
1139         for (i = 0; i < num_deps; ++i) {
1140                 p->post_dep_syncobjs[i] = drm_syncobj_find(p->filp, deps[i].handle);
1141                 if (!p->post_dep_syncobjs[i])
1142                         return -EINVAL;
1143                 p->num_post_dep_syncobjs++;
1144         }
1145         return 0;
1146 }
1147
1148 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
1149                                   struct amdgpu_cs_parser *p)
1150 {
1151         int i, r;
1152
1153         for (i = 0; i < p->nchunks; ++i) {
1154                 struct amdgpu_cs_chunk *chunk;
1155
1156                 chunk = &p->chunks[i];
1157
1158                 if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) {
1159                         r = amdgpu_cs_process_fence_dep(p, chunk);
1160                         if (r)
1161                                 return r;
1162                 } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_IN) {
1163                         r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
1164                         if (r)
1165                                 return r;
1166                 } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_OUT) {
1167                         r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
1168                         if (r)
1169                                 return r;
1170                 }
1171         }
1172
1173         return 0;
1174 }
1175
1176 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1177 {
1178         int i;
1179
1180         for (i = 0; i < p->num_post_dep_syncobjs; ++i)
1181                 drm_syncobj_replace_fence(p->post_dep_syncobjs[i], p->fence);
1182 }
1183
1184 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1185                             union drm_amdgpu_cs *cs)
1186 {
1187         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1188         struct drm_sched_entity *entity = p->entity;
1189         enum drm_sched_priority priority;
1190         struct amdgpu_ring *ring;
1191         struct amdgpu_bo_list_entry *e;
1192         struct amdgpu_job *job;
1193         uint64_t seq;
1194
1195         int r;
1196
1197         job = p->job;
1198         p->job = NULL;
1199
1200         r = drm_sched_job_init(&job->base, entity, p->filp);
1201         if (r)
1202                 goto error_unlock;
1203
1204         /* No memory allocation is allowed while holding the mn lock */
1205         amdgpu_mn_lock(p->mn);
1206         amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
1207                 struct amdgpu_bo *bo = e->robj;
1208
1209                 if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) {
1210                         r = -ERESTARTSYS;
1211                         goto error_abort;
1212                 }
1213         }
1214
1215         job->owner = p->filp;
1216         p->fence = dma_fence_get(&job->base.s_fence->finished);
1217
1218         amdgpu_ctx_add_fence(p->ctx, entity, p->fence, &seq);
1219         amdgpu_cs_post_dependencies(p);
1220
1221         if ((job->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) &&
1222             !p->ctx->preamble_presented) {
1223                 job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
1224                 p->ctx->preamble_presented = true;
1225         }
1226
1227         cs->out.handle = seq;
1228         job->uf_sequence = seq;
1229
1230         amdgpu_job_free_resources(job);
1231
1232         trace_amdgpu_cs_ioctl(job);
1233         amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->ticket);
1234         priority = job->base.s_priority;
1235         drm_sched_entity_push_job(&job->base, entity);
1236
1237         ring = to_amdgpu_ring(entity->rq->sched);
1238         amdgpu_ring_priority_get(ring, priority);
1239
1240         amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);
1241
1242         ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
1243         amdgpu_mn_unlock(p->mn);
1244
1245         return 0;
1246
1247 error_abort:
1248         dma_fence_put(&job->base.s_fence->finished);
1249         job->base.s_fence = NULL;
1250         amdgpu_mn_unlock(p->mn);
1251
1252 error_unlock:
1253         amdgpu_job_free(job);
1254         return r;
1255 }
1256
1257 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1258 {
1259         struct amdgpu_device *adev = dev->dev_private;
1260         union drm_amdgpu_cs *cs = data;
1261         struct amdgpu_cs_parser parser = {};
1262         bool reserved_buffers = false;
1263         int i, r;
1264
1265         if (!adev->accel_working)
1266                 return -EBUSY;
1267
1268         parser.adev = adev;
1269         parser.filp = filp;
1270
1271         r = amdgpu_cs_parser_init(&parser, data);
1272         if (r) {
1273                 DRM_ERROR("Failed to initialize parser !\n");
1274                 goto out;
1275         }
1276
1277         r = amdgpu_cs_ib_fill(adev, &parser);
1278         if (r)
1279                 goto out;
1280
1281         r = amdgpu_cs_parser_bos(&parser, data);
1282         if (r) {
1283                 if (r == -ENOMEM)
1284                         DRM_ERROR("Not enough memory for command submission!\n");
1285                 else if (r != -ERESTARTSYS)
1286                         DRM_ERROR("Failed to process the buffer list %d!\n", r);
1287                 goto out;
1288         }
1289
1290         reserved_buffers = true;
1291
1292         r = amdgpu_cs_dependencies(adev, &parser);
1293         if (r) {
1294                 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1295                 goto out;
1296         }
1297
1298         for (i = 0; i < parser.job->num_ibs; i++)
1299                 trace_amdgpu_cs(&parser, i);
1300
1301         r = amdgpu_cs_vm_handling(&parser);
1302         if (r)
1303                 goto out;
1304
1305         r = amdgpu_cs_submit(&parser, cs);
1306
1307 out:
1308         amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1309         return r;
1310 }
1311
1312 /**
1313  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1314  *
1315  * @dev: drm device
1316  * @data: data from userspace
1317  * @filp: file private
1318  *
1319  * Wait for the command submission identified by handle to finish.
1320  */
1321 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1322                          struct drm_file *filp)
1323 {
1324         union drm_amdgpu_wait_cs *wait = data;
1325         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1326         struct drm_sched_entity *entity;
1327         struct amdgpu_ctx *ctx;
1328         struct dma_fence *fence;
1329         long r;
1330
1331         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1332         if (ctx == NULL)
1333                 return -EINVAL;
1334
1335         r = amdgpu_ctx_get_entity(ctx, wait->in.ip_type, wait->in.ip_instance,
1336                                   wait->in.ring, &entity);
1337         if (r) {
1338                 amdgpu_ctx_put(ctx);
1339                 return r;
1340         }
1341
1342         fence = amdgpu_ctx_get_fence(ctx, entity, wait->in.handle);
1343         if (IS_ERR(fence))
1344                 r = PTR_ERR(fence);
1345         else if (fence) {
1346                 r = dma_fence_wait_timeout(fence, true, timeout);
1347                 if (r > 0 && fence->error)
1348                         r = fence->error;
1349                 dma_fence_put(fence);
1350         } else
1351                 r = 1;
1352
1353         amdgpu_ctx_put(ctx);
1354         if (r < 0)
1355                 return r;
1356
1357         memset(wait, 0, sizeof(*wait));
1358         wait->out.status = (r == 0);
1359
1360         return 0;
1361 }
1362
1363 /**
1364  * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1365  *
1366  * @adev: amdgpu device
1367  * @filp: file private
1368  * @user: drm_amdgpu_fence copied from user space
1369  */
1370 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1371                                              struct drm_file *filp,
1372                                              struct drm_amdgpu_fence *user)
1373 {
1374         struct drm_sched_entity *entity;
1375         struct amdgpu_ctx *ctx;
1376         struct dma_fence *fence;
1377         int r;
1378
1379         ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1380         if (ctx == NULL)
1381                 return ERR_PTR(-EINVAL);
1382
1383         r = amdgpu_ctx_get_entity(ctx, user->ip_type, user->ip_instance,
1384                                   user->ring, &entity);
1385         if (r) {
1386                 amdgpu_ctx_put(ctx);
1387                 return ERR_PTR(r);
1388         }
1389
1390         fence = amdgpu_ctx_get_fence(ctx, entity, user->seq_no);
1391         amdgpu_ctx_put(ctx);
1392
1393         return fence;
1394 }
1395
1396 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1397                                     struct drm_file *filp)
1398 {
1399         struct amdgpu_device *adev = dev->dev_private;
1400         union drm_amdgpu_fence_to_handle *info = data;
1401         struct dma_fence *fence;
1402         struct drm_syncobj *syncobj;
1403         struct sync_file *sync_file;
1404         int fd, r;
1405
1406         fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1407         if (IS_ERR(fence))
1408                 return PTR_ERR(fence);
1409
1410         switch (info->in.what) {
1411         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1412                 r = drm_syncobj_create(&syncobj, 0, fence);
1413                 dma_fence_put(fence);
1414                 if (r)
1415                         return r;
1416                 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1417                 drm_syncobj_put(syncobj);
1418                 return r;
1419
1420         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1421                 r = drm_syncobj_create(&syncobj, 0, fence);
1422                 dma_fence_put(fence);
1423                 if (r)
1424                         return r;
1425                 r = drm_syncobj_get_fd(syncobj, (int*)&info->out.handle);
1426                 drm_syncobj_put(syncobj);
1427                 return r;
1428
1429         case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1430                 fd = get_unused_fd_flags(O_CLOEXEC);
1431                 if (fd < 0) {
1432                         dma_fence_put(fence);
1433                         return fd;
1434                 }
1435
1436                 sync_file = sync_file_create(fence);
1437                 dma_fence_put(fence);
1438                 if (!sync_file) {
1439                         put_unused_fd(fd);
1440                         return -ENOMEM;
1441                 }
1442
1443                 fd_install(fd, sync_file->file);
1444                 info->out.handle = fd;
1445                 return 0;
1446
1447         default:
1448                 return -EINVAL;
1449         }
1450 }
1451
1452 /**
1453  * amdgpu_cs_wait_all_fence - wait on all fences to signal
1454  *
1455  * @adev: amdgpu device
1456  * @filp: file private
1457  * @wait: wait parameters
1458  * @fences: array of drm_amdgpu_fence
1459  */
1460 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1461                                      struct drm_file *filp,
1462                                      union drm_amdgpu_wait_fences *wait,
1463                                      struct drm_amdgpu_fence *fences)
1464 {
1465         uint32_t fence_count = wait->in.fence_count;
1466         unsigned int i;
1467         long r = 1;
1468
1469         for (i = 0; i < fence_count; i++) {
1470                 struct dma_fence *fence;
1471                 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1472
1473                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1474                 if (IS_ERR(fence))
1475                         return PTR_ERR(fence);
1476                 else if (!fence)
1477                         continue;
1478
1479                 r = dma_fence_wait_timeout(fence, true, timeout);
1480                 dma_fence_put(fence);
1481                 if (r < 0)
1482                         return r;
1483
1484                 if (r == 0)
1485                         break;
1486
1487                 if (fence->error)
1488                         return fence->error;
1489         }
1490
1491         memset(wait, 0, sizeof(*wait));
1492         wait->out.status = (r > 0);
1493
1494         return 0;
1495 }
1496
1497 /**
1498  * amdgpu_cs_wait_any_fence - wait on any fence to signal
1499  *
1500  * @adev: amdgpu device
1501  * @filp: file private
1502  * @wait: wait parameters
1503  * @fences: array of drm_amdgpu_fence
1504  */
1505 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1506                                     struct drm_file *filp,
1507                                     union drm_amdgpu_wait_fences *wait,
1508                                     struct drm_amdgpu_fence *fences)
1509 {
1510         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1511         uint32_t fence_count = wait->in.fence_count;
1512         uint32_t first = ~0;
1513         struct dma_fence **array;
1514         unsigned int i;
1515         long r;
1516
1517         /* Prepare the fence array */
1518         array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1519
1520         if (array == NULL)
1521                 return -ENOMEM;
1522
1523         for (i = 0; i < fence_count; i++) {
1524                 struct dma_fence *fence;
1525
1526                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1527                 if (IS_ERR(fence)) {
1528                         r = PTR_ERR(fence);
1529                         goto err_free_fence_array;
1530                 } else if (fence) {
1531                         array[i] = fence;
1532                 } else { /* NULL, the fence has been already signaled */
1533                         r = 1;
1534                         first = i;
1535                         goto out;
1536                 }
1537         }
1538
1539         r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1540                                        &first);
1541         if (r < 0)
1542                 goto err_free_fence_array;
1543
1544 out:
1545         memset(wait, 0, sizeof(*wait));
1546         wait->out.status = (r > 0);
1547         wait->out.first_signaled = first;
1548
1549         if (first < fence_count && array[first])
1550                 r = array[first]->error;
1551         else
1552                 r = 0;
1553
1554 err_free_fence_array:
1555         for (i = 0; i < fence_count; i++)
1556                 dma_fence_put(array[i]);
1557         kfree(array);
1558
1559         return r;
1560 }
1561
1562 /**
1563  * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1564  *
1565  * @dev: drm device
1566  * @data: data from userspace
1567  * @filp: file private
1568  */
1569 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1570                                 struct drm_file *filp)
1571 {
1572         struct amdgpu_device *adev = dev->dev_private;
1573         union drm_amdgpu_wait_fences *wait = data;
1574         uint32_t fence_count = wait->in.fence_count;
1575         struct drm_amdgpu_fence *fences_user;
1576         struct drm_amdgpu_fence *fences;
1577         int r;
1578
1579         /* Get the fences from userspace */
1580         fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1581                         GFP_KERNEL);
1582         if (fences == NULL)
1583                 return -ENOMEM;
1584
1585         fences_user = u64_to_user_ptr(wait->in.fences);
1586         if (copy_from_user(fences, fences_user,
1587                 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1588                 r = -EFAULT;
1589                 goto err_free_fences;
1590         }
1591
1592         if (wait->in.wait_all)
1593                 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1594         else
1595                 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1596
1597 err_free_fences:
1598         kfree(fences);
1599
1600         return r;
1601 }
1602
1603 /**
1604  * amdgpu_cs_find_bo_va - find bo_va for VM address
1605  *
1606  * @parser: command submission parser context
1607  * @addr: VM address
1608  * @bo: resulting BO of the mapping found
1609  *
1610  * Search the buffer objects in the command submission context for a certain
1611  * virtual memory address. Returns allocation structure when found, NULL
1612  * otherwise.
1613  */
1614 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1615                            uint64_t addr, struct amdgpu_bo **bo,
1616                            struct amdgpu_bo_va_mapping **map)
1617 {
1618         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1619         struct ttm_operation_ctx ctx = { false, false };
1620         struct amdgpu_vm *vm = &fpriv->vm;
1621         struct amdgpu_bo_va_mapping *mapping;
1622         int r;
1623
1624         addr /= AMDGPU_GPU_PAGE_SIZE;
1625
1626         mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1627         if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1628                 return -EINVAL;
1629
1630         *bo = mapping->bo_va->base.bo;
1631         *map = mapping;
1632
1633         /* Double check that the BO is reserved by this CS */
1634         if (READ_ONCE((*bo)->tbo.resv->lock.ctx) != &parser->ticket)
1635                 return -EINVAL;
1636
1637         if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1638                 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1639                 amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);
1640                 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1641                 if (r)
1642                         return r;
1643         }
1644
1645         return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
1646 }