2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/kthread.h>
29 #include <linux/console.h>
30 #include <linux/slab.h>
31 #include <linux/debugfs.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/amdgpu_drm.h>
36 #include <linux/vgaarb.h>
37 #include <linux/vga_switcheroo.h>
38 #include <linux/efi.h>
40 #include "amdgpu_trace.h"
41 #include "amdgpu_i2c.h"
43 #include "amdgpu_atombios.h"
44 #include "amdgpu_atomfirmware.h"
46 #ifdef CONFIG_DRM_AMDGPU_SI
49 #ifdef CONFIG_DRM_AMDGPU_CIK
54 #include "bif/bif_4_1_d.h"
55 #include <linux/pci.h>
56 #include <linux/firmware.h>
57 #include "amdgpu_vf_error.h"
59 #include "amdgpu_amdkfd.h"
60 #include "amdgpu_pm.h"
62 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
63 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
65 #define AMDGPU_RESUME_MS 2000
67 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
68 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
69 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev);
70 static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev);
72 static const char *amdgpu_asic_name[] = {
96 bool amdgpu_device_is_px(struct drm_device *dev)
98 struct amdgpu_device *adev = dev->dev_private;
100 if (adev->flags & AMD_IS_PX)
106 * MMIO register access helper functions.
108 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
113 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
114 return amdgpu_virt_kiq_rreg(adev, reg);
116 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
117 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
121 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
122 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
123 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
124 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
126 trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
130 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
133 trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
135 if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
136 adev->last_mm_index = v;
139 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
140 return amdgpu_virt_kiq_wreg(adev, reg, v);
142 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
143 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
147 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
148 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
149 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
150 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
153 if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
158 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
160 if ((reg * 4) < adev->rio_mem_size)
161 return ioread32(adev->rio_mem + (reg * 4));
163 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
164 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
168 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
170 if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
171 adev->last_mm_index = v;
174 if ((reg * 4) < adev->rio_mem_size)
175 iowrite32(v, adev->rio_mem + (reg * 4));
177 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
178 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
181 if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
187 * amdgpu_mm_rdoorbell - read a doorbell dword
189 * @adev: amdgpu_device pointer
190 * @index: doorbell index
192 * Returns the value in the doorbell aperture at the
193 * requested doorbell index (CIK).
195 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
197 if (index < adev->doorbell.num_doorbells) {
198 return readl(adev->doorbell.ptr + index);
200 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
206 * amdgpu_mm_wdoorbell - write a doorbell dword
208 * @adev: amdgpu_device pointer
209 * @index: doorbell index
212 * Writes @v to the doorbell aperture at the
213 * requested doorbell index (CIK).
215 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
217 if (index < adev->doorbell.num_doorbells) {
218 writel(v, adev->doorbell.ptr + index);
220 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
225 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
227 * @adev: amdgpu_device pointer
228 * @index: doorbell index
230 * Returns the value in the doorbell aperture at the
231 * requested doorbell index (VEGA10+).
233 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
235 if (index < adev->doorbell.num_doorbells) {
236 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
238 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
244 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
246 * @adev: amdgpu_device pointer
247 * @index: doorbell index
250 * Writes @v to the doorbell aperture at the
251 * requested doorbell index (VEGA10+).
253 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
255 if (index < adev->doorbell.num_doorbells) {
256 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
258 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
263 * amdgpu_invalid_rreg - dummy reg read function
265 * @adev: amdgpu device pointer
266 * @reg: offset of register
268 * Dummy register read function. Used for register blocks
269 * that certain asics don't have (all asics).
270 * Returns the value in the register.
272 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
274 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
280 * amdgpu_invalid_wreg - dummy reg write function
282 * @adev: amdgpu device pointer
283 * @reg: offset of register
284 * @v: value to write to the register
286 * Dummy register read function. Used for register blocks
287 * that certain asics don't have (all asics).
289 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
291 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
297 * amdgpu_block_invalid_rreg - dummy reg read function
299 * @adev: amdgpu device pointer
300 * @block: offset of instance
301 * @reg: offset of register
303 * Dummy register read function. Used for register blocks
304 * that certain asics don't have (all asics).
305 * Returns the value in the register.
307 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
308 uint32_t block, uint32_t reg)
310 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
317 * amdgpu_block_invalid_wreg - dummy reg write function
319 * @adev: amdgpu device pointer
320 * @block: offset of instance
321 * @reg: offset of register
322 * @v: value to write to the register
324 * Dummy register read function. Used for register blocks
325 * that certain asics don't have (all asics).
327 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
329 uint32_t reg, uint32_t v)
331 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
336 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
338 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
339 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
340 &adev->vram_scratch.robj,
341 &adev->vram_scratch.gpu_addr,
342 (void **)&adev->vram_scratch.ptr);
345 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
347 amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
351 * amdgpu_program_register_sequence - program an array of registers.
353 * @adev: amdgpu_device pointer
354 * @registers: pointer to the register array
355 * @array_size: size of the register array
357 * Programs an array or registers with and and or masks.
358 * This is a helper for setting golden registers.
360 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
361 const u32 *registers,
362 const u32 array_size)
364 u32 tmp, reg, and_mask, or_mask;
370 for (i = 0; i < array_size; i +=3) {
371 reg = registers[i + 0];
372 and_mask = registers[i + 1];
373 or_mask = registers[i + 2];
375 if (and_mask == 0xffffffff) {
386 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
388 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
392 * GPU doorbell aperture helpers function.
395 * amdgpu_doorbell_init - Init doorbell driver information.
397 * @adev: amdgpu_device pointer
399 * Init doorbell driver information (CIK)
400 * Returns 0 on success, error on failure.
402 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
404 /* No doorbell on SI hardware generation */
405 if (adev->asic_type < CHIP_BONAIRE) {
406 adev->doorbell.base = 0;
407 adev->doorbell.size = 0;
408 adev->doorbell.num_doorbells = 0;
409 adev->doorbell.ptr = NULL;
413 if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
416 /* doorbell bar mapping */
417 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
418 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
420 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
421 AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
422 if (adev->doorbell.num_doorbells == 0)
425 adev->doorbell.ptr = ioremap(adev->doorbell.base,
426 adev->doorbell.num_doorbells *
428 if (adev->doorbell.ptr == NULL)
435 * amdgpu_doorbell_fini - Tear down doorbell driver information.
437 * @adev: amdgpu_device pointer
439 * Tear down doorbell driver information (CIK)
441 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
443 iounmap(adev->doorbell.ptr);
444 adev->doorbell.ptr = NULL;
448 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
451 * @adev: amdgpu_device pointer
452 * @aperture_base: output returning doorbell aperture base physical address
453 * @aperture_size: output returning doorbell aperture size in bytes
454 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
456 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
457 * takes doorbells required for its own rings and reports the setup to amdkfd.
458 * amdgpu reserved doorbells are at the start of the doorbell aperture.
460 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
461 phys_addr_t *aperture_base,
462 size_t *aperture_size,
463 size_t *start_offset)
466 * The first num_doorbells are used by amdgpu.
467 * amdkfd takes whatever's left in the aperture.
469 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
470 *aperture_base = adev->doorbell.base;
471 *aperture_size = adev->doorbell.size;
472 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
482 * Writeback is the method by which the GPU updates special pages in memory
483 * with the status of certain GPU events (fences, ring pointers,etc.).
487 * amdgpu_wb_fini - Disable Writeback and free memory
489 * @adev: amdgpu_device pointer
491 * Disables Writeback and frees the Writeback memory (all asics).
492 * Used at driver shutdown.
494 static void amdgpu_wb_fini(struct amdgpu_device *adev)
496 if (adev->wb.wb_obj) {
497 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
499 (void **)&adev->wb.wb);
500 adev->wb.wb_obj = NULL;
505 * amdgpu_wb_init- Init Writeback driver info and allocate memory
507 * @adev: amdgpu_device pointer
509 * Initializes writeback and allocates writeback memory (all asics).
510 * Used at driver startup.
511 * Returns 0 on success or an -error on failure.
513 static int amdgpu_wb_init(struct amdgpu_device *adev)
517 if (adev->wb.wb_obj == NULL) {
518 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
519 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
520 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
521 &adev->wb.wb_obj, &adev->wb.gpu_addr,
522 (void **)&adev->wb.wb);
524 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
528 adev->wb.num_wb = AMDGPU_MAX_WB;
529 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
531 /* clear wb memory */
532 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t));
539 * amdgpu_wb_get - Allocate a wb entry
541 * @adev: amdgpu_device pointer
544 * Allocate a wb slot for use by the driver (all asics).
545 * Returns 0 on success or -EINVAL on failure.
547 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
549 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
551 if (offset < adev->wb.num_wb) {
552 __set_bit(offset, adev->wb.used);
553 *wb = offset << 3; /* convert to dw offset */
561 * amdgpu_wb_free - Free a wb entry
563 * @adev: amdgpu_device pointer
566 * Free a wb slot allocated for use by the driver (all asics)
568 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
570 if (wb < adev->wb.num_wb)
571 __clear_bit(wb >> 3, adev->wb.used);
575 * amdgpu_vram_location - try to find VRAM location
576 * @adev: amdgpu device structure holding all necessary informations
577 * @mc: memory controller structure holding memory informations
578 * @base: base address at which to put VRAM
580 * Function will try to place VRAM at base address provided
581 * as parameter (which is so far either PCI aperture address or
582 * for IGP TOM base address).
584 * If there is not enough space to fit the unvisible VRAM in the 32bits
585 * address space then we limit the VRAM size to the aperture.
587 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
588 * this shouldn't be a problem as we are using the PCI aperture as a reference.
589 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
592 * Note: we use mc_vram_size as on some board we need to program the mc to
593 * cover the whole aperture even if VRAM size is inferior to aperture size
594 * Novell bug 204882 + along with lots of ubuntu ones
596 * Note: when limiting vram it's safe to overwritte real_vram_size because
597 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
598 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
601 * Note: IGP TOM addr should be the same as the aperture addr, we don't
602 * explicitly check for that though.
604 * FIXME: when reducing VRAM size align new size on power of 2.
606 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
608 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
610 mc->vram_start = base;
611 if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
612 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
613 mc->real_vram_size = mc->aper_size;
614 mc->mc_vram_size = mc->aper_size;
616 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
617 if (limit && limit < mc->real_vram_size)
618 mc->real_vram_size = limit;
619 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
620 mc->mc_vram_size >> 20, mc->vram_start,
621 mc->vram_end, mc->real_vram_size >> 20);
625 * amdgpu_gart_location - try to find GTT location
626 * @adev: amdgpu device structure holding all necessary informations
627 * @mc: memory controller structure holding memory informations
629 * Function will place try to place GTT before or after VRAM.
631 * If GTT size is bigger than space left then we ajust GTT size.
632 * Thus function will never fails.
634 * FIXME: when reducing GTT size align new size on power of 2.
636 void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
638 u64 size_af, size_bf;
640 size_af = adev->mc.mc_mask - mc->vram_end;
641 size_bf = mc->vram_start;
642 if (size_bf > size_af) {
643 if (mc->gart_size > size_bf) {
644 dev_warn(adev->dev, "limiting GTT\n");
645 mc->gart_size = size_bf;
649 if (mc->gart_size > size_af) {
650 dev_warn(adev->dev, "limiting GTT\n");
651 mc->gart_size = size_af;
653 mc->gart_start = mc->vram_end + 1;
655 mc->gart_end = mc->gart_start + mc->gart_size - 1;
656 dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
657 mc->gart_size >> 20, mc->gart_start, mc->gart_end);
661 * Firmware Reservation functions
664 * amdgpu_fw_reserve_vram_fini - free fw reserved vram
666 * @adev: amdgpu_device pointer
668 * free fw reserved vram if it has been reserved.
670 void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev)
672 amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
673 NULL, &adev->fw_vram_usage.va);
677 * amdgpu_fw_reserve_vram_init - create bo vram reservation from fw
679 * @adev: amdgpu_device pointer
681 * create bo vram reservation from fw.
683 int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev)
687 u64 vram_size = adev->mc.visible_vram_size;
688 u64 offset = adev->fw_vram_usage.start_offset;
689 u64 size = adev->fw_vram_usage.size;
690 struct amdgpu_bo *bo;
692 adev->fw_vram_usage.va = NULL;
693 adev->fw_vram_usage.reserved_bo = NULL;
695 if (adev->fw_vram_usage.size > 0 &&
696 adev->fw_vram_usage.size <= vram_size) {
698 r = amdgpu_bo_create(adev, adev->fw_vram_usage.size,
699 PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
700 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
701 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, 0,
702 &adev->fw_vram_usage.reserved_bo);
706 r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
710 /* remove the original mem node and create a new one at the
713 bo = adev->fw_vram_usage.reserved_bo;
714 offset = ALIGN(offset, PAGE_SIZE);
715 for (i = 0; i < bo->placement.num_placement; ++i) {
716 bo->placements[i].fpfn = offset >> PAGE_SHIFT;
717 bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
720 ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
721 r = ttm_bo_mem_space(&bo->tbo, &bo->placement, &bo->tbo.mem,
726 r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
727 AMDGPU_GEM_DOMAIN_VRAM,
728 adev->fw_vram_usage.start_offset,
729 (adev->fw_vram_usage.start_offset +
730 adev->fw_vram_usage.size), NULL);
733 r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
734 &adev->fw_vram_usage.va);
738 amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
743 amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
745 amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
747 amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
749 adev->fw_vram_usage.va = NULL;
750 adev->fw_vram_usage.reserved_bo = NULL;
755 * amdgpu_device_resize_fb_bar - try to resize FB BAR
757 * @adev: amdgpu_device pointer
759 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
760 * to fail, but if any of the BARs is not accessible after the size we abort
761 * driver loading by returning -ENODEV.
763 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
765 u64 space_needed = roundup_pow_of_two(adev->mc.real_vram_size);
766 u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
771 if (amdgpu_sriov_vf(adev))
774 /* Disable memory decoding while we change the BAR addresses and size */
775 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
776 pci_write_config_word(adev->pdev, PCI_COMMAND,
777 cmd & ~PCI_COMMAND_MEMORY);
779 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
780 amdgpu_doorbell_fini(adev);
781 if (adev->asic_type >= CHIP_BONAIRE)
782 pci_release_resource(adev->pdev, 2);
784 pci_release_resource(adev->pdev, 0);
786 r = pci_resize_resource(adev->pdev, 0, rbar_size);
788 DRM_INFO("Not enough PCI address space for a large BAR.");
789 else if (r && r != -ENOTSUPP)
790 DRM_ERROR("Problem resizing BAR0 (%d).", r);
792 pci_assign_unassigned_bus_resources(adev->pdev->bus);
794 /* When the doorbell or fb BAR isn't available we have no chance of
797 r = amdgpu_doorbell_init(adev);
798 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
801 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
807 * GPU helpers function.
810 * amdgpu_need_post - check if the hw need post or not
812 * @adev: amdgpu_device pointer
814 * Check if the asic has been initialized (all asics) at driver startup
815 * or post is needed if hw reset is performed.
816 * Returns true if need or false if not.
818 bool amdgpu_need_post(struct amdgpu_device *adev)
822 if (amdgpu_sriov_vf(adev))
825 if (amdgpu_passthrough(adev)) {
826 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
827 * some old smc fw still need driver do vPost otherwise gpu hang, while
828 * those smc fw version above 22.15 doesn't have this flaw, so we force
829 * vpost executed for smc version below 22.15
831 if (adev->asic_type == CHIP_FIJI) {
834 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
835 /* force vPost if error occured */
839 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
840 if (fw_ver < 0x00160e00)
845 if (adev->has_hw_reset) {
846 adev->has_hw_reset = false;
850 /* bios scratch used on CIK+ */
851 if (adev->asic_type >= CHIP_BONAIRE)
852 return amdgpu_atombios_scratch_need_asic_init(adev);
854 /* check MEM_SIZE for older asics */
855 reg = amdgpu_asic_get_config_memsize(adev);
857 if ((reg != 0) && (reg != 0xffffffff))
864 * amdgpu_dummy_page_init - init dummy page used by the driver
866 * @adev: amdgpu_device pointer
868 * Allocate the dummy page used by the driver (all asics).
869 * This dummy page is used by the driver as a filler for gart entries
870 * when pages are taken out of the GART
871 * Returns 0 on sucess, -ENOMEM on failure.
873 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
875 if (adev->dummy_page.page)
877 adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
878 if (adev->dummy_page.page == NULL)
880 adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
881 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
882 if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
883 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
884 __free_page(adev->dummy_page.page);
885 adev->dummy_page.page = NULL;
892 * amdgpu_dummy_page_fini - free dummy page used by the driver
894 * @adev: amdgpu_device pointer
896 * Frees the dummy page used by the driver (all asics).
898 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
900 if (adev->dummy_page.page == NULL)
902 pci_unmap_page(adev->pdev, adev->dummy_page.addr,
903 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
904 __free_page(adev->dummy_page.page);
905 adev->dummy_page.page = NULL;
909 /* ATOM accessor methods */
911 * ATOM is an interpreted byte code stored in tables in the vbios. The
912 * driver registers callbacks to access registers and the interpreter
913 * in the driver parses the tables and executes then to program specific
914 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
915 * atombios.h, and atom.c
919 * cail_pll_read - read PLL register
921 * @info: atom card_info pointer
922 * @reg: PLL register offset
924 * Provides a PLL register accessor for the atom interpreter (r4xx+).
925 * Returns the value of the PLL register.
927 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
933 * cail_pll_write - write PLL register
935 * @info: atom card_info pointer
936 * @reg: PLL register offset
937 * @val: value to write to the pll register
939 * Provides a PLL register accessor for the atom interpreter (r4xx+).
941 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
947 * cail_mc_read - read MC (Memory Controller) register
949 * @info: atom card_info pointer
950 * @reg: MC register offset
952 * Provides an MC register accessor for the atom interpreter (r4xx+).
953 * Returns the value of the MC register.
955 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
961 * cail_mc_write - write MC (Memory Controller) register
963 * @info: atom card_info pointer
964 * @reg: MC register offset
965 * @val: value to write to the pll register
967 * Provides a MC register accessor for the atom interpreter (r4xx+).
969 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
975 * cail_reg_write - write MMIO register
977 * @info: atom card_info pointer
978 * @reg: MMIO register offset
979 * @val: value to write to the pll register
981 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
983 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
985 struct amdgpu_device *adev = info->dev->dev_private;
991 * cail_reg_read - read MMIO register
993 * @info: atom card_info pointer
994 * @reg: MMIO register offset
996 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
997 * Returns the value of the MMIO register.
999 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
1001 struct amdgpu_device *adev = info->dev->dev_private;
1009 * cail_ioreg_write - write IO register
1011 * @info: atom card_info pointer
1012 * @reg: IO register offset
1013 * @val: value to write to the pll register
1015 * Provides a IO register accessor for the atom interpreter (r4xx+).
1017 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
1019 struct amdgpu_device *adev = info->dev->dev_private;
1021 WREG32_IO(reg, val);
1025 * cail_ioreg_read - read IO register
1027 * @info: atom card_info pointer
1028 * @reg: IO register offset
1030 * Provides an IO register accessor for the atom interpreter (r4xx+).
1031 * Returns the value of the IO register.
1033 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
1035 struct amdgpu_device *adev = info->dev->dev_private;
1042 static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev,
1043 struct device_attribute *attr,
1046 struct drm_device *ddev = dev_get_drvdata(dev);
1047 struct amdgpu_device *adev = ddev->dev_private;
1048 struct atom_context *ctx = adev->mode_info.atom_context;
1050 return snprintf(buf, PAGE_SIZE, "%s\n", ctx->vbios_version);
1053 static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version,
1057 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
1059 * @adev: amdgpu_device pointer
1061 * Frees the driver info and register access callbacks for the ATOM
1062 * interpreter (r4xx+).
1063 * Called at driver shutdown.
1065 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
1067 if (adev->mode_info.atom_context) {
1068 kfree(adev->mode_info.atom_context->scratch);
1069 kfree(adev->mode_info.atom_context->iio);
1071 kfree(adev->mode_info.atom_context);
1072 adev->mode_info.atom_context = NULL;
1073 kfree(adev->mode_info.atom_card_info);
1074 adev->mode_info.atom_card_info = NULL;
1075 device_remove_file(adev->dev, &dev_attr_vbios_version);
1079 * amdgpu_atombios_init - init the driver info and callbacks for atombios
1081 * @adev: amdgpu_device pointer
1083 * Initializes the driver info and register access callbacks for the
1084 * ATOM interpreter (r4xx+).
1085 * Returns 0 on sucess, -ENOMEM on failure.
1086 * Called at driver startup.
1088 static int amdgpu_atombios_init(struct amdgpu_device *adev)
1090 struct card_info *atom_card_info =
1091 kzalloc(sizeof(struct card_info), GFP_KERNEL);
1094 if (!atom_card_info)
1097 adev->mode_info.atom_card_info = atom_card_info;
1098 atom_card_info->dev = adev->ddev;
1099 atom_card_info->reg_read = cail_reg_read;
1100 atom_card_info->reg_write = cail_reg_write;
1101 /* needed for iio ops */
1102 if (adev->rio_mem) {
1103 atom_card_info->ioreg_read = cail_ioreg_read;
1104 atom_card_info->ioreg_write = cail_ioreg_write;
1106 DRM_DEBUG("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n");
1107 atom_card_info->ioreg_read = cail_reg_read;
1108 atom_card_info->ioreg_write = cail_reg_write;
1110 atom_card_info->mc_read = cail_mc_read;
1111 atom_card_info->mc_write = cail_mc_write;
1112 atom_card_info->pll_read = cail_pll_read;
1113 atom_card_info->pll_write = cail_pll_write;
1115 adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
1116 if (!adev->mode_info.atom_context) {
1117 amdgpu_atombios_fini(adev);
1121 mutex_init(&adev->mode_info.atom_context->mutex);
1122 if (adev->is_atom_fw) {
1123 amdgpu_atomfirmware_scratch_regs_init(adev);
1124 amdgpu_atomfirmware_allocate_fb_scratch(adev);
1126 amdgpu_atombios_scratch_regs_init(adev);
1127 amdgpu_atombios_allocate_fb_scratch(adev);
1130 ret = device_create_file(adev->dev, &dev_attr_vbios_version);
1132 DRM_ERROR("Failed to create device file for VBIOS version\n");
1139 /* if we get transitioned to only one device, take VGA back */
1141 * amdgpu_vga_set_decode - enable/disable vga decode
1143 * @cookie: amdgpu_device pointer
1144 * @state: enable/disable vga decode
1146 * Enable/disable vga decode (all asics).
1147 * Returns VGA resource flags.
1149 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
1151 struct amdgpu_device *adev = cookie;
1152 amdgpu_asic_set_vga_state(adev, state);
1154 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1155 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1157 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1160 static void amdgpu_check_block_size(struct amdgpu_device *adev)
1162 /* defines number of bits in page table versus page directory,
1163 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1164 * page table and the remaining bits are in the page directory */
1165 if (amdgpu_vm_block_size == -1)
1168 if (amdgpu_vm_block_size < 9) {
1169 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1170 amdgpu_vm_block_size);
1174 if (amdgpu_vm_block_size > 24 ||
1175 (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1176 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1177 amdgpu_vm_block_size);
1184 amdgpu_vm_block_size = -1;
1187 static void amdgpu_check_vm_size(struct amdgpu_device *adev)
1189 /* no need to check the default value */
1190 if (amdgpu_vm_size == -1)
1193 if (!is_power_of_2(amdgpu_vm_size)) {
1194 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
1199 if (amdgpu_vm_size < 1) {
1200 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1206 * Max GPUVM size for Cayman, SI, CI VI are 40 bits.
1208 if (amdgpu_vm_size > 1024) {
1209 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
1217 amdgpu_vm_size = -1;
1221 * amdgpu_check_arguments - validate module params
1223 * @adev: amdgpu_device pointer
1225 * Validates certain module parameters and updates
1226 * the associated values used by the driver (all asics).
1228 static void amdgpu_check_arguments(struct amdgpu_device *adev)
1230 if (amdgpu_sched_jobs < 4) {
1231 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1233 amdgpu_sched_jobs = 4;
1234 } else if (!is_power_of_2(amdgpu_sched_jobs)){
1235 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1237 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1240 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1241 /* gart size must be greater or equal to 32M */
1242 dev_warn(adev->dev, "gart size (%d) too small\n",
1244 amdgpu_gart_size = -1;
1247 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1248 /* gtt size must be greater or equal to 32M */
1249 dev_warn(adev->dev, "gtt size (%d) too small\n",
1251 amdgpu_gtt_size = -1;
1254 /* valid range is between 4 and 9 inclusive */
1255 if (amdgpu_vm_fragment_size != -1 &&
1256 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1257 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1258 amdgpu_vm_fragment_size = -1;
1261 amdgpu_check_vm_size(adev);
1263 amdgpu_check_block_size(adev);
1265 if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
1266 !is_power_of_2(amdgpu_vram_page_split))) {
1267 dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
1268 amdgpu_vram_page_split);
1269 amdgpu_vram_page_split = 1024;
1274 * amdgpu_switcheroo_set_state - set switcheroo state
1276 * @pdev: pci dev pointer
1277 * @state: vga_switcheroo state
1279 * Callback for the switcheroo driver. Suspends or resumes the
1280 * the asics before or after it is powered up using ACPI methods.
1282 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1284 struct drm_device *dev = pci_get_drvdata(pdev);
1286 if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1289 if (state == VGA_SWITCHEROO_ON) {
1290 pr_info("amdgpu: switched on\n");
1291 /* don't suspend or resume card normally */
1292 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1294 amdgpu_device_resume(dev, true, true);
1296 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1297 drm_kms_helper_poll_enable(dev);
1299 pr_info("amdgpu: switched off\n");
1300 drm_kms_helper_poll_disable(dev);
1301 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1302 amdgpu_device_suspend(dev, true, true);
1303 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1308 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1310 * @pdev: pci dev pointer
1312 * Callback for the switcheroo driver. Check of the switcheroo
1313 * state can be changed.
1314 * Returns true if the state can be changed, false if not.
1316 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1318 struct drm_device *dev = pci_get_drvdata(pdev);
1321 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1322 * locking inversion with the driver load path. And the access here is
1323 * completely racy anyway. So don't bother with locking for now.
1325 return dev->open_count == 0;
1328 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1329 .set_gpu_state = amdgpu_switcheroo_set_state,
1331 .can_switch = amdgpu_switcheroo_can_switch,
1334 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1335 enum amd_ip_block_type block_type,
1336 enum amd_clockgating_state state)
1340 for (i = 0; i < adev->num_ip_blocks; i++) {
1341 if (!adev->ip_blocks[i].status.valid)
1343 if (adev->ip_blocks[i].version->type != block_type)
1345 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1347 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1348 (void *)adev, state);
1350 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1351 adev->ip_blocks[i].version->funcs->name, r);
1356 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1357 enum amd_ip_block_type block_type,
1358 enum amd_powergating_state state)
1362 for (i = 0; i < adev->num_ip_blocks; i++) {
1363 if (!adev->ip_blocks[i].status.valid)
1365 if (adev->ip_blocks[i].version->type != block_type)
1367 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1369 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1370 (void *)adev, state);
1372 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1373 adev->ip_blocks[i].version->funcs->name, r);
1378 void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)
1382 for (i = 0; i < adev->num_ip_blocks; i++) {
1383 if (!adev->ip_blocks[i].status.valid)
1385 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1386 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1390 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
1391 enum amd_ip_block_type block_type)
1395 for (i = 0; i < adev->num_ip_blocks; i++) {
1396 if (!adev->ip_blocks[i].status.valid)
1398 if (adev->ip_blocks[i].version->type == block_type) {
1399 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1409 bool amdgpu_is_idle(struct amdgpu_device *adev,
1410 enum amd_ip_block_type block_type)
1414 for (i = 0; i < adev->num_ip_blocks; i++) {
1415 if (!adev->ip_blocks[i].status.valid)
1417 if (adev->ip_blocks[i].version->type == block_type)
1418 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1424 struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
1425 enum amd_ip_block_type type)
1429 for (i = 0; i < adev->num_ip_blocks; i++)
1430 if (adev->ip_blocks[i].version->type == type)
1431 return &adev->ip_blocks[i];
1437 * amdgpu_ip_block_version_cmp
1439 * @adev: amdgpu_device pointer
1440 * @type: enum amd_ip_block_type
1441 * @major: major version
1442 * @minor: minor version
1444 * return 0 if equal or greater
1445 * return 1 if smaller or the ip_block doesn't exist
1447 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1448 enum amd_ip_block_type type,
1449 u32 major, u32 minor)
1451 struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type);
1453 if (ip_block && ((ip_block->version->major > major) ||
1454 ((ip_block->version->major == major) &&
1455 (ip_block->version->minor >= minor))))
1462 * amdgpu_ip_block_add
1464 * @adev: amdgpu_device pointer
1465 * @ip_block_version: pointer to the IP to add
1467 * Adds the IP block driver information to the collection of IPs
1470 int amdgpu_ip_block_add(struct amdgpu_device *adev,
1471 const struct amdgpu_ip_block_version *ip_block_version)
1473 if (!ip_block_version)
1476 DRM_DEBUG("add ip block number %d <%s>\n", adev->num_ip_blocks,
1477 ip_block_version->funcs->name);
1479 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1484 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1486 adev->enable_virtual_display = false;
1488 if (amdgpu_virtual_display) {
1489 struct drm_device *ddev = adev->ddev;
1490 const char *pci_address_name = pci_name(ddev->pdev);
1491 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1493 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1494 pciaddstr_tmp = pciaddstr;
1495 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1496 pciaddname = strsep(&pciaddname_tmp, ",");
1497 if (!strcmp("all", pciaddname)
1498 || !strcmp(pci_address_name, pciaddname)) {
1502 adev->enable_virtual_display = true;
1505 res = kstrtol(pciaddname_tmp, 10,
1513 adev->mode_info.num_crtc = num_crtc;
1515 adev->mode_info.num_crtc = 1;
1521 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1522 amdgpu_virtual_display, pci_address_name,
1523 adev->enable_virtual_display, adev->mode_info.num_crtc);
1529 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1531 const char *chip_name;
1534 const struct gpu_info_firmware_header_v1_0 *hdr;
1536 adev->firmware.gpu_info_fw = NULL;
1538 switch (adev->asic_type) {
1542 case CHIP_POLARIS11:
1543 case CHIP_POLARIS10:
1544 case CHIP_POLARIS12:
1547 #ifdef CONFIG_DRM_AMDGPU_SI
1554 #ifdef CONFIG_DRM_AMDGPU_CIK
1564 chip_name = "vega10";
1567 chip_name = "raven";
1571 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1572 err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1575 "Failed to load gpu_info firmware \"%s\"\n",
1579 err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1582 "Failed to validate gpu_info firmware \"%s\"\n",
1587 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1588 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1590 switch (hdr->version_major) {
1593 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1594 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1595 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1597 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1598 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1599 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1600 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1601 adev->gfx.config.max_texture_channel_caches =
1602 le32_to_cpu(gpu_info_fw->gc_num_tccs);
1603 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1604 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1605 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1606 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1607 adev->gfx.config.double_offchip_lds_buf =
1608 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1609 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1610 adev->gfx.cu_info.max_waves_per_simd =
1611 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1612 adev->gfx.cu_info.max_scratch_slots_per_cu =
1613 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1614 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1619 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1627 static int amdgpu_early_init(struct amdgpu_device *adev)
1631 amdgpu_device_enable_virtual_display(adev);
1633 switch (adev->asic_type) {
1637 case CHIP_POLARIS11:
1638 case CHIP_POLARIS10:
1639 case CHIP_POLARIS12:
1642 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1643 adev->family = AMDGPU_FAMILY_CZ;
1645 adev->family = AMDGPU_FAMILY_VI;
1647 r = vi_set_ip_blocks(adev);
1651 #ifdef CONFIG_DRM_AMDGPU_SI
1657 adev->family = AMDGPU_FAMILY_SI;
1658 r = si_set_ip_blocks(adev);
1663 #ifdef CONFIG_DRM_AMDGPU_CIK
1669 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1670 adev->family = AMDGPU_FAMILY_CI;
1672 adev->family = AMDGPU_FAMILY_KV;
1674 r = cik_set_ip_blocks(adev);
1681 if (adev->asic_type == CHIP_RAVEN)
1682 adev->family = AMDGPU_FAMILY_RV;
1684 adev->family = AMDGPU_FAMILY_AI;
1686 r = soc15_set_ip_blocks(adev);
1691 /* FIXME: not supported yet */
1695 r = amdgpu_device_parse_gpu_info_fw(adev);
1699 amdgpu_amdkfd_device_probe(adev);
1701 if (amdgpu_sriov_vf(adev)) {
1702 r = amdgpu_virt_request_full_gpu(adev, true);
1707 for (i = 0; i < adev->num_ip_blocks; i++) {
1708 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1709 DRM_ERROR("disabled ip block: %d <%s>\n",
1710 i, adev->ip_blocks[i].version->funcs->name);
1711 adev->ip_blocks[i].status.valid = false;
1713 if (adev->ip_blocks[i].version->funcs->early_init) {
1714 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1716 adev->ip_blocks[i].status.valid = false;
1718 DRM_ERROR("early_init of IP block <%s> failed %d\n",
1719 adev->ip_blocks[i].version->funcs->name, r);
1722 adev->ip_blocks[i].status.valid = true;
1725 adev->ip_blocks[i].status.valid = true;
1730 adev->cg_flags &= amdgpu_cg_mask;
1731 adev->pg_flags &= amdgpu_pg_mask;
1736 static int amdgpu_init(struct amdgpu_device *adev)
1740 for (i = 0; i < adev->num_ip_blocks; i++) {
1741 if (!adev->ip_blocks[i].status.valid)
1743 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1745 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1746 adev->ip_blocks[i].version->funcs->name, r);
1749 adev->ip_blocks[i].status.sw = true;
1750 /* need to do gmc hw init early so we can allocate gpu mem */
1751 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1752 r = amdgpu_vram_scratch_init(adev);
1754 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1757 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1759 DRM_ERROR("hw_init %d failed %d\n", i, r);
1762 r = amdgpu_wb_init(adev);
1764 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1767 adev->ip_blocks[i].status.hw = true;
1769 /* right after GMC hw init, we create CSA */
1770 if (amdgpu_sriov_vf(adev)) {
1771 r = amdgpu_allocate_static_csa(adev);
1773 DRM_ERROR("allocate CSA failed %d\n", r);
1780 for (i = 0; i < adev->num_ip_blocks; i++) {
1781 if (!adev->ip_blocks[i].status.sw)
1783 /* gmc hw init is done early */
1784 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC)
1786 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1788 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1789 adev->ip_blocks[i].version->funcs->name, r);
1792 adev->ip_blocks[i].status.hw = true;
1795 amdgpu_amdkfd_device_init(adev);
1797 if (amdgpu_sriov_vf(adev))
1798 amdgpu_virt_release_full_gpu(adev, true);
1803 static void amdgpu_fill_reset_magic(struct amdgpu_device *adev)
1805 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
1808 static bool amdgpu_check_vram_lost(struct amdgpu_device *adev)
1810 return !!memcmp(adev->gart.ptr, adev->reset_magic,
1811 AMDGPU_RESET_MAGIC_NUM);
1814 static int amdgpu_late_set_cg_state(struct amdgpu_device *adev)
1818 for (i = 0; i < adev->num_ip_blocks; i++) {
1819 if (!adev->ip_blocks[i].status.valid)
1821 /* skip CG for VCE/UVD, it's handled specially */
1822 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1823 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1824 /* enable clockgating to save power */
1825 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1828 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1829 adev->ip_blocks[i].version->funcs->name, r);
1837 static int amdgpu_late_init(struct amdgpu_device *adev)
1841 for (i = 0; i < adev->num_ip_blocks; i++) {
1842 if (!adev->ip_blocks[i].status.valid)
1844 if (adev->ip_blocks[i].version->funcs->late_init) {
1845 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1847 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1848 adev->ip_blocks[i].version->funcs->name, r);
1851 adev->ip_blocks[i].status.late_initialized = true;
1855 mod_delayed_work(system_wq, &adev->late_init_work,
1856 msecs_to_jiffies(AMDGPU_RESUME_MS));
1858 amdgpu_fill_reset_magic(adev);
1863 static int amdgpu_fini(struct amdgpu_device *adev)
1867 amdgpu_amdkfd_device_fini(adev);
1868 /* need to disable SMC first */
1869 for (i = 0; i < adev->num_ip_blocks; i++) {
1870 if (!adev->ip_blocks[i].status.hw)
1872 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
1873 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1874 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1875 AMD_CG_STATE_UNGATE);
1877 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1878 adev->ip_blocks[i].version->funcs->name, r);
1881 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1882 /* XXX handle errors */
1884 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1885 adev->ip_blocks[i].version->funcs->name, r);
1887 adev->ip_blocks[i].status.hw = false;
1892 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1893 if (!adev->ip_blocks[i].status.hw)
1895 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1896 amdgpu_free_static_csa(adev);
1897 amdgpu_wb_fini(adev);
1898 amdgpu_vram_scratch_fini(adev);
1901 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1902 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1903 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1904 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1905 AMD_CG_STATE_UNGATE);
1907 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1908 adev->ip_blocks[i].version->funcs->name, r);
1913 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1914 /* XXX handle errors */
1916 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1917 adev->ip_blocks[i].version->funcs->name, r);
1920 adev->ip_blocks[i].status.hw = false;
1923 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1924 if (!adev->ip_blocks[i].status.sw)
1926 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
1927 /* XXX handle errors */
1929 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1930 adev->ip_blocks[i].version->funcs->name, r);
1932 adev->ip_blocks[i].status.sw = false;
1933 adev->ip_blocks[i].status.valid = false;
1936 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1937 if (!adev->ip_blocks[i].status.late_initialized)
1939 if (adev->ip_blocks[i].version->funcs->late_fini)
1940 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
1941 adev->ip_blocks[i].status.late_initialized = false;
1944 if (amdgpu_sriov_vf(adev))
1945 if (amdgpu_virt_release_full_gpu(adev, false))
1946 DRM_ERROR("failed to release exclusive mode on fini\n");
1951 static void amdgpu_late_init_func_handler(struct work_struct *work)
1953 struct amdgpu_device *adev =
1954 container_of(work, struct amdgpu_device, late_init_work.work);
1955 amdgpu_late_set_cg_state(adev);
1958 int amdgpu_suspend(struct amdgpu_device *adev)
1962 if (amdgpu_sriov_vf(adev))
1963 amdgpu_virt_request_full_gpu(adev, false);
1965 /* ungate SMC block first */
1966 r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1967 AMD_CG_STATE_UNGATE);
1969 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
1972 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1973 if (!adev->ip_blocks[i].status.valid)
1975 /* ungate blocks so that suspend can properly shut them down */
1976 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1977 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1978 AMD_CG_STATE_UNGATE);
1980 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1981 adev->ip_blocks[i].version->funcs->name, r);
1984 /* XXX handle errors */
1985 r = adev->ip_blocks[i].version->funcs->suspend(adev);
1986 /* XXX handle errors */
1988 DRM_ERROR("suspend of IP block <%s> failed %d\n",
1989 adev->ip_blocks[i].version->funcs->name, r);
1993 if (amdgpu_sriov_vf(adev))
1994 amdgpu_virt_release_full_gpu(adev, false);
1999 static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev)
2003 static enum amd_ip_block_type ip_order[] = {
2004 AMD_IP_BLOCK_TYPE_GMC,
2005 AMD_IP_BLOCK_TYPE_COMMON,
2006 AMD_IP_BLOCK_TYPE_IH,
2009 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2011 struct amdgpu_ip_block *block;
2013 for (j = 0; j < adev->num_ip_blocks; j++) {
2014 block = &adev->ip_blocks[j];
2016 if (block->version->type != ip_order[i] ||
2017 !block->status.valid)
2020 r = block->version->funcs->hw_init(adev);
2021 DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
2028 static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev)
2032 static enum amd_ip_block_type ip_order[] = {
2033 AMD_IP_BLOCK_TYPE_SMC,
2034 AMD_IP_BLOCK_TYPE_PSP,
2035 AMD_IP_BLOCK_TYPE_DCE,
2036 AMD_IP_BLOCK_TYPE_GFX,
2037 AMD_IP_BLOCK_TYPE_SDMA,
2038 AMD_IP_BLOCK_TYPE_UVD,
2039 AMD_IP_BLOCK_TYPE_VCE
2042 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2044 struct amdgpu_ip_block *block;
2046 for (j = 0; j < adev->num_ip_blocks; j++) {
2047 block = &adev->ip_blocks[j];
2049 if (block->version->type != ip_order[i] ||
2050 !block->status.valid)
2053 r = block->version->funcs->hw_init(adev);
2054 DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
2061 static int amdgpu_resume_phase1(struct amdgpu_device *adev)
2065 for (i = 0; i < adev->num_ip_blocks; i++) {
2066 if (!adev->ip_blocks[i].status.valid)
2068 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2069 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2070 adev->ip_blocks[i].version->type ==
2071 AMD_IP_BLOCK_TYPE_IH) {
2072 r = adev->ip_blocks[i].version->funcs->resume(adev);
2074 DRM_ERROR("resume of IP block <%s> failed %d\n",
2075 adev->ip_blocks[i].version->funcs->name, r);
2084 static int amdgpu_resume_phase2(struct amdgpu_device *adev)
2088 for (i = 0; i < adev->num_ip_blocks; i++) {
2089 if (!adev->ip_blocks[i].status.valid)
2091 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2092 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2093 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH )
2095 r = adev->ip_blocks[i].version->funcs->resume(adev);
2097 DRM_ERROR("resume of IP block <%s> failed %d\n",
2098 adev->ip_blocks[i].version->funcs->name, r);
2106 static int amdgpu_resume(struct amdgpu_device *adev)
2110 r = amdgpu_resume_phase1(adev);
2113 r = amdgpu_resume_phase2(adev);
2118 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
2120 if (amdgpu_sriov_vf(adev)) {
2121 if (adev->is_atom_fw) {
2122 if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
2123 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2125 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
2126 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2129 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
2130 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2134 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
2136 switch (asic_type) {
2137 #if defined(CONFIG_DRM_AMD_DC)
2143 case CHIP_POLARIS11:
2144 case CHIP_POLARIS10:
2145 case CHIP_POLARIS12:
2148 #if defined(CONFIG_DRM_AMD_DC_PRE_VEGA)
2149 return amdgpu_dc != 0;
2153 return amdgpu_dc > 0;
2155 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2158 return amdgpu_dc != 0;
2166 * amdgpu_device_has_dc_support - check if dc is supported
2168 * @adev: amdgpu_device_pointer
2170 * Returns true for supported, false for not supported
2172 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
2174 if (amdgpu_sriov_vf(adev))
2177 return amdgpu_device_asic_has_dc_support(adev->asic_type);
2181 * amdgpu_device_init - initialize the driver
2183 * @adev: amdgpu_device pointer
2184 * @pdev: drm dev pointer
2185 * @pdev: pci dev pointer
2186 * @flags: driver flags
2188 * Initializes the driver info and hw (all asics).
2189 * Returns 0 for success or an error on failure.
2190 * Called at driver startup.
2192 int amdgpu_device_init(struct amdgpu_device *adev,
2193 struct drm_device *ddev,
2194 struct pci_dev *pdev,
2198 bool runtime = false;
2201 adev->shutdown = false;
2202 adev->dev = &pdev->dev;
2205 adev->flags = flags;
2206 adev->asic_type = flags & AMD_ASIC_MASK;
2207 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
2208 adev->mc.gart_size = 512 * 1024 * 1024;
2209 adev->accel_working = false;
2210 adev->num_rings = 0;
2211 adev->mman.buffer_funcs = NULL;
2212 adev->mman.buffer_funcs_ring = NULL;
2213 adev->vm_manager.vm_pte_funcs = NULL;
2214 adev->vm_manager.vm_pte_num_rings = 0;
2215 adev->gart.gart_funcs = NULL;
2216 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2217 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2219 adev->smc_rreg = &amdgpu_invalid_rreg;
2220 adev->smc_wreg = &amdgpu_invalid_wreg;
2221 adev->pcie_rreg = &amdgpu_invalid_rreg;
2222 adev->pcie_wreg = &amdgpu_invalid_wreg;
2223 adev->pciep_rreg = &amdgpu_invalid_rreg;
2224 adev->pciep_wreg = &amdgpu_invalid_wreg;
2225 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
2226 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
2227 adev->didt_rreg = &amdgpu_invalid_rreg;
2228 adev->didt_wreg = &amdgpu_invalid_wreg;
2229 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
2230 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
2231 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
2232 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
2234 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
2235 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
2236 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
2238 /* mutex initialization are all done here so we
2239 * can recall function without having locking issues */
2240 atomic_set(&adev->irq.ih.lock, 0);
2241 mutex_init(&adev->firmware.mutex);
2242 mutex_init(&adev->pm.mutex);
2243 mutex_init(&adev->gfx.gpu_clock_mutex);
2244 mutex_init(&adev->srbm_mutex);
2245 mutex_init(&adev->gfx.pipe_reserve_mutex);
2246 mutex_init(&adev->grbm_idx_mutex);
2247 mutex_init(&adev->mn_lock);
2248 mutex_init(&adev->virt.vf_errors.lock);
2249 hash_init(adev->mn_hash);
2250 mutex_init(&adev->lock_reset);
2252 amdgpu_check_arguments(adev);
2254 spin_lock_init(&adev->mmio_idx_lock);
2255 spin_lock_init(&adev->smc_idx_lock);
2256 spin_lock_init(&adev->pcie_idx_lock);
2257 spin_lock_init(&adev->uvd_ctx_idx_lock);
2258 spin_lock_init(&adev->didt_idx_lock);
2259 spin_lock_init(&adev->gc_cac_idx_lock);
2260 spin_lock_init(&adev->se_cac_idx_lock);
2261 spin_lock_init(&adev->audio_endpt_idx_lock);
2262 spin_lock_init(&adev->mm_stats.lock);
2264 INIT_LIST_HEAD(&adev->shadow_list);
2265 mutex_init(&adev->shadow_list_lock);
2267 INIT_LIST_HEAD(&adev->ring_lru_list);
2268 spin_lock_init(&adev->ring_lru_list_lock);
2270 INIT_DELAYED_WORK(&adev->late_init_work, amdgpu_late_init_func_handler);
2272 /* Registers mapping */
2273 /* TODO: block userspace mapping of io register */
2274 if (adev->asic_type >= CHIP_BONAIRE) {
2275 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
2276 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
2278 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
2279 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
2282 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
2283 if (adev->rmmio == NULL) {
2286 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
2287 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
2289 /* doorbell bar mapping */
2290 amdgpu_doorbell_init(adev);
2292 /* io port mapping */
2293 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2294 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
2295 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
2296 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
2300 if (adev->rio_mem == NULL)
2301 DRM_INFO("PCI I/O BAR is not found.\n");
2303 /* early init functions */
2304 r = amdgpu_early_init(adev);
2308 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
2309 /* this will fail for cards that aren't VGA class devices, just
2311 vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
2313 if (amdgpu_runtime_pm == 1)
2315 if (amdgpu_device_is_px(ddev))
2317 if (!pci_is_thunderbolt_attached(adev->pdev))
2318 vga_switcheroo_register_client(adev->pdev,
2319 &amdgpu_switcheroo_ops, runtime);
2321 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
2324 if (!amdgpu_get_bios(adev)) {
2329 r = amdgpu_atombios_init(adev);
2331 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2332 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2336 /* detect if we are with an SRIOV vbios */
2337 amdgpu_device_detect_sriov_bios(adev);
2339 /* Post card if necessary */
2340 if (amdgpu_need_post(adev)) {
2342 dev_err(adev->dev, "no vBIOS found\n");
2346 DRM_INFO("GPU posting now...\n");
2347 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2349 dev_err(adev->dev, "gpu post error!\n");
2354 if (adev->is_atom_fw) {
2355 /* Initialize clocks */
2356 r = amdgpu_atomfirmware_get_clock_info(adev);
2358 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
2359 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2363 /* Initialize clocks */
2364 r = amdgpu_atombios_get_clock_info(adev);
2366 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
2367 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2370 /* init i2c buses */
2371 if (!amdgpu_device_has_dc_support(adev))
2372 amdgpu_atombios_i2c_init(adev);
2376 r = amdgpu_fence_driver_init(adev);
2378 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
2379 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
2383 /* init the mode config */
2384 drm_mode_config_init(adev->ddev);
2386 r = amdgpu_init(adev);
2388 /* failed in exclusive mode due to timeout */
2389 if (amdgpu_sriov_vf(adev) &&
2390 !amdgpu_sriov_runtime(adev) &&
2391 amdgpu_virt_mmio_blocked(adev) &&
2392 !amdgpu_virt_wait_reset(adev)) {
2393 dev_err(adev->dev, "VF exclusive mode timeout\n");
2394 /* Don't send request since VF is inactive. */
2395 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
2396 adev->virt.ops = NULL;
2400 dev_err(adev->dev, "amdgpu_init failed\n");
2401 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
2406 adev->accel_working = true;
2408 amdgpu_vm_check_compute_bug(adev);
2410 /* Initialize the buffer migration limit. */
2411 if (amdgpu_moverate >= 0)
2412 max_MBps = amdgpu_moverate;
2414 max_MBps = 8; /* Allow 8 MB/s. */
2415 /* Get a log2 for easy divisions. */
2416 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
2418 r = amdgpu_ib_pool_init(adev);
2420 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2421 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2425 r = amdgpu_ib_ring_tests(adev);
2427 DRM_ERROR("ib ring test failed (%d).\n", r);
2429 if (amdgpu_sriov_vf(adev))
2430 amdgpu_virt_init_data_exchange(adev);
2432 amdgpu_fbdev_init(adev);
2434 r = amdgpu_pm_sysfs_init(adev);
2436 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
2438 r = amdgpu_gem_debugfs_init(adev);
2440 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2442 r = amdgpu_debugfs_regs_init(adev);
2444 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2446 r = amdgpu_debugfs_test_ib_ring_init(adev);
2448 DRM_ERROR("registering register test ib ring debugfs failed (%d).\n", r);
2450 r = amdgpu_debugfs_firmware_init(adev);
2452 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2454 r = amdgpu_debugfs_vbios_dump_init(adev);
2456 DRM_ERROR("Creating vbios dump debugfs failed (%d).\n", r);
2458 if ((amdgpu_testing & 1)) {
2459 if (adev->accel_working)
2460 amdgpu_test_moves(adev);
2462 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2464 if (amdgpu_benchmarking) {
2465 if (adev->accel_working)
2466 amdgpu_benchmark(adev, amdgpu_benchmarking);
2468 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2471 /* enable clockgating, etc. after ib tests, etc. since some blocks require
2472 * explicit gating rather than handling it automatically.
2474 r = amdgpu_late_init(adev);
2476 dev_err(adev->dev, "amdgpu_late_init failed\n");
2477 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
2484 amdgpu_vf_error_trans_all(adev);
2486 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2492 * amdgpu_device_fini - tear down the driver
2494 * @adev: amdgpu_device pointer
2496 * Tear down the driver info (all asics).
2497 * Called at driver shutdown.
2499 void amdgpu_device_fini(struct amdgpu_device *adev)
2503 DRM_INFO("amdgpu: finishing device.\n");
2504 adev->shutdown = true;
2505 if (adev->mode_info.mode_config_initialized)
2506 drm_crtc_force_disable_all(adev->ddev);
2507 /* evict vram memory */
2508 amdgpu_bo_evict_vram(adev);
2509 amdgpu_ib_pool_fini(adev);
2510 amdgpu_fence_driver_fini(adev);
2511 amdgpu_fbdev_fini(adev);
2512 r = amdgpu_fini(adev);
2513 if (adev->firmware.gpu_info_fw) {
2514 release_firmware(adev->firmware.gpu_info_fw);
2515 adev->firmware.gpu_info_fw = NULL;
2517 adev->accel_working = false;
2518 cancel_delayed_work_sync(&adev->late_init_work);
2519 /* free i2c buses */
2520 if (!amdgpu_device_has_dc_support(adev))
2521 amdgpu_i2c_fini(adev);
2522 amdgpu_atombios_fini(adev);
2525 if (!pci_is_thunderbolt_attached(adev->pdev))
2526 vga_switcheroo_unregister_client(adev->pdev);
2527 if (adev->flags & AMD_IS_PX)
2528 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2529 vga_client_register(adev->pdev, NULL, NULL, NULL);
2531 pci_iounmap(adev->pdev, adev->rio_mem);
2532 adev->rio_mem = NULL;
2533 iounmap(adev->rmmio);
2535 amdgpu_doorbell_fini(adev);
2536 amdgpu_pm_sysfs_fini(adev);
2537 amdgpu_debugfs_regs_cleanup(adev);
2545 * amdgpu_device_suspend - initiate device suspend
2547 * @pdev: drm dev pointer
2548 * @state: suspend state
2550 * Puts the hw in the suspend state (all asics).
2551 * Returns 0 for success or an error on failure.
2552 * Called at driver suspend.
2554 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
2556 struct amdgpu_device *adev;
2557 struct drm_crtc *crtc;
2558 struct drm_connector *connector;
2561 if (dev == NULL || dev->dev_private == NULL) {
2565 adev = dev->dev_private;
2567 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2570 drm_kms_helper_poll_disable(dev);
2572 if (!amdgpu_device_has_dc_support(adev)) {
2573 /* turn off display hw */
2574 drm_modeset_lock_all(dev);
2575 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2576 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
2578 drm_modeset_unlock_all(dev);
2581 amdgpu_amdkfd_suspend(adev);
2583 /* unpin the front buffers and cursors */
2584 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2585 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2586 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
2587 struct amdgpu_bo *robj;
2589 if (amdgpu_crtc->cursor_bo) {
2590 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2591 r = amdgpu_bo_reserve(aobj, true);
2593 amdgpu_bo_unpin(aobj);
2594 amdgpu_bo_unreserve(aobj);
2598 if (rfb == NULL || rfb->obj == NULL) {
2601 robj = gem_to_amdgpu_bo(rfb->obj);
2602 /* don't unpin kernel fb objects */
2603 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
2604 r = amdgpu_bo_reserve(robj, true);
2606 amdgpu_bo_unpin(robj);
2607 amdgpu_bo_unreserve(robj);
2611 /* evict vram memory */
2612 amdgpu_bo_evict_vram(adev);
2614 amdgpu_fence_driver_suspend(adev);
2616 r = amdgpu_suspend(adev);
2618 /* evict remaining vram memory
2619 * This second call to evict vram is to evict the gart page table
2622 amdgpu_bo_evict_vram(adev);
2624 amdgpu_atombios_scratch_regs_save(adev);
2625 pci_save_state(dev->pdev);
2627 /* Shut down the device */
2628 pci_disable_device(dev->pdev);
2629 pci_set_power_state(dev->pdev, PCI_D3hot);
2631 r = amdgpu_asic_reset(adev);
2633 DRM_ERROR("amdgpu asic reset failed\n");
2638 amdgpu_fbdev_set_suspend(adev, 1);
2645 * amdgpu_device_resume - initiate device resume
2647 * @pdev: drm dev pointer
2649 * Bring the hw back to operating state (all asics).
2650 * Returns 0 for success or an error on failure.
2651 * Called at driver resume.
2653 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2655 struct drm_connector *connector;
2656 struct amdgpu_device *adev = dev->dev_private;
2657 struct drm_crtc *crtc;
2660 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2667 pci_set_power_state(dev->pdev, PCI_D0);
2668 pci_restore_state(dev->pdev);
2669 r = pci_enable_device(dev->pdev);
2673 amdgpu_atombios_scratch_regs_restore(adev);
2676 if (amdgpu_need_post(adev)) {
2677 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2679 DRM_ERROR("amdgpu asic init failed\n");
2682 r = amdgpu_resume(adev);
2684 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
2687 amdgpu_fence_driver_resume(adev);
2690 r = amdgpu_ib_ring_tests(adev);
2692 DRM_ERROR("ib ring test failed (%d).\n", r);
2695 r = amdgpu_late_init(adev);
2700 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2701 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2703 if (amdgpu_crtc->cursor_bo) {
2704 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2705 r = amdgpu_bo_reserve(aobj, true);
2707 r = amdgpu_bo_pin(aobj,
2708 AMDGPU_GEM_DOMAIN_VRAM,
2709 &amdgpu_crtc->cursor_addr);
2711 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2712 amdgpu_bo_unreserve(aobj);
2716 r = amdgpu_amdkfd_resume(adev);
2720 /* blat the mode back in */
2722 if (!amdgpu_device_has_dc_support(adev)) {
2724 drm_helper_resume_force_mode(dev);
2726 /* turn on display hw */
2727 drm_modeset_lock_all(dev);
2728 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2729 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2731 drm_modeset_unlock_all(dev);
2734 * There is no equivalent atomic helper to turn on
2735 * display, so we defined our own function for this,
2736 * once suspend resume is supported by the atomic
2737 * framework this will be reworked
2739 amdgpu_dm_display_resume(adev);
2743 drm_kms_helper_poll_enable(dev);
2746 * Most of the connector probing functions try to acquire runtime pm
2747 * refs to ensure that the GPU is powered on when connector polling is
2748 * performed. Since we're calling this from a runtime PM callback,
2749 * trying to acquire rpm refs will cause us to deadlock.
2751 * Since we're guaranteed to be holding the rpm lock, it's safe to
2752 * temporarily disable the rpm helpers so this doesn't deadlock us.
2755 dev->dev->power.disable_depth++;
2757 if (!amdgpu_device_has_dc_support(adev))
2758 drm_helper_hpd_irq_event(dev);
2760 drm_kms_helper_hotplug_event(dev);
2762 dev->dev->power.disable_depth--;
2766 amdgpu_fbdev_set_suspend(adev, 0);
2775 static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
2778 bool asic_hang = false;
2780 if (amdgpu_sriov_vf(adev))
2783 for (i = 0; i < adev->num_ip_blocks; i++) {
2784 if (!adev->ip_blocks[i].status.valid)
2786 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
2787 adev->ip_blocks[i].status.hang =
2788 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
2789 if (adev->ip_blocks[i].status.hang) {
2790 DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
2797 static int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
2801 for (i = 0; i < adev->num_ip_blocks; i++) {
2802 if (!adev->ip_blocks[i].status.valid)
2804 if (adev->ip_blocks[i].status.hang &&
2805 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
2806 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
2815 static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
2819 for (i = 0; i < adev->num_ip_blocks; i++) {
2820 if (!adev->ip_blocks[i].status.valid)
2822 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
2823 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
2824 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
2825 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
2826 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
2827 if (adev->ip_blocks[i].status.hang) {
2828 DRM_INFO("Some block need full reset!\n");
2836 static int amdgpu_soft_reset(struct amdgpu_device *adev)
2840 for (i = 0; i < adev->num_ip_blocks; i++) {
2841 if (!adev->ip_blocks[i].status.valid)
2843 if (adev->ip_blocks[i].status.hang &&
2844 adev->ip_blocks[i].version->funcs->soft_reset) {
2845 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
2854 static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
2858 for (i = 0; i < adev->num_ip_blocks; i++) {
2859 if (!adev->ip_blocks[i].status.valid)
2861 if (adev->ip_blocks[i].status.hang &&
2862 adev->ip_blocks[i].version->funcs->post_soft_reset)
2863 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
2871 bool amdgpu_need_backup(struct amdgpu_device *adev)
2873 if (adev->flags & AMD_IS_APU)
2876 return amdgpu_lockup_timeout > 0 ? true : false;
2879 static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,
2880 struct amdgpu_ring *ring,
2881 struct amdgpu_bo *bo,
2882 struct dma_fence **fence)
2890 r = amdgpu_bo_reserve(bo, true);
2893 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
2894 /* if bo has been evicted, then no need to recover */
2895 if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
2896 r = amdgpu_bo_validate(bo->shadow);
2898 DRM_ERROR("bo validate failed!\n");
2902 r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
2905 DRM_ERROR("recover page table failed!\n");
2910 amdgpu_bo_unreserve(bo);
2915 * amdgpu_reset - reset ASIC/GPU for bare-metal or passthrough
2917 * @adev: amdgpu device pointer
2918 * @reset_flags: output param tells caller the reset result
2920 * attempt to do soft-reset or full-reset and reinitialize Asic
2921 * return 0 means successed otherwise failed
2923 static int amdgpu_reset(struct amdgpu_device *adev, uint64_t* reset_flags)
2925 bool need_full_reset, vram_lost = 0;
2928 need_full_reset = amdgpu_need_full_reset(adev);
2930 if (!need_full_reset) {
2931 amdgpu_pre_soft_reset(adev);
2932 r = amdgpu_soft_reset(adev);
2933 amdgpu_post_soft_reset(adev);
2934 if (r || amdgpu_check_soft_reset(adev)) {
2935 DRM_INFO("soft reset failed, will fallback to full reset!\n");
2936 need_full_reset = true;
2941 if (need_full_reset) {
2942 r = amdgpu_suspend(adev);
2945 amdgpu_atombios_scratch_regs_save(adev);
2946 r = amdgpu_asic_reset(adev);
2947 amdgpu_atombios_scratch_regs_restore(adev);
2949 amdgpu_atom_asic_init(adev->mode_info.atom_context);
2952 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
2953 r = amdgpu_resume_phase1(adev);
2957 vram_lost = amdgpu_check_vram_lost(adev);
2959 DRM_ERROR("VRAM is lost!\n");
2960 atomic_inc(&adev->vram_lost_counter);
2963 r = amdgpu_gtt_mgr_recover(
2964 &adev->mman.bdev.man[TTM_PL_TT]);
2968 r = amdgpu_resume_phase2(adev);
2973 amdgpu_fill_reset_magic(adev);
2979 amdgpu_irq_gpu_reset_resume_helper(adev);
2980 r = amdgpu_ib_ring_tests(adev);
2982 dev_err(adev->dev, "ib ring test failed (%d).\n", r);
2983 r = amdgpu_suspend(adev);
2984 need_full_reset = true;
2991 (*reset_flags) |= AMDGPU_RESET_INFO_VRAM_LOST;
2993 if (need_full_reset)
2994 (*reset_flags) |= AMDGPU_RESET_INFO_FULLRESET;
3001 * amdgpu_reset_sriov - reset ASIC for SR-IOV vf
3003 * @adev: amdgpu device pointer
3004 * @reset_flags: output param tells caller the reset result
3006 * do VF FLR and reinitialize Asic
3007 * return 0 means successed otherwise failed
3009 static int amdgpu_reset_sriov(struct amdgpu_device *adev, uint64_t *reset_flags, bool from_hypervisor)
3013 if (from_hypervisor)
3014 r = amdgpu_virt_request_full_gpu(adev, true);
3016 r = amdgpu_virt_reset_gpu(adev);
3020 /* Resume IP prior to SMC */
3021 r = amdgpu_sriov_reinit_early(adev);
3025 /* we need recover gart prior to run SMC/CP/SDMA resume */
3026 amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
3028 /* now we are okay to resume SMC/CP/SDMA */
3029 r = amdgpu_sriov_reinit_late(adev);
3033 amdgpu_irq_gpu_reset_resume_helper(adev);
3034 r = amdgpu_ib_ring_tests(adev);
3036 dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r);
3039 /* release full control of GPU after ib test */
3040 amdgpu_virt_release_full_gpu(adev, true);
3043 if (adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
3044 (*reset_flags) |= AMDGPU_RESET_INFO_VRAM_LOST;
3045 atomic_inc(&adev->vram_lost_counter);
3048 /* VF FLR or hotlink reset is always full-reset */
3049 (*reset_flags) |= AMDGPU_RESET_INFO_FULLRESET;
3056 * amdgpu_gpu_recover - reset the asic and recover scheduler
3058 * @adev: amdgpu device pointer
3059 * @job: which job trigger hang
3061 * Attempt to reset the GPU if it has hung (all asics).
3062 * Returns 0 for success or an error on failure.
3064 int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job)
3066 struct drm_atomic_state *state = NULL;
3067 uint64_t reset_flags = 0;
3070 if (!amdgpu_check_soft_reset(adev)) {
3071 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
3075 dev_info(adev->dev, "GPU reset begin!\n");
3077 mutex_lock(&adev->lock_reset);
3078 atomic_inc(&adev->gpu_reset_counter);
3079 adev->in_gpu_reset = 1;
3082 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
3083 /* store modesetting */
3084 if (amdgpu_device_has_dc_support(adev))
3085 state = drm_atomic_helper_suspend(adev->ddev);
3087 /* block scheduler */
3088 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3089 struct amdgpu_ring *ring = adev->rings[i];
3091 if (!ring || !ring->sched.thread)
3094 /* only focus on the ring hit timeout if &job not NULL */
3095 if (job && job->ring->idx != i)
3098 kthread_park(ring->sched.thread);
3099 amd_sched_hw_job_reset(&ring->sched, &job->base);
3101 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
3102 amdgpu_fence_driver_force_completion(ring);
3105 if (amdgpu_sriov_vf(adev))
3106 r = amdgpu_reset_sriov(adev, &reset_flags, job ? false : true);
3108 r = amdgpu_reset(adev, &reset_flags);
3111 if (((reset_flags & AMDGPU_RESET_INFO_FULLRESET) && !(adev->flags & AMD_IS_APU)) ||
3112 (reset_flags & AMDGPU_RESET_INFO_VRAM_LOST)) {
3113 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
3114 struct amdgpu_bo *bo, *tmp;
3115 struct dma_fence *fence = NULL, *next = NULL;
3117 DRM_INFO("recover vram bo from shadow\n");
3118 mutex_lock(&adev->shadow_list_lock);
3119 list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
3121 amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
3123 r = dma_fence_wait(fence, false);
3125 WARN(r, "recovery from shadow isn't completed\n");
3130 dma_fence_put(fence);
3133 mutex_unlock(&adev->shadow_list_lock);
3135 r = dma_fence_wait(fence, false);
3137 WARN(r, "recovery from shadow isn't completed\n");
3139 dma_fence_put(fence);
3142 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3143 struct amdgpu_ring *ring = adev->rings[i];
3145 if (!ring || !ring->sched.thread)
3148 /* only focus on the ring hit timeout if &job not NULL */
3149 if (job && job->ring->idx != i)
3152 amd_sched_job_recovery(&ring->sched);
3153 kthread_unpark(ring->sched.thread);
3156 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3157 struct amdgpu_ring *ring = adev->rings[i];
3159 if (!ring || !ring->sched.thread)
3162 /* only focus on the ring hit timeout if &job not NULL */
3163 if (job && job->ring->idx != i)
3166 kthread_unpark(adev->rings[i]->sched.thread);
3170 if (amdgpu_device_has_dc_support(adev)) {
3171 if (drm_atomic_helper_resume(adev->ddev, state))
3172 dev_info(adev->dev, "drm resume failed:%d\n", r);
3173 amdgpu_dm_display_resume(adev);
3175 drm_helper_resume_force_mode(adev->ddev);
3178 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
3181 /* bad news, how to tell it to userspace ? */
3182 dev_info(adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
3183 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
3185 dev_info(adev->dev, "GPU reset(%d) successed!\n",atomic_read(&adev->gpu_reset_counter));
3188 amdgpu_vf_error_trans_all(adev);
3189 adev->in_gpu_reset = 0;
3190 mutex_unlock(&adev->lock_reset);
3194 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
3199 if (amdgpu_pcie_gen_cap)
3200 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
3202 if (amdgpu_pcie_lane_cap)
3203 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
3205 /* covers APUs as well */
3206 if (pci_is_root_bus(adev->pdev->bus)) {
3207 if (adev->pm.pcie_gen_mask == 0)
3208 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3209 if (adev->pm.pcie_mlw_mask == 0)
3210 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3214 if (adev->pm.pcie_gen_mask == 0) {
3215 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
3217 adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3218 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3219 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
3221 if (mask & DRM_PCIE_SPEED_25)
3222 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
3223 if (mask & DRM_PCIE_SPEED_50)
3224 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
3225 if (mask & DRM_PCIE_SPEED_80)
3226 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
3228 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3231 if (adev->pm.pcie_mlw_mask == 0) {
3232 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
3236 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
3237 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3238 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3239 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3240 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3241 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3242 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3245 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3246 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3247 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3248 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3249 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3250 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3253 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3254 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3255 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3256 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3257 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3260 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3261 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3262 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3263 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3266 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3267 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3268 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3271 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3272 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3275 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
3281 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3289 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
3290 const struct drm_info_list *files,
3295 for (i = 0; i < adev->debugfs_count; i++) {
3296 if (adev->debugfs[i].files == files) {
3297 /* Already registered */
3302 i = adev->debugfs_count + 1;
3303 if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
3304 DRM_ERROR("Reached maximum number of debugfs components.\n");
3305 DRM_ERROR("Report so we increase "
3306 "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
3309 adev->debugfs[adev->debugfs_count].files = files;
3310 adev->debugfs[adev->debugfs_count].num_files = nfiles;
3311 adev->debugfs_count = i;
3312 #if defined(CONFIG_DEBUG_FS)
3313 drm_debugfs_create_files(files, nfiles,
3314 adev->ddev->primary->debugfs_root,
3315 adev->ddev->primary);
3320 #if defined(CONFIG_DEBUG_FS)
3322 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
3323 size_t size, loff_t *pos)
3325 struct amdgpu_device *adev = file_inode(f)->i_private;
3328 bool pm_pg_lock, use_bank;
3329 unsigned instance_bank, sh_bank, se_bank;
3331 if (size & 0x3 || *pos & 0x3)
3334 /* are we reading registers for which a PG lock is necessary? */
3335 pm_pg_lock = (*pos >> 23) & 1;
3337 if (*pos & (1ULL << 62)) {
3338 se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
3339 sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
3340 instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
3342 if (se_bank == 0x3FF)
3343 se_bank = 0xFFFFFFFF;
3344 if (sh_bank == 0x3FF)
3345 sh_bank = 0xFFFFFFFF;
3346 if (instance_bank == 0x3FF)
3347 instance_bank = 0xFFFFFFFF;
3353 *pos &= (1UL << 22) - 1;
3356 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
3357 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
3359 mutex_lock(&adev->grbm_idx_mutex);
3360 amdgpu_gfx_select_se_sh(adev, se_bank,
3361 sh_bank, instance_bank);
3365 mutex_lock(&adev->pm.mutex);
3370 if (*pos > adev->rmmio_size)
3373 value = RREG32(*pos >> 2);
3374 r = put_user(value, (uint32_t *)buf);
3388 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3389 mutex_unlock(&adev->grbm_idx_mutex);
3393 mutex_unlock(&adev->pm.mutex);
3398 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
3399 size_t size, loff_t *pos)
3401 struct amdgpu_device *adev = file_inode(f)->i_private;
3404 bool pm_pg_lock, use_bank;
3405 unsigned instance_bank, sh_bank, se_bank;
3407 if (size & 0x3 || *pos & 0x3)
3410 /* are we reading registers for which a PG lock is necessary? */
3411 pm_pg_lock = (*pos >> 23) & 1;
3413 if (*pos & (1ULL << 62)) {
3414 se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
3415 sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
3416 instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
3418 if (se_bank == 0x3FF)
3419 se_bank = 0xFFFFFFFF;
3420 if (sh_bank == 0x3FF)
3421 sh_bank = 0xFFFFFFFF;
3422 if (instance_bank == 0x3FF)
3423 instance_bank = 0xFFFFFFFF;
3429 *pos &= (1UL << 22) - 1;
3432 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
3433 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
3435 mutex_lock(&adev->grbm_idx_mutex);
3436 amdgpu_gfx_select_se_sh(adev, se_bank,
3437 sh_bank, instance_bank);
3441 mutex_lock(&adev->pm.mutex);
3446 if (*pos > adev->rmmio_size)
3449 r = get_user(value, (uint32_t *)buf);
3453 WREG32(*pos >> 2, value);
3462 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3463 mutex_unlock(&adev->grbm_idx_mutex);
3467 mutex_unlock(&adev->pm.mutex);
3472 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
3473 size_t size, loff_t *pos)
3475 struct amdgpu_device *adev = file_inode(f)->i_private;
3479 if (size & 0x3 || *pos & 0x3)
3485 value = RREG32_PCIE(*pos >> 2);
3486 r = put_user(value, (uint32_t *)buf);
3499 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
3500 size_t size, loff_t *pos)
3502 struct amdgpu_device *adev = file_inode(f)->i_private;
3506 if (size & 0x3 || *pos & 0x3)
3512 r = get_user(value, (uint32_t *)buf);
3516 WREG32_PCIE(*pos >> 2, value);
3527 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
3528 size_t size, loff_t *pos)
3530 struct amdgpu_device *adev = file_inode(f)->i_private;
3534 if (size & 0x3 || *pos & 0x3)
3540 value = RREG32_DIDT(*pos >> 2);
3541 r = put_user(value, (uint32_t *)buf);
3554 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
3555 size_t size, loff_t *pos)
3557 struct amdgpu_device *adev = file_inode(f)->i_private;
3561 if (size & 0x3 || *pos & 0x3)
3567 r = get_user(value, (uint32_t *)buf);
3571 WREG32_DIDT(*pos >> 2, value);
3582 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
3583 size_t size, loff_t *pos)
3585 struct amdgpu_device *adev = file_inode(f)->i_private;
3589 if (size & 0x3 || *pos & 0x3)
3595 value = RREG32_SMC(*pos);
3596 r = put_user(value, (uint32_t *)buf);
3609 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
3610 size_t size, loff_t *pos)
3612 struct amdgpu_device *adev = file_inode(f)->i_private;
3616 if (size & 0x3 || *pos & 0x3)
3622 r = get_user(value, (uint32_t *)buf);
3626 WREG32_SMC(*pos, value);
3637 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
3638 size_t size, loff_t *pos)
3640 struct amdgpu_device *adev = file_inode(f)->i_private;
3643 uint32_t *config, no_regs = 0;
3645 if (size & 0x3 || *pos & 0x3)
3648 config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
3652 /* version, increment each time something is added */
3653 config[no_regs++] = 3;
3654 config[no_regs++] = adev->gfx.config.max_shader_engines;
3655 config[no_regs++] = adev->gfx.config.max_tile_pipes;
3656 config[no_regs++] = adev->gfx.config.max_cu_per_sh;
3657 config[no_regs++] = adev->gfx.config.max_sh_per_se;
3658 config[no_regs++] = adev->gfx.config.max_backends_per_se;
3659 config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
3660 config[no_regs++] = adev->gfx.config.max_gprs;
3661 config[no_regs++] = adev->gfx.config.max_gs_threads;
3662 config[no_regs++] = adev->gfx.config.max_hw_contexts;
3663 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
3664 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
3665 config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
3666 config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
3667 config[no_regs++] = adev->gfx.config.num_tile_pipes;
3668 config[no_regs++] = adev->gfx.config.backend_enable_mask;
3669 config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
3670 config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
3671 config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
3672 config[no_regs++] = adev->gfx.config.num_gpus;
3673 config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
3674 config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
3675 config[no_regs++] = adev->gfx.config.gb_addr_config;
3676 config[no_regs++] = adev->gfx.config.num_rbs;
3679 config[no_regs++] = adev->rev_id;
3680 config[no_regs++] = adev->pg_flags;
3681 config[no_regs++] = adev->cg_flags;
3684 config[no_regs++] = adev->family;
3685 config[no_regs++] = adev->external_rev_id;
3688 config[no_regs++] = adev->pdev->device;
3689 config[no_regs++] = adev->pdev->revision;
3690 config[no_regs++] = adev->pdev->subsystem_device;
3691 config[no_regs++] = adev->pdev->subsystem_vendor;
3693 while (size && (*pos < no_regs * 4)) {
3696 value = config[*pos >> 2];
3697 r = put_user(value, (uint32_t *)buf);
3713 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
3714 size_t size, loff_t *pos)
3716 struct amdgpu_device *adev = file_inode(f)->i_private;
3717 int idx, x, outsize, r, valuesize;
3718 uint32_t values[16];
3720 if (size & 3 || *pos & 0x3)
3723 if (amdgpu_dpm == 0)
3726 /* convert offset to sensor number */
3729 valuesize = sizeof(values);
3730 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
3731 r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);
3735 if (size > valuesize)
3742 r = put_user(values[x++], (int32_t *)buf);
3749 return !r ? outsize : r;
3752 static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
3753 size_t size, loff_t *pos)
3755 struct amdgpu_device *adev = f->f_inode->i_private;
3758 uint32_t offset, se, sh, cu, wave, simd, data[32];
3760 if (size & 3 || *pos & 3)
3764 offset = (*pos & GENMASK_ULL(6, 0));
3765 se = (*pos & GENMASK_ULL(14, 7)) >> 7;
3766 sh = (*pos & GENMASK_ULL(22, 15)) >> 15;
3767 cu = (*pos & GENMASK_ULL(30, 23)) >> 23;
3768 wave = (*pos & GENMASK_ULL(36, 31)) >> 31;
3769 simd = (*pos & GENMASK_ULL(44, 37)) >> 37;
3771 /* switch to the specific se/sh/cu */
3772 mutex_lock(&adev->grbm_idx_mutex);
3773 amdgpu_gfx_select_se_sh(adev, se, sh, cu);
3776 if (adev->gfx.funcs->read_wave_data)
3777 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
3779 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3780 mutex_unlock(&adev->grbm_idx_mutex);
3785 while (size && (offset < x * 4)) {
3788 value = data[offset >> 2];
3789 r = put_user(value, (uint32_t *)buf);
3802 static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
3803 size_t size, loff_t *pos)
3805 struct amdgpu_device *adev = f->f_inode->i_private;
3808 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
3810 if (size & 3 || *pos & 3)
3814 offset = *pos & GENMASK_ULL(11, 0);
3815 se = (*pos & GENMASK_ULL(19, 12)) >> 12;
3816 sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
3817 cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
3818 wave = (*pos & GENMASK_ULL(43, 36)) >> 36;
3819 simd = (*pos & GENMASK_ULL(51, 44)) >> 44;
3820 thread = (*pos & GENMASK_ULL(59, 52)) >> 52;
3821 bank = (*pos & GENMASK_ULL(61, 60)) >> 60;
3823 data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
3827 /* switch to the specific se/sh/cu */
3828 mutex_lock(&adev->grbm_idx_mutex);
3829 amdgpu_gfx_select_se_sh(adev, se, sh, cu);
3832 if (adev->gfx.funcs->read_wave_vgprs)
3833 adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
3835 if (adev->gfx.funcs->read_wave_sgprs)
3836 adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
3839 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3840 mutex_unlock(&adev->grbm_idx_mutex);
3845 value = data[offset++];
3846 r = put_user(value, (uint32_t *)buf);
3862 static const struct file_operations amdgpu_debugfs_regs_fops = {
3863 .owner = THIS_MODULE,
3864 .read = amdgpu_debugfs_regs_read,
3865 .write = amdgpu_debugfs_regs_write,
3866 .llseek = default_llseek
3868 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
3869 .owner = THIS_MODULE,
3870 .read = amdgpu_debugfs_regs_didt_read,
3871 .write = amdgpu_debugfs_regs_didt_write,
3872 .llseek = default_llseek
3874 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
3875 .owner = THIS_MODULE,
3876 .read = amdgpu_debugfs_regs_pcie_read,
3877 .write = amdgpu_debugfs_regs_pcie_write,
3878 .llseek = default_llseek
3880 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
3881 .owner = THIS_MODULE,
3882 .read = amdgpu_debugfs_regs_smc_read,
3883 .write = amdgpu_debugfs_regs_smc_write,
3884 .llseek = default_llseek
3887 static const struct file_operations amdgpu_debugfs_gca_config_fops = {
3888 .owner = THIS_MODULE,
3889 .read = amdgpu_debugfs_gca_config_read,
3890 .llseek = default_llseek
3893 static const struct file_operations amdgpu_debugfs_sensors_fops = {
3894 .owner = THIS_MODULE,
3895 .read = amdgpu_debugfs_sensor_read,
3896 .llseek = default_llseek
3899 static const struct file_operations amdgpu_debugfs_wave_fops = {
3900 .owner = THIS_MODULE,
3901 .read = amdgpu_debugfs_wave_read,
3902 .llseek = default_llseek
3904 static const struct file_operations amdgpu_debugfs_gpr_fops = {
3905 .owner = THIS_MODULE,
3906 .read = amdgpu_debugfs_gpr_read,
3907 .llseek = default_llseek
3910 static const struct file_operations *debugfs_regs[] = {
3911 &amdgpu_debugfs_regs_fops,
3912 &amdgpu_debugfs_regs_didt_fops,
3913 &amdgpu_debugfs_regs_pcie_fops,
3914 &amdgpu_debugfs_regs_smc_fops,
3915 &amdgpu_debugfs_gca_config_fops,
3916 &amdgpu_debugfs_sensors_fops,
3917 &amdgpu_debugfs_wave_fops,
3918 &amdgpu_debugfs_gpr_fops,
3921 static const char *debugfs_regs_names[] = {
3926 "amdgpu_gca_config",
3932 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
3934 struct drm_minor *minor = adev->ddev->primary;
3935 struct dentry *ent, *root = minor->debugfs_root;
3938 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
3939 ent = debugfs_create_file(debugfs_regs_names[i],
3940 S_IFREG | S_IRUGO, root,
3941 adev, debugfs_regs[i]);
3943 for (j = 0; j < i; j++) {
3944 debugfs_remove(adev->debugfs_regs[i]);
3945 adev->debugfs_regs[i] = NULL;
3947 return PTR_ERR(ent);
3951 i_size_write(ent->d_inode, adev->rmmio_size);
3952 adev->debugfs_regs[i] = ent;
3958 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
3962 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
3963 if (adev->debugfs_regs[i]) {
3964 debugfs_remove(adev->debugfs_regs[i]);
3965 adev->debugfs_regs[i] = NULL;
3970 static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data)
3972 struct drm_info_node *node = (struct drm_info_node *) m->private;
3973 struct drm_device *dev = node->minor->dev;
3974 struct amdgpu_device *adev = dev->dev_private;
3977 /* hold on the scheduler */
3978 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
3979 struct amdgpu_ring *ring = adev->rings[i];
3981 if (!ring || !ring->sched.thread)
3983 kthread_park(ring->sched.thread);
3986 seq_printf(m, "run ib test:\n");
3987 r = amdgpu_ib_ring_tests(adev);
3989 seq_printf(m, "ib ring tests failed (%d).\n", r);
3991 seq_printf(m, "ib ring tests passed.\n");
3993 /* go on the scheduler */
3994 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
3995 struct amdgpu_ring *ring = adev->rings[i];
3997 if (!ring || !ring->sched.thread)
3999 kthread_unpark(ring->sched.thread);
4005 static const struct drm_info_list amdgpu_debugfs_test_ib_ring_list[] = {
4006 {"amdgpu_test_ib", &amdgpu_debugfs_test_ib}
4009 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev)
4011 return amdgpu_debugfs_add_files(adev,
4012 amdgpu_debugfs_test_ib_ring_list, 1);
4015 int amdgpu_debugfs_init(struct drm_minor *minor)
4020 static int amdgpu_debugfs_get_vbios_dump(struct seq_file *m, void *data)
4022 struct drm_info_node *node = (struct drm_info_node *) m->private;
4023 struct drm_device *dev = node->minor->dev;
4024 struct amdgpu_device *adev = dev->dev_private;
4026 seq_write(m, adev->bios, adev->bios_size);
4030 static const struct drm_info_list amdgpu_vbios_dump_list[] = {
4032 amdgpu_debugfs_get_vbios_dump,
4036 static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev)
4038 return amdgpu_debugfs_add_files(adev,
4039 amdgpu_vbios_dump_list, 1);
4042 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev)
4046 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
4050 static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev)
4054 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }