2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/power_supply.h>
29 #include <linux/kthread.h>
30 #include <linux/console.h>
31 #include <linux/slab.h>
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_probe_helper.h>
35 #include <drm/amdgpu_drm.h>
36 #include <linux/vgaarb.h>
37 #include <linux/vga_switcheroo.h>
38 #include <linux/efi.h>
40 #include "amdgpu_trace.h"
41 #include "amdgpu_i2c.h"
43 #include "amdgpu_atombios.h"
44 #include "amdgpu_atomfirmware.h"
46 #ifdef CONFIG_DRM_AMDGPU_SI
49 #ifdef CONFIG_DRM_AMDGPU_CIK
54 #include "bif/bif_4_1_d.h"
55 #include <linux/pci.h>
56 #include <linux/firmware.h>
57 #include "amdgpu_vf_error.h"
59 #include "amdgpu_amdkfd.h"
60 #include "amdgpu_pm.h"
62 #include "amdgpu_xgmi.h"
63 #include "amdgpu_ras.h"
65 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
66 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
67 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
68 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
69 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
71 #define AMDGPU_RESUME_MS 2000
73 static const char *amdgpu_asic_name[] = {
101 * DOC: pcie_replay_count
103 * The amdgpu driver provides a sysfs API for reporting the total number
104 * of PCIe replays (NAKs)
105 * The file pcie_replay_count is used for this and returns the total
106 * number of replays as a sum of the NAKs generated and NAKs received
109 static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
110 struct device_attribute *attr, char *buf)
112 struct drm_device *ddev = dev_get_drvdata(dev);
113 struct amdgpu_device *adev = ddev->dev_private;
114 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
116 return snprintf(buf, PAGE_SIZE, "%llu\n", cnt);
119 static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
120 amdgpu_device_get_pcie_replay_count, NULL);
122 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
125 * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control
127 * @dev: drm_device pointer
129 * Returns true if the device is a dGPU with HG/PX power control,
130 * otherwise return false.
132 bool amdgpu_device_is_px(struct drm_device *dev)
134 struct amdgpu_device *adev = dev->dev_private;
136 if (adev->flags & AMD_IS_PX)
142 * MMIO register access helper functions.
145 * amdgpu_mm_rreg - read a memory mapped IO register
147 * @adev: amdgpu_device pointer
148 * @reg: dword aligned register offset
149 * @acc_flags: access flags which require special behavior
151 * Returns the 32 bit value from the offset specified.
153 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
158 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
159 return amdgpu_virt_kiq_rreg(adev, reg);
161 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
162 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
166 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
167 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
168 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
169 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
171 trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
176 * MMIO register read with bytes helper functions
177 * @offset:bytes offset from MMIO start
182 * amdgpu_mm_rreg8 - read a memory mapped IO register
184 * @adev: amdgpu_device pointer
185 * @offset: byte aligned register offset
187 * Returns the 8 bit value from the offset specified.
189 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
190 if (offset < adev->rmmio_size)
191 return (readb(adev->rmmio + offset));
196 * MMIO register write with bytes helper functions
197 * @offset:bytes offset from MMIO start
198 * @value: the value want to be written to the register
202 * amdgpu_mm_wreg8 - read a memory mapped IO register
204 * @adev: amdgpu_device pointer
205 * @offset: byte aligned register offset
206 * @value: 8 bit value to write
208 * Writes the value specified to the offset specified.
210 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) {
211 if (offset < adev->rmmio_size)
212 writeb(value, adev->rmmio + offset);
218 * amdgpu_mm_wreg - write to a memory mapped IO register
220 * @adev: amdgpu_device pointer
221 * @reg: dword aligned register offset
222 * @v: 32 bit value to write to the register
223 * @acc_flags: access flags which require special behavior
225 * Writes the value specified to the offset specified.
227 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
230 trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
232 if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
233 adev->last_mm_index = v;
236 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
237 return amdgpu_virt_kiq_wreg(adev, reg, v);
239 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
240 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
244 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
245 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
246 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
247 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
250 if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
256 * amdgpu_io_rreg - read an IO register
258 * @adev: amdgpu_device pointer
259 * @reg: dword aligned register offset
261 * Returns the 32 bit value from the offset specified.
263 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
265 if ((reg * 4) < adev->rio_mem_size)
266 return ioread32(adev->rio_mem + (reg * 4));
268 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
269 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
274 * amdgpu_io_wreg - write to an IO register
276 * @adev: amdgpu_device pointer
277 * @reg: dword aligned register offset
278 * @v: 32 bit value to write to the register
280 * Writes the value specified to the offset specified.
282 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
284 if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
285 adev->last_mm_index = v;
288 if ((reg * 4) < adev->rio_mem_size)
289 iowrite32(v, adev->rio_mem + (reg * 4));
291 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
292 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
295 if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
301 * amdgpu_mm_rdoorbell - read a doorbell dword
303 * @adev: amdgpu_device pointer
304 * @index: doorbell index
306 * Returns the value in the doorbell aperture at the
307 * requested doorbell index (CIK).
309 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
311 if (index < adev->doorbell.num_doorbells) {
312 return readl(adev->doorbell.ptr + index);
314 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
320 * amdgpu_mm_wdoorbell - write a doorbell dword
322 * @adev: amdgpu_device pointer
323 * @index: doorbell index
326 * Writes @v to the doorbell aperture at the
327 * requested doorbell index (CIK).
329 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
331 if (index < adev->doorbell.num_doorbells) {
332 writel(v, adev->doorbell.ptr + index);
334 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
339 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
341 * @adev: amdgpu_device pointer
342 * @index: doorbell index
344 * Returns the value in the doorbell aperture at the
345 * requested doorbell index (VEGA10+).
347 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
349 if (index < adev->doorbell.num_doorbells) {
350 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
352 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
358 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
360 * @adev: amdgpu_device pointer
361 * @index: doorbell index
364 * Writes @v to the doorbell aperture at the
365 * requested doorbell index (VEGA10+).
367 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
369 if (index < adev->doorbell.num_doorbells) {
370 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
372 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
377 * amdgpu_invalid_rreg - dummy reg read function
379 * @adev: amdgpu device pointer
380 * @reg: offset of register
382 * Dummy register read function. Used for register blocks
383 * that certain asics don't have (all asics).
384 * Returns the value in the register.
386 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
388 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
394 * amdgpu_invalid_wreg - dummy reg write function
396 * @adev: amdgpu device pointer
397 * @reg: offset of register
398 * @v: value to write to the register
400 * Dummy register read function. Used for register blocks
401 * that certain asics don't have (all asics).
403 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
405 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
411 * amdgpu_block_invalid_rreg - dummy reg read function
413 * @adev: amdgpu device pointer
414 * @block: offset of instance
415 * @reg: offset of register
417 * Dummy register read function. Used for register blocks
418 * that certain asics don't have (all asics).
419 * Returns the value in the register.
421 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
422 uint32_t block, uint32_t reg)
424 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
431 * amdgpu_block_invalid_wreg - dummy reg write function
433 * @adev: amdgpu device pointer
434 * @block: offset of instance
435 * @reg: offset of register
436 * @v: value to write to the register
438 * Dummy register read function. Used for register blocks
439 * that certain asics don't have (all asics).
441 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
443 uint32_t reg, uint32_t v)
445 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
451 * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
453 * @adev: amdgpu device pointer
455 * Allocates a scratch page of VRAM for use by various things in the
458 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
460 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
461 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
462 &adev->vram_scratch.robj,
463 &adev->vram_scratch.gpu_addr,
464 (void **)&adev->vram_scratch.ptr);
468 * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
470 * @adev: amdgpu device pointer
472 * Frees the VRAM scratch page.
474 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
476 amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
480 * amdgpu_device_program_register_sequence - program an array of registers.
482 * @adev: amdgpu_device pointer
483 * @registers: pointer to the register array
484 * @array_size: size of the register array
486 * Programs an array or registers with and and or masks.
487 * This is a helper for setting golden registers.
489 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
490 const u32 *registers,
491 const u32 array_size)
493 u32 tmp, reg, and_mask, or_mask;
499 for (i = 0; i < array_size; i +=3) {
500 reg = registers[i + 0];
501 and_mask = registers[i + 1];
502 or_mask = registers[i + 2];
504 if (and_mask == 0xffffffff) {
516 * amdgpu_device_pci_config_reset - reset the GPU
518 * @adev: amdgpu_device pointer
520 * Resets the GPU using the pci config reset sequence.
521 * Only applicable to asics prior to vega10.
523 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
525 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
529 * GPU doorbell aperture helpers function.
532 * amdgpu_device_doorbell_init - Init doorbell driver information.
534 * @adev: amdgpu_device pointer
536 * Init doorbell driver information (CIK)
537 * Returns 0 on success, error on failure.
539 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
542 /* No doorbell on SI hardware generation */
543 if (adev->asic_type < CHIP_BONAIRE) {
544 adev->doorbell.base = 0;
545 adev->doorbell.size = 0;
546 adev->doorbell.num_doorbells = 0;
547 adev->doorbell.ptr = NULL;
551 if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
554 amdgpu_asic_init_doorbell_index(adev);
556 /* doorbell bar mapping */
557 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
558 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
560 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
561 adev->doorbell_index.max_assignment+1);
562 if (adev->doorbell.num_doorbells == 0)
565 /* For Vega, reserve and map two pages on doorbell BAR since SDMA
566 * paging queue doorbell use the second page. The
567 * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
568 * doorbells are in the first page. So with paging queue enabled,
569 * the max num_doorbells should + 1 page (0x400 in dword)
571 if (adev->asic_type >= CHIP_VEGA10)
572 adev->doorbell.num_doorbells += 0x400;
574 adev->doorbell.ptr = ioremap(adev->doorbell.base,
575 adev->doorbell.num_doorbells *
577 if (adev->doorbell.ptr == NULL)
584 * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
586 * @adev: amdgpu_device pointer
588 * Tear down doorbell driver information (CIK)
590 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
592 iounmap(adev->doorbell.ptr);
593 adev->doorbell.ptr = NULL;
599 * amdgpu_device_wb_*()
600 * Writeback is the method by which the GPU updates special pages in memory
601 * with the status of certain GPU events (fences, ring pointers,etc.).
605 * amdgpu_device_wb_fini - Disable Writeback and free memory
607 * @adev: amdgpu_device pointer
609 * Disables Writeback and frees the Writeback memory (all asics).
610 * Used at driver shutdown.
612 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
614 if (adev->wb.wb_obj) {
615 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
617 (void **)&adev->wb.wb);
618 adev->wb.wb_obj = NULL;
623 * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
625 * @adev: amdgpu_device pointer
627 * Initializes writeback and allocates writeback memory (all asics).
628 * Used at driver startup.
629 * Returns 0 on success or an -error on failure.
631 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
635 if (adev->wb.wb_obj == NULL) {
636 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
637 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
638 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
639 &adev->wb.wb_obj, &adev->wb.gpu_addr,
640 (void **)&adev->wb.wb);
642 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
646 adev->wb.num_wb = AMDGPU_MAX_WB;
647 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
649 /* clear wb memory */
650 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
657 * amdgpu_device_wb_get - Allocate a wb entry
659 * @adev: amdgpu_device pointer
662 * Allocate a wb slot for use by the driver (all asics).
663 * Returns 0 on success or -EINVAL on failure.
665 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
667 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
669 if (offset < adev->wb.num_wb) {
670 __set_bit(offset, adev->wb.used);
671 *wb = offset << 3; /* convert to dw offset */
679 * amdgpu_device_wb_free - Free a wb entry
681 * @adev: amdgpu_device pointer
684 * Free a wb slot allocated for use by the driver (all asics)
686 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
689 if (wb < adev->wb.num_wb)
690 __clear_bit(wb, adev->wb.used);
694 * amdgpu_device_resize_fb_bar - try to resize FB BAR
696 * @adev: amdgpu_device pointer
698 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
699 * to fail, but if any of the BARs is not accessible after the size we abort
700 * driver loading by returning -ENODEV.
702 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
704 u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
705 u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
706 struct pci_bus *root;
707 struct resource *res;
713 if (amdgpu_sriov_vf(adev))
716 /* Check if the root BUS has 64bit memory resources */
717 root = adev->pdev->bus;
721 pci_bus_for_each_resource(root, res, i) {
722 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
723 res->start > 0x100000000ull)
727 /* Trying to resize is pointless without a root hub window above 4GB */
731 /* Disable memory decoding while we change the BAR addresses and size */
732 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
733 pci_write_config_word(adev->pdev, PCI_COMMAND,
734 cmd & ~PCI_COMMAND_MEMORY);
736 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
737 amdgpu_device_doorbell_fini(adev);
738 if (adev->asic_type >= CHIP_BONAIRE)
739 pci_release_resource(adev->pdev, 2);
741 pci_release_resource(adev->pdev, 0);
743 r = pci_resize_resource(adev->pdev, 0, rbar_size);
745 DRM_INFO("Not enough PCI address space for a large BAR.");
746 else if (r && r != -ENOTSUPP)
747 DRM_ERROR("Problem resizing BAR0 (%d).", r);
749 pci_assign_unassigned_bus_resources(adev->pdev->bus);
751 /* When the doorbell or fb BAR isn't available we have no chance of
754 r = amdgpu_device_doorbell_init(adev);
755 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
758 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
764 * GPU helpers function.
767 * amdgpu_device_need_post - check if the hw need post or not
769 * @adev: amdgpu_device pointer
771 * Check if the asic has been initialized (all asics) at driver startup
772 * or post is needed if hw reset is performed.
773 * Returns true if need or false if not.
775 bool amdgpu_device_need_post(struct amdgpu_device *adev)
779 if (amdgpu_sriov_vf(adev))
782 if (amdgpu_passthrough(adev)) {
783 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
784 * some old smc fw still need driver do vPost otherwise gpu hang, while
785 * those smc fw version above 22.15 doesn't have this flaw, so we force
786 * vpost executed for smc version below 22.15
788 if (adev->asic_type == CHIP_FIJI) {
791 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
792 /* force vPost if error occured */
796 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
797 if (fw_ver < 0x00160e00)
802 if (adev->has_hw_reset) {
803 adev->has_hw_reset = false;
807 /* bios scratch used on CIK+ */
808 if (adev->asic_type >= CHIP_BONAIRE)
809 return amdgpu_atombios_scratch_need_asic_init(adev);
811 /* check MEM_SIZE for older asics */
812 reg = amdgpu_asic_get_config_memsize(adev);
814 if ((reg != 0) && (reg != 0xffffffff))
820 /* if we get transitioned to only one device, take VGA back */
822 * amdgpu_device_vga_set_decode - enable/disable vga decode
824 * @cookie: amdgpu_device pointer
825 * @state: enable/disable vga decode
827 * Enable/disable vga decode (all asics).
828 * Returns VGA resource flags.
830 static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
832 struct amdgpu_device *adev = cookie;
833 amdgpu_asic_set_vga_state(adev, state);
835 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
836 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
838 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
842 * amdgpu_device_check_block_size - validate the vm block size
844 * @adev: amdgpu_device pointer
846 * Validates the vm block size specified via module parameter.
847 * The vm block size defines number of bits in page table versus page directory,
848 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
849 * page table and the remaining bits are in the page directory.
851 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
853 /* defines number of bits in page table versus page directory,
854 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
855 * page table and the remaining bits are in the page directory */
856 if (amdgpu_vm_block_size == -1)
859 if (amdgpu_vm_block_size < 9) {
860 dev_warn(adev->dev, "VM page table size (%d) too small\n",
861 amdgpu_vm_block_size);
862 amdgpu_vm_block_size = -1;
867 * amdgpu_device_check_vm_size - validate the vm size
869 * @adev: amdgpu_device pointer
871 * Validates the vm size in GB specified via module parameter.
872 * The VM size is the size of the GPU virtual memory space in GB.
874 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
876 /* no need to check the default value */
877 if (amdgpu_vm_size == -1)
880 if (amdgpu_vm_size < 1) {
881 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
887 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
890 bool is_os_64 = (sizeof(void *) == 8) ? true : false;
891 uint64_t total_memory;
892 uint64_t dram_size_seven_GB = 0x1B8000000;
893 uint64_t dram_size_three_GB = 0xB8000000;
895 if (amdgpu_smu_memory_pool_size == 0)
899 DRM_WARN("Not 64-bit OS, feature not supported\n");
903 total_memory = (uint64_t)si.totalram * si.mem_unit;
905 if ((amdgpu_smu_memory_pool_size == 1) ||
906 (amdgpu_smu_memory_pool_size == 2)) {
907 if (total_memory < dram_size_three_GB)
909 } else if ((amdgpu_smu_memory_pool_size == 4) ||
910 (amdgpu_smu_memory_pool_size == 8)) {
911 if (total_memory < dram_size_seven_GB)
914 DRM_WARN("Smu memory pool size not supported\n");
917 adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
922 DRM_WARN("No enough system memory\n");
924 adev->pm.smu_prv_buffer_size = 0;
928 * amdgpu_device_check_arguments - validate module params
930 * @adev: amdgpu_device pointer
932 * Validates certain module parameters and updates
933 * the associated values used by the driver (all asics).
935 static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
939 if (amdgpu_sched_jobs < 4) {
940 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
942 amdgpu_sched_jobs = 4;
943 } else if (!is_power_of_2(amdgpu_sched_jobs)){
944 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
946 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
949 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
950 /* gart size must be greater or equal to 32M */
951 dev_warn(adev->dev, "gart size (%d) too small\n",
953 amdgpu_gart_size = -1;
956 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
957 /* gtt size must be greater or equal to 32M */
958 dev_warn(adev->dev, "gtt size (%d) too small\n",
960 amdgpu_gtt_size = -1;
963 /* valid range is between 4 and 9 inclusive */
964 if (amdgpu_vm_fragment_size != -1 &&
965 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
966 dev_warn(adev->dev, "valid range is between 4 and 9\n");
967 amdgpu_vm_fragment_size = -1;
970 amdgpu_device_check_smu_prv_buffer_size(adev);
972 amdgpu_device_check_vm_size(adev);
974 amdgpu_device_check_block_size(adev);
976 ret = amdgpu_device_get_job_timeout_settings(adev);
978 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
982 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
988 * amdgpu_switcheroo_set_state - set switcheroo state
990 * @pdev: pci dev pointer
991 * @state: vga_switcheroo state
993 * Callback for the switcheroo driver. Suspends or resumes the
994 * the asics before or after it is powered up using ACPI methods.
996 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
998 struct drm_device *dev = pci_get_drvdata(pdev);
1000 if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1003 if (state == VGA_SWITCHEROO_ON) {
1004 pr_info("amdgpu: switched on\n");
1005 /* don't suspend or resume card normally */
1006 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1008 amdgpu_device_resume(dev, true, true);
1010 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1011 drm_kms_helper_poll_enable(dev);
1013 pr_info("amdgpu: switched off\n");
1014 drm_kms_helper_poll_disable(dev);
1015 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1016 amdgpu_device_suspend(dev, true, true);
1017 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1022 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1024 * @pdev: pci dev pointer
1026 * Callback for the switcheroo driver. Check of the switcheroo
1027 * state can be changed.
1028 * Returns true if the state can be changed, false if not.
1030 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1032 struct drm_device *dev = pci_get_drvdata(pdev);
1035 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1036 * locking inversion with the driver load path. And the access here is
1037 * completely racy anyway. So don't bother with locking for now.
1039 return dev->open_count == 0;
1042 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1043 .set_gpu_state = amdgpu_switcheroo_set_state,
1045 .can_switch = amdgpu_switcheroo_can_switch,
1049 * amdgpu_device_ip_set_clockgating_state - set the CG state
1051 * @dev: amdgpu_device pointer
1052 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1053 * @state: clockgating state (gate or ungate)
1055 * Sets the requested clockgating state for all instances of
1056 * the hardware IP specified.
1057 * Returns the error code from the last instance.
1059 int amdgpu_device_ip_set_clockgating_state(void *dev,
1060 enum amd_ip_block_type block_type,
1061 enum amd_clockgating_state state)
1063 struct amdgpu_device *adev = dev;
1066 for (i = 0; i < adev->num_ip_blocks; i++) {
1067 if (!adev->ip_blocks[i].status.valid)
1069 if (adev->ip_blocks[i].version->type != block_type)
1071 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1073 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1074 (void *)adev, state);
1076 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1077 adev->ip_blocks[i].version->funcs->name, r);
1083 * amdgpu_device_ip_set_powergating_state - set the PG state
1085 * @dev: amdgpu_device pointer
1086 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1087 * @state: powergating state (gate or ungate)
1089 * Sets the requested powergating state for all instances of
1090 * the hardware IP specified.
1091 * Returns the error code from the last instance.
1093 int amdgpu_device_ip_set_powergating_state(void *dev,
1094 enum amd_ip_block_type block_type,
1095 enum amd_powergating_state state)
1097 struct amdgpu_device *adev = dev;
1100 for (i = 0; i < adev->num_ip_blocks; i++) {
1101 if (!adev->ip_blocks[i].status.valid)
1103 if (adev->ip_blocks[i].version->type != block_type)
1105 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1107 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1108 (void *)adev, state);
1110 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1111 adev->ip_blocks[i].version->funcs->name, r);
1117 * amdgpu_device_ip_get_clockgating_state - get the CG state
1119 * @adev: amdgpu_device pointer
1120 * @flags: clockgating feature flags
1122 * Walks the list of IPs on the device and updates the clockgating
1123 * flags for each IP.
1124 * Updates @flags with the feature flags for each hardware IP where
1125 * clockgating is enabled.
1127 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1132 for (i = 0; i < adev->num_ip_blocks; i++) {
1133 if (!adev->ip_blocks[i].status.valid)
1135 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1136 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1141 * amdgpu_device_ip_wait_for_idle - wait for idle
1143 * @adev: amdgpu_device pointer
1144 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1146 * Waits for the request hardware IP to be idle.
1147 * Returns 0 for success or a negative error code on failure.
1149 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1150 enum amd_ip_block_type block_type)
1154 for (i = 0; i < adev->num_ip_blocks; i++) {
1155 if (!adev->ip_blocks[i].status.valid)
1157 if (adev->ip_blocks[i].version->type == block_type) {
1158 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1169 * amdgpu_device_ip_is_idle - is the hardware IP idle
1171 * @adev: amdgpu_device pointer
1172 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1174 * Check if the hardware IP is idle or not.
1175 * Returns true if it the IP is idle, false if not.
1177 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1178 enum amd_ip_block_type block_type)
1182 for (i = 0; i < adev->num_ip_blocks; i++) {
1183 if (!adev->ip_blocks[i].status.valid)
1185 if (adev->ip_blocks[i].version->type == block_type)
1186 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1193 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1195 * @adev: amdgpu_device pointer
1196 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1198 * Returns a pointer to the hardware IP block structure
1199 * if it exists for the asic, otherwise NULL.
1201 struct amdgpu_ip_block *
1202 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1203 enum amd_ip_block_type type)
1207 for (i = 0; i < adev->num_ip_blocks; i++)
1208 if (adev->ip_blocks[i].version->type == type)
1209 return &adev->ip_blocks[i];
1215 * amdgpu_device_ip_block_version_cmp
1217 * @adev: amdgpu_device pointer
1218 * @type: enum amd_ip_block_type
1219 * @major: major version
1220 * @minor: minor version
1222 * return 0 if equal or greater
1223 * return 1 if smaller or the ip_block doesn't exist
1225 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1226 enum amd_ip_block_type type,
1227 u32 major, u32 minor)
1229 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1231 if (ip_block && ((ip_block->version->major > major) ||
1232 ((ip_block->version->major == major) &&
1233 (ip_block->version->minor >= minor))))
1240 * amdgpu_device_ip_block_add
1242 * @adev: amdgpu_device pointer
1243 * @ip_block_version: pointer to the IP to add
1245 * Adds the IP block driver information to the collection of IPs
1248 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1249 const struct amdgpu_ip_block_version *ip_block_version)
1251 if (!ip_block_version)
1254 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1255 ip_block_version->funcs->name);
1257 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1263 * amdgpu_device_enable_virtual_display - enable virtual display feature
1265 * @adev: amdgpu_device pointer
1267 * Enabled the virtual display feature if the user has enabled it via
1268 * the module parameter virtual_display. This feature provides a virtual
1269 * display hardware on headless boards or in virtualized environments.
1270 * This function parses and validates the configuration string specified by
1271 * the user and configues the virtual display configuration (number of
1272 * virtual connectors, crtcs, etc.) specified.
1274 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1276 adev->enable_virtual_display = false;
1278 if (amdgpu_virtual_display) {
1279 struct drm_device *ddev = adev->ddev;
1280 const char *pci_address_name = pci_name(ddev->pdev);
1281 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1283 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1284 pciaddstr_tmp = pciaddstr;
1285 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1286 pciaddname = strsep(&pciaddname_tmp, ",");
1287 if (!strcmp("all", pciaddname)
1288 || !strcmp(pci_address_name, pciaddname)) {
1292 adev->enable_virtual_display = true;
1295 res = kstrtol(pciaddname_tmp, 10,
1303 adev->mode_info.num_crtc = num_crtc;
1305 adev->mode_info.num_crtc = 1;
1311 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1312 amdgpu_virtual_display, pci_address_name,
1313 adev->enable_virtual_display, adev->mode_info.num_crtc);
1320 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1322 * @adev: amdgpu_device pointer
1324 * Parses the asic configuration parameters specified in the gpu info
1325 * firmware and makes them availale to the driver for use in configuring
1327 * Returns 0 on success, -EINVAL on failure.
1329 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1331 const char *chip_name;
1334 const struct gpu_info_firmware_header_v1_0 *hdr;
1336 adev->firmware.gpu_info_fw = NULL;
1338 switch (adev->asic_type) {
1342 case CHIP_POLARIS10:
1343 case CHIP_POLARIS11:
1344 case CHIP_POLARIS12:
1348 #ifdef CONFIG_DRM_AMDGPU_SI
1355 #ifdef CONFIG_DRM_AMDGPU_CIK
1366 chip_name = "vega10";
1369 chip_name = "vega12";
1372 if (adev->rev_id >= 8)
1373 chip_name = "raven2";
1374 else if (adev->pdev->device == 0x15d8)
1375 chip_name = "picasso";
1377 chip_name = "raven";
1381 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1382 err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1385 "Failed to load gpu_info firmware \"%s\"\n",
1389 err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1392 "Failed to validate gpu_info firmware \"%s\"\n",
1397 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1398 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1400 switch (hdr->version_major) {
1403 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1404 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1405 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1407 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1408 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1409 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1410 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1411 adev->gfx.config.max_texture_channel_caches =
1412 le32_to_cpu(gpu_info_fw->gc_num_tccs);
1413 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1414 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1415 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1416 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1417 adev->gfx.config.double_offchip_lds_buf =
1418 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1419 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1420 adev->gfx.cu_info.max_waves_per_simd =
1421 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1422 adev->gfx.cu_info.max_scratch_slots_per_cu =
1423 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1424 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1429 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1438 * amdgpu_device_ip_early_init - run early init for hardware IPs
1440 * @adev: amdgpu_device pointer
1442 * Early initialization pass for hardware IPs. The hardware IPs that make
1443 * up each asic are discovered each IP's early_init callback is run. This
1444 * is the first stage in initializing the asic.
1445 * Returns 0 on success, negative error code on failure.
1447 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
1451 amdgpu_device_enable_virtual_display(adev);
1453 switch (adev->asic_type) {
1457 case CHIP_POLARIS10:
1458 case CHIP_POLARIS11:
1459 case CHIP_POLARIS12:
1463 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1464 adev->family = AMDGPU_FAMILY_CZ;
1466 adev->family = AMDGPU_FAMILY_VI;
1468 r = vi_set_ip_blocks(adev);
1472 #ifdef CONFIG_DRM_AMDGPU_SI
1478 adev->family = AMDGPU_FAMILY_SI;
1479 r = si_set_ip_blocks(adev);
1484 #ifdef CONFIG_DRM_AMDGPU_CIK
1490 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1491 adev->family = AMDGPU_FAMILY_CI;
1493 adev->family = AMDGPU_FAMILY_KV;
1495 r = cik_set_ip_blocks(adev);
1504 if (adev->asic_type == CHIP_RAVEN)
1505 adev->family = AMDGPU_FAMILY_RV;
1507 adev->family = AMDGPU_FAMILY_AI;
1509 r = soc15_set_ip_blocks(adev);
1514 /* FIXME: not supported yet */
1518 r = amdgpu_device_parse_gpu_info_fw(adev);
1522 amdgpu_amdkfd_device_probe(adev);
1524 if (amdgpu_sriov_vf(adev)) {
1525 r = amdgpu_virt_request_full_gpu(adev, true);
1529 /* query the reg access mode at the very beginning */
1530 amdgpu_virt_init_reg_access_mode(adev);
1533 adev->pm.pp_feature = amdgpu_pp_feature_mask;
1534 if (amdgpu_sriov_vf(adev))
1535 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
1537 for (i = 0; i < adev->num_ip_blocks; i++) {
1538 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1539 DRM_ERROR("disabled ip block: %d <%s>\n",
1540 i, adev->ip_blocks[i].version->funcs->name);
1541 adev->ip_blocks[i].status.valid = false;
1543 if (adev->ip_blocks[i].version->funcs->early_init) {
1544 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1546 adev->ip_blocks[i].status.valid = false;
1548 DRM_ERROR("early_init of IP block <%s> failed %d\n",
1549 adev->ip_blocks[i].version->funcs->name, r);
1552 adev->ip_blocks[i].status.valid = true;
1555 adev->ip_blocks[i].status.valid = true;
1558 /* get the vbios after the asic_funcs are set up */
1559 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
1561 if (!amdgpu_get_bios(adev))
1564 r = amdgpu_atombios_init(adev);
1566 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1567 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
1573 adev->cg_flags &= amdgpu_cg_mask;
1574 adev->pg_flags &= amdgpu_pg_mask;
1579 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
1583 for (i = 0; i < adev->num_ip_blocks; i++) {
1584 if (!adev->ip_blocks[i].status.sw)
1586 if (adev->ip_blocks[i].status.hw)
1588 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1589 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
1590 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
1591 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1593 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1594 adev->ip_blocks[i].version->funcs->name, r);
1597 adev->ip_blocks[i].status.hw = true;
1604 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
1608 for (i = 0; i < adev->num_ip_blocks; i++) {
1609 if (!adev->ip_blocks[i].status.sw)
1611 if (adev->ip_blocks[i].status.hw)
1613 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1615 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1616 adev->ip_blocks[i].version->funcs->name, r);
1619 adev->ip_blocks[i].status.hw = true;
1625 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
1629 uint32_t smu_version;
1631 if (adev->asic_type >= CHIP_VEGA10) {
1632 for (i = 0; i < adev->num_ip_blocks; i++) {
1633 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
1634 if (adev->in_gpu_reset || adev->in_suspend) {
1635 if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset)
1636 break; /* sriov gpu reset, psp need to do hw_init before IH because of hw limit */
1637 r = adev->ip_blocks[i].version->funcs->resume(adev);
1639 DRM_ERROR("resume of IP block <%s> failed %d\n",
1640 adev->ip_blocks[i].version->funcs->name, r);
1644 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1646 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1647 adev->ip_blocks[i].version->funcs->name, r);
1651 adev->ip_blocks[i].status.hw = true;
1655 r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
1661 * amdgpu_device_ip_init - run init for hardware IPs
1663 * @adev: amdgpu_device pointer
1665 * Main initialization pass for hardware IPs. The list of all the hardware
1666 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
1667 * are run. sw_init initializes the software state associated with each IP
1668 * and hw_init initializes the hardware associated with each IP.
1669 * Returns 0 on success, negative error code on failure.
1671 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
1675 r = amdgpu_ras_init(adev);
1679 for (i = 0; i < adev->num_ip_blocks; i++) {
1680 if (!adev->ip_blocks[i].status.valid)
1682 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1684 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1685 adev->ip_blocks[i].version->funcs->name, r);
1688 adev->ip_blocks[i].status.sw = true;
1690 /* need to do gmc hw init early so we can allocate gpu mem */
1691 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1692 r = amdgpu_device_vram_scratch_init(adev);
1694 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1697 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1699 DRM_ERROR("hw_init %d failed %d\n", i, r);
1702 r = amdgpu_device_wb_init(adev);
1704 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
1707 adev->ip_blocks[i].status.hw = true;
1709 /* right after GMC hw init, we create CSA */
1710 if (amdgpu_sriov_vf(adev)) {
1711 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
1712 AMDGPU_GEM_DOMAIN_VRAM,
1715 DRM_ERROR("allocate CSA failed %d\n", r);
1722 r = amdgpu_ib_pool_init(adev);
1724 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1725 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
1729 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
1733 r = amdgpu_device_ip_hw_init_phase1(adev);
1737 r = amdgpu_device_fw_loading(adev);
1741 r = amdgpu_device_ip_hw_init_phase2(adev);
1745 if (adev->gmc.xgmi.num_physical_nodes > 1)
1746 amdgpu_xgmi_add_device(adev);
1747 amdgpu_amdkfd_device_init(adev);
1750 if (amdgpu_sriov_vf(adev)) {
1752 amdgpu_virt_init_data_exchange(adev);
1753 amdgpu_virt_release_full_gpu(adev, true);
1760 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
1762 * @adev: amdgpu_device pointer
1764 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
1765 * this function before a GPU reset. If the value is retained after a
1766 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
1768 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
1770 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
1774 * amdgpu_device_check_vram_lost - check if vram is valid
1776 * @adev: amdgpu_device pointer
1778 * Checks the reset magic value written to the gart pointer in VRAM.
1779 * The driver calls this after a GPU reset to see if the contents of
1780 * VRAM is lost or now.
1781 * returns true if vram is lost, false if not.
1783 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
1785 return !!memcmp(adev->gart.ptr, adev->reset_magic,
1786 AMDGPU_RESET_MAGIC_NUM);
1790 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
1792 * @adev: amdgpu_device pointer
1794 * The list of all the hardware IPs that make up the asic is walked and the
1795 * set_clockgating_state callbacks are run.
1796 * Late initialization pass enabling clockgating for hardware IPs.
1797 * Fini or suspend, pass disabling clockgating for hardware IPs.
1798 * Returns 0 on success, negative error code on failure.
1801 static int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1802 enum amd_clockgating_state state)
1806 if (amdgpu_emu_mode == 1)
1809 for (j = 0; j < adev->num_ip_blocks; j++) {
1810 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
1811 if (!adev->ip_blocks[i].status.late_initialized)
1813 /* skip CG for VCE/UVD, it's handled specially */
1814 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1815 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1816 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1817 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
1818 /* enable clockgating to save power */
1819 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1822 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1823 adev->ip_blocks[i].version->funcs->name, r);
1832 static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state)
1836 if (amdgpu_emu_mode == 1)
1839 for (j = 0; j < adev->num_ip_blocks; j++) {
1840 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
1841 if (!adev->ip_blocks[i].status.late_initialized)
1843 /* skip CG for VCE/UVD, it's handled specially */
1844 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1845 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1846 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1847 adev->ip_blocks[i].version->funcs->set_powergating_state) {
1848 /* enable powergating to save power */
1849 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
1852 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
1853 adev->ip_blocks[i].version->funcs->name, r);
1861 static int amdgpu_device_enable_mgpu_fan_boost(void)
1863 struct amdgpu_gpu_instance *gpu_ins;
1864 struct amdgpu_device *adev;
1867 mutex_lock(&mgpu_info.mutex);
1870 * MGPU fan boost feature should be enabled
1871 * only when there are two or more dGPUs in
1874 if (mgpu_info.num_dgpu < 2)
1877 for (i = 0; i < mgpu_info.num_dgpu; i++) {
1878 gpu_ins = &(mgpu_info.gpu_ins[i]);
1879 adev = gpu_ins->adev;
1880 if (!(adev->flags & AMD_IS_APU) &&
1881 !gpu_ins->mgpu_fan_enabled &&
1882 adev->powerplay.pp_funcs &&
1883 adev->powerplay.pp_funcs->enable_mgpu_fan_boost) {
1884 ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
1888 gpu_ins->mgpu_fan_enabled = 1;
1893 mutex_unlock(&mgpu_info.mutex);
1899 * amdgpu_device_ip_late_init - run late init for hardware IPs
1901 * @adev: amdgpu_device pointer
1903 * Late initialization pass for hardware IPs. The list of all the hardware
1904 * IPs that make up the asic is walked and the late_init callbacks are run.
1905 * late_init covers any special initialization that an IP requires
1906 * after all of the have been initialized or something that needs to happen
1907 * late in the init process.
1908 * Returns 0 on success, negative error code on failure.
1910 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
1914 for (i = 0; i < adev->num_ip_blocks; i++) {
1915 if (!adev->ip_blocks[i].status.hw)
1917 if (adev->ip_blocks[i].version->funcs->late_init) {
1918 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1920 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1921 adev->ip_blocks[i].version->funcs->name, r);
1925 adev->ip_blocks[i].status.late_initialized = true;
1928 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
1929 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
1931 amdgpu_device_fill_reset_magic(adev);
1933 r = amdgpu_device_enable_mgpu_fan_boost();
1935 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
1937 /* set to low pstate by default */
1938 amdgpu_xgmi_set_pstate(adev, 0);
1944 * amdgpu_device_ip_fini - run fini for hardware IPs
1946 * @adev: amdgpu_device pointer
1948 * Main teardown pass for hardware IPs. The list of all the hardware
1949 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
1950 * are run. hw_fini tears down the hardware associated with each IP
1951 * and sw_fini tears down any software state associated with each IP.
1952 * Returns 0 on success, negative error code on failure.
1954 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
1958 amdgpu_ras_pre_fini(adev);
1960 if (adev->gmc.xgmi.num_physical_nodes > 1)
1961 amdgpu_xgmi_remove_device(adev);
1963 amdgpu_amdkfd_device_fini(adev);
1965 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
1966 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
1968 /* need to disable SMC first */
1969 for (i = 0; i < adev->num_ip_blocks; i++) {
1970 if (!adev->ip_blocks[i].status.hw)
1972 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
1973 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1974 /* XXX handle errors */
1976 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1977 adev->ip_blocks[i].version->funcs->name, r);
1979 adev->ip_blocks[i].status.hw = false;
1984 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1985 if (!adev->ip_blocks[i].status.hw)
1988 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1989 /* XXX handle errors */
1991 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1992 adev->ip_blocks[i].version->funcs->name, r);
1995 adev->ip_blocks[i].status.hw = false;
1999 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2000 if (!adev->ip_blocks[i].status.sw)
2003 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2004 amdgpu_ucode_free_bo(adev);
2005 amdgpu_free_static_csa(&adev->virt.csa_obj);
2006 amdgpu_device_wb_fini(adev);
2007 amdgpu_device_vram_scratch_fini(adev);
2008 amdgpu_ib_pool_fini(adev);
2011 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
2012 /* XXX handle errors */
2014 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
2015 adev->ip_blocks[i].version->funcs->name, r);
2017 adev->ip_blocks[i].status.sw = false;
2018 adev->ip_blocks[i].status.valid = false;
2021 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2022 if (!adev->ip_blocks[i].status.late_initialized)
2024 if (adev->ip_blocks[i].version->funcs->late_fini)
2025 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
2026 adev->ip_blocks[i].status.late_initialized = false;
2029 amdgpu_ras_fini(adev);
2031 if (amdgpu_sriov_vf(adev))
2032 if (amdgpu_virt_release_full_gpu(adev, false))
2033 DRM_ERROR("failed to release exclusive mode on fini\n");
2039 * amdgpu_device_delayed_init_work_handler - work handler for IB tests
2041 * @work: work_struct.
2043 static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
2045 struct amdgpu_device *adev =
2046 container_of(work, struct amdgpu_device, delayed_init_work.work);
2049 r = amdgpu_ib_ring_tests(adev);
2051 DRM_ERROR("ib ring test failed (%d).\n", r);
2054 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
2056 struct amdgpu_device *adev =
2057 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
2059 mutex_lock(&adev->gfx.gfx_off_mutex);
2060 if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
2061 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2062 adev->gfx.gfx_off_state = true;
2064 mutex_unlock(&adev->gfx.gfx_off_mutex);
2068 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2070 * @adev: amdgpu_device pointer
2072 * Main suspend function for hardware IPs. The list of all the hardware
2073 * IPs that make up the asic is walked, clockgating is disabled and the
2074 * suspend callbacks are run. suspend puts the hardware and software state
2075 * in each IP into a state suitable for suspend.
2076 * Returns 0 on success, negative error code on failure.
2078 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
2082 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2083 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2085 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2086 if (!adev->ip_blocks[i].status.valid)
2088 /* displays are handled separately */
2089 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) {
2090 /* XXX handle errors */
2091 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2092 /* XXX handle errors */
2094 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2095 adev->ip_blocks[i].version->funcs->name, r);
2104 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
2106 * @adev: amdgpu_device pointer
2108 * Main suspend function for hardware IPs. The list of all the hardware
2109 * IPs that make up the asic is walked, clockgating is disabled and the
2110 * suspend callbacks are run. suspend puts the hardware and software state
2111 * in each IP into a state suitable for suspend.
2112 * Returns 0 on success, negative error code on failure.
2114 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
2118 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2119 if (!adev->ip_blocks[i].status.valid)
2121 /* displays are handled in phase1 */
2122 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
2124 /* XXX handle errors */
2125 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2126 /* XXX handle errors */
2128 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2129 adev->ip_blocks[i].version->funcs->name, r);
2137 * amdgpu_device_ip_suspend - run suspend for hardware IPs
2139 * @adev: amdgpu_device pointer
2141 * Main suspend function for hardware IPs. The list of all the hardware
2142 * IPs that make up the asic is walked, clockgating is disabled and the
2143 * suspend callbacks are run. suspend puts the hardware and software state
2144 * in each IP into a state suitable for suspend.
2145 * Returns 0 on success, negative error code on failure.
2147 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
2151 if (amdgpu_sriov_vf(adev))
2152 amdgpu_virt_request_full_gpu(adev, false);
2154 r = amdgpu_device_ip_suspend_phase1(adev);
2157 r = amdgpu_device_ip_suspend_phase2(adev);
2159 if (amdgpu_sriov_vf(adev))
2160 amdgpu_virt_release_full_gpu(adev, false);
2165 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
2169 static enum amd_ip_block_type ip_order[] = {
2170 AMD_IP_BLOCK_TYPE_GMC,
2171 AMD_IP_BLOCK_TYPE_COMMON,
2172 AMD_IP_BLOCK_TYPE_PSP,
2173 AMD_IP_BLOCK_TYPE_IH,
2176 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2178 struct amdgpu_ip_block *block;
2180 for (j = 0; j < adev->num_ip_blocks; j++) {
2181 block = &adev->ip_blocks[j];
2183 if (block->version->type != ip_order[i] ||
2184 !block->status.valid)
2187 r = block->version->funcs->hw_init(adev);
2188 DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2197 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
2201 static enum amd_ip_block_type ip_order[] = {
2202 AMD_IP_BLOCK_TYPE_SMC,
2203 AMD_IP_BLOCK_TYPE_DCE,
2204 AMD_IP_BLOCK_TYPE_GFX,
2205 AMD_IP_BLOCK_TYPE_SDMA,
2206 AMD_IP_BLOCK_TYPE_UVD,
2207 AMD_IP_BLOCK_TYPE_VCE
2210 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2212 struct amdgpu_ip_block *block;
2214 for (j = 0; j < adev->num_ip_blocks; j++) {
2215 block = &adev->ip_blocks[j];
2217 if (block->version->type != ip_order[i] ||
2218 !block->status.valid)
2221 r = block->version->funcs->hw_init(adev);
2222 DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2232 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
2234 * @adev: amdgpu_device pointer
2236 * First resume function for hardware IPs. The list of all the hardware
2237 * IPs that make up the asic is walked and the resume callbacks are run for
2238 * COMMON, GMC, and IH. resume puts the hardware into a functional state
2239 * after a suspend and updates the software state as necessary. This
2240 * function is also used for restoring the GPU after a GPU reset.
2241 * Returns 0 on success, negative error code on failure.
2243 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
2247 for (i = 0; i < adev->num_ip_blocks; i++) {
2248 if (!adev->ip_blocks[i].status.valid)
2250 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2251 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2252 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2253 r = adev->ip_blocks[i].version->funcs->resume(adev);
2255 DRM_ERROR("resume of IP block <%s> failed %d\n",
2256 adev->ip_blocks[i].version->funcs->name, r);
2266 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
2268 * @adev: amdgpu_device pointer
2270 * First resume function for hardware IPs. The list of all the hardware
2271 * IPs that make up the asic is walked and the resume callbacks are run for
2272 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
2273 * functional state after a suspend and updates the software state as
2274 * necessary. This function is also used for restoring the GPU after a GPU
2276 * Returns 0 on success, negative error code on failure.
2278 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
2282 for (i = 0; i < adev->num_ip_blocks; i++) {
2283 if (!adev->ip_blocks[i].status.valid)
2285 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2286 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2287 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
2288 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
2290 r = adev->ip_blocks[i].version->funcs->resume(adev);
2292 DRM_ERROR("resume of IP block <%s> failed %d\n",
2293 adev->ip_blocks[i].version->funcs->name, r);
2302 * amdgpu_device_ip_resume - run resume for hardware IPs
2304 * @adev: amdgpu_device pointer
2306 * Main resume function for hardware IPs. The hardware IPs
2307 * are split into two resume functions because they are
2308 * are also used in in recovering from a GPU reset and some additional
2309 * steps need to be take between them. In this case (S3/S4) they are
2311 * Returns 0 on success, negative error code on failure.
2313 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
2317 r = amdgpu_device_ip_resume_phase1(adev);
2321 r = amdgpu_device_fw_loading(adev);
2325 r = amdgpu_device_ip_resume_phase2(adev);
2331 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
2333 * @adev: amdgpu_device pointer
2335 * Query the VBIOS data tables to determine if the board supports SR-IOV.
2337 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
2339 if (amdgpu_sriov_vf(adev)) {
2340 if (adev->is_atom_fw) {
2341 if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
2342 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2344 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
2345 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2348 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
2349 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2354 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
2356 * @asic_type: AMD asic type
2358 * Check if there is DC (new modesetting infrastructre) support for an asic.
2359 * returns true if DC has support, false if not.
2361 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
2363 switch (asic_type) {
2364 #if defined(CONFIG_DRM_AMD_DC)
2370 * We have systems in the wild with these ASICs that require
2371 * LVDS and VGA support which is not supported with DC.
2373 * Fallback to the non-DC driver here by default so as not to
2374 * cause regressions.
2376 return amdgpu_dc > 0;
2380 case CHIP_POLARIS10:
2381 case CHIP_POLARIS11:
2382 case CHIP_POLARIS12:
2389 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2392 return amdgpu_dc != 0;
2400 * amdgpu_device_has_dc_support - check if dc is supported
2402 * @adev: amdgpu_device_pointer
2404 * Returns true for supported, false for not supported
2406 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
2408 if (amdgpu_sriov_vf(adev))
2411 return amdgpu_device_asic_has_dc_support(adev->asic_type);
2415 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
2417 struct amdgpu_device *adev =
2418 container_of(__work, struct amdgpu_device, xgmi_reset_work);
2420 adev->asic_reset_res = amdgpu_asic_reset(adev);
2421 if (adev->asic_reset_res)
2422 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
2423 adev->asic_reset_res, adev->ddev->unique);
2428 * amdgpu_device_init - initialize the driver
2430 * @adev: amdgpu_device pointer
2431 * @ddev: drm dev pointer
2432 * @pdev: pci dev pointer
2433 * @flags: driver flags
2435 * Initializes the driver info and hw (all asics).
2436 * Returns 0 for success or an error on failure.
2437 * Called at driver startup.
2439 int amdgpu_device_init(struct amdgpu_device *adev,
2440 struct drm_device *ddev,
2441 struct pci_dev *pdev,
2445 bool runtime = false;
2448 adev->shutdown = false;
2449 adev->dev = &pdev->dev;
2452 adev->flags = flags;
2453 adev->asic_type = flags & AMD_ASIC_MASK;
2454 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
2455 if (amdgpu_emu_mode == 1)
2456 adev->usec_timeout *= 2;
2457 adev->gmc.gart_size = 512 * 1024 * 1024;
2458 adev->accel_working = false;
2459 adev->num_rings = 0;
2460 adev->mman.buffer_funcs = NULL;
2461 adev->mman.buffer_funcs_ring = NULL;
2462 adev->vm_manager.vm_pte_funcs = NULL;
2463 adev->vm_manager.vm_pte_num_rqs = 0;
2464 adev->gmc.gmc_funcs = NULL;
2465 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2466 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2468 adev->smc_rreg = &amdgpu_invalid_rreg;
2469 adev->smc_wreg = &amdgpu_invalid_wreg;
2470 adev->pcie_rreg = &amdgpu_invalid_rreg;
2471 adev->pcie_wreg = &amdgpu_invalid_wreg;
2472 adev->pciep_rreg = &amdgpu_invalid_rreg;
2473 adev->pciep_wreg = &amdgpu_invalid_wreg;
2474 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
2475 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
2476 adev->didt_rreg = &amdgpu_invalid_rreg;
2477 adev->didt_wreg = &amdgpu_invalid_wreg;
2478 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
2479 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
2480 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
2481 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
2483 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
2484 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
2485 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
2487 /* mutex initialization are all done here so we
2488 * can recall function without having locking issues */
2489 atomic_set(&adev->irq.ih.lock, 0);
2490 mutex_init(&adev->firmware.mutex);
2491 mutex_init(&adev->pm.mutex);
2492 mutex_init(&adev->gfx.gpu_clock_mutex);
2493 mutex_init(&adev->srbm_mutex);
2494 mutex_init(&adev->gfx.pipe_reserve_mutex);
2495 mutex_init(&adev->gfx.gfx_off_mutex);
2496 mutex_init(&adev->grbm_idx_mutex);
2497 mutex_init(&adev->mn_lock);
2498 mutex_init(&adev->virt.vf_errors.lock);
2499 hash_init(adev->mn_hash);
2500 mutex_init(&adev->lock_reset);
2501 mutex_init(&adev->virt.dpm_mutex);
2503 r = amdgpu_device_check_arguments(adev);
2507 spin_lock_init(&adev->mmio_idx_lock);
2508 spin_lock_init(&adev->smc_idx_lock);
2509 spin_lock_init(&adev->pcie_idx_lock);
2510 spin_lock_init(&adev->uvd_ctx_idx_lock);
2511 spin_lock_init(&adev->didt_idx_lock);
2512 spin_lock_init(&adev->gc_cac_idx_lock);
2513 spin_lock_init(&adev->se_cac_idx_lock);
2514 spin_lock_init(&adev->audio_endpt_idx_lock);
2515 spin_lock_init(&adev->mm_stats.lock);
2517 INIT_LIST_HEAD(&adev->shadow_list);
2518 mutex_init(&adev->shadow_list_lock);
2520 INIT_LIST_HEAD(&adev->ring_lru_list);
2521 spin_lock_init(&adev->ring_lru_list_lock);
2523 INIT_DELAYED_WORK(&adev->delayed_init_work,
2524 amdgpu_device_delayed_init_work_handler);
2525 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
2526 amdgpu_device_delay_enable_gfx_off);
2528 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
2530 adev->gfx.gfx_off_req_count = 1;
2531 adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true : false;
2533 /* Registers mapping */
2534 /* TODO: block userspace mapping of io register */
2535 if (adev->asic_type >= CHIP_BONAIRE) {
2536 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
2537 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
2539 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
2540 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
2543 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
2544 if (adev->rmmio == NULL) {
2547 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
2548 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
2550 /* io port mapping */
2551 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2552 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
2553 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
2554 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
2558 if (adev->rio_mem == NULL)
2559 DRM_INFO("PCI I/O BAR is not found.\n");
2561 amdgpu_device_get_pcie_info(adev);
2563 /* early init functions */
2564 r = amdgpu_device_ip_early_init(adev);
2568 /* doorbell bar mapping and doorbell index init*/
2569 amdgpu_device_doorbell_init(adev);
2571 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
2572 /* this will fail for cards that aren't VGA class devices, just
2574 vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
2576 if (amdgpu_device_is_px(ddev))
2578 if (!pci_is_thunderbolt_attached(adev->pdev))
2579 vga_switcheroo_register_client(adev->pdev,
2580 &amdgpu_switcheroo_ops, runtime);
2582 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
2584 if (amdgpu_emu_mode == 1) {
2585 /* post the asic on emulation mode */
2586 emu_soc_asic_init(adev);
2587 goto fence_driver_init;
2590 /* detect if we are with an SRIOV vbios */
2591 amdgpu_device_detect_sriov_bios(adev);
2593 /* check if we need to reset the asic
2594 * E.g., driver was not cleanly unloaded previously, etc.
2596 if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
2597 r = amdgpu_asic_reset(adev);
2599 dev_err(adev->dev, "asic reset on init failed\n");
2604 /* Post card if necessary */
2605 if (amdgpu_device_need_post(adev)) {
2607 dev_err(adev->dev, "no vBIOS found\n");
2611 DRM_INFO("GPU posting now...\n");
2612 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2614 dev_err(adev->dev, "gpu post error!\n");
2619 if (adev->is_atom_fw) {
2620 /* Initialize clocks */
2621 r = amdgpu_atomfirmware_get_clock_info(adev);
2623 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
2624 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2628 /* Initialize clocks */
2629 r = amdgpu_atombios_get_clock_info(adev);
2631 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
2632 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2635 /* init i2c buses */
2636 if (!amdgpu_device_has_dc_support(adev))
2637 amdgpu_atombios_i2c_init(adev);
2642 r = amdgpu_fence_driver_init(adev);
2644 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
2645 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
2649 /* init the mode config */
2650 drm_mode_config_init(adev->ddev);
2652 r = amdgpu_device_ip_init(adev);
2654 /* failed in exclusive mode due to timeout */
2655 if (amdgpu_sriov_vf(adev) &&
2656 !amdgpu_sriov_runtime(adev) &&
2657 amdgpu_virt_mmio_blocked(adev) &&
2658 !amdgpu_virt_wait_reset(adev)) {
2659 dev_err(adev->dev, "VF exclusive mode timeout\n");
2660 /* Don't send request since VF is inactive. */
2661 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
2662 adev->virt.ops = NULL;
2666 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
2667 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
2668 if (amdgpu_virt_request_full_gpu(adev, false))
2669 amdgpu_virt_release_full_gpu(adev, false);
2673 adev->accel_working = true;
2675 amdgpu_vm_check_compute_bug(adev);
2677 /* Initialize the buffer migration limit. */
2678 if (amdgpu_moverate >= 0)
2679 max_MBps = amdgpu_moverate;
2681 max_MBps = 8; /* Allow 8 MB/s. */
2682 /* Get a log2 for easy divisions. */
2683 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
2685 amdgpu_fbdev_init(adev);
2687 if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
2688 amdgpu_pm_virt_sysfs_init(adev);
2690 r = amdgpu_pm_sysfs_init(adev);
2692 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
2694 r = amdgpu_ucode_sysfs_init(adev);
2696 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
2698 r = amdgpu_debugfs_gem_init(adev);
2700 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2702 r = amdgpu_debugfs_regs_init(adev);
2704 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2706 r = amdgpu_debugfs_firmware_init(adev);
2708 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2710 r = amdgpu_debugfs_init(adev);
2712 DRM_ERROR("Creating debugfs files failed (%d).\n", r);
2714 if ((amdgpu_testing & 1)) {
2715 if (adev->accel_working)
2716 amdgpu_test_moves(adev);
2718 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2720 if (amdgpu_benchmarking) {
2721 if (adev->accel_working)
2722 amdgpu_benchmark(adev, amdgpu_benchmarking);
2724 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2727 /* enable clockgating, etc. after ib tests, etc. since some blocks require
2728 * explicit gating rather than handling it automatically.
2730 r = amdgpu_device_ip_late_init(adev);
2732 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
2733 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
2738 amdgpu_ras_resume(adev);
2740 queue_delayed_work(system_wq, &adev->delayed_init_work,
2741 msecs_to_jiffies(AMDGPU_RESUME_MS));
2743 r = device_create_file(adev->dev, &dev_attr_pcie_replay_count);
2745 dev_err(adev->dev, "Could not create pcie_replay_count");
2752 amdgpu_vf_error_trans_all(adev);
2754 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2760 * amdgpu_device_fini - tear down the driver
2762 * @adev: amdgpu_device pointer
2764 * Tear down the driver info (all asics).
2765 * Called at driver shutdown.
2767 void amdgpu_device_fini(struct amdgpu_device *adev)
2771 DRM_INFO("amdgpu: finishing device.\n");
2772 adev->shutdown = true;
2773 /* disable all interrupts */
2774 amdgpu_irq_disable_all(adev);
2775 if (adev->mode_info.mode_config_initialized){
2776 if (!amdgpu_device_has_dc_support(adev))
2777 drm_helper_force_disable_all(adev->ddev);
2779 drm_atomic_helper_shutdown(adev->ddev);
2781 amdgpu_fence_driver_fini(adev);
2782 amdgpu_pm_sysfs_fini(adev);
2783 amdgpu_fbdev_fini(adev);
2784 r = amdgpu_device_ip_fini(adev);
2785 if (adev->firmware.gpu_info_fw) {
2786 release_firmware(adev->firmware.gpu_info_fw);
2787 adev->firmware.gpu_info_fw = NULL;
2789 adev->accel_working = false;
2790 cancel_delayed_work_sync(&adev->delayed_init_work);
2791 /* free i2c buses */
2792 if (!amdgpu_device_has_dc_support(adev))
2793 amdgpu_i2c_fini(adev);
2795 if (amdgpu_emu_mode != 1)
2796 amdgpu_atombios_fini(adev);
2800 if (!pci_is_thunderbolt_attached(adev->pdev))
2801 vga_switcheroo_unregister_client(adev->pdev);
2802 if (adev->flags & AMD_IS_PX)
2803 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2804 vga_client_register(adev->pdev, NULL, NULL, NULL);
2806 pci_iounmap(adev->pdev, adev->rio_mem);
2807 adev->rio_mem = NULL;
2808 iounmap(adev->rmmio);
2810 amdgpu_device_doorbell_fini(adev);
2811 if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
2812 amdgpu_pm_virt_sysfs_fini(adev);
2814 amdgpu_debugfs_regs_cleanup(adev);
2815 device_remove_file(adev->dev, &dev_attr_pcie_replay_count);
2816 amdgpu_ucode_sysfs_fini(adev);
2824 * amdgpu_device_suspend - initiate device suspend
2826 * @dev: drm dev pointer
2827 * @suspend: suspend state
2828 * @fbcon : notify the fbdev of suspend
2830 * Puts the hw in the suspend state (all asics).
2831 * Returns 0 for success or an error on failure.
2832 * Called at driver suspend.
2834 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
2836 struct amdgpu_device *adev;
2837 struct drm_crtc *crtc;
2838 struct drm_connector *connector;
2841 if (dev == NULL || dev->dev_private == NULL) {
2845 adev = dev->dev_private;
2847 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2850 adev->in_suspend = true;
2851 drm_kms_helper_poll_disable(dev);
2854 amdgpu_fbdev_set_suspend(adev, 1);
2856 cancel_delayed_work_sync(&adev->delayed_init_work);
2858 if (!amdgpu_device_has_dc_support(adev)) {
2859 /* turn off display hw */
2860 drm_modeset_lock_all(dev);
2861 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2862 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
2864 drm_modeset_unlock_all(dev);
2865 /* unpin the front buffers and cursors */
2866 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2867 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2868 struct drm_framebuffer *fb = crtc->primary->fb;
2869 struct amdgpu_bo *robj;
2871 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
2872 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2873 r = amdgpu_bo_reserve(aobj, true);
2875 amdgpu_bo_unpin(aobj);
2876 amdgpu_bo_unreserve(aobj);
2880 if (fb == NULL || fb->obj[0] == NULL) {
2883 robj = gem_to_amdgpu_bo(fb->obj[0]);
2884 /* don't unpin kernel fb objects */
2885 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
2886 r = amdgpu_bo_reserve(robj, true);
2888 amdgpu_bo_unpin(robj);
2889 amdgpu_bo_unreserve(robj);
2895 amdgpu_amdkfd_suspend(adev);
2897 amdgpu_ras_suspend(adev);
2899 r = amdgpu_device_ip_suspend_phase1(adev);
2901 /* evict vram memory */
2902 amdgpu_bo_evict_vram(adev);
2904 amdgpu_fence_driver_suspend(adev);
2906 r = amdgpu_device_ip_suspend_phase2(adev);
2908 /* evict remaining vram memory
2909 * This second call to evict vram is to evict the gart page table
2912 amdgpu_bo_evict_vram(adev);
2914 pci_save_state(dev->pdev);
2916 /* Shut down the device */
2917 pci_disable_device(dev->pdev);
2918 pci_set_power_state(dev->pdev, PCI_D3hot);
2920 r = amdgpu_asic_reset(adev);
2922 DRM_ERROR("amdgpu asic reset failed\n");
2929 * amdgpu_device_resume - initiate device resume
2931 * @dev: drm dev pointer
2932 * @resume: resume state
2933 * @fbcon : notify the fbdev of resume
2935 * Bring the hw back to operating state (all asics).
2936 * Returns 0 for success or an error on failure.
2937 * Called at driver resume.
2939 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2941 struct drm_connector *connector;
2942 struct amdgpu_device *adev = dev->dev_private;
2943 struct drm_crtc *crtc;
2946 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2950 pci_set_power_state(dev->pdev, PCI_D0);
2951 pci_restore_state(dev->pdev);
2952 r = pci_enable_device(dev->pdev);
2958 if (amdgpu_device_need_post(adev)) {
2959 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2961 DRM_ERROR("amdgpu asic init failed\n");
2964 r = amdgpu_device_ip_resume(adev);
2966 DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r);
2969 amdgpu_fence_driver_resume(adev);
2972 r = amdgpu_device_ip_late_init(adev);
2976 queue_delayed_work(system_wq, &adev->delayed_init_work,
2977 msecs_to_jiffies(AMDGPU_RESUME_MS));
2979 if (!amdgpu_device_has_dc_support(adev)) {
2981 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2982 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2984 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
2985 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2986 r = amdgpu_bo_reserve(aobj, true);
2988 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2990 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2991 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2992 amdgpu_bo_unreserve(aobj);
2997 r = amdgpu_amdkfd_resume(adev);
3001 /* Make sure IB tests flushed */
3002 flush_delayed_work(&adev->delayed_init_work);
3004 /* blat the mode back in */
3006 if (!amdgpu_device_has_dc_support(adev)) {
3008 drm_helper_resume_force_mode(dev);
3010 /* turn on display hw */
3011 drm_modeset_lock_all(dev);
3012 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3013 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
3015 drm_modeset_unlock_all(dev);
3017 amdgpu_fbdev_set_suspend(adev, 0);
3020 drm_kms_helper_poll_enable(dev);
3022 amdgpu_ras_resume(adev);
3025 * Most of the connector probing functions try to acquire runtime pm
3026 * refs to ensure that the GPU is powered on when connector polling is
3027 * performed. Since we're calling this from a runtime PM callback,
3028 * trying to acquire rpm refs will cause us to deadlock.
3030 * Since we're guaranteed to be holding the rpm lock, it's safe to
3031 * temporarily disable the rpm helpers so this doesn't deadlock us.
3034 dev->dev->power.disable_depth++;
3036 if (!amdgpu_device_has_dc_support(adev))
3037 drm_helper_hpd_irq_event(dev);
3039 drm_kms_helper_hotplug_event(dev);
3041 dev->dev->power.disable_depth--;
3043 adev->in_suspend = false;
3049 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
3051 * @adev: amdgpu_device pointer
3053 * The list of all the hardware IPs that make up the asic is walked and
3054 * the check_soft_reset callbacks are run. check_soft_reset determines
3055 * if the asic is still hung or not.
3056 * Returns true if any of the IPs are still in a hung state, false if not.
3058 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
3061 bool asic_hang = false;
3063 if (amdgpu_sriov_vf(adev))
3066 if (amdgpu_asic_need_full_reset(adev))
3069 for (i = 0; i < adev->num_ip_blocks; i++) {
3070 if (!adev->ip_blocks[i].status.valid)
3072 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
3073 adev->ip_blocks[i].status.hang =
3074 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
3075 if (adev->ip_blocks[i].status.hang) {
3076 DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
3084 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
3086 * @adev: amdgpu_device pointer
3088 * The list of all the hardware IPs that make up the asic is walked and the
3089 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
3090 * handles any IP specific hardware or software state changes that are
3091 * necessary for a soft reset to succeed.
3092 * Returns 0 on success, negative error code on failure.
3094 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
3098 for (i = 0; i < adev->num_ip_blocks; i++) {
3099 if (!adev->ip_blocks[i].status.valid)
3101 if (adev->ip_blocks[i].status.hang &&
3102 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
3103 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
3113 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
3115 * @adev: amdgpu_device pointer
3117 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
3118 * reset is necessary to recover.
3119 * Returns true if a full asic reset is required, false if not.
3121 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
3125 if (amdgpu_asic_need_full_reset(adev))
3128 for (i = 0; i < adev->num_ip_blocks; i++) {
3129 if (!adev->ip_blocks[i].status.valid)
3131 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
3132 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
3133 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
3134 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
3135 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3136 if (adev->ip_blocks[i].status.hang) {
3137 DRM_INFO("Some block need full reset!\n");
3146 * amdgpu_device_ip_soft_reset - do a soft reset
3148 * @adev: amdgpu_device pointer
3150 * The list of all the hardware IPs that make up the asic is walked and the
3151 * soft_reset callbacks are run if the block is hung. soft_reset handles any
3152 * IP specific hardware or software state changes that are necessary to soft
3154 * Returns 0 on success, negative error code on failure.
3156 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
3160 for (i = 0; i < adev->num_ip_blocks; i++) {
3161 if (!adev->ip_blocks[i].status.valid)
3163 if (adev->ip_blocks[i].status.hang &&
3164 adev->ip_blocks[i].version->funcs->soft_reset) {
3165 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
3175 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
3177 * @adev: amdgpu_device pointer
3179 * The list of all the hardware IPs that make up the asic is walked and the
3180 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
3181 * handles any IP specific hardware or software state changes that are
3182 * necessary after the IP has been soft reset.
3183 * Returns 0 on success, negative error code on failure.
3185 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
3189 for (i = 0; i < adev->num_ip_blocks; i++) {
3190 if (!adev->ip_blocks[i].status.valid)
3192 if (adev->ip_blocks[i].status.hang &&
3193 adev->ip_blocks[i].version->funcs->post_soft_reset)
3194 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
3203 * amdgpu_device_recover_vram - Recover some VRAM contents
3205 * @adev: amdgpu_device pointer
3207 * Restores the contents of VRAM buffers from the shadows in GTT. Used to
3208 * restore things like GPUVM page tables after a GPU reset where
3209 * the contents of VRAM might be lost.
3212 * 0 on success, negative error code on failure.
3214 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
3216 struct dma_fence *fence = NULL, *next = NULL;
3217 struct amdgpu_bo *shadow;
3220 if (amdgpu_sriov_runtime(adev))
3221 tmo = msecs_to_jiffies(8000);
3223 tmo = msecs_to_jiffies(100);
3225 DRM_INFO("recover vram bo from shadow start\n");
3226 mutex_lock(&adev->shadow_list_lock);
3227 list_for_each_entry(shadow, &adev->shadow_list, shadow_list) {
3229 /* No need to recover an evicted BO */
3230 if (shadow->tbo.mem.mem_type != TTM_PL_TT ||
3231 shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET ||
3232 shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM)
3235 r = amdgpu_bo_restore_shadow(shadow, &next);
3240 tmo = dma_fence_wait_timeout(fence, false, tmo);
3241 dma_fence_put(fence);
3246 } else if (tmo < 0) {
3254 mutex_unlock(&adev->shadow_list_lock);
3257 tmo = dma_fence_wait_timeout(fence, false, tmo);
3258 dma_fence_put(fence);
3260 if (r < 0 || tmo <= 0) {
3261 DRM_ERROR("recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
3265 DRM_INFO("recover vram bo from shadow done\n");
3271 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
3273 * @adev: amdgpu device pointer
3274 * @from_hypervisor: request from hypervisor
3276 * do VF FLR and reinitialize Asic
3277 * return 0 means succeeded otherwise failed
3279 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
3280 bool from_hypervisor)
3284 if (from_hypervisor)
3285 r = amdgpu_virt_request_full_gpu(adev, true);
3287 r = amdgpu_virt_reset_gpu(adev);
3291 amdgpu_amdkfd_pre_reset(adev);
3293 /* Resume IP prior to SMC */
3294 r = amdgpu_device_ip_reinit_early_sriov(adev);
3298 /* we need recover gart prior to run SMC/CP/SDMA resume */
3299 amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
3301 r = amdgpu_device_fw_loading(adev);
3305 /* now we are okay to resume SMC/CP/SDMA */
3306 r = amdgpu_device_ip_reinit_late_sriov(adev);
3310 amdgpu_irq_gpu_reset_resume_helper(adev);
3311 r = amdgpu_ib_ring_tests(adev);
3312 amdgpu_amdkfd_post_reset(adev);
3315 amdgpu_virt_init_data_exchange(adev);
3316 amdgpu_virt_release_full_gpu(adev, true);
3317 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
3318 atomic_inc(&adev->vram_lost_counter);
3319 r = amdgpu_device_recover_vram(adev);
3326 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
3328 * @adev: amdgpu device pointer
3330 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
3333 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
3335 if (!amdgpu_device_ip_check_soft_reset(adev)) {
3336 DRM_INFO("Timeout, but no hardware hang detected.\n");
3340 if (amdgpu_gpu_recovery == 0)
3343 if (amdgpu_sriov_vf(adev))
3346 if (amdgpu_gpu_recovery == -1) {
3347 switch (adev->asic_type) {
3353 case CHIP_POLARIS10:
3354 case CHIP_POLARIS11:
3355 case CHIP_POLARIS12:
3369 DRM_INFO("GPU recovery disabled.\n");
3374 static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
3375 struct amdgpu_job *job,
3376 bool *need_full_reset_arg)
3379 bool need_full_reset = *need_full_reset_arg;
3381 /* block all schedulers and reset given job's ring */
3382 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3383 struct amdgpu_ring *ring = adev->rings[i];
3385 if (!ring || !ring->sched.thread)
3388 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
3389 amdgpu_fence_driver_force_completion(ring);
3393 drm_sched_increase_karma(&job->base);
3395 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
3396 if (!amdgpu_sriov_vf(adev)) {
3398 if (!need_full_reset)
3399 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
3401 if (!need_full_reset) {
3402 amdgpu_device_ip_pre_soft_reset(adev);
3403 r = amdgpu_device_ip_soft_reset(adev);
3404 amdgpu_device_ip_post_soft_reset(adev);
3405 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
3406 DRM_INFO("soft reset failed, will fallback to full reset!\n");
3407 need_full_reset = true;
3411 if (need_full_reset)
3412 r = amdgpu_device_ip_suspend(adev);
3414 *need_full_reset_arg = need_full_reset;
3420 static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
3421 struct list_head *device_list_handle,
3422 bool *need_full_reset_arg)
3424 struct amdgpu_device *tmp_adev = NULL;
3425 bool need_full_reset = *need_full_reset_arg, vram_lost = false;
3429 * ASIC reset has to be done on all HGMI hive nodes ASAP
3430 * to allow proper links negotiation in FW (within 1 sec)
3432 if (need_full_reset) {
3433 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3434 /* For XGMI run all resets in parallel to speed up the process */
3435 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
3436 if (!queue_work(system_highpri_wq, &tmp_adev->xgmi_reset_work))
3439 r = amdgpu_asic_reset(tmp_adev);
3442 DRM_ERROR("ASIC reset failed with error, %d for drm dev, %s",
3443 r, tmp_adev->ddev->unique);
3448 /* For XGMI wait for all PSP resets to complete before proceed */
3450 list_for_each_entry(tmp_adev, device_list_handle,
3452 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
3453 flush_work(&tmp_adev->xgmi_reset_work);
3454 r = tmp_adev->asic_reset_res;
3460 list_for_each_entry(tmp_adev, device_list_handle,
3462 amdgpu_ras_reserve_bad_pages(tmp_adev);
3468 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3469 if (need_full_reset) {
3471 if (amdgpu_atom_asic_init(tmp_adev->mode_info.atom_context))
3472 DRM_WARN("asic atom init failed!");
3475 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
3476 r = amdgpu_device_ip_resume_phase1(tmp_adev);
3480 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
3482 DRM_INFO("VRAM is lost due to GPU reset!\n");
3483 atomic_inc(&tmp_adev->vram_lost_counter);
3486 r = amdgpu_gtt_mgr_recover(
3487 &tmp_adev->mman.bdev.man[TTM_PL_TT]);
3491 r = amdgpu_device_fw_loading(tmp_adev);
3495 r = amdgpu_device_ip_resume_phase2(tmp_adev);
3500 amdgpu_device_fill_reset_magic(tmp_adev);
3502 r = amdgpu_device_ip_late_init(tmp_adev);
3507 amdgpu_ras_resume(tmp_adev);
3509 /* Update PSP FW topology after reset */
3510 if (hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1)
3511 r = amdgpu_xgmi_update_topology(hive, tmp_adev);
3518 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
3519 r = amdgpu_ib_ring_tests(tmp_adev);
3521 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
3522 r = amdgpu_device_ip_suspend(tmp_adev);
3523 need_full_reset = true;
3530 r = amdgpu_device_recover_vram(tmp_adev);
3532 tmp_adev->asic_reset_res = r;
3536 *need_full_reset_arg = need_full_reset;
3540 static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, bool trylock)
3543 if (!mutex_trylock(&adev->lock_reset))
3546 mutex_lock(&adev->lock_reset);
3548 atomic_inc(&adev->gpu_reset_counter);
3549 adev->in_gpu_reset = 1;
3550 /* Block kfd: SRIOV would do it separately */
3551 if (!amdgpu_sriov_vf(adev))
3552 amdgpu_amdkfd_pre_reset(adev);
3557 static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
3559 /*unlock kfd: SRIOV would do it separately */
3560 if (!amdgpu_sriov_vf(adev))
3561 amdgpu_amdkfd_post_reset(adev);
3562 amdgpu_vf_error_trans_all(adev);
3563 adev->in_gpu_reset = 0;
3564 mutex_unlock(&adev->lock_reset);
3569 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
3571 * @adev: amdgpu device pointer
3572 * @job: which job trigger hang
3574 * Attempt to reset the GPU if it has hung (all asics).
3575 * Attempt to do soft-reset or full-reset and reinitialize Asic
3576 * Returns 0 for success or an error on failure.
3579 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
3580 struct amdgpu_job *job)
3582 struct list_head device_list, *device_list_handle = NULL;
3583 bool need_full_reset, job_signaled;
3584 struct amdgpu_hive_info *hive = NULL;
3585 struct amdgpu_device *tmp_adev = NULL;
3588 need_full_reset = job_signaled = false;
3589 INIT_LIST_HEAD(&device_list);
3591 dev_info(adev->dev, "GPU reset begin!\n");
3593 cancel_delayed_work_sync(&adev->delayed_init_work);
3595 hive = amdgpu_get_xgmi_hive(adev, false);
3598 * Here we trylock to avoid chain of resets executing from
3599 * either trigger by jobs on different adevs in XGMI hive or jobs on
3600 * different schedulers for same device while this TO handler is running.
3601 * We always reset all schedulers for device and all devices for XGMI
3602 * hive so that should take care of them too.
3605 if (hive && !mutex_trylock(&hive->reset_lock)) {
3606 DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress",
3607 job->base.id, hive->hive_id);
3611 /* Start with adev pre asic reset first for soft reset check.*/
3612 if (!amdgpu_device_lock_adev(adev, !hive)) {
3613 DRM_INFO("Bailing on TDR for s_job:%llx, as another already in progress",
3618 /* Build list of devices to reset */
3619 if (adev->gmc.xgmi.num_physical_nodes > 1) {
3621 amdgpu_device_unlock_adev(adev);
3626 * In case we are in XGMI hive mode device reset is done for all the
3627 * nodes in the hive to retrain all XGMI links and hence the reset
3628 * sequence is executed in loop on all nodes.
3630 device_list_handle = &hive->device_list;
3632 list_add_tail(&adev->gmc.xgmi.head, &device_list);
3633 device_list_handle = &device_list;
3636 /* block all schedulers and reset given job's ring */
3637 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3638 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3639 struct amdgpu_ring *ring = tmp_adev->rings[i];
3641 if (!ring || !ring->sched.thread)
3644 drm_sched_stop(&ring->sched, &job->base);
3650 * Must check guilty signal here since after this point all old
3651 * HW fences are force signaled.
3653 * job->base holds a reference to parent fence
3655 if (job && job->base.s_fence->parent &&
3656 dma_fence_is_signaled(job->base.s_fence->parent))
3657 job_signaled = true;
3659 if (!amdgpu_device_ip_need_full_reset(adev))
3660 device_list_handle = &device_list;
3663 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
3668 /* Guilty job will be freed after this*/
3669 r = amdgpu_device_pre_asic_reset(adev,
3673 /*TODO Should we stop ?*/
3674 DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
3675 r, adev->ddev->unique);
3676 adev->asic_reset_res = r;
3679 retry: /* Rest of adevs pre asic reset from XGMI hive. */
3680 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3682 if (tmp_adev == adev)
3685 amdgpu_device_lock_adev(tmp_adev, false);
3686 r = amdgpu_device_pre_asic_reset(tmp_adev,
3689 /*TODO Should we stop ?*/
3691 DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
3692 r, tmp_adev->ddev->unique);
3693 tmp_adev->asic_reset_res = r;
3697 /* Actual ASIC resets if needed.*/
3698 /* TODO Implement XGMI hive reset logic for SRIOV */
3699 if (amdgpu_sriov_vf(adev)) {
3700 r = amdgpu_device_reset_sriov(adev, job ? false : true);
3702 adev->asic_reset_res = r;
3704 r = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset);
3705 if (r && r == -EAGAIN)
3711 /* Post ASIC reset for all devs .*/
3712 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3713 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3714 struct amdgpu_ring *ring = tmp_adev->rings[i];
3716 if (!ring || !ring->sched.thread)
3719 /* No point to resubmit jobs if we didn't HW reset*/
3720 if (!tmp_adev->asic_reset_res && !job_signaled)
3721 drm_sched_resubmit_jobs(&ring->sched);
3723 drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res);
3726 if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) {
3727 drm_helper_resume_force_mode(tmp_adev->ddev);
3730 tmp_adev->asic_reset_res = 0;
3733 /* bad news, how to tell it to userspace ? */
3734 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
3735 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
3737 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&adev->gpu_reset_counter));
3740 amdgpu_device_unlock_adev(tmp_adev);
3744 mutex_unlock(&hive->reset_lock);
3747 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
3752 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
3754 * @adev: amdgpu_device pointer
3756 * Fetchs and stores in the driver the PCIE capabilities (gen speed
3757 * and lanes) of the slot the device is in. Handles APUs and
3758 * virtualized environments where PCIE config space may not be available.
3760 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
3762 struct pci_dev *pdev;
3763 enum pci_bus_speed speed_cap, platform_speed_cap;
3764 enum pcie_link_width platform_link_width;
3766 if (amdgpu_pcie_gen_cap)
3767 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
3769 if (amdgpu_pcie_lane_cap)
3770 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
3772 /* covers APUs as well */
3773 if (pci_is_root_bus(adev->pdev->bus)) {
3774 if (adev->pm.pcie_gen_mask == 0)
3775 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3776 if (adev->pm.pcie_mlw_mask == 0)
3777 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3781 if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
3784 pcie_bandwidth_available(adev->pdev, NULL,
3785 &platform_speed_cap, &platform_link_width);
3787 if (adev->pm.pcie_gen_mask == 0) {
3790 speed_cap = pcie_get_speed_cap(pdev);
3791 if (speed_cap == PCI_SPEED_UNKNOWN) {
3792 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3793 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3794 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
3796 if (speed_cap == PCIE_SPEED_16_0GT)
3797 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3798 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3799 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
3800 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
3801 else if (speed_cap == PCIE_SPEED_8_0GT)
3802 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3803 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3804 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
3805 else if (speed_cap == PCIE_SPEED_5_0GT)
3806 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3807 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
3809 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
3812 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
3813 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3814 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
3816 if (platform_speed_cap == PCIE_SPEED_16_0GT)
3817 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3818 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3819 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
3820 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
3821 else if (platform_speed_cap == PCIE_SPEED_8_0GT)
3822 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3823 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3824 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
3825 else if (platform_speed_cap == PCIE_SPEED_5_0GT)
3826 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3827 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
3829 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
3833 if (adev->pm.pcie_mlw_mask == 0) {
3834 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
3835 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
3837 switch (platform_link_width) {
3839 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
3840 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3841 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3842 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3843 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3844 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3845 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3848 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3849 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3850 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3851 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3852 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3853 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3856 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3857 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3858 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3859 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3860 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3863 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3864 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3865 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3866 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3869 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3870 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3871 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3874 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3875 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3878 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;