2 * Copyright 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include "amdgpu_ids.h"
25 #include <linux/idr.h>
26 #include <linux/dma-fence-array.h>
30 #include "amdgpu_trace.h"
35 * PASIDs are global address space identifiers that can be shared
36 * between the GPU, an IOMMU and the driver. VMs on different devices
37 * may use the same PASID if they share the same address
38 * space. Therefore PASIDs are allocated using a global IDA. VMs are
39 * looked up from the PASID per amdgpu_device.
41 static DEFINE_IDA(amdgpu_pasid_ida);
43 /* Helper to free pasid from a fence callback */
44 struct amdgpu_pasid_cb {
45 struct dma_fence_cb cb;
50 * amdgpu_pasid_alloc - Allocate a PASID
51 * @bits: Maximum width of the PASID in bits, must be at least 1
53 * Allocates a PASID of the given width while keeping smaller PASIDs
54 * available if possible.
56 * Returns a positive integer on success. Returns %-EINVAL if bits==0.
57 * Returns %-ENOSPC if no PASID was available. Returns %-ENOMEM on
58 * memory allocation failure.
60 int amdgpu_pasid_alloc(unsigned int bits)
64 for (bits = min(bits, 31U); bits > 0; bits--) {
65 pasid = ida_simple_get(&amdgpu_pasid_ida,
66 1U << (bits - 1), 1U << bits,
73 trace_amdgpu_pasid_allocated(pasid);
79 * amdgpu_pasid_free - Free a PASID
80 * @pasid: PASID to free
82 void amdgpu_pasid_free(unsigned int pasid)
84 trace_amdgpu_pasid_freed(pasid);
85 ida_simple_remove(&amdgpu_pasid_ida, pasid);
88 static void amdgpu_pasid_free_cb(struct dma_fence *fence,
89 struct dma_fence_cb *_cb)
91 struct amdgpu_pasid_cb *cb =
92 container_of(_cb, struct amdgpu_pasid_cb, cb);
94 amdgpu_pasid_free(cb->pasid);
100 * amdgpu_pasid_free_delayed - free pasid when fences signal
102 * @resv: reservation object with the fences to wait for
103 * @pasid: pasid to free
105 * Free the pasid only after all the fences in resv are signaled.
107 void amdgpu_pasid_free_delayed(struct reservation_object *resv,
110 struct dma_fence *fence, **fences;
111 struct amdgpu_pasid_cb *cb;
115 r = reservation_object_get_fences_rcu(resv, NULL, &count, &fences);
120 amdgpu_pasid_free(pasid);
128 uint64_t context = dma_fence_context_alloc(1);
129 struct dma_fence_array *array;
131 array = dma_fence_array_create(count, fences, context,
137 fence = &array->base;
140 cb = kmalloc(sizeof(*cb), GFP_KERNEL);
142 /* Last resort when we are OOM */
143 dma_fence_wait(fence, false);
144 dma_fence_put(fence);
145 amdgpu_pasid_free(pasid);
148 if (dma_fence_add_callback(fence, &cb->cb,
149 amdgpu_pasid_free_cb))
150 amdgpu_pasid_free_cb(fence, &cb->cb);
156 /* Not enough memory for the delayed delete, as last resort
157 * block for all the fences to complete.
159 reservation_object_wait_timeout_rcu(resv, true, false,
160 MAX_SCHEDULE_TIMEOUT);
161 amdgpu_pasid_free(pasid);
167 * VMIDs are a per VMHUB identifier for page tables handling.
171 * amdgpu_vmid_had_gpu_reset - check if reset occured since last use
173 * @adev: amdgpu_device pointer
174 * @id: VMID structure
176 * Check if GPU reset occured since last use of the VMID.
178 bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev,
179 struct amdgpu_vmid *id)
181 return id->current_gpu_reset_count !=
182 atomic_read(&adev->gpu_reset_counter);
186 * amdgpu_vm_grab_idle - grab idle VMID
188 * @vm: vm to allocate id for
189 * @ring: ring we want to submit job to
190 * @sync: sync object where we add dependencies
191 * @idle: resulting idle VMID
193 * Try to find an idle VMID, if none is idle add a fence to wait to the sync
194 * object. Returns -ENOMEM when we are out of memory.
196 static int amdgpu_vmid_grab_idle(struct amdgpu_vm *vm,
197 struct amdgpu_ring *ring,
198 struct amdgpu_sync *sync,
199 struct amdgpu_vmid **idle)
201 struct amdgpu_device *adev = ring->adev;
202 unsigned vmhub = ring->funcs->vmhub;
203 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
204 struct dma_fence **fences;
208 fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL);
212 /* Check if we have an idle VMID */
214 list_for_each_entry((*idle), &id_mgr->ids_lru, list) {
215 fences[i] = amdgpu_sync_peek_fence(&(*idle)->active, ring);
221 /* If we can't find a idle VMID to use, wait till one becomes available */
222 if (&(*idle)->list == &id_mgr->ids_lru) {
223 u64 fence_context = adev->vm_manager.fence_context + ring->idx;
224 unsigned seqno = ++adev->vm_manager.seqno[ring->idx];
225 struct dma_fence_array *array;
229 for (j = 0; j < i; ++j)
230 dma_fence_get(fences[j]);
232 array = dma_fence_array_create(i, fences, fence_context,
235 for (j = 0; j < i; ++j)
236 dma_fence_put(fences[j]);
241 r = amdgpu_sync_fence(adev, sync, &array->base, false);
242 dma_fence_put(&array->base);
252 * amdgpu_vm_grab_reserved - try to assign reserved VMID
254 * @vm: vm to allocate id for
255 * @ring: ring we want to submit job to
256 * @sync: sync object where we add dependencies
257 * @fence: fence protecting ID from reuse
258 * @job: job who wants to use the VMID
260 * Try to assign a reserved VMID.
262 static int amdgpu_vmid_grab_reserved(struct amdgpu_vm *vm,
263 struct amdgpu_ring *ring,
264 struct amdgpu_sync *sync,
265 struct dma_fence *fence,
266 struct amdgpu_job *job)
268 struct amdgpu_device *adev = ring->adev;
269 unsigned vmhub = ring->funcs->vmhub;
270 uint64_t fence_context = adev->fence_context + ring->idx;
271 struct amdgpu_vmid *id = vm->reserved_vmid[vmhub];
272 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
273 struct dma_fence *updates = sync->last_vm_update;
274 bool needs_flush = vm->use_cpu_for_update;
277 if (updates && id->flushed_updates &&
278 updates->context == id->flushed_updates->context &&
279 !dma_fence_is_later(updates, id->flushed_updates))
282 if (id->owner != vm->entity.fence_context ||
283 job->vm_pd_addr != id->pd_gpu_addr ||
284 updates || !id->last_flush ||
285 (id->last_flush->context != fence_context &&
286 !dma_fence_is_signaled(id->last_flush))) {
287 struct dma_fence *tmp;
289 /* to prevent one context starved by another context */
291 tmp = amdgpu_sync_peek_fence(&id->active, ring);
293 r = amdgpu_sync_fence(adev, sync, tmp, false);
299 /* Good we can use this VMID. Remember this submission as
302 r = amdgpu_sync_fence(ring->adev, &id->active, fence, false);
307 dma_fence_put(id->flushed_updates);
308 id->flushed_updates = dma_fence_get(updates);
310 id->pd_gpu_addr = job->vm_pd_addr;
311 id->owner = vm->entity.fence_context;
312 job->vm_needs_flush = needs_flush;
314 dma_fence_put(id->last_flush);
315 id->last_flush = NULL;
317 job->vmid = id - id_mgr->ids;
318 job->pasid = vm->pasid;
319 trace_amdgpu_vm_grab_id(vm, ring, job);
324 * amdgpu_vm_grab_id - allocate the next free VMID
326 * @vm: vm to allocate id for
327 * @ring: ring we want to submit job to
328 * @sync: sync object where we add dependencies
329 * @fence: fence protecting ID from reuse
330 * @job: job who wants to use the VMID
332 * Allocate an id for the vm, adding fences to the sync obj as necessary.
334 int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
335 struct amdgpu_sync *sync, struct dma_fence *fence,
336 struct amdgpu_job *job)
338 struct amdgpu_device *adev = ring->adev;
339 unsigned vmhub = ring->funcs->vmhub;
340 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
341 uint64_t fence_context = adev->fence_context + ring->idx;
342 struct dma_fence *updates = sync->last_vm_update;
343 struct amdgpu_vmid *id, *idle;
346 mutex_lock(&id_mgr->lock);
347 r = amdgpu_vmid_grab_idle(vm, ring, sync, &idle);
351 if (vm->reserved_vmid[vmhub]) {
352 r = amdgpu_vmid_grab_reserved(vm, ring, sync, fence, job);
353 mutex_unlock(&id_mgr->lock);
357 job->vm_needs_flush = vm->use_cpu_for_update;
358 /* Check if we can use a VMID already assigned to this VM */
359 list_for_each_entry_reverse(id, &id_mgr->ids_lru, list) {
360 struct dma_fence *flushed;
361 bool needs_flush = vm->use_cpu_for_update;
363 /* Check all the prerequisites to using this VMID */
364 if (id->owner != vm->entity.fence_context)
367 if (job->vm_pd_addr != id->pd_gpu_addr)
370 if (!id->last_flush ||
371 (id->last_flush->context != fence_context &&
372 !dma_fence_is_signaled(id->last_flush)))
375 flushed = id->flushed_updates;
376 if (updates && (!flushed || dma_fence_is_later(updates, flushed)))
379 /* Concurrent flushes are only possible starting with Vega10 */
380 if (adev->asic_type < CHIP_VEGA10 && needs_flush)
383 /* Good we can use this VMID. Remember this submission as
386 r = amdgpu_sync_fence(ring->adev, &id->active, fence, false);
390 if (updates && (!flushed || dma_fence_is_later(updates, flushed))) {
391 dma_fence_put(id->flushed_updates);
392 id->flushed_updates = dma_fence_get(updates);
398 goto no_flush_needed;
402 /* Still no ID to use? Then use the idle one found earlier */
405 /* Remember this submission as user of the VMID */
406 r = amdgpu_sync_fence(ring->adev, &id->active, fence, false);
410 id->pd_gpu_addr = job->vm_pd_addr;
411 dma_fence_put(id->flushed_updates);
412 id->flushed_updates = dma_fence_get(updates);
413 id->owner = vm->entity.fence_context;
416 job->vm_needs_flush = true;
417 dma_fence_put(id->last_flush);
418 id->last_flush = NULL;
421 list_move_tail(&id->list, &id_mgr->ids_lru);
423 job->vmid = id - id_mgr->ids;
424 job->pasid = vm->pasid;
425 trace_amdgpu_vm_grab_id(vm, ring, job);
428 mutex_unlock(&id_mgr->lock);
432 int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,
433 struct amdgpu_vm *vm,
436 struct amdgpu_vmid_mgr *id_mgr;
437 struct amdgpu_vmid *idle;
440 id_mgr = &adev->vm_manager.id_mgr[vmhub];
441 mutex_lock(&id_mgr->lock);
442 if (vm->reserved_vmid[vmhub])
444 if (atomic_inc_return(&id_mgr->reserved_vmid_num) >
445 AMDGPU_VM_MAX_RESERVED_VMID) {
446 DRM_ERROR("Over limitation of reserved vmid\n");
447 atomic_dec(&id_mgr->reserved_vmid_num);
451 /* Select the first entry VMID */
452 idle = list_first_entry(&id_mgr->ids_lru, struct amdgpu_vmid, list);
453 list_del_init(&idle->list);
454 vm->reserved_vmid[vmhub] = idle;
455 mutex_unlock(&id_mgr->lock);
459 mutex_unlock(&id_mgr->lock);
463 void amdgpu_vmid_free_reserved(struct amdgpu_device *adev,
464 struct amdgpu_vm *vm,
467 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
469 mutex_lock(&id_mgr->lock);
470 if (vm->reserved_vmid[vmhub]) {
471 list_add(&vm->reserved_vmid[vmhub]->list,
473 vm->reserved_vmid[vmhub] = NULL;
474 atomic_dec(&id_mgr->reserved_vmid_num);
476 mutex_unlock(&id_mgr->lock);
480 * amdgpu_vmid_reset - reset VMID to zero
482 * @adev: amdgpu device structure
483 * @vmid: vmid number to use
485 * Reset saved GDW, GWS and OA to force switch on next flush.
487 void amdgpu_vmid_reset(struct amdgpu_device *adev, unsigned vmhub,
490 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
491 struct amdgpu_vmid *id = &id_mgr->ids[vmid];
493 mutex_lock(&id_mgr->lock);
501 mutex_unlock(&id_mgr->lock);
505 * amdgpu_vmid_reset_all - reset VMID to zero
507 * @adev: amdgpu device structure
509 * Reset VMID to force flush on next use
511 void amdgpu_vmid_reset_all(struct amdgpu_device *adev)
515 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
516 struct amdgpu_vmid_mgr *id_mgr =
517 &adev->vm_manager.id_mgr[i];
519 for (j = 1; j < id_mgr->num_ids; ++j)
520 amdgpu_vmid_reset(adev, i, j);
525 * amdgpu_vmid_mgr_init - init the VMID manager
527 * @adev: amdgpu_device pointer
529 * Initialize the VM manager structures
531 void amdgpu_vmid_mgr_init(struct amdgpu_device *adev)
535 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
536 struct amdgpu_vmid_mgr *id_mgr =
537 &adev->vm_manager.id_mgr[i];
539 mutex_init(&id_mgr->lock);
540 INIT_LIST_HEAD(&id_mgr->ids_lru);
541 atomic_set(&id_mgr->reserved_vmid_num, 0);
543 /* skip over VMID 0, since it is the system VM */
544 for (j = 1; j < id_mgr->num_ids; ++j) {
545 amdgpu_vmid_reset(adev, i, j);
546 amdgpu_sync_create(&id_mgr->ids[i].active);
547 list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru);
551 adev->vm_manager.fence_context =
552 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
553 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
554 adev->vm_manager.seqno[i] = 0;
558 * amdgpu_vmid_mgr_fini - cleanup VM manager
560 * @adev: amdgpu_device pointer
562 * Cleanup the VM manager and free resources.
564 void amdgpu_vmid_mgr_fini(struct amdgpu_device *adev)
568 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
569 struct amdgpu_vmid_mgr *id_mgr =
570 &adev->vm_manager.id_mgr[i];
572 mutex_destroy(&id_mgr->lock);
573 for (j = 0; j < AMDGPU_NUM_VMID; ++j) {
574 struct amdgpu_vmid *id = &id_mgr->ids[j];
576 amdgpu_sync_free(&id->active);
577 dma_fence_put(id->flushed_updates);
578 dma_fence_put(id->last_flush);