2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 * DOC: Interrupt Handling
32 * Interrupts generated within GPU hardware raise interrupt requests that are
33 * passed to amdgpu IRQ handler which is responsible for detecting source and
34 * type of the interrupt and dispatching matching handlers. If handling an
35 * interrupt requires calling kernel functions that may sleep processing is
36 * dispatched to work handlers.
38 * If MSI functionality is not disabled by module parameter then MSI
39 * support will be enabled.
41 * For GPU interrupt sources that may be driven by another driver, IRQ domain
42 * support is used (with mapping between virtual and hardware IRQs).
45 #include <linux/irq.h>
47 #include <drm/drm_crtc_helper.h>
48 #include <drm/amdgpu_drm.h>
50 #include "amdgpu_ih.h"
52 #include "amdgpu_connectors.h"
53 #include "amdgpu_trace.h"
54 #include "amdgpu_amdkfd.h"
56 #include <linux/pm_runtime.h>
58 #ifdef CONFIG_DRM_AMD_DC
59 #include "amdgpu_dm_irq.h"
62 #define AMDGPU_WAIT_IDLE_TIMEOUT 200
65 * amdgpu_hotplug_work_func - work handler for display hotplug event
67 * @work: work struct pointer
69 * This is the hotplug event work handler (all ASICs).
70 * The work gets scheduled from the IRQ handler if there
71 * was a hotplug interrupt. It walks through the connector table
72 * and calls hotplug handler for each connector. After this, it sends
73 * a DRM hotplug event to alert userspace.
75 * This design approach is required in order to defer hotplug event handling
76 * from the IRQ handler to a work handler because hotplug handler has to use
77 * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may
80 static void amdgpu_hotplug_work_func(struct work_struct *work)
82 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
84 struct drm_device *dev = adev->ddev;
85 struct drm_mode_config *mode_config = &dev->mode_config;
86 struct drm_connector *connector;
88 mutex_lock(&mode_config->mutex);
89 list_for_each_entry(connector, &mode_config->connector_list, head)
90 amdgpu_connector_hotplug(connector);
91 mutex_unlock(&mode_config->mutex);
92 /* Just fire off a uevent and let userspace tell us what to do */
93 drm_helper_hpd_irq_event(dev);
97 * amdgpu_irq_reset_work_func - execute GPU reset
99 * @work: work struct pointer
101 * Execute scheduled GPU reset (Cayman+).
102 * This function is called when the IRQ handler thinks we need a GPU reset.
104 static void amdgpu_irq_reset_work_func(struct work_struct *work)
106 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
109 if (!amdgpu_sriov_vf(adev) && amdgpu_device_should_recover_gpu(adev))
110 amdgpu_device_gpu_recover(adev, NULL);
114 * amdgpu_irq_disable_all - disable *all* interrupts
116 * @adev: amdgpu device pointer
118 * Disable all types of interrupts from all sources.
120 void amdgpu_irq_disable_all(struct amdgpu_device *adev)
122 unsigned long irqflags;
126 spin_lock_irqsave(&adev->irq.lock, irqflags);
127 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
128 if (!adev->irq.client[i].sources)
131 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
132 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
134 if (!src || !src->funcs->set || !src->num_types)
137 for (k = 0; k < src->num_types; ++k) {
138 atomic_set(&src->enabled_types[k], 0);
139 r = src->funcs->set(adev, src, k,
140 AMDGPU_IRQ_STATE_DISABLE);
142 DRM_ERROR("error disabling interrupt (%d)\n",
147 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
151 * amdgpu_irq_callback - callback from the IH ring
153 * @adev: amdgpu device pointer
154 * @ih: amdgpu ih ring
156 * Callback from IH ring processing to handle the entry at the current position
157 * and advance the read pointer.
159 static void amdgpu_irq_callback(struct amdgpu_device *adev,
160 struct amdgpu_ih_ring *ih)
162 u32 ring_index = ih->rptr >> 2;
163 struct amdgpu_iv_entry entry;
165 /* Prescreening of high-frequency interrupts */
166 if (!amdgpu_ih_prescreen_iv(adev))
169 /* Before dispatching irq to IP blocks, send it to amdkfd */
170 amdgpu_amdkfd_interrupt(adev, (const void *) &ih->ring[ring_index]);
172 entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
173 amdgpu_ih_decode_iv(adev, &entry);
175 amdgpu_irq_dispatch(adev, &entry);
179 * amdgpu_irq_handler - IRQ handler
181 * @irq: IRQ number (unused)
182 * @arg: pointer to DRM device
184 * IRQ handler for amdgpu driver (all ASICs).
187 * result of handling the IRQ, as defined by &irqreturn_t
189 irqreturn_t amdgpu_irq_handler(int irq, void *arg)
191 struct drm_device *dev = (struct drm_device *) arg;
192 struct amdgpu_device *adev = dev->dev_private;
195 ret = amdgpu_ih_process(adev, &adev->irq.ih, amdgpu_irq_callback);
196 if (ret == IRQ_HANDLED)
197 pm_runtime_mark_last_busy(dev->dev);
202 * amdgpu_msi_ok - check whether MSI functionality is enabled
204 * @adev: amdgpu device pointer (unused)
206 * Checks whether MSI functionality has been disabled via module parameter
210 * *true* if MSIs are allowed to be enabled or *false* otherwise
212 static bool amdgpu_msi_ok(struct amdgpu_device *adev)
216 else if (amdgpu_msi == 0)
223 * amdgpu_irq_init - initialize interrupt handling
225 * @adev: amdgpu device pointer
227 * Sets up work functions for hotplug and reset interrupts, enables MSI
228 * functionality, initializes vblank, hotplug and reset interrupt handling.
231 * 0 on success or error code on failure
233 int amdgpu_irq_init(struct amdgpu_device *adev)
237 spin_lock_init(&adev->irq.lock);
239 /* Enable MSI if not disabled by module parameter */
240 adev->irq.msi_enabled = false;
242 if (amdgpu_msi_ok(adev)) {
243 int ret = pci_enable_msi(adev->pdev);
245 adev->irq.msi_enabled = true;
246 dev_dbg(adev->dev, "amdgpu: using MSI.\n");
250 if (!amdgpu_device_has_dc_support(adev)) {
251 if (!adev->enable_virtual_display)
252 /* Disable vblank IRQs aggressively for power-saving */
253 /* XXX: can this be enabled for DC? */
254 adev->ddev->vblank_disable_immediate = true;
256 r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
261 INIT_WORK(&adev->hotplug_work,
262 amdgpu_hotplug_work_func);
265 INIT_WORK(&adev->reset_work, amdgpu_irq_reset_work_func);
267 adev->irq.installed = true;
268 r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
270 adev->irq.installed = false;
271 if (!amdgpu_device_has_dc_support(adev))
272 flush_work(&adev->hotplug_work);
273 cancel_work_sync(&adev->reset_work);
276 adev->ddev->max_vblank_count = 0x00ffffff;
278 DRM_DEBUG("amdgpu: irq initialized.\n");
283 * amdgpu_irq_fini - shut down interrupt handling
285 * @adev: amdgpu device pointer
287 * Tears down work functions for hotplug and reset interrupts, disables MSI
288 * functionality, shuts down vblank, hotplug and reset interrupt handling,
289 * turns off interrupts from all sources (all ASICs).
291 void amdgpu_irq_fini(struct amdgpu_device *adev)
295 if (adev->irq.installed) {
296 drm_irq_uninstall(adev->ddev);
297 adev->irq.installed = false;
298 if (adev->irq.msi_enabled)
299 pci_disable_msi(adev->pdev);
300 if (!amdgpu_device_has_dc_support(adev))
301 flush_work(&adev->hotplug_work);
302 cancel_work_sync(&adev->reset_work);
305 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
306 if (!adev->irq.client[i].sources)
309 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
310 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
315 kfree(src->enabled_types);
316 src->enabled_types = NULL;
320 adev->irq.client[i].sources[j] = NULL;
323 kfree(adev->irq.client[i].sources);
324 adev->irq.client[i].sources = NULL;
329 * amdgpu_irq_add_id - register IRQ source
331 * @adev: amdgpu device pointer
332 * @client_id: client id
334 * @source: IRQ source pointer
336 * Registers IRQ source on a client.
339 * 0 on success or error code otherwise
341 int amdgpu_irq_add_id(struct amdgpu_device *adev,
342 unsigned client_id, unsigned src_id,
343 struct amdgpu_irq_src *source)
345 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX)
348 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
354 if (!adev->irq.client[client_id].sources) {
355 adev->irq.client[client_id].sources =
356 kcalloc(AMDGPU_MAX_IRQ_SRC_ID,
357 sizeof(struct amdgpu_irq_src *),
359 if (!adev->irq.client[client_id].sources)
363 if (adev->irq.client[client_id].sources[src_id] != NULL)
366 if (source->num_types && !source->enabled_types) {
369 types = kcalloc(source->num_types, sizeof(atomic_t),
374 source->enabled_types = types;
377 adev->irq.client[client_id].sources[src_id] = source;
382 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks
384 * @adev: amdgpu device pointer
385 * @entry: interrupt vector pointer
387 * Dispatches IRQ to IP blocks.
389 void amdgpu_irq_dispatch(struct amdgpu_device *adev,
390 struct amdgpu_iv_entry *entry)
392 unsigned client_id = entry->client_id;
393 unsigned src_id = entry->src_id;
394 struct amdgpu_irq_src *src;
397 trace_amdgpu_iv(entry);
399 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) {
400 DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
404 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
405 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
409 if (adev->irq.virq[src_id]) {
410 generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id));
412 if (!adev->irq.client[client_id].sources) {
413 DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",
418 src = adev->irq.client[client_id].sources[src_id];
420 DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
424 r = src->funcs->process(adev, src, entry);
426 DRM_ERROR("error processing interrupt (%d)\n", r);
431 * amdgpu_irq_update - update hardware interrupt state
433 * @adev: amdgpu device pointer
434 * @src: interrupt source pointer
435 * @type: type of interrupt
437 * Updates interrupt state for the specific source (all ASICs).
439 int amdgpu_irq_update(struct amdgpu_device *adev,
440 struct amdgpu_irq_src *src, unsigned type)
442 unsigned long irqflags;
443 enum amdgpu_interrupt_state state;
446 spin_lock_irqsave(&adev->irq.lock, irqflags);
448 /* We need to determine after taking the lock, otherwise
449 we might disable just enabled interrupts again */
450 if (amdgpu_irq_enabled(adev, src, type))
451 state = AMDGPU_IRQ_STATE_ENABLE;
453 state = AMDGPU_IRQ_STATE_DISABLE;
455 r = src->funcs->set(adev, src, type, state);
456 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
461 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources
463 * @adev: amdgpu device pointer
465 * Updates state of all types of interrupts on all sources on resume after
468 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
472 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
473 if (!adev->irq.client[i].sources)
476 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
477 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
481 for (k = 0; k < src->num_types; k++)
482 amdgpu_irq_update(adev, src, k);
488 * amdgpu_irq_get - enable interrupt
490 * @adev: amdgpu device pointer
491 * @src: interrupt source pointer
492 * @type: type of interrupt
494 * Enables specified type of interrupt on the specified source (all ASICs).
497 * 0 on success or error code otherwise
499 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
502 if (!adev->ddev->irq_enabled)
505 if (type >= src->num_types)
508 if (!src->enabled_types || !src->funcs->set)
511 if (atomic_inc_return(&src->enabled_types[type]) == 1)
512 return amdgpu_irq_update(adev, src, type);
518 * amdgpu_irq_put - disable interrupt
520 * @adev: amdgpu device pointer
521 * @src: interrupt source pointer
522 * @type: type of interrupt
524 * Enables specified type of interrupt on the specified source (all ASICs).
527 * 0 on success or error code otherwise
529 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
532 if (!adev->ddev->irq_enabled)
535 if (type >= src->num_types)
538 if (!src->enabled_types || !src->funcs->set)
541 if (atomic_dec_and_test(&src->enabled_types[type]))
542 return amdgpu_irq_update(adev, src, type);
548 * amdgpu_irq_enabled - check whether interrupt is enabled or not
550 * @adev: amdgpu device pointer
551 * @src: interrupt source pointer
552 * @type: type of interrupt
554 * Checks whether the given type of interrupt is enabled on the given source.
557 * *true* if interrupt is enabled, *false* if interrupt is disabled or on
560 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
563 if (!adev->ddev->irq_enabled)
566 if (type >= src->num_types)
569 if (!src->enabled_types || !src->funcs->set)
572 return !!atomic_read(&src->enabled_types[type]);
575 /* XXX: Generic IRQ handling */
576 static void amdgpu_irq_mask(struct irq_data *irqd)
581 static void amdgpu_irq_unmask(struct irq_data *irqd)
586 /* amdgpu hardware interrupt chip descriptor */
587 static struct irq_chip amdgpu_irq_chip = {
589 .irq_mask = amdgpu_irq_mask,
590 .irq_unmask = amdgpu_irq_unmask,
594 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers
596 * @d: amdgpu IRQ domain pointer (unused)
597 * @irq: virtual IRQ number
598 * @hwirq: hardware irq number
600 * Current implementation assigns simple interrupt handler to the given virtual
604 * 0 on success or error code otherwise
606 static int amdgpu_irqdomain_map(struct irq_domain *d,
607 unsigned int irq, irq_hw_number_t hwirq)
609 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID)
612 irq_set_chip_and_handler(irq,
613 &amdgpu_irq_chip, handle_simple_irq);
617 /* Implementation of methods for amdgpu IRQ domain */
618 static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
619 .map = amdgpu_irqdomain_map,
623 * amdgpu_irq_add_domain - create a linear IRQ domain
625 * @adev: amdgpu device pointer
627 * Creates an IRQ domain for GPU interrupt sources
628 * that may be driven by another driver (e.g., ACP).
631 * 0 on success or error code otherwise
633 int amdgpu_irq_add_domain(struct amdgpu_device *adev)
635 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,
636 &amdgpu_hw_irqdomain_ops, adev);
637 if (!adev->irq.domain) {
638 DRM_ERROR("GPU irq add domain failed\n");
646 * amdgpu_irq_remove_domain - remove the IRQ domain
648 * @adev: amdgpu device pointer
650 * Removes the IRQ domain for GPU interrupt sources
651 * that may be driven by another driver (e.g., ACP).
653 void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
655 if (adev->irq.domain) {
656 irq_domain_remove(adev->irq.domain);
657 adev->irq.domain = NULL;
662 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs
664 * @adev: amdgpu device pointer
665 * @src_id: IH source id
667 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ
668 * Use this for components that generate a GPU interrupt, but are driven
669 * by a different driver (e.g., ACP).
674 unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id)
676 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);
678 return adev->irq.virq[src_id];