2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 #include <drm/amdgpu_drm.h>
31 #include "amdgpu_sched.h"
32 #include "amdgpu_uvd.h"
33 #include "amdgpu_vce.h"
36 #include <linux/vga_switcheroo.h>
37 #include <linux/slab.h>
38 #include <linux/pm_runtime.h>
39 #include "amdgpu_amdkfd.h"
40 #include "amdgpu_gem.h"
41 #include "amdgpu_display.h"
43 static void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
45 struct amdgpu_gpu_instance *gpu_instance;
48 mutex_lock(&mgpu_info.mutex);
50 for (i = 0; i < mgpu_info.num_gpu; i++) {
51 gpu_instance = &(mgpu_info.gpu_ins[i]);
52 if (gpu_instance->adev == adev) {
53 mgpu_info.gpu_ins[i] =
54 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
56 if (adev->flags & AMD_IS_APU)
64 mutex_unlock(&mgpu_info.mutex);
68 * amdgpu_driver_unload_kms - Main unload function for KMS.
70 * @dev: drm dev pointer
72 * This is the main unload function for KMS (all asics).
73 * Returns 0 on success.
75 void amdgpu_driver_unload_kms(struct drm_device *dev)
77 struct amdgpu_device *adev = dev->dev_private;
82 amdgpu_unregister_gpu_instance(adev);
84 if (adev->rmmio == NULL)
87 if (amdgpu_sriov_vf(adev))
88 amdgpu_virt_request_full_gpu(adev, false);
90 if (amdgpu_device_is_px(dev)) {
91 pm_runtime_get_sync(dev->dev);
92 pm_runtime_forbid(dev->dev);
95 amdgpu_acpi_fini(adev);
97 amdgpu_device_fini(adev);
101 dev->dev_private = NULL;
104 static void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
106 struct amdgpu_gpu_instance *gpu_instance;
108 mutex_lock(&mgpu_info.mutex);
110 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
111 DRM_ERROR("Cannot register more gpu instance\n");
112 mutex_unlock(&mgpu_info.mutex);
116 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
117 gpu_instance->adev = adev;
118 gpu_instance->mgpu_fan_enabled = 0;
121 if (adev->flags & AMD_IS_APU)
124 mgpu_info.num_dgpu++;
126 mutex_unlock(&mgpu_info.mutex);
130 * amdgpu_driver_load_kms - Main load function for KMS.
132 * @dev: drm dev pointer
133 * @flags: device flags
135 * This is the main load function for KMS (all asics).
136 * Returns 0 on success, error on failure.
138 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
140 struct amdgpu_device *adev;
143 #ifdef CONFIG_DRM_AMDGPU_SI
144 if (!amdgpu_si_support) {
145 switch (flags & AMD_ASIC_MASK) {
152 "SI support provided by radeon.\n");
154 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
160 #ifdef CONFIG_DRM_AMDGPU_CIK
161 if (!amdgpu_cik_support) {
162 switch (flags & AMD_ASIC_MASK) {
169 "CIK support provided by radeon.\n");
171 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
178 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
182 dev->dev_private = (void *)adev;
184 if ((amdgpu_runtime_pm != 0) &&
186 (amdgpu_is_atpx_hybrid() ||
187 amdgpu_has_atpx_dgpu_power_cntl()) &&
188 ((flags & AMD_IS_APU) == 0) &&
189 !pci_is_thunderbolt_attached(dev->pdev))
192 /* amdgpu_device_init should report only fatal error
193 * like memory allocation failure or iomapping failure,
194 * or memory manager initialization failure, it must
195 * properly initialize the GPU MC controller and permit
198 r = amdgpu_device_init(adev, dev, dev->pdev, flags);
200 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
204 /* Call ACPI methods: require modeset init
205 * but failure is not fatal
208 acpi_status = amdgpu_acpi_init(adev);
210 dev_dbg(&dev->pdev->dev,
211 "Error during ACPI methods call\n");
214 if (amdgpu_device_is_px(dev)) {
215 pm_runtime_use_autosuspend(dev->dev);
216 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
217 pm_runtime_set_active(dev->dev);
218 pm_runtime_allow(dev->dev);
219 pm_runtime_mark_last_busy(dev->dev);
220 pm_runtime_put_autosuspend(dev->dev);
223 amdgpu_register_gpu_instance(adev);
226 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
227 if (adev->rmmio && amdgpu_device_is_px(dev))
228 pm_runtime_put_noidle(dev->dev);
229 amdgpu_driver_unload_kms(dev);
235 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
236 struct drm_amdgpu_query_fw *query_fw,
237 struct amdgpu_device *adev)
239 switch (query_fw->fw_type) {
240 case AMDGPU_INFO_FW_VCE:
241 fw_info->ver = adev->vce.fw_version;
242 fw_info->feature = adev->vce.fb_version;
244 case AMDGPU_INFO_FW_UVD:
245 fw_info->ver = adev->uvd.fw_version;
246 fw_info->feature = 0;
248 case AMDGPU_INFO_FW_VCN:
249 fw_info->ver = adev->vcn.fw_version;
250 fw_info->feature = 0;
252 case AMDGPU_INFO_FW_GMC:
253 fw_info->ver = adev->gmc.fw_version;
254 fw_info->feature = 0;
256 case AMDGPU_INFO_FW_GFX_ME:
257 fw_info->ver = adev->gfx.me_fw_version;
258 fw_info->feature = adev->gfx.me_feature_version;
260 case AMDGPU_INFO_FW_GFX_PFP:
261 fw_info->ver = adev->gfx.pfp_fw_version;
262 fw_info->feature = adev->gfx.pfp_feature_version;
264 case AMDGPU_INFO_FW_GFX_CE:
265 fw_info->ver = adev->gfx.ce_fw_version;
266 fw_info->feature = adev->gfx.ce_feature_version;
268 case AMDGPU_INFO_FW_GFX_RLC:
269 fw_info->ver = adev->gfx.rlc_fw_version;
270 fw_info->feature = adev->gfx.rlc_feature_version;
272 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
273 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
274 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
276 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
277 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
278 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
280 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
281 fw_info->ver = adev->gfx.rlc_srls_fw_version;
282 fw_info->feature = adev->gfx.rlc_srls_feature_version;
284 case AMDGPU_INFO_FW_GFX_MEC:
285 if (query_fw->index == 0) {
286 fw_info->ver = adev->gfx.mec_fw_version;
287 fw_info->feature = adev->gfx.mec_feature_version;
288 } else if (query_fw->index == 1) {
289 fw_info->ver = adev->gfx.mec2_fw_version;
290 fw_info->feature = adev->gfx.mec2_feature_version;
294 case AMDGPU_INFO_FW_SMC:
295 fw_info->ver = adev->pm.fw_version;
296 fw_info->feature = 0;
298 case AMDGPU_INFO_FW_SDMA:
299 if (query_fw->index >= adev->sdma.num_instances)
301 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
302 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
304 case AMDGPU_INFO_FW_SOS:
305 fw_info->ver = adev->psp.sos_fw_version;
306 fw_info->feature = adev->psp.sos_feature_version;
308 case AMDGPU_INFO_FW_ASD:
309 fw_info->ver = adev->psp.asd_fw_version;
310 fw_info->feature = adev->psp.asd_feature_version;
312 case AMDGPU_INFO_FW_DMCU:
313 fw_info->ver = adev->dm.dmcu_fw_version;
314 fw_info->feature = 0;
322 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
323 struct drm_amdgpu_info *info,
324 struct drm_amdgpu_info_hw_ip *result)
326 uint32_t ib_start_alignment = 0;
327 uint32_t ib_size_alignment = 0;
328 enum amd_ip_block_type type;
329 unsigned int num_rings = 0;
332 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
335 switch (info->query_hw_ip.type) {
336 case AMDGPU_HW_IP_GFX:
337 type = AMD_IP_BLOCK_TYPE_GFX;
338 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
339 if (adev->gfx.gfx_ring[i].ready)
341 ib_start_alignment = 32;
342 ib_size_alignment = 32;
344 case AMDGPU_HW_IP_COMPUTE:
345 type = AMD_IP_BLOCK_TYPE_GFX;
346 for (i = 0; i < adev->gfx.num_compute_rings; i++)
347 if (adev->gfx.compute_ring[i].ready)
349 ib_start_alignment = 32;
350 ib_size_alignment = 32;
352 case AMDGPU_HW_IP_DMA:
353 type = AMD_IP_BLOCK_TYPE_SDMA;
354 for (i = 0; i < adev->sdma.num_instances; i++)
355 if (adev->sdma.instance[i].ring.ready)
357 ib_start_alignment = 256;
358 ib_size_alignment = 4;
360 case AMDGPU_HW_IP_UVD:
361 type = AMD_IP_BLOCK_TYPE_UVD;
362 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
363 if (adev->uvd.harvest_config & (1 << i))
366 if (adev->uvd.inst[i].ring.ready)
369 ib_start_alignment = 64;
370 ib_size_alignment = 64;
372 case AMDGPU_HW_IP_VCE:
373 type = AMD_IP_BLOCK_TYPE_VCE;
374 for (i = 0; i < adev->vce.num_rings; i++)
375 if (adev->vce.ring[i].ready)
377 ib_start_alignment = 4;
378 ib_size_alignment = 1;
380 case AMDGPU_HW_IP_UVD_ENC:
381 type = AMD_IP_BLOCK_TYPE_UVD;
382 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
383 if (adev->uvd.harvest_config & (1 << i))
386 for (j = 0; j < adev->uvd.num_enc_rings; j++)
387 if (adev->uvd.inst[i].ring_enc[j].ready)
390 ib_start_alignment = 64;
391 ib_size_alignment = 64;
393 case AMDGPU_HW_IP_VCN_DEC:
394 type = AMD_IP_BLOCK_TYPE_VCN;
395 if (adev->vcn.ring_dec.ready)
397 ib_start_alignment = 16;
398 ib_size_alignment = 16;
400 case AMDGPU_HW_IP_VCN_ENC:
401 type = AMD_IP_BLOCK_TYPE_VCN;
402 for (i = 0; i < adev->vcn.num_enc_rings; i++)
403 if (adev->vcn.ring_enc[i].ready)
405 ib_start_alignment = 64;
406 ib_size_alignment = 1;
408 case AMDGPU_HW_IP_VCN_JPEG:
409 type = AMD_IP_BLOCK_TYPE_VCN;
410 if (adev->vcn.ring_jpeg.ready)
412 ib_start_alignment = 16;
413 ib_size_alignment = 16;
419 for (i = 0; i < adev->num_ip_blocks; i++)
420 if (adev->ip_blocks[i].version->type == type &&
421 adev->ip_blocks[i].status.valid)
424 if (i == adev->num_ip_blocks)
427 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
430 result->hw_ip_version_major = adev->ip_blocks[i].version->major;
431 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
432 result->capabilities_flags = 0;
433 result->available_rings = (1 << num_rings) - 1;
434 result->ib_start_alignment = ib_start_alignment;
435 result->ib_size_alignment = ib_size_alignment;
440 * Userspace get information ioctl
443 * amdgpu_info_ioctl - answer a device specific request.
445 * @adev: amdgpu device pointer
446 * @data: request object
449 * This function is used to pass device specific parameters to the userspace
450 * drivers. Examples include: pci device id, pipeline parms, tiling params,
452 * Returns 0 on success, -EINVAL on failure.
454 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
456 struct amdgpu_device *adev = dev->dev_private;
457 struct drm_amdgpu_info *info = data;
458 struct amdgpu_mode_info *minfo = &adev->mode_info;
459 void __user *out = (void __user *)(uintptr_t)info->return_pointer;
460 uint32_t size = info->return_size;
461 struct drm_crtc *crtc;
465 int ui32_size = sizeof(ui32);
467 if (!info->return_size || !info->return_pointer)
470 switch (info->query) {
471 case AMDGPU_INFO_ACCEL_WORKING:
472 ui32 = adev->accel_working;
473 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
474 case AMDGPU_INFO_CRTC_FROM_ID:
475 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
476 crtc = (struct drm_crtc *)minfo->crtcs[i];
477 if (crtc && crtc->base.id == info->mode_crtc.id) {
478 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
479 ui32 = amdgpu_crtc->crtc_id;
485 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
488 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
489 case AMDGPU_INFO_HW_IP_INFO: {
490 struct drm_amdgpu_info_hw_ip ip = {};
493 ret = amdgpu_hw_ip_info(adev, info, &ip);
497 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
498 return ret ? -EFAULT : 0;
500 case AMDGPU_INFO_HW_IP_COUNT: {
501 enum amd_ip_block_type type;
504 switch (info->query_hw_ip.type) {
505 case AMDGPU_HW_IP_GFX:
506 type = AMD_IP_BLOCK_TYPE_GFX;
508 case AMDGPU_HW_IP_COMPUTE:
509 type = AMD_IP_BLOCK_TYPE_GFX;
511 case AMDGPU_HW_IP_DMA:
512 type = AMD_IP_BLOCK_TYPE_SDMA;
514 case AMDGPU_HW_IP_UVD:
515 type = AMD_IP_BLOCK_TYPE_UVD;
517 case AMDGPU_HW_IP_VCE:
518 type = AMD_IP_BLOCK_TYPE_VCE;
520 case AMDGPU_HW_IP_UVD_ENC:
521 type = AMD_IP_BLOCK_TYPE_UVD;
523 case AMDGPU_HW_IP_VCN_DEC:
524 case AMDGPU_HW_IP_VCN_ENC:
525 case AMDGPU_HW_IP_VCN_JPEG:
526 type = AMD_IP_BLOCK_TYPE_VCN;
532 for (i = 0; i < adev->num_ip_blocks; i++)
533 if (adev->ip_blocks[i].version->type == type &&
534 adev->ip_blocks[i].status.valid &&
535 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
538 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
540 case AMDGPU_INFO_TIMESTAMP:
541 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
542 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
543 case AMDGPU_INFO_FW_VERSION: {
544 struct drm_amdgpu_info_firmware fw_info;
547 /* We only support one instance of each IP block right now. */
548 if (info->query_fw.ip_instance != 0)
551 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
555 return copy_to_user(out, &fw_info,
556 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
558 case AMDGPU_INFO_NUM_BYTES_MOVED:
559 ui64 = atomic64_read(&adev->num_bytes_moved);
560 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
561 case AMDGPU_INFO_NUM_EVICTIONS:
562 ui64 = atomic64_read(&adev->num_evictions);
563 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
564 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
565 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
566 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
567 case AMDGPU_INFO_VRAM_USAGE:
568 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
569 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
570 case AMDGPU_INFO_VIS_VRAM_USAGE:
571 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
572 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
573 case AMDGPU_INFO_GTT_USAGE:
574 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
575 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
576 case AMDGPU_INFO_GDS_CONFIG: {
577 struct drm_amdgpu_info_gds gds_info;
579 memset(&gds_info, 0, sizeof(gds_info));
580 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size;
581 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size;
582 gds_info.gds_total_size = adev->gds.mem.total_size;
583 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size;
584 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size;
585 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size;
586 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size;
587 return copy_to_user(out, &gds_info,
588 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
590 case AMDGPU_INFO_VRAM_GTT: {
591 struct drm_amdgpu_info_vram_gtt vram_gtt;
593 vram_gtt.vram_size = adev->gmc.real_vram_size -
594 atomic64_read(&adev->vram_pin_size);
595 vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size -
596 atomic64_read(&adev->visible_pin_size);
597 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
598 vram_gtt.gtt_size *= PAGE_SIZE;
599 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
600 return copy_to_user(out, &vram_gtt,
601 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
603 case AMDGPU_INFO_MEMORY: {
604 struct drm_amdgpu_memory_info mem;
606 memset(&mem, 0, sizeof(mem));
607 mem.vram.total_heap_size = adev->gmc.real_vram_size;
608 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
609 atomic64_read(&adev->vram_pin_size);
610 mem.vram.heap_usage =
611 amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
612 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
614 mem.cpu_accessible_vram.total_heap_size =
615 adev->gmc.visible_vram_size;
616 mem.cpu_accessible_vram.usable_heap_size = adev->gmc.visible_vram_size -
617 atomic64_read(&adev->visible_pin_size);
618 mem.cpu_accessible_vram.heap_usage =
619 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
620 mem.cpu_accessible_vram.max_allocation =
621 mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
623 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size;
624 mem.gtt.total_heap_size *= PAGE_SIZE;
625 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
626 atomic64_read(&adev->gart_pin_size);
628 amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
629 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
631 return copy_to_user(out, &mem,
632 min((size_t)size, sizeof(mem)))
635 case AMDGPU_INFO_READ_MMR_REG: {
636 unsigned n, alloc_size;
638 unsigned se_num = (info->read_mmr_reg.instance >>
639 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
640 AMDGPU_INFO_MMR_SE_INDEX_MASK;
641 unsigned sh_num = (info->read_mmr_reg.instance >>
642 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
643 AMDGPU_INFO_MMR_SH_INDEX_MASK;
645 /* set full masks if the userspace set all bits
646 * in the bitfields */
647 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
649 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
652 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
655 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
657 for (i = 0; i < info->read_mmr_reg.count; i++)
658 if (amdgpu_asic_read_register(adev, se_num, sh_num,
659 info->read_mmr_reg.dword_offset + i,
661 DRM_DEBUG_KMS("unallowed offset %#x\n",
662 info->read_mmr_reg.dword_offset + i);
666 n = copy_to_user(out, regs, min(size, alloc_size));
668 return n ? -EFAULT : 0;
670 case AMDGPU_INFO_DEV_INFO: {
671 struct drm_amdgpu_info_device dev_info = {};
674 dev_info.device_id = dev->pdev->device;
675 dev_info.chip_rev = adev->rev_id;
676 dev_info.external_rev = adev->external_rev_id;
677 dev_info.pci_rev = dev->pdev->revision;
678 dev_info.family = adev->family;
679 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
680 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
681 /* return all clocks in KHz */
682 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
683 if (adev->pm.dpm_enabled) {
684 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
685 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
687 dev_info.max_engine_clock = adev->clock.default_sclk * 10;
688 dev_info.max_memory_clock = adev->clock.default_mclk * 10;
690 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
691 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
692 adev->gfx.config.max_shader_engines;
693 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
695 dev_info.ids_flags = 0;
696 if (adev->flags & AMD_IS_APU)
697 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
698 if (amdgpu_sriov_vf(adev))
699 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
701 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
702 vm_size -= AMDGPU_VA_RESERVED_SIZE;
704 /* Older VCE FW versions are buggy and can handle only 40bits */
705 if (adev->vce.fw_version &&
706 adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
707 vm_size = min(vm_size, 1ULL << 40);
709 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
710 dev_info.virtual_address_max =
711 min(vm_size, AMDGPU_GMC_HOLE_START);
713 if (vm_size > AMDGPU_GMC_HOLE_START) {
714 dev_info.high_va_offset = AMDGPU_GMC_HOLE_END;
715 dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
717 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
718 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
719 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
720 dev_info.cu_active_number = adev->gfx.cu_info.number;
721 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
722 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
723 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
724 sizeof(adev->gfx.cu_info.ao_cu_bitmap));
725 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
726 sizeof(adev->gfx.cu_info.bitmap));
727 dev_info.vram_type = adev->gmc.vram_type;
728 dev_info.vram_bit_width = adev->gmc.vram_width;
729 dev_info.vce_harvest_config = adev->vce.harvest_config;
730 dev_info.gc_double_offchip_lds_buf =
731 adev->gfx.config.double_offchip_lds_buf;
734 dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;
735 dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;
736 dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;
737 dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;
738 dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;
739 dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;
740 dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;
741 dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;
743 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
744 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
745 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
746 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
747 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
748 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
749 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
751 return copy_to_user(out, &dev_info,
752 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
754 case AMDGPU_INFO_VCE_CLOCK_TABLE: {
756 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
757 struct amd_vce_state *vce_state;
759 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
760 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
762 vce_clk_table.entries[i].sclk = vce_state->sclk;
763 vce_clk_table.entries[i].mclk = vce_state->mclk;
764 vce_clk_table.entries[i].eclk = vce_state->evclk;
765 vce_clk_table.num_valid_entries++;
769 return copy_to_user(out, &vce_clk_table,
770 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
772 case AMDGPU_INFO_VBIOS: {
773 uint32_t bios_size = adev->bios_size;
775 switch (info->vbios_info.type) {
776 case AMDGPU_INFO_VBIOS_SIZE:
777 return copy_to_user(out, &bios_size,
778 min((size_t)size, sizeof(bios_size)))
780 case AMDGPU_INFO_VBIOS_IMAGE: {
782 uint32_t bios_offset = info->vbios_info.offset;
784 if (bios_offset >= bios_size)
787 bios = adev->bios + bios_offset;
788 return copy_to_user(out, bios,
789 min((size_t)size, (size_t)(bios_size - bios_offset)))
793 DRM_DEBUG_KMS("Invalid request %d\n",
794 info->vbios_info.type);
798 case AMDGPU_INFO_NUM_HANDLES: {
799 struct drm_amdgpu_info_num_handles handle;
801 switch (info->query_hw_ip.type) {
802 case AMDGPU_HW_IP_UVD:
803 /* Starting Polaris, we support unlimited UVD handles */
804 if (adev->asic_type < CHIP_POLARIS10) {
805 handle.uvd_max_handles = adev->uvd.max_handles;
806 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
808 return copy_to_user(out, &handle,
809 min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
819 case AMDGPU_INFO_SENSOR: {
820 if (!adev->pm.dpm_enabled)
823 switch (info->sensor_info.type) {
824 case AMDGPU_INFO_SENSOR_GFX_SCLK:
825 /* get sclk in Mhz */
826 if (amdgpu_dpm_read_sensor(adev,
827 AMDGPU_PP_SENSOR_GFX_SCLK,
828 (void *)&ui32, &ui32_size)) {
833 case AMDGPU_INFO_SENSOR_GFX_MCLK:
834 /* get mclk in Mhz */
835 if (amdgpu_dpm_read_sensor(adev,
836 AMDGPU_PP_SENSOR_GFX_MCLK,
837 (void *)&ui32, &ui32_size)) {
842 case AMDGPU_INFO_SENSOR_GPU_TEMP:
843 /* get temperature in millidegrees C */
844 if (amdgpu_dpm_read_sensor(adev,
845 AMDGPU_PP_SENSOR_GPU_TEMP,
846 (void *)&ui32, &ui32_size)) {
850 case AMDGPU_INFO_SENSOR_GPU_LOAD:
852 if (amdgpu_dpm_read_sensor(adev,
853 AMDGPU_PP_SENSOR_GPU_LOAD,
854 (void *)&ui32, &ui32_size)) {
858 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
859 /* get average GPU power */
860 if (amdgpu_dpm_read_sensor(adev,
861 AMDGPU_PP_SENSOR_GPU_POWER,
862 (void *)&ui32, &ui32_size)) {
867 case AMDGPU_INFO_SENSOR_VDDNB:
868 /* get VDDNB in millivolts */
869 if (amdgpu_dpm_read_sensor(adev,
870 AMDGPU_PP_SENSOR_VDDNB,
871 (void *)&ui32, &ui32_size)) {
875 case AMDGPU_INFO_SENSOR_VDDGFX:
876 /* get VDDGFX in millivolts */
877 if (amdgpu_dpm_read_sensor(adev,
878 AMDGPU_PP_SENSOR_VDDGFX,
879 (void *)&ui32, &ui32_size)) {
883 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
884 /* get stable pstate sclk in Mhz */
885 if (amdgpu_dpm_read_sensor(adev,
886 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
887 (void *)&ui32, &ui32_size)) {
892 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
893 /* get stable pstate mclk in Mhz */
894 if (amdgpu_dpm_read_sensor(adev,
895 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
896 (void *)&ui32, &ui32_size)) {
902 DRM_DEBUG_KMS("Invalid request %d\n",
903 info->sensor_info.type);
906 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
908 case AMDGPU_INFO_VRAM_LOST_COUNTER:
909 ui32 = atomic_read(&adev->vram_lost_counter);
910 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
912 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
920 * Outdated mess for old drm with Xorg being in charge (void function now).
923 * amdgpu_driver_lastclose_kms - drm callback for last close
925 * @dev: drm dev pointer
927 * Switch vga_switcheroo state after last close (all asics).
929 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
931 drm_fb_helper_lastclose(dev);
932 vga_switcheroo_process_delayed_switch();
936 * amdgpu_driver_open_kms - drm callback for open
938 * @dev: drm dev pointer
939 * @file_priv: drm file
941 * On device open, init vm on cayman+ (all asics).
942 * Returns 0 on success, error on failure.
944 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
946 struct amdgpu_device *adev = dev->dev_private;
947 struct amdgpu_fpriv *fpriv;
950 /* Ensure IB tests are run on ring */
951 flush_delayed_work(&adev->late_init_work);
953 file_priv->driver_priv = NULL;
955 r = pm_runtime_get_sync(dev->dev);
959 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
960 if (unlikely(!fpriv)) {
965 pasid = amdgpu_pasid_alloc(16);
967 dev_warn(adev->dev, "No more PASIDs available!");
970 r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
974 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
975 if (!fpriv->prt_va) {
980 if (amdgpu_sriov_vf(adev)) {
981 r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va);
986 mutex_init(&fpriv->bo_list_lock);
987 idr_init(&fpriv->bo_list_handles);
989 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
991 file_priv->driver_priv = fpriv;
995 amdgpu_vm_fini(adev, &fpriv->vm);
999 amdgpu_pasid_free(pasid);
1004 pm_runtime_mark_last_busy(dev->dev);
1005 pm_runtime_put_autosuspend(dev->dev);
1011 * amdgpu_driver_postclose_kms - drm callback for post close
1013 * @dev: drm dev pointer
1014 * @file_priv: drm file
1016 * On device post close, tear down vm on cayman+ (all asics).
1018 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1019 struct drm_file *file_priv)
1021 struct amdgpu_device *adev = dev->dev_private;
1022 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1023 struct amdgpu_bo_list *list;
1024 struct amdgpu_bo *pd;
1031 pm_runtime_get_sync(dev->dev);
1033 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1034 amdgpu_uvd_free_handles(adev, file_priv);
1035 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1036 amdgpu_vce_free_handles(adev, file_priv);
1038 amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
1040 if (amdgpu_sriov_vf(adev)) {
1041 /* TODO: how to handle reserve failure */
1042 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1043 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
1044 fpriv->csa_va = NULL;
1045 amdgpu_bo_unreserve(adev->virt.csa_obj);
1048 pasid = fpriv->vm.pasid;
1049 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
1051 amdgpu_vm_fini(adev, &fpriv->vm);
1052 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1055 amdgpu_pasid_free_delayed(pd->tbo.resv, pasid);
1056 amdgpu_bo_unref(&pd);
1058 idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1059 amdgpu_bo_list_put(list);
1061 idr_destroy(&fpriv->bo_list_handles);
1062 mutex_destroy(&fpriv->bo_list_lock);
1065 file_priv->driver_priv = NULL;
1067 pm_runtime_mark_last_busy(dev->dev);
1068 pm_runtime_put_autosuspend(dev->dev);
1072 * VBlank related functions.
1075 * amdgpu_get_vblank_counter_kms - get frame count
1077 * @dev: drm dev pointer
1078 * @pipe: crtc to get the frame count from
1080 * Gets the frame count on the requested crtc (all asics).
1081 * Returns frame count on success, -EINVAL on failure.
1083 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
1085 struct amdgpu_device *adev = dev->dev_private;
1086 int vpos, hpos, stat;
1089 if (pipe >= adev->mode_info.num_crtc) {
1090 DRM_ERROR("Invalid crtc %u\n", pipe);
1094 /* The hw increments its frame counter at start of vsync, not at start
1095 * of vblank, as is required by DRM core vblank counter handling.
1096 * Cook the hw count here to make it appear to the caller as if it
1097 * incremented at start of vblank. We measure distance to start of
1098 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1099 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1100 * result by 1 to give the proper appearance to caller.
1102 if (adev->mode_info.crtcs[pipe]) {
1103 /* Repeat readout if needed to provide stable result if
1104 * we cross start of vsync during the queries.
1107 count = amdgpu_display_vblank_get_counter(adev, pipe);
1108 /* Ask amdgpu_display_get_crtc_scanoutpos to return
1109 * vpos as distance to start of vblank, instead of
1110 * regular vertical scanout pos.
1112 stat = amdgpu_display_get_crtc_scanoutpos(
1113 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1114 &vpos, &hpos, NULL, NULL,
1115 &adev->mode_info.crtcs[pipe]->base.hwmode);
1116 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1118 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1119 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1120 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1122 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1125 /* Bump counter if we are at >= leading edge of vblank,
1126 * but before vsync where vpos would turn negative and
1127 * the hw counter really increments.
1133 /* Fallback to use value as is. */
1134 count = amdgpu_display_vblank_get_counter(adev, pipe);
1135 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1142 * amdgpu_enable_vblank_kms - enable vblank interrupt
1144 * @dev: drm dev pointer
1145 * @pipe: crtc to enable vblank interrupt for
1147 * Enable the interrupt on the requested crtc (all asics).
1148 * Returns 0 on success, -EINVAL on failure.
1150 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1152 struct amdgpu_device *adev = dev->dev_private;
1153 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1155 return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1159 * amdgpu_disable_vblank_kms - disable vblank interrupt
1161 * @dev: drm dev pointer
1162 * @pipe: crtc to disable vblank interrupt for
1164 * Disable the interrupt on the requested crtc (all asics).
1166 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1168 struct amdgpu_device *adev = dev->dev_private;
1169 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1171 amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1174 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
1175 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1176 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1177 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1178 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
1179 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1180 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1182 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1183 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1184 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1185 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1186 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1187 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1188 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1189 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1190 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1191 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)
1193 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
1198 #if defined(CONFIG_DEBUG_FS)
1200 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1202 struct drm_info_node *node = (struct drm_info_node *) m->private;
1203 struct drm_device *dev = node->minor->dev;
1204 struct amdgpu_device *adev = dev->dev_private;
1205 struct drm_amdgpu_info_firmware fw_info;
1206 struct drm_amdgpu_query_fw query_fw;
1207 struct atom_context *ctx = adev->mode_info.atom_context;
1211 query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1212 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1215 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1216 fw_info.feature, fw_info.ver);
1219 query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1220 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1223 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1224 fw_info.feature, fw_info.ver);
1227 query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1228 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1231 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1232 fw_info.feature, fw_info.ver);
1235 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1236 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1239 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1240 fw_info.feature, fw_info.ver);
1243 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1244 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1247 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1248 fw_info.feature, fw_info.ver);
1251 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1252 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1255 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1256 fw_info.feature, fw_info.ver);
1259 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1260 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1263 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1264 fw_info.feature, fw_info.ver);
1266 /* RLC SAVE RESTORE LIST CNTL */
1267 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1268 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1271 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1272 fw_info.feature, fw_info.ver);
1274 /* RLC SAVE RESTORE LIST GPM MEM */
1275 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1276 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1279 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1280 fw_info.feature, fw_info.ver);
1282 /* RLC SAVE RESTORE LIST SRM MEM */
1283 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1284 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1287 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1288 fw_info.feature, fw_info.ver);
1291 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1293 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1296 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1297 fw_info.feature, fw_info.ver);
1300 if (adev->asic_type == CHIP_KAVERI ||
1301 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
1303 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1306 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1307 fw_info.feature, fw_info.ver);
1311 query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1312 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1315 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1316 fw_info.feature, fw_info.ver);
1320 query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1321 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1324 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1325 fw_info.feature, fw_info.ver);
1328 query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1329 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1332 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1333 fw_info.feature, fw_info.ver);
1336 query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1337 for (i = 0; i < adev->sdma.num_instances; i++) {
1339 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1342 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1343 i, fw_info.feature, fw_info.ver);
1347 query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1348 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1351 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1352 fw_info.feature, fw_info.ver);
1355 query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1356 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1359 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1360 fw_info.feature, fw_info.ver);
1363 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1368 static const struct drm_info_list amdgpu_firmware_info_list[] = {
1369 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1373 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1375 #if defined(CONFIG_DEBUG_FS)
1376 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1377 ARRAY_SIZE(amdgpu_firmware_info_list));