drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu_sched.h"
  32 #include "amdgpu_uvd.h"
  33 #include "amdgpu_vce.h"
  34 #include "atom.h"
  35
  36 #include <linux/vga_switcheroo.h>
  37 #include <linux/slab.h>
  38 #include <linux/pm_runtime.h>
  39 #include "amdgpu_amdkfd.h"
  40 #include "amdgpu_gem.h"
  41 #include "amdgpu_display.h"
  42
  43 /**
  44  * amdgpu_driver_unload_kms - Main unload function for KMS.
  45  *
  46  * @dev: drm dev pointer
  47  *
  48  * This is the main unload function for KMS (all asics).
  49  * Returns 0 on success.
  50  */
  51 void amdgpu_driver_unload_kms(struct drm_device *dev)
  52 {
  53         struct amdgpu_device *adev = dev->dev_private;
  54
  55         if (adev == NULL)
  56                 return;
  57
  58         if (adev->rmmio == NULL)
  59                 goto done_free;
  60
  61         if (amdgpu_sriov_vf(adev))
  62                 amdgpu_virt_request_full_gpu(adev, false);
  63
  64         if (amdgpu_device_is_px(dev)) {
  65                 pm_runtime_get_sync(dev->dev);
  66                 pm_runtime_forbid(dev->dev);
  67         }
  68
  69         amdgpu_acpi_fini(adev);
  70
  71         amdgpu_device_fini(adev);
  72
  73 done_free:
  74         kfree(adev);
  75         dev->dev_private = NULL;
  76 }
  77
  78 /**
  79  * amdgpu_driver_load_kms - Main load function for KMS.
  80  *
  81  * @dev: drm dev pointer
  82  * @flags: device flags
  83  *
  84  * This is the main load function for KMS (all asics).
  85  * Returns 0 on success, error on failure.
  86  */
  87 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
  88 {
  89         struct amdgpu_device *adev;
  90         int r, acpi_status;
  91
  92 #ifdef CONFIG_DRM_AMDGPU_SI
  93         if (!amdgpu_si_support) {
  94                 switch (flags & AMD_ASIC_MASK) {
  95                 case CHIP_TAHITI:
  96                 case CHIP_PITCAIRN:
  97                 case CHIP_VERDE:
  98                 case CHIP_OLAND:
  99                 case CHIP_HAINAN:
 100                         dev_info(dev->dev,
 101                                  "SI support provided by radeon.\n");
 102                         dev_info(dev->dev,
 103                                  "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
 104                                 );
 105                         return -ENODEV;
 106                 }
 107         }
 108 #endif
 109 #ifdef CONFIG_DRM_AMDGPU_CIK
 110         if (!amdgpu_cik_support) {
 111                 switch (flags & AMD_ASIC_MASK) {
 112                 case CHIP_KAVERI:
 113                 case CHIP_BONAIRE:
 114                 case CHIP_HAWAII:
 115                 case CHIP_KABINI:
 116                 case CHIP_MULLINS:
 117                         dev_info(dev->dev,
 118                                  "CIK support provided by radeon.\n");
 119                         dev_info(dev->dev,
 120                                  "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
 121                                 );
 122                         return -ENODEV;
 123                 }
 124         }
 125 #endif
 126
 127         adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
 128         if (adev == NULL) {
 129                 return -ENOMEM;
 130         }
 131         dev->dev_private = (void *)adev;
 132
 133         if ((amdgpu_runtime_pm != 0) &&
 134             amdgpu_has_atpx() &&
 135             (amdgpu_is_atpx_hybrid() ||
 136              amdgpu_has_atpx_dgpu_power_cntl()) &&
 137             ((flags & AMD_IS_APU) == 0) &&
 138             !pci_is_thunderbolt_attached(dev->pdev))
 139                 flags |= AMD_IS_PX;
 140
 141         /* amdgpu_device_init should report only fatal error
 142          * like memory allocation failure or iomapping failure,
 143          * or memory manager initialization failure, it must
 144          * properly initialize the GPU MC controller and permit
 145          * VRAM allocation
 146          */
 147         r = amdgpu_device_init(adev, dev, dev->pdev, flags);
 148         if (r) {
 149                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 150                 goto out;
 151         }
 152
 153         /* Call ACPI methods: require modeset init
 154          * but failure is not fatal
 155          */
 156         if (!r) {
 157                 acpi_status = amdgpu_acpi_init(adev);
 158                 if (acpi_status)
 159                 dev_dbg(&dev->pdev->dev,
 160                                 "Error during ACPI methods call\n");
 161         }
 162
 163         if (amdgpu_device_is_px(dev)) {
 164                 pm_runtime_use_autosuspend(dev->dev);
 165                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 166                 pm_runtime_set_active(dev->dev);
 167                 pm_runtime_allow(dev->dev);
 168                 pm_runtime_mark_last_busy(dev->dev);
 169                 pm_runtime_put_autosuspend(dev->dev);
 170         }
 171
 172 out:
 173         if (r) {
 174                 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
 175                 if (adev->rmmio && amdgpu_device_is_px(dev))
 176                         pm_runtime_put_noidle(dev->dev);
 177                 amdgpu_driver_unload_kms(dev);
 178         }
 179
 180         return r;
 181 }
 182
 183 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 184                                 struct drm_amdgpu_query_fw *query_fw,
 185                                 struct amdgpu_device *adev)
 186 {
 187         switch (query_fw->fw_type) {
 188         case AMDGPU_INFO_FW_VCE:
 189                 fw_info->ver = adev->vce.fw_version;
 190                 fw_info->feature = adev->vce.fb_version;
 191                 break;
 192         case AMDGPU_INFO_FW_UVD:
 193                 fw_info->ver = adev->uvd.fw_version;
 194                 fw_info->feature = 0;
 195                 break;
 196         case AMDGPU_INFO_FW_VCN:
 197                 fw_info->ver = adev->vcn.fw_version;
 198                 fw_info->feature = 0;
 199                 break;
 200         case AMDGPU_INFO_FW_GMC:
 201                 fw_info->ver = adev->gmc.fw_version;
 202                 fw_info->feature = 0;
 203                 break;
 204         case AMDGPU_INFO_FW_GFX_ME:
 205                 fw_info->ver = adev->gfx.me_fw_version;
 206                 fw_info->feature = adev->gfx.me_feature_version;
 207                 break;
 208         case AMDGPU_INFO_FW_GFX_PFP:
 209                 fw_info->ver = adev->gfx.pfp_fw_version;
 210                 fw_info->feature = adev->gfx.pfp_feature_version;
 211                 break;
 212         case AMDGPU_INFO_FW_GFX_CE:
 213                 fw_info->ver = adev->gfx.ce_fw_version;
 214                 fw_info->feature = adev->gfx.ce_feature_version;
 215                 break;
 216         case AMDGPU_INFO_FW_GFX_RLC:
 217                 fw_info->ver = adev->gfx.rlc_fw_version;
 218                 fw_info->feature = adev->gfx.rlc_feature_version;
 219                 break;
 220         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 221                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 222                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 223                 break;
 224         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 225                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 226                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 227                 break;
 228         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 229                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 230                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 231                 break;
 232         case AMDGPU_INFO_FW_GFX_MEC:
 233                 if (query_fw->index == 0) {
 234                         fw_info->ver = adev->gfx.mec_fw_version;
 235                         fw_info->feature = adev->gfx.mec_feature_version;
 236                 } else if (query_fw->index == 1) {
 237                         fw_info->ver = adev->gfx.mec2_fw_version;
 238                         fw_info->feature = adev->gfx.mec2_feature_version;
 239                 } else
 240                         return -EINVAL;
 241                 break;
 242         case AMDGPU_INFO_FW_SMC:
 243                 fw_info->ver = adev->pm.fw_version;
 244                 fw_info->feature = 0;
 245                 break;
 246         case AMDGPU_INFO_FW_SDMA:
 247                 if (query_fw->index >= adev->sdma.num_instances)
 248                         return -EINVAL;
 249                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 250                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 251                 break;
 252         case AMDGPU_INFO_FW_SOS:
 253                 fw_info->ver = adev->psp.sos_fw_version;
 254                 fw_info->feature = adev->psp.sos_feature_version;
 255                 break;
 256         case AMDGPU_INFO_FW_ASD:
 257                 fw_info->ver = adev->psp.asd_fw_version;
 258                 fw_info->feature = adev->psp.asd_feature_version;
 259                 break;
 260         default:
 261                 return -EINVAL;
 262         }
 263         return 0;
 264 }
 265
 266 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 267                              struct drm_amdgpu_info *info,
 268                              struct drm_amdgpu_info_hw_ip *result)
 269 {
 270         uint32_t ib_start_alignment = 0;
 271         uint32_t ib_size_alignment = 0;
 272         enum amd_ip_block_type type;
 273         unsigned int num_rings = 0;
 274         unsigned int i, j;
 275
 276         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 277                 return -EINVAL;
 278
 279         switch (info->query_hw_ip.type) {
 280         case AMDGPU_HW_IP_GFX:
 281                 type = AMD_IP_BLOCK_TYPE_GFX;
 282                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 283                         if (adev->gfx.gfx_ring[i].ready)
 284                                 ++num_rings;
 285                 ib_start_alignment = 32;
 286                 ib_size_alignment = 32;
 287                 break;
 288         case AMDGPU_HW_IP_COMPUTE:
 289                 type = AMD_IP_BLOCK_TYPE_GFX;
 290                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 291                         if (adev->gfx.compute_ring[i].ready)
 292                                 ++num_rings;
 293                 ib_start_alignment = 32;
 294                 ib_size_alignment = 32;
 295                 break;
 296         case AMDGPU_HW_IP_DMA:
 297                 type = AMD_IP_BLOCK_TYPE_SDMA;
 298                 for (i = 0; i < adev->sdma.num_instances; i++)
 299                         if (adev->sdma.instance[i].ring.ready)
 300                                 ++num_rings;
 301                 ib_start_alignment = 256;
 302                 ib_size_alignment = 4;
 303                 break;
 304         case AMDGPU_HW_IP_UVD:
 305                 type = AMD_IP_BLOCK_TYPE_UVD;
 306                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 307                         if (adev->uvd.harvest_config & (1 << i))
 308                                 continue;
 309
 310                         if (adev->uvd.inst[i].ring.ready)
 311                                 ++num_rings;
 312                 }
 313                 ib_start_alignment = 64;
 314                 ib_size_alignment = 64;
 315                 break;
 316         case AMDGPU_HW_IP_VCE:
 317                 type = AMD_IP_BLOCK_TYPE_VCE;
 318                 for (i = 0; i < adev->vce.num_rings; i++)
 319                         if (adev->vce.ring[i].ready)
 320                                 ++num_rings;
 321                 ib_start_alignment = 4;
 322                 ib_size_alignment = 1;
 323                 break;
 324         case AMDGPU_HW_IP_UVD_ENC:
 325                 type = AMD_IP_BLOCK_TYPE_UVD;
 326                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 327                         if (adev->uvd.harvest_config & (1 << i))
 328                                 continue;
 329
 330                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 331                                 if (adev->uvd.inst[i].ring_enc[j].ready)
 332                                         ++num_rings;
 333                 }
 334                 ib_start_alignment = 64;
 335                 ib_size_alignment = 64;
 336                 break;
 337         case AMDGPU_HW_IP_VCN_DEC:
 338                 type = AMD_IP_BLOCK_TYPE_VCN;
 339                 if (adev->vcn.ring_dec.ready)
 340                         ++num_rings;
 341                 ib_start_alignment = 16;
 342                 ib_size_alignment = 16;
 343                 break;
 344         case AMDGPU_HW_IP_VCN_ENC:
 345                 type = AMD_IP_BLOCK_TYPE_VCN;
 346                 for (i = 0; i < adev->vcn.num_enc_rings; i++)
 347                         if (adev->vcn.ring_enc[i].ready)
 348                                 ++num_rings;
 349                 ib_start_alignment = 64;
 350                 ib_size_alignment = 1;
 351                 break;
 352         case AMDGPU_HW_IP_VCN_JPEG:
 353                 type = AMD_IP_BLOCK_TYPE_VCN;
 354                 if (adev->vcn.ring_jpeg.ready)
 355                         ++num_rings;
 356                 ib_start_alignment = 16;
 357                 ib_size_alignment = 16;
 358                 break;
 359         default:
 360                 return -EINVAL;
 361         }
 362
 363         for (i = 0; i < adev->num_ip_blocks; i++)
 364                 if (adev->ip_blocks[i].version->type == type &&
 365                     adev->ip_blocks[i].status.valid)
 366                         break;
 367
 368         if (i == adev->num_ip_blocks)
 369                 return 0;
 370
 371         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 372                         num_rings);
 373
 374         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 375         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 376         result->capabilities_flags = 0;
 377         result->available_rings = (1 << num_rings) - 1;
 378         result->ib_start_alignment = ib_start_alignment;
 379         result->ib_size_alignment = ib_size_alignment;
 380         return 0;
 381 }
 382
 383 /*
 384  * Userspace get information ioctl
 385  */
 386 /**
 387  * amdgpu_info_ioctl - answer a device specific request.
 388  *
 389  * @adev: amdgpu device pointer
 390  * @data: request object
 391  * @filp: drm filp
 392  *
 393  * This function is used to pass device specific parameters to the userspace
 394  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 395  * etc. (all asics).
 396  * Returns 0 on success, -EINVAL on failure.
 397  */
 398 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 399 {
 400         struct amdgpu_device *adev = dev->dev_private;
 401         struct drm_amdgpu_info *info = data;
 402         struct amdgpu_mode_info *minfo = &adev->mode_info;
 403         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 404         uint32_t size = info->return_size;
 405         struct drm_crtc *crtc;
 406         uint32_t ui32 = 0;
 407         uint64_t ui64 = 0;
 408         int i, found;
 409         int ui32_size = sizeof(ui32);
 410
 411         if (!info->return_size || !info->return_pointer)
 412                 return -EINVAL;
 413
 414         /* Ensure IB tests are run on ring */
 415         flush_delayed_work(&adev->late_init_work);
 416
 417         switch (info->query) {
 418         case AMDGPU_INFO_ACCEL_WORKING:
 419                 ui32 = adev->accel_working;
 420                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 421         case AMDGPU_INFO_CRTC_FROM_ID:
 422                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 423                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 424                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 425                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 426                                 ui32 = amdgpu_crtc->crtc_id;
 427                                 found = 1;
 428                                 break;
 429                         }
 430                 }
 431                 if (!found) {
 432                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 433                         return -EINVAL;
 434                 }
 435                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 436         case AMDGPU_INFO_HW_IP_INFO: {
 437                 struct drm_amdgpu_info_hw_ip ip = {};
 438                 int ret;
 439
 440                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 441                 if (ret)
 442                         return ret;
 443
 444                 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
 445                 return ret ? -EFAULT : 0;
 446         }
 447         case AMDGPU_INFO_HW_IP_COUNT: {
 448                 enum amd_ip_block_type type;
 449                 uint32_t count = 0;
 450
 451                 switch (info->query_hw_ip.type) {
 452                 case AMDGPU_HW_IP_GFX:
 453                         type = AMD_IP_BLOCK_TYPE_GFX;
 454                         break;
 455                 case AMDGPU_HW_IP_COMPUTE:
 456                         type = AMD_IP_BLOCK_TYPE_GFX;
 457                         break;
 458                 case AMDGPU_HW_IP_DMA:
 459                         type = AMD_IP_BLOCK_TYPE_SDMA;
 460                         break;
 461                 case AMDGPU_HW_IP_UVD:
 462                         type = AMD_IP_BLOCK_TYPE_UVD;
 463                         break;
 464                 case AMDGPU_HW_IP_VCE:
 465                         type = AMD_IP_BLOCK_TYPE_VCE;
 466                         break;
 467                 case AMDGPU_HW_IP_UVD_ENC:
 468                         type = AMD_IP_BLOCK_TYPE_UVD;
 469                         break;
 470                 case AMDGPU_HW_IP_VCN_DEC:
 471                 case AMDGPU_HW_IP_VCN_ENC:
 472                 case AMDGPU_HW_IP_VCN_JPEG:
 473                         type = AMD_IP_BLOCK_TYPE_VCN;
 474                         break;
 475                 default:
 476                         return -EINVAL;
 477                 }
 478
 479                 for (i = 0; i < adev->num_ip_blocks; i++)
 480                         if (adev->ip_blocks[i].version->type == type &&
 481                             adev->ip_blocks[i].status.valid &&
 482                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 483                                 count++;
 484
 485                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 486         }
 487         case AMDGPU_INFO_TIMESTAMP:
 488                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 489                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 490         case AMDGPU_INFO_FW_VERSION: {
 491                 struct drm_amdgpu_info_firmware fw_info;
 492                 int ret;
 493
 494                 /* We only support one instance of each IP block right now. */
 495                 if (info->query_fw.ip_instance != 0)
 496                         return -EINVAL;
 497
 498                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 499                 if (ret)
 500                         return ret;
 501
 502                 return copy_to_user(out, &fw_info,
 503                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 504         }
 505         case AMDGPU_INFO_NUM_BYTES_MOVED:
 506                 ui64 = atomic64_read(&adev->num_bytes_moved);
 507                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 508         case AMDGPU_INFO_NUM_EVICTIONS:
 509                 ui64 = atomic64_read(&adev->num_evictions);
 510                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 511         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 512                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 513                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 514         case AMDGPU_INFO_VRAM_USAGE:
 515                 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 516                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 517         case AMDGPU_INFO_VIS_VRAM_USAGE:
 518                 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 519                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 520         case AMDGPU_INFO_GTT_USAGE:
 521                 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
 522                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 523         case AMDGPU_INFO_GDS_CONFIG: {
 524                 struct drm_amdgpu_info_gds gds_info;
 525
 526                 memset(&gds_info, 0, sizeof(gds_info));
 527                 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT;
 528                 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT;
 529                 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT;
 530                 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT;
 531                 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT;
 532                 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT;
 533                 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT;
 534                 return copy_to_user(out, &gds_info,
 535                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 536         }
 537         case AMDGPU_INFO_VRAM_GTT: {
 538                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 539
 540                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 541                         atomic64_read(&adev->vram_pin_size);
 542                 vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size -
 543                         atomic64_read(&adev->visible_pin_size);
 544                 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
 545                 vram_gtt.gtt_size *= PAGE_SIZE;
 546                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 547                 return copy_to_user(out, &vram_gtt,
 548                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 549         }
 550         case AMDGPU_INFO_MEMORY: {
 551                 struct drm_amdgpu_memory_info mem;
 552
 553                 memset(&mem, 0, sizeof(mem));
 554                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 555                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 556                         atomic64_read(&adev->vram_pin_size);
 557                 mem.vram.heap_usage =
 558                         amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 559                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 560
 561                 mem.cpu_accessible_vram.total_heap_size =
 562                         adev->gmc.visible_vram_size;
 563                 mem.cpu_accessible_vram.usable_heap_size = adev->gmc.visible_vram_size -
 564                         atomic64_read(&adev->visible_pin_size);
 565                 mem.cpu_accessible_vram.heap_usage =
 566                         amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 567                 mem.cpu_accessible_vram.max_allocation =
 568                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 569
 570                 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size;
 571                 mem.gtt.total_heap_size *= PAGE_SIZE;
 572                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 573                         atomic64_read(&adev->gart_pin_size);
 574                 mem.gtt.heap_usage =
 575                         amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
 576                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 577
 578                 return copy_to_user(out, &mem,
 579                                     min((size_t)size, sizeof(mem)))
 580                                     ? -EFAULT : 0;
 581         }
 582         case AMDGPU_INFO_READ_MMR_REG: {
 583                 unsigned n, alloc_size;
 584                 uint32_t *regs;
 585                 unsigned se_num = (info->read_mmr_reg.instance >>
 586                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 587                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 588                 unsigned sh_num = (info->read_mmr_reg.instance >>
 589                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 590                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 591
 592                 /* set full masks if the userspace set all bits
 593                  * in the bitfields */
 594                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 595                         se_num = 0xffffffff;
 596                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 597                         sh_num = 0xffffffff;
 598
 599                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 600                 if (!regs)
 601                         return -ENOMEM;
 602                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 603
 604                 for (i = 0; i < info->read_mmr_reg.count; i++)
 605                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 606                                                       info->read_mmr_reg.dword_offset + i,
 607                                                       &regs[i])) {
 608                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 609                                               info->read_mmr_reg.dword_offset + i);
 610                                 kfree(regs);
 611                                 return -EFAULT;
 612                         }
 613                 n = copy_to_user(out, regs, min(size, alloc_size));
 614                 kfree(regs);
 615                 return n ? -EFAULT : 0;
 616         }
 617         case AMDGPU_INFO_DEV_INFO: {
 618                 struct drm_amdgpu_info_device dev_info = {};
 619                 uint64_t vm_size;
 620
 621                 dev_info.device_id = dev->pdev->device;
 622                 dev_info.chip_rev = adev->rev_id;
 623                 dev_info.external_rev = adev->external_rev_id;
 624                 dev_info.pci_rev = dev->pdev->revision;
 625                 dev_info.family = adev->family;
 626                 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
 627                 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 628                 /* return all clocks in KHz */
 629                 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 630                 if (adev->pm.dpm_enabled) {
 631                         dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 632                         dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 633                 } else {
 634                         dev_info.max_engine_clock = adev->clock.default_sclk * 10;
 635                         dev_info.max_memory_clock = adev->clock.default_mclk * 10;
 636                 }
 637                 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 638                 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
 639                         adev->gfx.config.max_shader_engines;
 640                 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 641                 dev_info._pad = 0;
 642                 dev_info.ids_flags = 0;
 643                 if (adev->flags & AMD_IS_APU)
 644                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 645                 if (amdgpu_sriov_vf(adev))
 646                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 647
 648                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 649                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 650
 651                 /* Older VCE FW versions are buggy and can handle only 40bits */
 652                 if (adev->vce.fw_version &&
 653                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 654                         vm_size = min(vm_size, 1ULL << 40);
 655
 656                 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 657                 dev_info.virtual_address_max =
 658                         min(vm_size, AMDGPU_VA_HOLE_START);
 659
 660                 if (vm_size > AMDGPU_VA_HOLE_START) {
 661                         dev_info.high_va_offset = AMDGPU_VA_HOLE_END;
 662                         dev_info.high_va_max = AMDGPU_VA_HOLE_END | vm_size;
 663                 }
 664                 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 665                 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 666                 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
 667                 dev_info.cu_active_number = adev->gfx.cu_info.number;
 668                 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 669                 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
 670                 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 671                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 672                 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 673                        sizeof(adev->gfx.cu_info.bitmap));
 674                 dev_info.vram_type = adev->gmc.vram_type;
 675                 dev_info.vram_bit_width = adev->gmc.vram_width;
 676                 dev_info.vce_harvest_config = adev->vce.harvest_config;
 677                 dev_info.gc_double_offchip_lds_buf =
 678                         adev->gfx.config.double_offchip_lds_buf;
 679
 680                 if (amdgpu_ngg) {
 681                         dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;
 682                         dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;
 683                         dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;
 684                         dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;
 685                         dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;
 686                         dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;
 687                         dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;
 688                         dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;
 689                 }
 690                 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
 691                 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 692                 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 693                 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 694                 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 695                 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 696                 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 697
 698                 return copy_to_user(out, &dev_info,
 699                                     min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
 700         }
 701         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 702                 unsigned i;
 703                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 704                 struct amd_vce_state *vce_state;
 705
 706                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 707                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 708                         if (vce_state) {
 709                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 710                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 711                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 712                                 vce_clk_table.num_valid_entries++;
 713                         }
 714                 }
 715
 716                 return copy_to_user(out, &vce_clk_table,
 717                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 718         }
 719         case AMDGPU_INFO_VBIOS: {
 720                 uint32_t bios_size = adev->bios_size;
 721
 722                 switch (info->vbios_info.type) {
 723                 case AMDGPU_INFO_VBIOS_SIZE:
 724                         return copy_to_user(out, &bios_size,
 725                                         min((size_t)size, sizeof(bios_size)))
 726                                         ? -EFAULT : 0;
 727                 case AMDGPU_INFO_VBIOS_IMAGE: {
 728                         uint8_t *bios;
 729                         uint32_t bios_offset = info->vbios_info.offset;
 730
 731                         if (bios_offset >= bios_size)
 732                                 return -EINVAL;
 733
 734                         bios = adev->bios + bios_offset;
 735                         return copy_to_user(out, bios,
 736                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 737                                         ? -EFAULT : 0;
 738                 }
 739                 default:
 740                         DRM_DEBUG_KMS("Invalid request %d\n",
 741                                         info->vbios_info.type);
 742                         return -EINVAL;
 743                 }
 744         }
 745         case AMDGPU_INFO_NUM_HANDLES: {
 746                 struct drm_amdgpu_info_num_handles handle;
 747
 748                 switch (info->query_hw_ip.type) {
 749                 case AMDGPU_HW_IP_UVD:
 750                         /* Starting Polaris, we support unlimited UVD handles */
 751                         if (adev->asic_type < CHIP_POLARIS10) {
 752                                 handle.uvd_max_handles = adev->uvd.max_handles;
 753                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 754
 755                                 return copy_to_user(out, &handle,
 756                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 757                         } else {
 758                                 return -ENODATA;
 759                         }
 760
 761                         break;
 762                 default:
 763                         return -EINVAL;
 764                 }
 765         }
 766         case AMDGPU_INFO_SENSOR: {
 767                 if (!adev->pm.dpm_enabled)
 768                         return -ENOENT;
 769
 770                 switch (info->sensor_info.type) {
 771                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 772                         /* get sclk in Mhz */
 773                         if (amdgpu_dpm_read_sensor(adev,
 774                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 775                                                    (void *)&ui32, &ui32_size)) {
 776                                 return -EINVAL;
 777                         }
 778                         ui32 /= 100;
 779                         break;
 780                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 781                         /* get mclk in Mhz */
 782                         if (amdgpu_dpm_read_sensor(adev,
 783                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 784                                                    (void *)&ui32, &ui32_size)) {
 785                                 return -EINVAL;
 786                         }
 787                         ui32 /= 100;
 788                         break;
 789                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 790                         /* get temperature in millidegrees C */
 791                         if (amdgpu_dpm_read_sensor(adev,
 792                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 793                                                    (void *)&ui32, &ui32_size)) {
 794                                 return -EINVAL;
 795                         }
 796                         break;
 797                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 798                         /* get GPU load */
 799                         if (amdgpu_dpm_read_sensor(adev,
 800                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 801                                                    (void *)&ui32, &ui32_size)) {
 802                                 return -EINVAL;
 803                         }
 804                         break;
 805                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 806                         /* get average GPU power */
 807                         if (amdgpu_dpm_read_sensor(adev,
 808                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 809                                                    (void *)&ui32, &ui32_size)) {
 810                                 return -EINVAL;
 811                         }
 812                         ui32 >>= 8;
 813                         break;
 814                 case AMDGPU_INFO_SENSOR_VDDNB:
 815                         /* get VDDNB in millivolts */
 816                         if (amdgpu_dpm_read_sensor(adev,
 817                                                    AMDGPU_PP_SENSOR_VDDNB,
 818                                                    (void *)&ui32, &ui32_size)) {
 819                                 return -EINVAL;
 820                         }
 821                         break;
 822                 case AMDGPU_INFO_SENSOR_VDDGFX:
 823                         /* get VDDGFX in millivolts */
 824                         if (amdgpu_dpm_read_sensor(adev,
 825                                                    AMDGPU_PP_SENSOR_VDDGFX,
 826                                                    (void *)&ui32, &ui32_size)) {
 827                                 return -EINVAL;
 828                         }
 829                         break;
 830                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 831                         /* get stable pstate sclk in Mhz */
 832                         if (amdgpu_dpm_read_sensor(adev,
 833                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 834                                                    (void *)&ui32, &ui32_size)) {
 835                                 return -EINVAL;
 836                         }
 837                         ui32 /= 100;
 838                         break;
 839                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
 840                         /* get stable pstate mclk in Mhz */
 841                         if (amdgpu_dpm_read_sensor(adev,
 842                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 843                                                    (void *)&ui32, &ui32_size)) {
 844                                 return -EINVAL;
 845                         }
 846                         ui32 /= 100;
 847                         break;
 848                 default:
 849                         DRM_DEBUG_KMS("Invalid request %d\n",
 850                                       info->sensor_info.type);
 851                         return -EINVAL;
 852                 }
 853                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 854         }
 855         case AMDGPU_INFO_VRAM_LOST_COUNTER:
 856                 ui32 = atomic_read(&adev->vram_lost_counter);
 857                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 858         default:
 859                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
 860                 return -EINVAL;
 861         }
 862         return 0;
 863 }
 864
 865
 866 /*
 867  * Outdated mess for old drm with Xorg being in charge (void function now).
 868  */
 869 /**
 870  * amdgpu_driver_lastclose_kms - drm callback for last close
 871  *
 872  * @dev: drm dev pointer
 873  *
 874  * Switch vga_switcheroo state after last close (all asics).
 875  */
 876 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
 877 {
 878         drm_fb_helper_lastclose(dev);
 879         vga_switcheroo_process_delayed_switch();
 880 }
 881
 882 /**
 883  * amdgpu_driver_open_kms - drm callback for open
 884  *
 885  * @dev: drm dev pointer
 886  * @file_priv: drm file
 887  *
 888  * On device open, init vm on cayman+ (all asics).
 889  * Returns 0 on success, error on failure.
 890  */
 891 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 892 {
 893         struct amdgpu_device *adev = dev->dev_private;
 894         struct amdgpu_fpriv *fpriv;
 895         int r, pasid;
 896
 897         file_priv->driver_priv = NULL;
 898
 899         r = pm_runtime_get_sync(dev->dev);
 900         if (r < 0)
 901                 return r;
 902
 903         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 904         if (unlikely(!fpriv)) {
 905                 r = -ENOMEM;
 906                 goto out_suspend;
 907         }
 908
 909         pasid = amdgpu_pasid_alloc(16);
 910         if (pasid < 0) {
 911                 dev_warn(adev->dev, "No more PASIDs available!");
 912                 pasid = 0;
 913         }
 914         r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
 915         if (r)
 916                 goto error_pasid;
 917
 918         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
 919         if (!fpriv->prt_va) {
 920                 r = -ENOMEM;
 921                 goto error_vm;
 922         }
 923
 924         if (amdgpu_sriov_vf(adev)) {
 925                 r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va);
 926                 if (r)
 927                         goto error_vm;
 928         }
 929
 930         mutex_init(&fpriv->bo_list_lock);
 931         idr_init(&fpriv->bo_list_handles);
 932
 933         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
 934
 935         file_priv->driver_priv = fpriv;
 936         goto out_suspend;
 937
 938 error_vm:
 939         amdgpu_vm_fini(adev, &fpriv->vm);
 940
 941 error_pasid:
 942         if (pasid)
 943                 amdgpu_pasid_free(pasid);
 944
 945         kfree(fpriv);
 946
 947 out_suspend:
 948         pm_runtime_mark_last_busy(dev->dev);
 949         pm_runtime_put_autosuspend(dev->dev);
 950
 951         return r;
 952 }
 953
 954 /**
 955  * amdgpu_driver_postclose_kms - drm callback for post close
 956  *
 957  * @dev: drm dev pointer
 958  * @file_priv: drm file
 959  *
 960  * On device post close, tear down vm on cayman+ (all asics).
 961  */
 962 void amdgpu_driver_postclose_kms(struct drm_device *dev,
 963                                  struct drm_file *file_priv)
 964 {
 965         struct amdgpu_device *adev = dev->dev_private;
 966         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 967         struct amdgpu_bo_list *list;
 968         struct amdgpu_bo *pd;
 969         unsigned int pasid;
 970         int handle;
 971
 972         if (!fpriv)
 973                 return;
 974
 975         pm_runtime_get_sync(dev->dev);
 976
 977         if (adev->asic_type != CHIP_RAVEN) {
 978                 amdgpu_uvd_free_handles(adev, file_priv);
 979                 amdgpu_vce_free_handles(adev, file_priv);
 980         }
 981
 982         amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
 983
 984         if (amdgpu_sriov_vf(adev)) {
 985                 /* TODO: how to handle reserve failure */
 986                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
 987                 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
 988                 fpriv->csa_va = NULL;
 989                 amdgpu_bo_unreserve(adev->virt.csa_obj);
 990         }
 991
 992         pasid = fpriv->vm.pasid;
 993         pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
 994
 995         amdgpu_vm_fini(adev, &fpriv->vm);
 996         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
 997
 998         if (pasid)
 999                 amdgpu_pasid_free_delayed(pd->tbo.resv, pasid);
1000         amdgpu_bo_unref(&pd);
1001
1002         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1003                 amdgpu_bo_list_put(list);
1004
1005         idr_destroy(&fpriv->bo_list_handles);
1006         mutex_destroy(&fpriv->bo_list_lock);
1007
1008         kfree(fpriv);
1009         file_priv->driver_priv = NULL;
1010
1011         pm_runtime_mark_last_busy(dev->dev);
1012         pm_runtime_put_autosuspend(dev->dev);
1013 }
1014
1015 /*
1016  * VBlank related functions.
1017  */
1018 /**
1019  * amdgpu_get_vblank_counter_kms - get frame count
1020  *
1021  * @dev: drm dev pointer
1022  * @pipe: crtc to get the frame count from
1023  *
1024  * Gets the frame count on the requested crtc (all asics).
1025  * Returns frame count on success, -EINVAL on failure.
1026  */
1027 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
1028 {
1029         struct amdgpu_device *adev = dev->dev_private;
1030         int vpos, hpos, stat;
1031         u32 count;
1032
1033         if (pipe >= adev->mode_info.num_crtc) {
1034                 DRM_ERROR("Invalid crtc %u\n", pipe);
1035                 return -EINVAL;
1036         }
1037
1038         /* The hw increments its frame counter at start of vsync, not at start
1039          * of vblank, as is required by DRM core vblank counter handling.
1040          * Cook the hw count here to make it appear to the caller as if it
1041          * incremented at start of vblank. We measure distance to start of
1042          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1043          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1044          * result by 1 to give the proper appearance to caller.
1045          */
1046         if (adev->mode_info.crtcs[pipe]) {
1047                 /* Repeat readout if needed to provide stable result if
1048                  * we cross start of vsync during the queries.
1049                  */
1050                 do {
1051                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1052                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1053                          * vpos as distance to start of vblank, instead of
1054                          * regular vertical scanout pos.
1055                          */
1056                         stat = amdgpu_display_get_crtc_scanoutpos(
1057                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1058                                 &vpos, &hpos, NULL, NULL,
1059                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1060                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1061
1062                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1063                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1064                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1065                 } else {
1066                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1067                                       pipe, vpos);
1068
1069                         /* Bump counter if we are at >= leading edge of vblank,
1070                          * but before vsync where vpos would turn negative and
1071                          * the hw counter really increments.
1072                          */
1073                         if (vpos >= 0)
1074                                 count++;
1075                 }
1076         } else {
1077                 /* Fallback to use value as is. */
1078                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1079                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1080         }
1081
1082         return count;
1083 }
1084
1085 /**
1086  * amdgpu_enable_vblank_kms - enable vblank interrupt
1087  *
1088  * @dev: drm dev pointer
1089  * @pipe: crtc to enable vblank interrupt for
1090  *
1091  * Enable the interrupt on the requested crtc (all asics).
1092  * Returns 0 on success, -EINVAL on failure.
1093  */
1094 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1095 {
1096         struct amdgpu_device *adev = dev->dev_private;
1097         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1098
1099         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1100 }
1101
1102 /**
1103  * amdgpu_disable_vblank_kms - disable vblank interrupt
1104  *
1105  * @dev: drm dev pointer
1106  * @pipe: crtc to disable vblank interrupt for
1107  *
1108  * Disable the interrupt on the requested crtc (all asics).
1109  */
1110 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1111 {
1112         struct amdgpu_device *adev = dev->dev_private;
1113         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1114
1115         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1116 }
1117
1118 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
1119         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1120         DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1121         DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1122         DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
1123         DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1124         DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1125         /* KMS */
1126         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1127         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1128         DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1129         DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1130         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1131         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1132         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1133         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1134         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1135         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)
1136 };
1137 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
1138
1139 /*
1140  * Debugfs info
1141  */
1142 #if defined(CONFIG_DEBUG_FS)
1143
1144 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1145 {
1146         struct drm_info_node *node = (struct drm_info_node *) m->private;
1147         struct drm_device *dev = node->minor->dev;
1148         struct amdgpu_device *adev = dev->dev_private;
1149         struct drm_amdgpu_info_firmware fw_info;
1150         struct drm_amdgpu_query_fw query_fw;
1151         struct atom_context *ctx = adev->mode_info.atom_context;
1152         int ret, i;
1153
1154         /* VCE */
1155         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1156         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1157         if (ret)
1158                 return ret;
1159         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1160                    fw_info.feature, fw_info.ver);
1161
1162         /* UVD */
1163         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1164         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1165         if (ret)
1166                 return ret;
1167         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1168                    fw_info.feature, fw_info.ver);
1169
1170         /* GMC */
1171         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1172         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1173         if (ret)
1174                 return ret;
1175         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1176                    fw_info.feature, fw_info.ver);
1177
1178         /* ME */
1179         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1180         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1181         if (ret)
1182                 return ret;
1183         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1184                    fw_info.feature, fw_info.ver);
1185
1186         /* PFP */
1187         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1188         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1189         if (ret)
1190                 return ret;
1191         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1192                    fw_info.feature, fw_info.ver);
1193
1194         /* CE */
1195         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1196         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1197         if (ret)
1198                 return ret;
1199         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1200                    fw_info.feature, fw_info.ver);
1201
1202         /* RLC */
1203         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1204         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1205         if (ret)
1206                 return ret;
1207         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1208                    fw_info.feature, fw_info.ver);
1209
1210         /* RLC SAVE RESTORE LIST CNTL */
1211         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1212         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1213         if (ret)
1214                 return ret;
1215         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1216                    fw_info.feature, fw_info.ver);
1217
1218         /* RLC SAVE RESTORE LIST GPM MEM */
1219         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1220         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1221         if (ret)
1222                 return ret;
1223         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1224                    fw_info.feature, fw_info.ver);
1225
1226         /* RLC SAVE RESTORE LIST SRM MEM */
1227         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1228         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1229         if (ret)
1230                 return ret;
1231         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1232                    fw_info.feature, fw_info.ver);
1233
1234         /* MEC */
1235         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1236         query_fw.index = 0;
1237         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1238         if (ret)
1239                 return ret;
1240         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1241                    fw_info.feature, fw_info.ver);
1242
1243         /* MEC2 */
1244         if (adev->asic_type == CHIP_KAVERI ||
1245             (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
1246                 query_fw.index = 1;
1247                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1248                 if (ret)
1249                         return ret;
1250                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1251                            fw_info.feature, fw_info.ver);
1252         }
1253
1254         /* PSP SOS */
1255         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1256         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1257         if (ret)
1258                 return ret;
1259         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1260                    fw_info.feature, fw_info.ver);
1261
1262
1263         /* PSP ASD */
1264         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1265         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1266         if (ret)
1267                 return ret;
1268         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1269                    fw_info.feature, fw_info.ver);
1270
1271         /* SMC */
1272         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1273         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1274         if (ret)
1275                 return ret;
1276         seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1277                    fw_info.feature, fw_info.ver);
1278
1279         /* SDMA */
1280         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1281         for (i = 0; i < adev->sdma.num_instances; i++) {
1282                 query_fw.index = i;
1283                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1284                 if (ret)
1285                         return ret;
1286                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1287                            i, fw_info.feature, fw_info.ver);
1288         }
1289
1290         /* VCN */
1291         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1292         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1293         if (ret)
1294                 return ret;
1295         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1296                    fw_info.feature, fw_info.ver);
1297
1298
1299         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1300
1301         return 0;
1302 }
1303
1304 static const struct drm_info_list amdgpu_firmware_info_list[] = {
1305         {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1306 };
1307 #endif
1308
1309 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1310 {
1311 #if defined(CONFIG_DEBUG_FS)
1312         return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1313                                         ARRAY_SIZE(amdgpu_firmware_info_list));
1314 #else
1315         return 0;
1316 #endif
1317 }