2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 #include <drm/amdgpu_drm.h>
31 #include "amdgpu_uvd.h"
32 #include "amdgpu_vce.h"
34 #include <linux/vga_switcheroo.h>
35 #include <linux/slab.h>
36 #include <linux/pm_runtime.h>
37 #include "amdgpu_amdkfd.h"
40 * amdgpu_driver_unload_kms - Main unload function for KMS.
42 * @dev: drm dev pointer
44 * This is the main unload function for KMS (all asics).
45 * Returns 0 on success.
47 void amdgpu_driver_unload_kms(struct drm_device *dev)
49 struct amdgpu_device *adev = dev->dev_private;
54 if (adev->rmmio == NULL)
57 if (amdgpu_sriov_vf(adev))
58 amdgpu_virt_request_full_gpu(adev, false);
60 if (amdgpu_device_is_px(dev)) {
61 pm_runtime_get_sync(dev->dev);
62 pm_runtime_forbid(dev->dev);
65 amdgpu_amdkfd_device_fini(adev);
67 amdgpu_acpi_fini(adev);
69 amdgpu_device_fini(adev);
73 dev->dev_private = NULL;
77 * amdgpu_driver_load_kms - Main load function for KMS.
79 * @dev: drm dev pointer
80 * @flags: device flags
82 * This is the main load function for KMS (all asics).
83 * Returns 0 on success, error on failure.
85 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
87 struct amdgpu_device *adev;
90 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
94 dev->dev_private = (void *)adev;
96 if ((amdgpu_runtime_pm != 0) &&
98 (amdgpu_is_atpx_hybrid() ||
99 amdgpu_has_atpx_dgpu_power_cntl()) &&
100 ((flags & AMD_IS_APU) == 0) &&
101 !pci_is_thunderbolt_attached(dev->pdev))
104 /* amdgpu_device_init should report only fatal error
105 * like memory allocation failure or iomapping failure,
106 * or memory manager initialization failure, it must
107 * properly initialize the GPU MC controller and permit
110 r = amdgpu_device_init(adev, dev, dev->pdev, flags);
112 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
116 /* Call ACPI methods: require modeset init
117 * but failure is not fatal
120 acpi_status = amdgpu_acpi_init(adev);
122 dev_dbg(&dev->pdev->dev,
123 "Error during ACPI methods call\n");
126 amdgpu_amdkfd_load_interface(adev);
127 amdgpu_amdkfd_device_probe(adev);
128 amdgpu_amdkfd_device_init(adev);
130 if (amdgpu_device_is_px(dev)) {
131 pm_runtime_use_autosuspend(dev->dev);
132 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
133 pm_runtime_set_active(dev->dev);
134 pm_runtime_allow(dev->dev);
135 pm_runtime_mark_last_busy(dev->dev);
136 pm_runtime_put_autosuspend(dev->dev);
139 if (amdgpu_sriov_vf(adev))
140 amdgpu_virt_release_full_gpu(adev, true);
144 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
145 if (adev->rmmio && amdgpu_device_is_px(dev))
146 pm_runtime_put_noidle(dev->dev);
147 amdgpu_driver_unload_kms(dev);
153 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
154 struct drm_amdgpu_query_fw *query_fw,
155 struct amdgpu_device *adev)
157 switch (query_fw->fw_type) {
158 case AMDGPU_INFO_FW_VCE:
159 fw_info->ver = adev->vce.fw_version;
160 fw_info->feature = adev->vce.fb_version;
162 case AMDGPU_INFO_FW_UVD:
163 fw_info->ver = adev->uvd.fw_version;
164 fw_info->feature = 0;
166 case AMDGPU_INFO_FW_GMC:
167 fw_info->ver = adev->mc.fw_version;
168 fw_info->feature = 0;
170 case AMDGPU_INFO_FW_GFX_ME:
171 fw_info->ver = adev->gfx.me_fw_version;
172 fw_info->feature = adev->gfx.me_feature_version;
174 case AMDGPU_INFO_FW_GFX_PFP:
175 fw_info->ver = adev->gfx.pfp_fw_version;
176 fw_info->feature = adev->gfx.pfp_feature_version;
178 case AMDGPU_INFO_FW_GFX_CE:
179 fw_info->ver = adev->gfx.ce_fw_version;
180 fw_info->feature = adev->gfx.ce_feature_version;
182 case AMDGPU_INFO_FW_GFX_RLC:
183 fw_info->ver = adev->gfx.rlc_fw_version;
184 fw_info->feature = adev->gfx.rlc_feature_version;
186 case AMDGPU_INFO_FW_GFX_MEC:
187 if (query_fw->index == 0) {
188 fw_info->ver = adev->gfx.mec_fw_version;
189 fw_info->feature = adev->gfx.mec_feature_version;
190 } else if (query_fw->index == 1) {
191 fw_info->ver = adev->gfx.mec2_fw_version;
192 fw_info->feature = adev->gfx.mec2_feature_version;
196 case AMDGPU_INFO_FW_SMC:
197 fw_info->ver = adev->pm.fw_version;
198 fw_info->feature = 0;
200 case AMDGPU_INFO_FW_SDMA:
201 if (query_fw->index >= adev->sdma.num_instances)
203 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
204 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
206 case AMDGPU_INFO_FW_SOS:
207 fw_info->ver = adev->psp.sos_fw_version;
208 fw_info->feature = adev->psp.sos_feature_version;
210 case AMDGPU_INFO_FW_ASD:
211 fw_info->ver = adev->psp.asd_fw_version;
212 fw_info->feature = adev->psp.asd_feature_version;
221 * Userspace get information ioctl
224 * amdgpu_info_ioctl - answer a device specific request.
226 * @adev: amdgpu device pointer
227 * @data: request object
230 * This function is used to pass device specific parameters to the userspace
231 * drivers. Examples include: pci device id, pipeline parms, tiling params,
233 * Returns 0 on success, -EINVAL on failure.
235 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
237 struct amdgpu_device *adev = dev->dev_private;
238 struct drm_amdgpu_info *info = data;
239 struct amdgpu_mode_info *minfo = &adev->mode_info;
240 void __user *out = (void __user *)(uintptr_t)info->return_pointer;
241 uint32_t size = info->return_size;
242 struct drm_crtc *crtc;
246 int ui32_size = sizeof(ui32);
248 if (!info->return_size || !info->return_pointer)
251 switch (info->query) {
252 case AMDGPU_INFO_ACCEL_WORKING:
253 ui32 = adev->accel_working;
254 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
255 case AMDGPU_INFO_CRTC_FROM_ID:
256 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
257 crtc = (struct drm_crtc *)minfo->crtcs[i];
258 if (crtc && crtc->base.id == info->mode_crtc.id) {
259 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
260 ui32 = amdgpu_crtc->crtc_id;
266 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
269 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
270 case AMDGPU_INFO_HW_IP_INFO: {
271 struct drm_amdgpu_info_hw_ip ip = {};
272 enum amd_ip_block_type type;
273 uint32_t ring_mask = 0;
274 uint32_t ib_start_alignment = 0;
275 uint32_t ib_size_alignment = 0;
277 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
280 switch (info->query_hw_ip.type) {
281 case AMDGPU_HW_IP_GFX:
282 type = AMD_IP_BLOCK_TYPE_GFX;
283 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
284 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i);
285 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
286 ib_size_alignment = 8;
288 case AMDGPU_HW_IP_COMPUTE:
289 type = AMD_IP_BLOCK_TYPE_GFX;
290 for (i = 0; i < adev->gfx.num_compute_rings; i++)
291 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i);
292 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
293 ib_size_alignment = 8;
295 case AMDGPU_HW_IP_DMA:
296 type = AMD_IP_BLOCK_TYPE_SDMA;
297 for (i = 0; i < adev->sdma.num_instances; i++)
298 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i);
299 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
300 ib_size_alignment = 1;
302 case AMDGPU_HW_IP_UVD:
303 type = AMD_IP_BLOCK_TYPE_UVD;
304 ring_mask = adev->uvd.ring.ready ? 1 : 0;
305 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
306 ib_size_alignment = 16;
308 case AMDGPU_HW_IP_VCE:
309 type = AMD_IP_BLOCK_TYPE_VCE;
310 for (i = 0; i < adev->vce.num_rings; i++)
311 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);
312 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
313 ib_size_alignment = 1;
315 case AMDGPU_HW_IP_UVD_ENC:
316 type = AMD_IP_BLOCK_TYPE_UVD;
317 for (i = 0; i < adev->uvd.num_enc_rings; i++)
318 ring_mask |= ((adev->uvd.ring_enc[i].ready ? 1 : 0) << i);
319 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
320 ib_size_alignment = 1;
326 for (i = 0; i < adev->num_ip_blocks; i++) {
327 if (adev->ip_blocks[i].version->type == type &&
328 adev->ip_blocks[i].status.valid) {
329 ip.hw_ip_version_major = adev->ip_blocks[i].version->major;
330 ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor;
331 ip.capabilities_flags = 0;
332 ip.available_rings = ring_mask;
333 ip.ib_start_alignment = ib_start_alignment;
334 ip.ib_size_alignment = ib_size_alignment;
338 return copy_to_user(out, &ip,
339 min((size_t)size, sizeof(ip))) ? -EFAULT : 0;
341 case AMDGPU_INFO_HW_IP_COUNT: {
342 enum amd_ip_block_type type;
345 switch (info->query_hw_ip.type) {
346 case AMDGPU_HW_IP_GFX:
347 type = AMD_IP_BLOCK_TYPE_GFX;
349 case AMDGPU_HW_IP_COMPUTE:
350 type = AMD_IP_BLOCK_TYPE_GFX;
352 case AMDGPU_HW_IP_DMA:
353 type = AMD_IP_BLOCK_TYPE_SDMA;
355 case AMDGPU_HW_IP_UVD:
356 type = AMD_IP_BLOCK_TYPE_UVD;
358 case AMDGPU_HW_IP_VCE:
359 type = AMD_IP_BLOCK_TYPE_VCE;
361 case AMDGPU_HW_IP_UVD_ENC:
362 type = AMD_IP_BLOCK_TYPE_UVD;
368 for (i = 0; i < adev->num_ip_blocks; i++)
369 if (adev->ip_blocks[i].version->type == type &&
370 adev->ip_blocks[i].status.valid &&
371 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
374 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
376 case AMDGPU_INFO_TIMESTAMP:
377 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
378 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
379 case AMDGPU_INFO_FW_VERSION: {
380 struct drm_amdgpu_info_firmware fw_info;
383 /* We only support one instance of each IP block right now. */
384 if (info->query_fw.ip_instance != 0)
387 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
391 return copy_to_user(out, &fw_info,
392 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
394 case AMDGPU_INFO_NUM_BYTES_MOVED:
395 ui64 = atomic64_read(&adev->num_bytes_moved);
396 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
397 case AMDGPU_INFO_NUM_EVICTIONS:
398 ui64 = atomic64_read(&adev->num_evictions);
399 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
400 case AMDGPU_INFO_VRAM_USAGE:
401 ui64 = atomic64_read(&adev->vram_usage);
402 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
403 case AMDGPU_INFO_VIS_VRAM_USAGE:
404 ui64 = atomic64_read(&adev->vram_vis_usage);
405 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
406 case AMDGPU_INFO_GTT_USAGE:
407 ui64 = atomic64_read(&adev->gtt_usage);
408 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
409 case AMDGPU_INFO_GDS_CONFIG: {
410 struct drm_amdgpu_info_gds gds_info;
412 memset(&gds_info, 0, sizeof(gds_info));
413 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT;
414 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT;
415 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT;
416 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT;
417 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT;
418 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT;
419 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT;
420 return copy_to_user(out, &gds_info,
421 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
423 case AMDGPU_INFO_VRAM_GTT: {
424 struct drm_amdgpu_info_vram_gtt vram_gtt;
426 vram_gtt.vram_size = adev->mc.real_vram_size;
427 vram_gtt.vram_size -= adev->vram_pin_size;
428 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size;
429 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size);
430 vram_gtt.gtt_size = adev->mc.gtt_size;
431 vram_gtt.gtt_size -= adev->gart_pin_size;
432 return copy_to_user(out, &vram_gtt,
433 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
435 case AMDGPU_INFO_MEMORY: {
436 struct drm_amdgpu_memory_info mem;
438 memset(&mem, 0, sizeof(mem));
439 mem.vram.total_heap_size = adev->mc.real_vram_size;
440 mem.vram.usable_heap_size =
441 adev->mc.real_vram_size - adev->vram_pin_size;
442 mem.vram.heap_usage = atomic64_read(&adev->vram_usage);
443 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
445 mem.cpu_accessible_vram.total_heap_size =
446 adev->mc.visible_vram_size;
447 mem.cpu_accessible_vram.usable_heap_size =
448 adev->mc.visible_vram_size -
449 (adev->vram_pin_size - adev->invisible_pin_size);
450 mem.cpu_accessible_vram.heap_usage =
451 atomic64_read(&adev->vram_vis_usage);
452 mem.cpu_accessible_vram.max_allocation =
453 mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
455 mem.gtt.total_heap_size = adev->mc.gtt_size;
456 mem.gtt.usable_heap_size =
457 adev->mc.gtt_size - adev->gart_pin_size;
458 mem.gtt.heap_usage = atomic64_read(&adev->gtt_usage);
459 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
461 return copy_to_user(out, &mem,
462 min((size_t)size, sizeof(mem)))
465 case AMDGPU_INFO_READ_MMR_REG: {
466 unsigned n, alloc_size;
468 unsigned se_num = (info->read_mmr_reg.instance >>
469 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
470 AMDGPU_INFO_MMR_SE_INDEX_MASK;
471 unsigned sh_num = (info->read_mmr_reg.instance >>
472 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
473 AMDGPU_INFO_MMR_SH_INDEX_MASK;
475 /* set full masks if the userspace set all bits
476 * in the bitfields */
477 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
479 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
482 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
485 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
487 for (i = 0; i < info->read_mmr_reg.count; i++)
488 if (amdgpu_asic_read_register(adev, se_num, sh_num,
489 info->read_mmr_reg.dword_offset + i,
491 DRM_DEBUG_KMS("unallowed offset %#x\n",
492 info->read_mmr_reg.dword_offset + i);
496 n = copy_to_user(out, regs, min(size, alloc_size));
498 return n ? -EFAULT : 0;
500 case AMDGPU_INFO_DEV_INFO: {
501 struct drm_amdgpu_info_device dev_info = {};
503 dev_info.device_id = dev->pdev->device;
504 dev_info.chip_rev = adev->rev_id;
505 dev_info.external_rev = adev->external_rev_id;
506 dev_info.pci_rev = dev->pdev->revision;
507 dev_info.family = adev->family;
508 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
509 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
510 /* return all clocks in KHz */
511 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
512 if (adev->pm.dpm_enabled) {
513 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
514 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
516 dev_info.max_engine_clock = adev->pm.default_sclk * 10;
517 dev_info.max_memory_clock = adev->pm.default_mclk * 10;
519 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
520 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
521 adev->gfx.config.max_shader_engines;
522 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
524 dev_info.ids_flags = 0;
525 if (adev->flags & AMD_IS_APU)
526 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
527 if (amdgpu_sriov_vf(adev))
528 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
529 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
530 dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
531 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
532 dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) *
533 AMDGPU_GPU_PAGE_SIZE;
534 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
536 dev_info.cu_active_number = adev->gfx.cu_info.number;
537 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
538 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
539 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
540 sizeof(adev->gfx.cu_info.bitmap));
541 dev_info.vram_type = adev->mc.vram_type;
542 dev_info.vram_bit_width = adev->mc.vram_width;
543 dev_info.vce_harvest_config = adev->vce.harvest_config;
544 dev_info.gc_double_offchip_lds_buf =
545 adev->gfx.config.double_offchip_lds_buf;
548 dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;
549 dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;
550 dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;
551 dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;
552 dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;
553 dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;
554 dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;
555 dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;
557 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
558 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
559 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
560 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
561 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
562 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
563 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
565 return copy_to_user(out, &dev_info,
566 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
568 case AMDGPU_INFO_VCE_CLOCK_TABLE: {
570 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
571 struct amd_vce_state *vce_state;
573 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
574 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
576 vce_clk_table.entries[i].sclk = vce_state->sclk;
577 vce_clk_table.entries[i].mclk = vce_state->mclk;
578 vce_clk_table.entries[i].eclk = vce_state->evclk;
579 vce_clk_table.num_valid_entries++;
583 return copy_to_user(out, &vce_clk_table,
584 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
586 case AMDGPU_INFO_VBIOS: {
587 uint32_t bios_size = adev->bios_size;
589 switch (info->vbios_info.type) {
590 case AMDGPU_INFO_VBIOS_SIZE:
591 return copy_to_user(out, &bios_size,
592 min((size_t)size, sizeof(bios_size)))
594 case AMDGPU_INFO_VBIOS_IMAGE: {
596 uint32_t bios_offset = info->vbios_info.offset;
598 if (bios_offset >= bios_size)
601 bios = adev->bios + bios_offset;
602 return copy_to_user(out, bios,
603 min((size_t)size, (size_t)(bios_size - bios_offset)))
607 DRM_DEBUG_KMS("Invalid request %d\n",
608 info->vbios_info.type);
612 case AMDGPU_INFO_NUM_HANDLES: {
613 struct drm_amdgpu_info_num_handles handle;
615 switch (info->query_hw_ip.type) {
616 case AMDGPU_HW_IP_UVD:
617 /* Starting Polaris, we support unlimited UVD handles */
618 if (adev->asic_type < CHIP_POLARIS10) {
619 handle.uvd_max_handles = adev->uvd.max_handles;
620 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
622 return copy_to_user(out, &handle,
623 min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
633 case AMDGPU_INFO_SENSOR: {
634 struct pp_gpu_power query = {0};
635 int query_size = sizeof(query);
640 switch (info->sensor_info.type) {
641 case AMDGPU_INFO_SENSOR_GFX_SCLK:
642 /* get sclk in Mhz */
643 if (amdgpu_dpm_read_sensor(adev,
644 AMDGPU_PP_SENSOR_GFX_SCLK,
645 (void *)&ui32, &ui32_size)) {
650 case AMDGPU_INFO_SENSOR_GFX_MCLK:
651 /* get mclk in Mhz */
652 if (amdgpu_dpm_read_sensor(adev,
653 AMDGPU_PP_SENSOR_GFX_MCLK,
654 (void *)&ui32, &ui32_size)) {
659 case AMDGPU_INFO_SENSOR_GPU_TEMP:
660 /* get temperature in millidegrees C */
661 if (amdgpu_dpm_read_sensor(adev,
662 AMDGPU_PP_SENSOR_GPU_TEMP,
663 (void *)&ui32, &ui32_size)) {
667 case AMDGPU_INFO_SENSOR_GPU_LOAD:
669 if (amdgpu_dpm_read_sensor(adev,
670 AMDGPU_PP_SENSOR_GPU_LOAD,
671 (void *)&ui32, &ui32_size)) {
675 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
676 /* get average GPU power */
677 if (amdgpu_dpm_read_sensor(adev,
678 AMDGPU_PP_SENSOR_GPU_POWER,
679 (void *)&query, &query_size)) {
682 ui32 = query.average_gpu_power >> 8;
684 case AMDGPU_INFO_SENSOR_VDDNB:
685 /* get VDDNB in millivolts */
686 if (amdgpu_dpm_read_sensor(adev,
687 AMDGPU_PP_SENSOR_VDDNB,
688 (void *)&ui32, &ui32_size)) {
692 case AMDGPU_INFO_SENSOR_VDDGFX:
693 /* get VDDGFX in millivolts */
694 if (amdgpu_dpm_read_sensor(adev,
695 AMDGPU_PP_SENSOR_VDDGFX,
696 (void *)&ui32, &ui32_size)) {
701 DRM_DEBUG_KMS("Invalid request %d\n",
702 info->sensor_info.type);
705 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
708 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
716 * Outdated mess for old drm with Xorg being in charge (void function now).
719 * amdgpu_driver_lastclose_kms - drm callback for last close
721 * @dev: drm dev pointer
723 * Switch vga_switcheroo state after last close (all asics).
725 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
727 struct amdgpu_device *adev = dev->dev_private;
729 amdgpu_fbdev_restore_mode(adev);
730 vga_switcheroo_process_delayed_switch();
734 * amdgpu_driver_open_kms - drm callback for open
736 * @dev: drm dev pointer
737 * @file_priv: drm file
739 * On device open, init vm on cayman+ (all asics).
740 * Returns 0 on success, error on failure.
742 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
744 struct amdgpu_device *adev = dev->dev_private;
745 struct amdgpu_fpriv *fpriv;
748 file_priv->driver_priv = NULL;
750 r = pm_runtime_get_sync(dev->dev);
754 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
755 if (unlikely(!fpriv)) {
760 r = amdgpu_vm_init(adev, &fpriv->vm);
766 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
767 if (!fpriv->prt_va) {
769 amdgpu_vm_fini(adev, &fpriv->vm);
774 if (amdgpu_sriov_vf(adev)) {
775 r = amdgpu_map_static_csa(adev, &fpriv->vm);
780 mutex_init(&fpriv->bo_list_lock);
781 idr_init(&fpriv->bo_list_handles);
783 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
785 file_priv->driver_priv = fpriv;
788 pm_runtime_mark_last_busy(dev->dev);
789 pm_runtime_put_autosuspend(dev->dev);
795 * amdgpu_driver_postclose_kms - drm callback for post close
797 * @dev: drm dev pointer
798 * @file_priv: drm file
800 * On device post close, tear down vm on cayman+ (all asics).
802 void amdgpu_driver_postclose_kms(struct drm_device *dev,
803 struct drm_file *file_priv)
805 struct amdgpu_device *adev = dev->dev_private;
806 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
807 struct amdgpu_bo_list *list;
813 pm_runtime_get_sync(dev->dev);
815 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
817 amdgpu_uvd_free_handles(adev, file_priv);
818 amdgpu_vce_free_handles(adev, file_priv);
820 amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
822 if (amdgpu_sriov_vf(adev)) {
823 /* TODO: how to handle reserve failure */
824 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
825 amdgpu_vm_bo_rmv(adev, fpriv->vm.csa_bo_va);
826 fpriv->vm.csa_bo_va = NULL;
827 amdgpu_bo_unreserve(adev->virt.csa_obj);
830 amdgpu_vm_fini(adev, &fpriv->vm);
832 idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
833 amdgpu_bo_list_free(list);
835 idr_destroy(&fpriv->bo_list_handles);
836 mutex_destroy(&fpriv->bo_list_lock);
839 file_priv->driver_priv = NULL;
841 pm_runtime_mark_last_busy(dev->dev);
842 pm_runtime_put_autosuspend(dev->dev);
846 * VBlank related functions.
849 * amdgpu_get_vblank_counter_kms - get frame count
851 * @dev: drm dev pointer
852 * @pipe: crtc to get the frame count from
854 * Gets the frame count on the requested crtc (all asics).
855 * Returns frame count on success, -EINVAL on failure.
857 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
859 struct amdgpu_device *adev = dev->dev_private;
860 int vpos, hpos, stat;
863 if (pipe >= adev->mode_info.num_crtc) {
864 DRM_ERROR("Invalid crtc %u\n", pipe);
868 /* The hw increments its frame counter at start of vsync, not at start
869 * of vblank, as is required by DRM core vblank counter handling.
870 * Cook the hw count here to make it appear to the caller as if it
871 * incremented at start of vblank. We measure distance to start of
872 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
873 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
874 * result by 1 to give the proper appearance to caller.
876 if (adev->mode_info.crtcs[pipe]) {
877 /* Repeat readout if needed to provide stable result if
878 * we cross start of vsync during the queries.
881 count = amdgpu_display_vblank_get_counter(adev, pipe);
882 /* Ask amdgpu_get_crtc_scanoutpos to return vpos as
883 * distance to start of vblank, instead of regular
884 * vertical scanout pos.
886 stat = amdgpu_get_crtc_scanoutpos(
887 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
888 &vpos, &hpos, NULL, NULL,
889 &adev->mode_info.crtcs[pipe]->base.hwmode);
890 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
892 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
893 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
894 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
896 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
899 /* Bump counter if we are at >= leading edge of vblank,
900 * but before vsync where vpos would turn negative and
901 * the hw counter really increments.
907 /* Fallback to use value as is. */
908 count = amdgpu_display_vblank_get_counter(adev, pipe);
909 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
916 * amdgpu_enable_vblank_kms - enable vblank interrupt
918 * @dev: drm dev pointer
919 * @pipe: crtc to enable vblank interrupt for
921 * Enable the interrupt on the requested crtc (all asics).
922 * Returns 0 on success, -EINVAL on failure.
924 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
926 struct amdgpu_device *adev = dev->dev_private;
927 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
929 return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
933 * amdgpu_disable_vblank_kms - disable vblank interrupt
935 * @dev: drm dev pointer
936 * @pipe: crtc to disable vblank interrupt for
938 * Disable the interrupt on the requested crtc (all asics).
940 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
942 struct amdgpu_device *adev = dev->dev_private;
943 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
945 amdgpu_irq_put(adev, &adev->crtc_irq, idx);
948 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
949 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
950 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
951 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
953 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
954 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
955 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
956 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
957 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
958 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
959 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
960 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
961 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
962 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
964 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
969 #if defined(CONFIG_DEBUG_FS)
971 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
973 struct drm_info_node *node = (struct drm_info_node *) m->private;
974 struct drm_device *dev = node->minor->dev;
975 struct amdgpu_device *adev = dev->dev_private;
976 struct drm_amdgpu_info_firmware fw_info;
977 struct drm_amdgpu_query_fw query_fw;
981 query_fw.fw_type = AMDGPU_INFO_FW_VCE;
982 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
985 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
986 fw_info.feature, fw_info.ver);
989 query_fw.fw_type = AMDGPU_INFO_FW_UVD;
990 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
993 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
994 fw_info.feature, fw_info.ver);
997 query_fw.fw_type = AMDGPU_INFO_FW_GMC;
998 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1001 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1002 fw_info.feature, fw_info.ver);
1005 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1006 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1009 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1010 fw_info.feature, fw_info.ver);
1013 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1014 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1017 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1018 fw_info.feature, fw_info.ver);
1021 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1022 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1025 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1026 fw_info.feature, fw_info.ver);
1029 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1030 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1033 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1034 fw_info.feature, fw_info.ver);
1037 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1039 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1042 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1043 fw_info.feature, fw_info.ver);
1046 if (adev->asic_type == CHIP_KAVERI ||
1047 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
1049 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1052 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1053 fw_info.feature, fw_info.ver);
1057 query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1058 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1061 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1062 fw_info.feature, fw_info.ver);
1066 query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1067 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1070 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1071 fw_info.feature, fw_info.ver);
1074 query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1075 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1078 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1079 fw_info.feature, fw_info.ver);
1082 query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1083 for (i = 0; i < adev->sdma.num_instances; i++) {
1085 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1088 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1089 i, fw_info.feature, fw_info.ver);
1095 static const struct drm_info_list amdgpu_firmware_info_list[] = {
1096 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1100 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1102 #if defined(CONFIG_DEBUG_FS)
1103 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1104 ARRAY_SIZE(amdgpu_firmware_info_list));