drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include "amdgpu.h"
  30 #include <drm/drm_debugfs.h>
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu_sched.h"
  33 #include "amdgpu_uvd.h"
  34 #include "amdgpu_vce.h"
  35 #include "atom.h"
  36
  37 #include <linux/vga_switcheroo.h>
  38 #include <linux/slab.h>
  39 #include <linux/uaccess.h>
  40 #include <linux/pci.h>
  41 #include <linux/pm_runtime.h>
  42 #include "amdgpu_amdkfd.h"
  43 #include "amdgpu_gem.h"
  44 #include "amdgpu_display.h"
  45 #include "amdgpu_ras.h"
  46
  47 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
  48 {
  49         struct amdgpu_gpu_instance *gpu_instance;
  50         int i;
  51
  52         mutex_lock(&mgpu_info.mutex);
  53
  54         for (i = 0; i < mgpu_info.num_gpu; i++) {
  55                 gpu_instance = &(mgpu_info.gpu_ins[i]);
  56                 if (gpu_instance->adev == adev) {
  57                         mgpu_info.gpu_ins[i] =
  58                                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
  59                         mgpu_info.num_gpu--;
  60                         if (adev->flags & AMD_IS_APU)
  61                                 mgpu_info.num_apu--;
  62                         else
  63                                 mgpu_info.num_dgpu--;
  64                         break;
  65                 }
  66         }
  67
  68         mutex_unlock(&mgpu_info.mutex);
  69 }
  70
  71 /**
  72  * amdgpu_driver_unload_kms - Main unload function for KMS.
  73  *
  74  * @dev: drm dev pointer
  75  *
  76  * This is the main unload function for KMS (all asics).
  77  * Returns 0 on success.
  78  */
  79 void amdgpu_driver_unload_kms(struct drm_device *dev)
  80 {
  81         struct amdgpu_device *adev = dev->dev_private;
  82
  83         if (adev == NULL)
  84                 return;
  85
  86         amdgpu_unregister_gpu_instance(adev);
  87
  88         if (adev->rmmio == NULL)
  89                 goto done_free;
  90
  91         if (amdgpu_sriov_vf(adev))
  92                 amdgpu_virt_request_full_gpu(adev, false);
  93
  94         if (amdgpu_device_is_px(dev)) {
  95                 pm_runtime_get_sync(dev->dev);
  96                 pm_runtime_forbid(dev->dev);
  97         }
  98
  99         amdgpu_acpi_fini(adev);
 100
 101         amdgpu_device_fini(adev);
 102
 103 done_free:
 104         kfree(adev);
 105         dev->dev_private = NULL;
 106 }
 107
 108 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
 109 {
 110         struct amdgpu_gpu_instance *gpu_instance;
 111
 112         mutex_lock(&mgpu_info.mutex);
 113
 114         if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
 115                 DRM_ERROR("Cannot register more gpu instance\n");
 116                 mutex_unlock(&mgpu_info.mutex);
 117                 return;
 118         }
 119
 120         gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
 121         gpu_instance->adev = adev;
 122         gpu_instance->mgpu_fan_enabled = 0;
 123
 124         mgpu_info.num_gpu++;
 125         if (adev->flags & AMD_IS_APU)
 126                 mgpu_info.num_apu++;
 127         else
 128                 mgpu_info.num_dgpu++;
 129
 130         mutex_unlock(&mgpu_info.mutex);
 131 }
 132
 133 /**
 134  * amdgpu_driver_load_kms - Main load function for KMS.
 135  *
 136  * @dev: drm dev pointer
 137  * @flags: device flags
 138  *
 139  * This is the main load function for KMS (all asics).
 140  * Returns 0 on success, error on failure.
 141  */
 142 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
 143 {
 144         struct amdgpu_device *adev;
 145         int r, acpi_status;
 146
 147 #ifdef CONFIG_DRM_AMDGPU_SI
 148         if (!amdgpu_si_support) {
 149                 switch (flags & AMD_ASIC_MASK) {
 150                 case CHIP_TAHITI:
 151                 case CHIP_PITCAIRN:
 152                 case CHIP_VERDE:
 153                 case CHIP_OLAND:
 154                 case CHIP_HAINAN:
 155                         dev_info(dev->dev,
 156                                  "SI support provided by radeon.\n");
 157                         dev_info(dev->dev,
 158                                  "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
 159                                 );
 160                         return -ENODEV;
 161                 }
 162         }
 163 #endif
 164 #ifdef CONFIG_DRM_AMDGPU_CIK
 165         if (!amdgpu_cik_support) {
 166                 switch (flags & AMD_ASIC_MASK) {
 167                 case CHIP_KAVERI:
 168                 case CHIP_BONAIRE:
 169                 case CHIP_HAWAII:
 170                 case CHIP_KABINI:
 171                 case CHIP_MULLINS:
 172                         dev_info(dev->dev,
 173                                  "CIK support provided by radeon.\n");
 174                         dev_info(dev->dev,
 175                                  "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
 176                                 );
 177                         return -ENODEV;
 178                 }
 179         }
 180 #endif
 181
 182         adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
 183         if (adev == NULL) {
 184                 return -ENOMEM;
 185         }
 186         dev->dev_private = (void *)adev;
 187
 188         if ((amdgpu_runtime_pm != 0) &&
 189             amdgpu_has_atpx() &&
 190             (amdgpu_is_atpx_hybrid() ||
 191              amdgpu_has_atpx_dgpu_power_cntl()) &&
 192             ((flags & AMD_IS_APU) == 0) &&
 193             !pci_is_thunderbolt_attached(dev->pdev))
 194                 flags |= AMD_IS_PX;
 195
 196         /* amdgpu_device_init should report only fatal error
 197          * like memory allocation failure or iomapping failure,
 198          * or memory manager initialization failure, it must
 199          * properly initialize the GPU MC controller and permit
 200          * VRAM allocation
 201          */
 202         r = amdgpu_device_init(adev, dev, dev->pdev, flags);
 203         if (r) {
 204                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 205                 goto out;
 206         }
 207
 208         /* Call ACPI methods: require modeset init
 209          * but failure is not fatal
 210          */
 211         if (!r) {
 212                 acpi_status = amdgpu_acpi_init(adev);
 213                 if (acpi_status)
 214                         dev_dbg(&dev->pdev->dev,
 215                                 "Error during ACPI methods call\n");
 216         }
 217
 218         if (amdgpu_device_is_px(dev)) {
 219                 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP);
 220                 pm_runtime_use_autosuspend(dev->dev);
 221                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 222                 pm_runtime_set_active(dev->dev);
 223                 pm_runtime_allow(dev->dev);
 224                 pm_runtime_mark_last_busy(dev->dev);
 225                 pm_runtime_put_autosuspend(dev->dev);
 226         }
 227
 228         amdgpu_register_gpu_instance(adev);
 229 out:
 230         if (r) {
 231                 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
 232                 if (adev->rmmio && amdgpu_device_is_px(dev))
 233                         pm_runtime_put_noidle(dev->dev);
 234                 amdgpu_driver_unload_kms(dev);
 235         }
 236
 237         return r;
 238 }
 239
 240 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 241                                 struct drm_amdgpu_query_fw *query_fw,
 242                                 struct amdgpu_device *adev)
 243 {
 244         switch (query_fw->fw_type) {
 245         case AMDGPU_INFO_FW_VCE:
 246                 fw_info->ver = adev->vce.fw_version;
 247                 fw_info->feature = adev->vce.fb_version;
 248                 break;
 249         case AMDGPU_INFO_FW_UVD:
 250                 fw_info->ver = adev->uvd.fw_version;
 251                 fw_info->feature = 0;
 252                 break;
 253         case AMDGPU_INFO_FW_VCN:
 254                 fw_info->ver = adev->vcn.fw_version;
 255                 fw_info->feature = 0;
 256                 break;
 257         case AMDGPU_INFO_FW_GMC:
 258                 fw_info->ver = adev->gmc.fw_version;
 259                 fw_info->feature = 0;
 260                 break;
 261         case AMDGPU_INFO_FW_GFX_ME:
 262                 fw_info->ver = adev->gfx.me_fw_version;
 263                 fw_info->feature = adev->gfx.me_feature_version;
 264                 break;
 265         case AMDGPU_INFO_FW_GFX_PFP:
 266                 fw_info->ver = adev->gfx.pfp_fw_version;
 267                 fw_info->feature = adev->gfx.pfp_feature_version;
 268                 break;
 269         case AMDGPU_INFO_FW_GFX_CE:
 270                 fw_info->ver = adev->gfx.ce_fw_version;
 271                 fw_info->feature = adev->gfx.ce_feature_version;
 272                 break;
 273         case AMDGPU_INFO_FW_GFX_RLC:
 274                 fw_info->ver = adev->gfx.rlc_fw_version;
 275                 fw_info->feature = adev->gfx.rlc_feature_version;
 276                 break;
 277         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 278                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 279                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 280                 break;
 281         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 282                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 283                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 284                 break;
 285         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 286                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 287                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 288                 break;
 289         case AMDGPU_INFO_FW_GFX_MEC:
 290                 if (query_fw->index == 0) {
 291                         fw_info->ver = adev->gfx.mec_fw_version;
 292                         fw_info->feature = adev->gfx.mec_feature_version;
 293                 } else if (query_fw->index == 1) {
 294                         fw_info->ver = adev->gfx.mec2_fw_version;
 295                         fw_info->feature = adev->gfx.mec2_feature_version;
 296                 } else
 297                         return -EINVAL;
 298                 break;
 299         case AMDGPU_INFO_FW_SMC:
 300                 fw_info->ver = adev->pm.fw_version;
 301                 fw_info->feature = 0;
 302                 break;
 303         case AMDGPU_INFO_FW_TA:
 304                 if (query_fw->index > 1)
 305                         return -EINVAL;
 306                 if (query_fw->index == 0) {
 307                         fw_info->ver = adev->psp.ta_fw_version;
 308                         fw_info->feature = adev->psp.ta_xgmi_ucode_version;
 309                 } else {
 310                         fw_info->ver = adev->psp.ta_fw_version;
 311                         fw_info->feature = adev->psp.ta_ras_ucode_version;
 312                 }
 313                 break;
 314         case AMDGPU_INFO_FW_SDMA:
 315                 if (query_fw->index >= adev->sdma.num_instances)
 316                         return -EINVAL;
 317                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 318                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 319                 break;
 320         case AMDGPU_INFO_FW_SOS:
 321                 fw_info->ver = adev->psp.sos_fw_version;
 322                 fw_info->feature = adev->psp.sos_feature_version;
 323                 break;
 324         case AMDGPU_INFO_FW_ASD:
 325                 fw_info->ver = adev->psp.asd_fw_version;
 326                 fw_info->feature = adev->psp.asd_feature_version;
 327                 break;
 328         case AMDGPU_INFO_FW_DMCU:
 329                 fw_info->ver = adev->dm.dmcu_fw_version;
 330                 fw_info->feature = 0;
 331                 break;
 332         default:
 333                 return -EINVAL;
 334         }
 335         return 0;
 336 }
 337
 338 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 339                              struct drm_amdgpu_info *info,
 340                              struct drm_amdgpu_info_hw_ip *result)
 341 {
 342         uint32_t ib_start_alignment = 0;
 343         uint32_t ib_size_alignment = 0;
 344         enum amd_ip_block_type type;
 345         unsigned int num_rings = 0;
 346         unsigned int i, j;
 347
 348         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 349                 return -EINVAL;
 350
 351         switch (info->query_hw_ip.type) {
 352         case AMDGPU_HW_IP_GFX:
 353                 type = AMD_IP_BLOCK_TYPE_GFX;
 354                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 355                         if (adev->gfx.gfx_ring[i].sched.ready)
 356                                 ++num_rings;
 357                 ib_start_alignment = 32;
 358                 ib_size_alignment = 32;
 359                 break;
 360         case AMDGPU_HW_IP_COMPUTE:
 361                 type = AMD_IP_BLOCK_TYPE_GFX;
 362                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 363                         if (adev->gfx.compute_ring[i].sched.ready)
 364                                 ++num_rings;
 365                 ib_start_alignment = 32;
 366                 ib_size_alignment = 32;
 367                 break;
 368         case AMDGPU_HW_IP_DMA:
 369                 type = AMD_IP_BLOCK_TYPE_SDMA;
 370                 for (i = 0; i < adev->sdma.num_instances; i++)
 371                         if (adev->sdma.instance[i].ring.sched.ready)
 372                                 ++num_rings;
 373                 ib_start_alignment = 256;
 374                 ib_size_alignment = 4;
 375                 break;
 376         case AMDGPU_HW_IP_UVD:
 377                 type = AMD_IP_BLOCK_TYPE_UVD;
 378                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 379                         if (adev->uvd.harvest_config & (1 << i))
 380                                 continue;
 381
 382                         if (adev->uvd.inst[i].ring.sched.ready)
 383                                 ++num_rings;
 384                 }
 385                 ib_start_alignment = 64;
 386                 ib_size_alignment = 64;
 387                 break;
 388         case AMDGPU_HW_IP_VCE:
 389                 type = AMD_IP_BLOCK_TYPE_VCE;
 390                 for (i = 0; i < adev->vce.num_rings; i++)
 391                         if (adev->vce.ring[i].sched.ready)
 392                                 ++num_rings;
 393                 ib_start_alignment = 4;
 394                 ib_size_alignment = 1;
 395                 break;
 396         case AMDGPU_HW_IP_UVD_ENC:
 397                 type = AMD_IP_BLOCK_TYPE_UVD;
 398                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 399                         if (adev->uvd.harvest_config & (1 << i))
 400                                 continue;
 401
 402                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 403                                 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
 404                                         ++num_rings;
 405                 }
 406                 ib_start_alignment = 64;
 407                 ib_size_alignment = 64;
 408                 break;
 409         case AMDGPU_HW_IP_VCN_DEC:
 410                 type = AMD_IP_BLOCK_TYPE_VCN;
 411                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 412                         if (adev->uvd.harvest_config & (1 << i))
 413                                 continue;
 414
 415                         if (adev->vcn.inst[i].ring_dec.sched.ready)
 416                                 ++num_rings;
 417                 }
 418                 ib_start_alignment = 16;
 419                 ib_size_alignment = 16;
 420                 break;
 421         case AMDGPU_HW_IP_VCN_ENC:
 422                 type = AMD_IP_BLOCK_TYPE_VCN;
 423                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 424                         if (adev->uvd.harvest_config & (1 << i))
 425                                 continue;
 426
 427                         for (j = 0; j < adev->vcn.num_enc_rings; j++)
 428                                 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
 429                                         ++num_rings;
 430                 }
 431                 ib_start_alignment = 64;
 432                 ib_size_alignment = 1;
 433                 break;
 434         case AMDGPU_HW_IP_VCN_JPEG:
 435                 type = AMD_IP_BLOCK_TYPE_VCN;
 436                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 437                         if (adev->uvd.harvest_config & (1 << i))
 438                                 continue;
 439
 440                         if (adev->vcn.inst[i].ring_jpeg.sched.ready)
 441                                 ++num_rings;
 442                 }
 443                 ib_start_alignment = 16;
 444                 ib_size_alignment = 16;
 445                 break;
 446         default:
 447                 return -EINVAL;
 448         }
 449
 450         for (i = 0; i < adev->num_ip_blocks; i++)
 451                 if (adev->ip_blocks[i].version->type == type &&
 452                     adev->ip_blocks[i].status.valid)
 453                         break;
 454
 455         if (i == adev->num_ip_blocks)
 456                 return 0;
 457
 458         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 459                         num_rings);
 460
 461         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 462         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 463         result->capabilities_flags = 0;
 464         result->available_rings = (1 << num_rings) - 1;
 465         result->ib_start_alignment = ib_start_alignment;
 466         result->ib_size_alignment = ib_size_alignment;
 467         return 0;
 468 }
 469
 470 /*
 471  * Userspace get information ioctl
 472  */
 473 /**
 474  * amdgpu_info_ioctl - answer a device specific request.
 475  *
 476  * @adev: amdgpu device pointer
 477  * @data: request object
 478  * @filp: drm filp
 479  *
 480  * This function is used to pass device specific parameters to the userspace
 481  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 482  * etc. (all asics).
 483  * Returns 0 on success, -EINVAL on failure.
 484  */
 485 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 486 {
 487         struct amdgpu_device *adev = dev->dev_private;
 488         struct drm_amdgpu_info *info = data;
 489         struct amdgpu_mode_info *minfo = &adev->mode_info;
 490         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 491         uint32_t size = info->return_size;
 492         struct drm_crtc *crtc;
 493         uint32_t ui32 = 0;
 494         uint64_t ui64 = 0;
 495         int i, found;
 496         int ui32_size = sizeof(ui32);
 497
 498         if (!info->return_size || !info->return_pointer)
 499                 return -EINVAL;
 500
 501         switch (info->query) {
 502         case AMDGPU_INFO_ACCEL_WORKING:
 503                 ui32 = adev->accel_working;
 504                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 505         case AMDGPU_INFO_CRTC_FROM_ID:
 506                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 507                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 508                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 509                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 510                                 ui32 = amdgpu_crtc->crtc_id;
 511                                 found = 1;
 512                                 break;
 513                         }
 514                 }
 515                 if (!found) {
 516                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 517                         return -EINVAL;
 518                 }
 519                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 520         case AMDGPU_INFO_HW_IP_INFO: {
 521                 struct drm_amdgpu_info_hw_ip ip = {};
 522                 int ret;
 523
 524                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 525                 if (ret)
 526                         return ret;
 527
 528                 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
 529                 return ret ? -EFAULT : 0;
 530         }
 531         case AMDGPU_INFO_HW_IP_COUNT: {
 532                 enum amd_ip_block_type type;
 533                 uint32_t count = 0;
 534
 535                 switch (info->query_hw_ip.type) {
 536                 case AMDGPU_HW_IP_GFX:
 537                         type = AMD_IP_BLOCK_TYPE_GFX;
 538                         break;
 539                 case AMDGPU_HW_IP_COMPUTE:
 540                         type = AMD_IP_BLOCK_TYPE_GFX;
 541                         break;
 542                 case AMDGPU_HW_IP_DMA:
 543                         type = AMD_IP_BLOCK_TYPE_SDMA;
 544                         break;
 545                 case AMDGPU_HW_IP_UVD:
 546                         type = AMD_IP_BLOCK_TYPE_UVD;
 547                         break;
 548                 case AMDGPU_HW_IP_VCE:
 549                         type = AMD_IP_BLOCK_TYPE_VCE;
 550                         break;
 551                 case AMDGPU_HW_IP_UVD_ENC:
 552                         type = AMD_IP_BLOCK_TYPE_UVD;
 553                         break;
 554                 case AMDGPU_HW_IP_VCN_DEC:
 555                 case AMDGPU_HW_IP_VCN_ENC:
 556                 case AMDGPU_HW_IP_VCN_JPEG:
 557                         type = AMD_IP_BLOCK_TYPE_VCN;
 558                         break;
 559                 default:
 560                         return -EINVAL;
 561                 }
 562
 563                 for (i = 0; i < adev->num_ip_blocks; i++)
 564                         if (adev->ip_blocks[i].version->type == type &&
 565                             adev->ip_blocks[i].status.valid &&
 566                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 567                                 count++;
 568
 569                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 570         }
 571         case AMDGPU_INFO_TIMESTAMP:
 572                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 573                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 574         case AMDGPU_INFO_FW_VERSION: {
 575                 struct drm_amdgpu_info_firmware fw_info;
 576                 int ret;
 577
 578                 /* We only support one instance of each IP block right now. */
 579                 if (info->query_fw.ip_instance != 0)
 580                         return -EINVAL;
 581
 582                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 583                 if (ret)
 584                         return ret;
 585
 586                 return copy_to_user(out, &fw_info,
 587                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 588         }
 589         case AMDGPU_INFO_NUM_BYTES_MOVED:
 590                 ui64 = atomic64_read(&adev->num_bytes_moved);
 591                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 592         case AMDGPU_INFO_NUM_EVICTIONS:
 593                 ui64 = atomic64_read(&adev->num_evictions);
 594                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 595         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 596                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 597                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 598         case AMDGPU_INFO_VRAM_USAGE:
 599                 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 600                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 601         case AMDGPU_INFO_VIS_VRAM_USAGE:
 602                 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 603                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 604         case AMDGPU_INFO_GTT_USAGE:
 605                 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
 606                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 607         case AMDGPU_INFO_GDS_CONFIG: {
 608                 struct drm_amdgpu_info_gds gds_info;
 609
 610                 memset(&gds_info, 0, sizeof(gds_info));
 611                 gds_info.compute_partition_size = adev->gds.gds_size;
 612                 gds_info.gds_total_size = adev->gds.gds_size;
 613                 gds_info.gws_per_compute_partition = adev->gds.gws_size;
 614                 gds_info.oa_per_compute_partition = adev->gds.oa_size;
 615                 return copy_to_user(out, &gds_info,
 616                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 617         }
 618         case AMDGPU_INFO_VRAM_GTT: {
 619                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 620
 621                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 622                         atomic64_read(&adev->vram_pin_size);
 623                 vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size -
 624                         atomic64_read(&adev->visible_pin_size);
 625                 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
 626                 vram_gtt.gtt_size *= PAGE_SIZE;
 627                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 628                 return copy_to_user(out, &vram_gtt,
 629                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 630         }
 631         case AMDGPU_INFO_MEMORY: {
 632                 struct drm_amdgpu_memory_info mem;
 633
 634                 memset(&mem, 0, sizeof(mem));
 635                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 636                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 637                         atomic64_read(&adev->vram_pin_size);
 638                 mem.vram.heap_usage =
 639                         amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 640                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 641
 642                 mem.cpu_accessible_vram.total_heap_size =
 643                         adev->gmc.visible_vram_size;
 644                 mem.cpu_accessible_vram.usable_heap_size = adev->gmc.visible_vram_size -
 645                         atomic64_read(&adev->visible_pin_size);
 646                 mem.cpu_accessible_vram.heap_usage =
 647                         amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 648                 mem.cpu_accessible_vram.max_allocation =
 649                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 650
 651                 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size;
 652                 mem.gtt.total_heap_size *= PAGE_SIZE;
 653                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 654                         atomic64_read(&adev->gart_pin_size);
 655                 mem.gtt.heap_usage =
 656                         amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
 657                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 658
 659                 return copy_to_user(out, &mem,
 660                                     min((size_t)size, sizeof(mem)))
 661                                     ? -EFAULT : 0;
 662         }
 663         case AMDGPU_INFO_READ_MMR_REG: {
 664                 unsigned n, alloc_size;
 665                 uint32_t *regs;
 666                 unsigned se_num = (info->read_mmr_reg.instance >>
 667                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 668                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 669                 unsigned sh_num = (info->read_mmr_reg.instance >>
 670                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 671                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 672
 673                 /* set full masks if the userspace set all bits
 674                  * in the bitfields */
 675                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 676                         se_num = 0xffffffff;
 677                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 678                         sh_num = 0xffffffff;
 679
 680                 if (info->read_mmr_reg.count > 128)
 681                         return -EINVAL;
 682
 683                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 684                 if (!regs)
 685                         return -ENOMEM;
 686                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 687
 688                 for (i = 0; i < info->read_mmr_reg.count; i++)
 689                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 690                                                       info->read_mmr_reg.dword_offset + i,
 691                                                       &regs[i])) {
 692                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 693                                               info->read_mmr_reg.dword_offset + i);
 694                                 kfree(regs);
 695                                 return -EFAULT;
 696                         }
 697                 n = copy_to_user(out, regs, min(size, alloc_size));
 698                 kfree(regs);
 699                 return n ? -EFAULT : 0;
 700         }
 701         case AMDGPU_INFO_DEV_INFO: {
 702                 struct drm_amdgpu_info_device dev_info = {};
 703                 uint64_t vm_size;
 704
 705                 dev_info.device_id = dev->pdev->device;
 706                 dev_info.chip_rev = adev->rev_id;
 707                 dev_info.external_rev = adev->external_rev_id;
 708                 dev_info.pci_rev = dev->pdev->revision;
 709                 dev_info.family = adev->family;
 710                 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
 711                 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 712                 /* return all clocks in KHz */
 713                 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 714                 if (adev->pm.dpm_enabled) {
 715                         dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 716                         dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 717                 } else if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
 718                            adev->virt.ops->get_pp_clk) {
 719                         dev_info.max_engine_clock = amdgpu_virt_get_sclk(adev, false) * 10;
 720                         dev_info.max_memory_clock = amdgpu_virt_get_mclk(adev, false) * 10;
 721                 } else {
 722                         dev_info.max_engine_clock = adev->clock.default_sclk * 10;
 723                         dev_info.max_memory_clock = adev->clock.default_mclk * 10;
 724                 }
 725                 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 726                 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
 727                         adev->gfx.config.max_shader_engines;
 728                 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 729                 dev_info._pad = 0;
 730                 dev_info.ids_flags = 0;
 731                 if (adev->flags & AMD_IS_APU)
 732                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 733                 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
 734                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 735
 736                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 737                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 738
 739                 /* Older VCE FW versions are buggy and can handle only 40bits */
 740                 if (adev->vce.fw_version &&
 741                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 742                         vm_size = min(vm_size, 1ULL << 40);
 743
 744                 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 745                 dev_info.virtual_address_max =
 746                         min(vm_size, AMDGPU_GMC_HOLE_START);
 747
 748                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 749                         dev_info.high_va_offset = AMDGPU_GMC_HOLE_END;
 750                         dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 751                 }
 752                 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 753                 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 754                 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
 755                 dev_info.cu_active_number = adev->gfx.cu_info.number;
 756                 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 757                 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
 758                 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 759                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 760                 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 761                        sizeof(adev->gfx.cu_info.bitmap));
 762                 dev_info.vram_type = adev->gmc.vram_type;
 763                 dev_info.vram_bit_width = adev->gmc.vram_width;
 764                 dev_info.vce_harvest_config = adev->vce.harvest_config;
 765                 dev_info.gc_double_offchip_lds_buf =
 766                         adev->gfx.config.double_offchip_lds_buf;
 767
 768                 if (amdgpu_ngg) {
 769                         dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;
 770                         dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;
 771                         dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;
 772                         dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;
 773                         dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;
 774                         dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;
 775                         dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;
 776                         dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;
 777                 }
 778                 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
 779                 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 780                 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 781                 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 782                 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 783                 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 784                 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 785
 786                 if (adev->family >= AMDGPU_FAMILY_NV)
 787                         dev_info.pa_sc_tile_steering_override =
 788                                 adev->gfx.config.pa_sc_tile_steering_override;
 789
 790                 dev_info.tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
 791
 792                 return copy_to_user(out, &dev_info,
 793                                     min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
 794         }
 795         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 796                 unsigned i;
 797                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 798                 struct amd_vce_state *vce_state;
 799
 800                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 801                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 802                         if (vce_state) {
 803                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 804                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 805                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 806                                 vce_clk_table.num_valid_entries++;
 807                         }
 808                 }
 809
 810                 return copy_to_user(out, &vce_clk_table,
 811                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 812         }
 813         case AMDGPU_INFO_VBIOS: {
 814                 uint32_t bios_size = adev->bios_size;
 815
 816                 switch (info->vbios_info.type) {
 817                 case AMDGPU_INFO_VBIOS_SIZE:
 818                         return copy_to_user(out, &bios_size,
 819                                         min((size_t)size, sizeof(bios_size)))
 820                                         ? -EFAULT : 0;
 821                 case AMDGPU_INFO_VBIOS_IMAGE: {
 822                         uint8_t *bios;
 823                         uint32_t bios_offset = info->vbios_info.offset;
 824
 825                         if (bios_offset >= bios_size)
 826                                 return -EINVAL;
 827
 828                         bios = adev->bios + bios_offset;
 829                         return copy_to_user(out, bios,
 830                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 831                                         ? -EFAULT : 0;
 832                 }
 833                 default:
 834                         DRM_DEBUG_KMS("Invalid request %d\n",
 835                                         info->vbios_info.type);
 836                         return -EINVAL;
 837                 }
 838         }
 839         case AMDGPU_INFO_NUM_HANDLES: {
 840                 struct drm_amdgpu_info_num_handles handle;
 841
 842                 switch (info->query_hw_ip.type) {
 843                 case AMDGPU_HW_IP_UVD:
 844                         /* Starting Polaris, we support unlimited UVD handles */
 845                         if (adev->asic_type < CHIP_POLARIS10) {
 846                                 handle.uvd_max_handles = adev->uvd.max_handles;
 847                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 848
 849                                 return copy_to_user(out, &handle,
 850                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 851                         } else {
 852                                 return -ENODATA;
 853                         }
 854
 855                         break;
 856                 default:
 857                         return -EINVAL;
 858                 }
 859         }
 860         case AMDGPU_INFO_SENSOR: {
 861                 if (!adev->pm.dpm_enabled)
 862                         return -ENOENT;
 863
 864                 switch (info->sensor_info.type) {
 865                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 866                         /* get sclk in Mhz */
 867                         if (amdgpu_dpm_read_sensor(adev,
 868                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 869                                                    (void *)&ui32, &ui32_size)) {
 870                                 return -EINVAL;
 871                         }
 872                         ui32 /= 100;
 873                         break;
 874                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 875                         /* get mclk in Mhz */
 876                         if (amdgpu_dpm_read_sensor(adev,
 877                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 878                                                    (void *)&ui32, &ui32_size)) {
 879                                 return -EINVAL;
 880                         }
 881                         ui32 /= 100;
 882                         break;
 883                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 884                         /* get temperature in millidegrees C */
 885                         if (amdgpu_dpm_read_sensor(adev,
 886                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 887                                                    (void *)&ui32, &ui32_size)) {
 888                                 return -EINVAL;
 889                         }
 890                         break;
 891                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 892                         /* get GPU load */
 893                         if (amdgpu_dpm_read_sensor(adev,
 894                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 895                                                    (void *)&ui32, &ui32_size)) {
 896                                 return -EINVAL;
 897                         }
 898                         break;
 899                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 900                         /* get average GPU power */
 901                         if (amdgpu_dpm_read_sensor(adev,
 902                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 903                                                    (void *)&ui32, &ui32_size)) {
 904                                 return -EINVAL;
 905                         }
 906                         ui32 >>= 8;
 907                         break;
 908                 case AMDGPU_INFO_SENSOR_VDDNB:
 909                         /* get VDDNB in millivolts */
 910                         if (amdgpu_dpm_read_sensor(adev,
 911                                                    AMDGPU_PP_SENSOR_VDDNB,
 912                                                    (void *)&ui32, &ui32_size)) {
 913                                 return -EINVAL;
 914                         }
 915                         break;
 916                 case AMDGPU_INFO_SENSOR_VDDGFX:
 917                         /* get VDDGFX in millivolts */
 918                         if (amdgpu_dpm_read_sensor(adev,
 919                                                    AMDGPU_PP_SENSOR_VDDGFX,
 920                                                    (void *)&ui32, &ui32_size)) {
 921                                 return -EINVAL;
 922                         }
 923                         break;
 924                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 925                         /* get stable pstate sclk in Mhz */
 926                         if (amdgpu_dpm_read_sensor(adev,
 927                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 928                                                    (void *)&ui32, &ui32_size)) {
 929                                 return -EINVAL;
 930                         }
 931                         ui32 /= 100;
 932                         break;
 933                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
 934                         /* get stable pstate mclk in Mhz */
 935                         if (amdgpu_dpm_read_sensor(adev,
 936                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 937                                                    (void *)&ui32, &ui32_size)) {
 938                                 return -EINVAL;
 939                         }
 940                         ui32 /= 100;
 941                         break;
 942                 default:
 943                         DRM_DEBUG_KMS("Invalid request %d\n",
 944                                       info->sensor_info.type);
 945                         return -EINVAL;
 946                 }
 947                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 948         }
 949         case AMDGPU_INFO_VRAM_LOST_COUNTER:
 950                 ui32 = atomic_read(&adev->vram_lost_counter);
 951                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 952         case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
 953                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 954                 uint64_t ras_mask;
 955
 956                 if (!ras)
 957                         return -EINVAL;
 958                 ras_mask = (uint64_t)ras->supported << 32 | ras->features;
 959
 960                 return copy_to_user(out, &ras_mask,
 961                                 min_t(u64, size, sizeof(ras_mask))) ?
 962                         -EFAULT : 0;
 963         }
 964         default:
 965                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
 966                 return -EINVAL;
 967         }
 968         return 0;
 969 }
 970
 971
 972 /*
 973  * Outdated mess for old drm with Xorg being in charge (void function now).
 974  */
 975 /**
 976  * amdgpu_driver_lastclose_kms - drm callback for last close
 977  *
 978  * @dev: drm dev pointer
 979  *
 980  * Switch vga_switcheroo state after last close (all asics).
 981  */
 982 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
 983 {
 984         drm_fb_helper_lastclose(dev);
 985         vga_switcheroo_process_delayed_switch();
 986 }
 987
 988 /**
 989  * amdgpu_driver_open_kms - drm callback for open
 990  *
 991  * @dev: drm dev pointer
 992  * @file_priv: drm file
 993  *
 994  * On device open, init vm on cayman+ (all asics).
 995  * Returns 0 on success, error on failure.
 996  */
 997 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 998 {
 999         struct amdgpu_device *adev = dev->dev_private;
1000         struct amdgpu_fpriv *fpriv;
1001         int r, pasid;
1002
1003         /* Ensure IB tests are run on ring */
1004         flush_delayed_work(&adev->delayed_init_work);
1005
1006         file_priv->driver_priv = NULL;
1007
1008         r = pm_runtime_get_sync(dev->dev);
1009         if (r < 0)
1010                 return r;
1011
1012         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1013         if (unlikely(!fpriv)) {
1014                 r = -ENOMEM;
1015                 goto out_suspend;
1016         }
1017
1018         pasid = amdgpu_pasid_alloc(16);
1019         if (pasid < 0) {
1020                 dev_warn(adev->dev, "No more PASIDs available!");
1021                 pasid = 0;
1022         }
1023         r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
1024         if (r)
1025                 goto error_pasid;
1026
1027         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1028         if (!fpriv->prt_va) {
1029                 r = -ENOMEM;
1030                 goto error_vm;
1031         }
1032
1033         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1034                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1035
1036                 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1037                                                 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1038                 if (r)
1039                         goto error_vm;
1040         }
1041
1042         mutex_init(&fpriv->bo_list_lock);
1043         idr_init(&fpriv->bo_list_handles);
1044
1045         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
1046
1047         file_priv->driver_priv = fpriv;
1048         goto out_suspend;
1049
1050 error_vm:
1051         amdgpu_vm_fini(adev, &fpriv->vm);
1052
1053 error_pasid:
1054         if (pasid)
1055                 amdgpu_pasid_free(pasid);
1056
1057         kfree(fpriv);
1058
1059 out_suspend:
1060         pm_runtime_mark_last_busy(dev->dev);
1061         pm_runtime_put_autosuspend(dev->dev);
1062
1063         return r;
1064 }
1065
1066 /**
1067  * amdgpu_driver_postclose_kms - drm callback for post close
1068  *
1069  * @dev: drm dev pointer
1070  * @file_priv: drm file
1071  *
1072  * On device post close, tear down vm on cayman+ (all asics).
1073  */
1074 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1075                                  struct drm_file *file_priv)
1076 {
1077         struct amdgpu_device *adev = dev->dev_private;
1078         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1079         struct amdgpu_bo_list *list;
1080         struct amdgpu_bo *pd;
1081         unsigned int pasid;
1082         int handle;
1083
1084         if (!fpriv)
1085                 return;
1086
1087         pm_runtime_get_sync(dev->dev);
1088
1089         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1090                 amdgpu_uvd_free_handles(adev, file_priv);
1091         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1092                 amdgpu_vce_free_handles(adev, file_priv);
1093
1094         amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
1095
1096         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1097                 /* TODO: how to handle reserve failure */
1098                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1099                 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
1100                 fpriv->csa_va = NULL;
1101                 amdgpu_bo_unreserve(adev->virt.csa_obj);
1102         }
1103
1104         pasid = fpriv->vm.pasid;
1105         pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
1106
1107         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1108         amdgpu_vm_fini(adev, &fpriv->vm);
1109
1110         if (pasid)
1111                 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1112         amdgpu_bo_unref(&pd);
1113
1114         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1115                 amdgpu_bo_list_put(list);
1116
1117         idr_destroy(&fpriv->bo_list_handles);
1118         mutex_destroy(&fpriv->bo_list_lock);
1119
1120         kfree(fpriv);
1121         file_priv->driver_priv = NULL;
1122
1123         pm_runtime_mark_last_busy(dev->dev);
1124         pm_runtime_put_autosuspend(dev->dev);
1125 }
1126
1127 /*
1128  * VBlank related functions.
1129  */
1130 /**
1131  * amdgpu_get_vblank_counter_kms - get frame count
1132  *
1133  * @dev: drm dev pointer
1134  * @pipe: crtc to get the frame count from
1135  *
1136  * Gets the frame count on the requested crtc (all asics).
1137  * Returns frame count on success, -EINVAL on failure.
1138  */
1139 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
1140 {
1141         struct amdgpu_device *adev = dev->dev_private;
1142         int vpos, hpos, stat;
1143         u32 count;
1144
1145         if (pipe >= adev->mode_info.num_crtc) {
1146                 DRM_ERROR("Invalid crtc %u\n", pipe);
1147                 return -EINVAL;
1148         }
1149
1150         /* The hw increments its frame counter at start of vsync, not at start
1151          * of vblank, as is required by DRM core vblank counter handling.
1152          * Cook the hw count here to make it appear to the caller as if it
1153          * incremented at start of vblank. We measure distance to start of
1154          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1155          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1156          * result by 1 to give the proper appearance to caller.
1157          */
1158         if (adev->mode_info.crtcs[pipe]) {
1159                 /* Repeat readout if needed to provide stable result if
1160                  * we cross start of vsync during the queries.
1161                  */
1162                 do {
1163                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1164                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1165                          * vpos as distance to start of vblank, instead of
1166                          * regular vertical scanout pos.
1167                          */
1168                         stat = amdgpu_display_get_crtc_scanoutpos(
1169                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1170                                 &vpos, &hpos, NULL, NULL,
1171                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1172                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1173
1174                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1175                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1176                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1177                 } else {
1178                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1179                                       pipe, vpos);
1180
1181                         /* Bump counter if we are at >= leading edge of vblank,
1182                          * but before vsync where vpos would turn negative and
1183                          * the hw counter really increments.
1184                          */
1185                         if (vpos >= 0)
1186                                 count++;
1187                 }
1188         } else {
1189                 /* Fallback to use value as is. */
1190                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1191                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1192         }
1193
1194         return count;
1195 }
1196
1197 /**
1198  * amdgpu_enable_vblank_kms - enable vblank interrupt
1199  *
1200  * @dev: drm dev pointer
1201  * @pipe: crtc to enable vblank interrupt for
1202  *
1203  * Enable the interrupt on the requested crtc (all asics).
1204  * Returns 0 on success, -EINVAL on failure.
1205  */
1206 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1207 {
1208         struct amdgpu_device *adev = dev->dev_private;
1209         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1210
1211         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1212 }
1213
1214 /**
1215  * amdgpu_disable_vblank_kms - disable vblank interrupt
1216  *
1217  * @dev: drm dev pointer
1218  * @pipe: crtc to disable vblank interrupt for
1219  *
1220  * Disable the interrupt on the requested crtc (all asics).
1221  */
1222 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1223 {
1224         struct amdgpu_device *adev = dev->dev_private;
1225         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1226
1227         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1228 }
1229
1230 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
1231         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1232         DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1233         DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1234         DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
1235         DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1236         DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1237         /* KMS */
1238         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1239         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1240         DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1241         DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1242         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1243         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1244         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1245         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1246         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1247         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)
1248 };
1249 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
1250
1251 /*
1252  * Debugfs info
1253  */
1254 #if defined(CONFIG_DEBUG_FS)
1255
1256 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1257 {
1258         struct drm_info_node *node = (struct drm_info_node *) m->private;
1259         struct drm_device *dev = node->minor->dev;
1260         struct amdgpu_device *adev = dev->dev_private;
1261         struct drm_amdgpu_info_firmware fw_info;
1262         struct drm_amdgpu_query_fw query_fw;
1263         struct atom_context *ctx = adev->mode_info.atom_context;
1264         int ret, i;
1265
1266         /* VCE */
1267         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1268         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1269         if (ret)
1270                 return ret;
1271         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1272                    fw_info.feature, fw_info.ver);
1273
1274         /* UVD */
1275         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1276         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1277         if (ret)
1278                 return ret;
1279         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1280                    fw_info.feature, fw_info.ver);
1281
1282         /* GMC */
1283         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1284         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1285         if (ret)
1286                 return ret;
1287         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1288                    fw_info.feature, fw_info.ver);
1289
1290         /* ME */
1291         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1292         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1293         if (ret)
1294                 return ret;
1295         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1296                    fw_info.feature, fw_info.ver);
1297
1298         /* PFP */
1299         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1300         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1301         if (ret)
1302                 return ret;
1303         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1304                    fw_info.feature, fw_info.ver);
1305
1306         /* CE */
1307         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1308         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1309         if (ret)
1310                 return ret;
1311         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1312                    fw_info.feature, fw_info.ver);
1313
1314         /* RLC */
1315         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1316         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1317         if (ret)
1318                 return ret;
1319         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1320                    fw_info.feature, fw_info.ver);
1321
1322         /* RLC SAVE RESTORE LIST CNTL */
1323         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1324         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1325         if (ret)
1326                 return ret;
1327         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1328                    fw_info.feature, fw_info.ver);
1329
1330         /* RLC SAVE RESTORE LIST GPM MEM */
1331         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1332         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1333         if (ret)
1334                 return ret;
1335         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1336                    fw_info.feature, fw_info.ver);
1337
1338         /* RLC SAVE RESTORE LIST SRM MEM */
1339         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1340         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1341         if (ret)
1342                 return ret;
1343         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1344                    fw_info.feature, fw_info.ver);
1345
1346         /* MEC */
1347         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1348         query_fw.index = 0;
1349         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1350         if (ret)
1351                 return ret;
1352         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1353                    fw_info.feature, fw_info.ver);
1354
1355         /* MEC2 */
1356         if (adev->asic_type == CHIP_KAVERI ||
1357             (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
1358                 query_fw.index = 1;
1359                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1360                 if (ret)
1361                         return ret;
1362                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1363                            fw_info.feature, fw_info.ver);
1364         }
1365
1366         /* PSP SOS */
1367         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1368         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1369         if (ret)
1370                 return ret;
1371         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1372                    fw_info.feature, fw_info.ver);
1373
1374
1375         /* PSP ASD */
1376         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1377         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1378         if (ret)
1379                 return ret;
1380         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1381                    fw_info.feature, fw_info.ver);
1382
1383         query_fw.fw_type = AMDGPU_INFO_FW_TA;
1384         for (i = 0; i < 2; i++) {
1385                 query_fw.index = i;
1386                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1387                 if (ret)
1388                         continue;
1389                 seq_printf(m, "TA %s feature version: %u, firmware version: 0x%08x\n",
1390                                 i ? "RAS" : "XGMI", fw_info.feature, fw_info.ver);
1391         }
1392
1393         /* SMC */
1394         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1395         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1396         if (ret)
1397                 return ret;
1398         seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1399                    fw_info.feature, fw_info.ver);
1400
1401         /* SDMA */
1402         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1403         for (i = 0; i < adev->sdma.num_instances; i++) {
1404                 query_fw.index = i;
1405                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1406                 if (ret)
1407                         return ret;
1408                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1409                            i, fw_info.feature, fw_info.ver);
1410         }
1411
1412         /* VCN */
1413         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1414         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1415         if (ret)
1416                 return ret;
1417         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1418                    fw_info.feature, fw_info.ver);
1419
1420         /* DMCU */
1421         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1422         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1423         if (ret)
1424                 return ret;
1425         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1426                    fw_info.feature, fw_info.ver);
1427
1428
1429         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1430
1431         return 0;
1432 }
1433
1434 static const struct drm_info_list amdgpu_firmware_info_list[] = {
1435         {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1436 };
1437 #endif
1438
1439 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1440 {
1441 #if defined(CONFIG_DEBUG_FS)
1442         return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1443                                         ARRAY_SIZE(amdgpu_firmware_info_list));
1444 #else
1445         return 0;
1446 #endif
1447 }