drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu_sched.h"
  32 #include "amdgpu_uvd.h"
  33 #include "amdgpu_vce.h"
  34 #include "atom.h"
  35
  36 #include <linux/vga_switcheroo.h>
  37 #include <linux/slab.h>
  38 #include <linux/pm_runtime.h>
  39 #include "amdgpu_amdkfd.h"
  40 #include "amdgpu_gem.h"
  41 #include "amdgpu_display.h"
  42
  43 /**
  44  * amdgpu_driver_unload_kms - Main unload function for KMS.
  45  *
  46  * @dev: drm dev pointer
  47  *
  48  * This is the main unload function for KMS (all asics).
  49  * Returns 0 on success.
  50  */
  51 void amdgpu_driver_unload_kms(struct drm_device *dev)
  52 {
  53         struct amdgpu_device *adev = dev->dev_private;
  54
  55         if (adev == NULL)
  56                 return;
  57
  58         if (adev->rmmio == NULL)
  59                 goto done_free;
  60
  61         if (amdgpu_sriov_vf(adev))
  62                 amdgpu_virt_request_full_gpu(adev, false);
  63
  64         if (amdgpu_device_is_px(dev)) {
  65                 pm_runtime_get_sync(dev->dev);
  66                 pm_runtime_forbid(dev->dev);
  67         }
  68
  69         amdgpu_acpi_fini(adev);
  70
  71         amdgpu_device_fini(adev);
  72
  73 done_free:
  74         kfree(adev);
  75         dev->dev_private = NULL;
  76 }
  77
  78 /**
  79  * amdgpu_driver_load_kms - Main load function for KMS.
  80  *
  81  * @dev: drm dev pointer
  82  * @flags: device flags
  83  *
  84  * This is the main load function for KMS (all asics).
  85  * Returns 0 on success, error on failure.
  86  */
  87 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
  88 {
  89         struct amdgpu_device *adev;
  90         int r, acpi_status;
  91
  92 #ifdef CONFIG_DRM_AMDGPU_SI
  93         if (!amdgpu_si_support) {
  94                 switch (flags & AMD_ASIC_MASK) {
  95                 case CHIP_TAHITI:
  96                 case CHIP_PITCAIRN:
  97                 case CHIP_VERDE:
  98                 case CHIP_OLAND:
  99                 case CHIP_HAINAN:
 100                         dev_info(dev->dev,
 101                                  "SI support provided by radeon.\n");
 102                         dev_info(dev->dev,
 103                                  "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
 104                                 );
 105                         return -ENODEV;
 106                 }
 107         }
 108 #endif
 109 #ifdef CONFIG_DRM_AMDGPU_CIK
 110         if (!amdgpu_cik_support) {
 111                 switch (flags & AMD_ASIC_MASK) {
 112                 case CHIP_KAVERI:
 113                 case CHIP_BONAIRE:
 114                 case CHIP_HAWAII:
 115                 case CHIP_KABINI:
 116                 case CHIP_MULLINS:
 117                         dev_info(dev->dev,
 118                                  "CIK support provided by radeon.\n");
 119                         dev_info(dev->dev,
 120                                  "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
 121                                 );
 122                         return -ENODEV;
 123                 }
 124         }
 125 #endif
 126
 127         adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
 128         if (adev == NULL) {
 129                 return -ENOMEM;
 130         }
 131         dev->dev_private = (void *)adev;
 132
 133         if ((amdgpu_runtime_pm != 0) &&
 134             amdgpu_has_atpx() &&
 135             (amdgpu_is_atpx_hybrid() ||
 136              amdgpu_has_atpx_dgpu_power_cntl()) &&
 137             ((flags & AMD_IS_APU) == 0) &&
 138             !pci_is_thunderbolt_attached(dev->pdev))
 139                 flags |= AMD_IS_PX;
 140
 141         /* amdgpu_device_init should report only fatal error
 142          * like memory allocation failure or iomapping failure,
 143          * or memory manager initialization failure, it must
 144          * properly initialize the GPU MC controller and permit
 145          * VRAM allocation
 146          */
 147         r = amdgpu_device_init(adev, dev, dev->pdev, flags);
 148         if (r) {
 149                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 150                 goto out;
 151         }
 152
 153         /* Call ACPI methods: require modeset init
 154          * but failure is not fatal
 155          */
 156         if (!r) {
 157                 acpi_status = amdgpu_acpi_init(adev);
 158                 if (acpi_status)
 159                 dev_dbg(&dev->pdev->dev,
 160                                 "Error during ACPI methods call\n");
 161         }
 162
 163         if (amdgpu_device_is_px(dev)) {
 164                 pm_runtime_use_autosuspend(dev->dev);
 165                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 166                 pm_runtime_set_active(dev->dev);
 167                 pm_runtime_allow(dev->dev);
 168                 pm_runtime_mark_last_busy(dev->dev);
 169                 pm_runtime_put_autosuspend(dev->dev);
 170         }
 171
 172 out:
 173         if (r) {
 174                 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
 175                 if (adev->rmmio && amdgpu_device_is_px(dev))
 176                         pm_runtime_put_noidle(dev->dev);
 177                 amdgpu_driver_unload_kms(dev);
 178         }
 179
 180         return r;
 181 }
 182
 183 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 184                                 struct drm_amdgpu_query_fw *query_fw,
 185                                 struct amdgpu_device *adev)
 186 {
 187         switch (query_fw->fw_type) {
 188         case AMDGPU_INFO_FW_VCE:
 189                 fw_info->ver = adev->vce.fw_version;
 190                 fw_info->feature = adev->vce.fb_version;
 191                 break;
 192         case AMDGPU_INFO_FW_UVD:
 193                 fw_info->ver = adev->uvd.fw_version;
 194                 fw_info->feature = 0;
 195                 break;
 196         case AMDGPU_INFO_FW_VCN:
 197                 fw_info->ver = adev->vcn.fw_version;
 198                 fw_info->feature = 0;
 199                 break;
 200         case AMDGPU_INFO_FW_GMC:
 201                 fw_info->ver = adev->gmc.fw_version;
 202                 fw_info->feature = 0;
 203                 break;
 204         case AMDGPU_INFO_FW_GFX_ME:
 205                 fw_info->ver = adev->gfx.me_fw_version;
 206                 fw_info->feature = adev->gfx.me_feature_version;
 207                 break;
 208         case AMDGPU_INFO_FW_GFX_PFP:
 209                 fw_info->ver = adev->gfx.pfp_fw_version;
 210                 fw_info->feature = adev->gfx.pfp_feature_version;
 211                 break;
 212         case AMDGPU_INFO_FW_GFX_CE:
 213                 fw_info->ver = adev->gfx.ce_fw_version;
 214                 fw_info->feature = adev->gfx.ce_feature_version;
 215                 break;
 216         case AMDGPU_INFO_FW_GFX_RLC:
 217                 fw_info->ver = adev->gfx.rlc_fw_version;
 218                 fw_info->feature = adev->gfx.rlc_feature_version;
 219                 break;
 220         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 221                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 222                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 223                 break;
 224         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 225                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 226                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 227                 break;
 228         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 229                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 230                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 231                 break;
 232         case AMDGPU_INFO_FW_GFX_MEC:
 233                 if (query_fw->index == 0) {
 234                         fw_info->ver = adev->gfx.mec_fw_version;
 235                         fw_info->feature = adev->gfx.mec_feature_version;
 236                 } else if (query_fw->index == 1) {
 237                         fw_info->ver = adev->gfx.mec2_fw_version;
 238                         fw_info->feature = adev->gfx.mec2_feature_version;
 239                 } else
 240                         return -EINVAL;
 241                 break;
 242         case AMDGPU_INFO_FW_SMC:
 243                 fw_info->ver = adev->pm.fw_version;
 244                 fw_info->feature = 0;
 245                 break;
 246         case AMDGPU_INFO_FW_SDMA:
 247                 if (query_fw->index >= adev->sdma.num_instances)
 248                         return -EINVAL;
 249                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 250                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 251                 break;
 252         case AMDGPU_INFO_FW_SOS:
 253                 fw_info->ver = adev->psp.sos_fw_version;
 254                 fw_info->feature = adev->psp.sos_feature_version;
 255                 break;
 256         case AMDGPU_INFO_FW_ASD:
 257                 fw_info->ver = adev->psp.asd_fw_version;
 258                 fw_info->feature = adev->psp.asd_feature_version;
 259                 break;
 260         default:
 261                 return -EINVAL;
 262         }
 263         return 0;
 264 }
 265
 266 /*
 267  * Userspace get information ioctl
 268  */
 269 /**
 270  * amdgpu_info_ioctl - answer a device specific request.
 271  *
 272  * @adev: amdgpu device pointer
 273  * @data: request object
 274  * @filp: drm filp
 275  *
 276  * This function is used to pass device specific parameters to the userspace
 277  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 278  * etc. (all asics).
 279  * Returns 0 on success, -EINVAL on failure.
 280  */
 281 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 282 {
 283         struct amdgpu_device *adev = dev->dev_private;
 284         struct drm_amdgpu_info *info = data;
 285         struct amdgpu_mode_info *minfo = &adev->mode_info;
 286         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 287         uint32_t size = info->return_size;
 288         struct drm_crtc *crtc;
 289         uint32_t ui32 = 0;
 290         uint64_t ui64 = 0;
 291         int i, j, found;
 292         int ui32_size = sizeof(ui32);
 293
 294         if (!info->return_size || !info->return_pointer)
 295                 return -EINVAL;
 296
 297         /* Ensure IB tests are run on ring */
 298         flush_delayed_work(&adev->late_init_work);
 299
 300         switch (info->query) {
 301         case AMDGPU_INFO_ACCEL_WORKING:
 302                 ui32 = adev->accel_working;
 303                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 304         case AMDGPU_INFO_CRTC_FROM_ID:
 305                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 306                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 307                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 308                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 309                                 ui32 = amdgpu_crtc->crtc_id;
 310                                 found = 1;
 311                                 break;
 312                         }
 313                 }
 314                 if (!found) {
 315                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 316                         return -EINVAL;
 317                 }
 318                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 319         case AMDGPU_INFO_HW_IP_INFO: {
 320                 struct drm_amdgpu_info_hw_ip ip = {};
 321                 enum amd_ip_block_type type;
 322                 uint32_t ring_mask = 0;
 323                 uint32_t ib_start_alignment = 0;
 324                 uint32_t ib_size_alignment = 0;
 325
 326                 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 327                         return -EINVAL;
 328
 329                 switch (info->query_hw_ip.type) {
 330                 case AMDGPU_HW_IP_GFX:
 331                         type = AMD_IP_BLOCK_TYPE_GFX;
 332                         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 333                                 ring_mask |= adev->gfx.gfx_ring[i].ready << i;
 334                         ib_start_alignment = 32;
 335                         ib_size_alignment = 32;
 336                         break;
 337                 case AMDGPU_HW_IP_COMPUTE:
 338                         type = AMD_IP_BLOCK_TYPE_GFX;
 339                         for (i = 0; i < adev->gfx.num_compute_rings; i++)
 340                                 ring_mask |= adev->gfx.compute_ring[i].ready << i;
 341                         ib_start_alignment = 32;
 342                         ib_size_alignment = 32;
 343                         break;
 344                 case AMDGPU_HW_IP_DMA:
 345                         type = AMD_IP_BLOCK_TYPE_SDMA;
 346                         for (i = 0; i < adev->sdma.num_instances; i++)
 347                                 ring_mask |= adev->sdma.instance[i].ring.ready << i;
 348                         ib_start_alignment = 256;
 349                         ib_size_alignment = 4;
 350                         break;
 351                 case AMDGPU_HW_IP_UVD:
 352                         type = AMD_IP_BLOCK_TYPE_UVD;
 353                         for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 354                                 if (adev->uvd.harvest_config & (1 << i))
 355                                         continue;
 356                                 ring_mask |= adev->uvd.inst[i].ring.ready;
 357                         }
 358                         ib_start_alignment = 64;
 359                         ib_size_alignment = 64;
 360                         break;
 361                 case AMDGPU_HW_IP_VCE:
 362                         type = AMD_IP_BLOCK_TYPE_VCE;
 363                         for (i = 0; i < adev->vce.num_rings; i++)
 364                                 ring_mask |= adev->vce.ring[i].ready << i;
 365                         ib_start_alignment = 4;
 366                         ib_size_alignment = 1;
 367                         break;
 368                 case AMDGPU_HW_IP_UVD_ENC:
 369                         type = AMD_IP_BLOCK_TYPE_UVD;
 370                         for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 371                                 if (adev->uvd.harvest_config & (1 << i))
 372                                         continue;
 373                                 for (j = 0; j < adev->uvd.num_enc_rings; j++)
 374                                         ring_mask |= adev->uvd.inst[i].ring_enc[j].ready << j;
 375                         }
 376                         ib_start_alignment = 64;
 377                         ib_size_alignment = 64;
 378                         break;
 379                 case AMDGPU_HW_IP_VCN_DEC:
 380                         type = AMD_IP_BLOCK_TYPE_VCN;
 381                         ring_mask = adev->vcn.ring_dec.ready;
 382                         ib_start_alignment = 16;
 383                         ib_size_alignment = 16;
 384                         break;
 385                 case AMDGPU_HW_IP_VCN_ENC:
 386                         type = AMD_IP_BLOCK_TYPE_VCN;
 387                         for (i = 0; i < adev->vcn.num_enc_rings; i++)
 388                                 ring_mask |= adev->vcn.ring_enc[i].ready << i;
 389                         ib_start_alignment = 64;
 390                         ib_size_alignment = 1;
 391                         break;
 392                 case AMDGPU_HW_IP_VCN_JPEG:
 393                         type = AMD_IP_BLOCK_TYPE_VCN;
 394                         ring_mask = adev->vcn.ring_jpeg.ready;
 395                         ib_start_alignment = 16;
 396                         ib_size_alignment = 16;
 397                         break;
 398                 default:
 399                         return -EINVAL;
 400                 }
 401
 402                 for (i = 0; i < adev->num_ip_blocks; i++) {
 403                         if (adev->ip_blocks[i].version->type == type &&
 404                             adev->ip_blocks[i].status.valid) {
 405                                 ip.hw_ip_version_major = adev->ip_blocks[i].version->major;
 406                                 ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 407                                 ip.capabilities_flags = 0;
 408                                 ip.available_rings = ring_mask;
 409                                 ip.ib_start_alignment = ib_start_alignment;
 410                                 ip.ib_size_alignment = ib_size_alignment;
 411                                 break;
 412                         }
 413                 }
 414                 return copy_to_user(out, &ip,
 415                                     min((size_t)size, sizeof(ip))) ? -EFAULT : 0;
 416         }
 417         case AMDGPU_INFO_HW_IP_COUNT: {
 418                 enum amd_ip_block_type type;
 419                 uint32_t count = 0;
 420
 421                 switch (info->query_hw_ip.type) {
 422                 case AMDGPU_HW_IP_GFX:
 423                         type = AMD_IP_BLOCK_TYPE_GFX;
 424                         break;
 425                 case AMDGPU_HW_IP_COMPUTE:
 426                         type = AMD_IP_BLOCK_TYPE_GFX;
 427                         break;
 428                 case AMDGPU_HW_IP_DMA:
 429                         type = AMD_IP_BLOCK_TYPE_SDMA;
 430                         break;
 431                 case AMDGPU_HW_IP_UVD:
 432                         type = AMD_IP_BLOCK_TYPE_UVD;
 433                         break;
 434                 case AMDGPU_HW_IP_VCE:
 435                         type = AMD_IP_BLOCK_TYPE_VCE;
 436                         break;
 437                 case AMDGPU_HW_IP_UVD_ENC:
 438                         type = AMD_IP_BLOCK_TYPE_UVD;
 439                         break;
 440                 case AMDGPU_HW_IP_VCN_DEC:
 441                 case AMDGPU_HW_IP_VCN_ENC:
 442                 case AMDGPU_HW_IP_VCN_JPEG:
 443                         type = AMD_IP_BLOCK_TYPE_VCN;
 444                         break;
 445                 default:
 446                         return -EINVAL;
 447                 }
 448
 449                 for (i = 0; i < adev->num_ip_blocks; i++)
 450                         if (adev->ip_blocks[i].version->type == type &&
 451                             adev->ip_blocks[i].status.valid &&
 452                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 453                                 count++;
 454
 455                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 456         }
 457         case AMDGPU_INFO_TIMESTAMP:
 458                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 459                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 460         case AMDGPU_INFO_FW_VERSION: {
 461                 struct drm_amdgpu_info_firmware fw_info;
 462                 int ret;
 463
 464                 /* We only support one instance of each IP block right now. */
 465                 if (info->query_fw.ip_instance != 0)
 466                         return -EINVAL;
 467
 468                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 469                 if (ret)
 470                         return ret;
 471
 472                 return copy_to_user(out, &fw_info,
 473                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 474         }
 475         case AMDGPU_INFO_NUM_BYTES_MOVED:
 476                 ui64 = atomic64_read(&adev->num_bytes_moved);
 477                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 478         case AMDGPU_INFO_NUM_EVICTIONS:
 479                 ui64 = atomic64_read(&adev->num_evictions);
 480                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 481         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 482                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 483                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 484         case AMDGPU_INFO_VRAM_USAGE:
 485                 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 486                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 487         case AMDGPU_INFO_VIS_VRAM_USAGE:
 488                 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 489                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 490         case AMDGPU_INFO_GTT_USAGE:
 491                 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
 492                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 493         case AMDGPU_INFO_GDS_CONFIG: {
 494                 struct drm_amdgpu_info_gds gds_info;
 495
 496                 memset(&gds_info, 0, sizeof(gds_info));
 497                 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT;
 498                 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT;
 499                 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT;
 500                 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT;
 501                 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT;
 502                 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT;
 503                 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT;
 504                 return copy_to_user(out, &gds_info,
 505                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 506         }
 507         case AMDGPU_INFO_VRAM_GTT: {
 508                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 509
 510                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 511                         atomic64_read(&adev->vram_pin_size);
 512                 vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size -
 513                         atomic64_read(&adev->visible_pin_size);
 514                 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
 515                 vram_gtt.gtt_size *= PAGE_SIZE;
 516                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 517                 return copy_to_user(out, &vram_gtt,
 518                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 519         }
 520         case AMDGPU_INFO_MEMORY: {
 521                 struct drm_amdgpu_memory_info mem;
 522
 523                 memset(&mem, 0, sizeof(mem));
 524                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 525                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 526                         atomic64_read(&adev->vram_pin_size);
 527                 mem.vram.heap_usage =
 528                         amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 529                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 530
 531                 mem.cpu_accessible_vram.total_heap_size =
 532                         adev->gmc.visible_vram_size;
 533                 mem.cpu_accessible_vram.usable_heap_size = adev->gmc.visible_vram_size -
 534                         atomic64_read(&adev->visible_pin_size);
 535                 mem.cpu_accessible_vram.heap_usage =
 536                         amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 537                 mem.cpu_accessible_vram.max_allocation =
 538                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 539
 540                 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size;
 541                 mem.gtt.total_heap_size *= PAGE_SIZE;
 542                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 543                         atomic64_read(&adev->gart_pin_size);
 544                 mem.gtt.heap_usage =
 545                         amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
 546                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 547
 548                 return copy_to_user(out, &mem,
 549                                     min((size_t)size, sizeof(mem)))
 550                                     ? -EFAULT : 0;
 551         }
 552         case AMDGPU_INFO_READ_MMR_REG: {
 553                 unsigned n, alloc_size;
 554                 uint32_t *regs;
 555                 unsigned se_num = (info->read_mmr_reg.instance >>
 556                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 557                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 558                 unsigned sh_num = (info->read_mmr_reg.instance >>
 559                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 560                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 561
 562                 /* set full masks if the userspace set all bits
 563                  * in the bitfields */
 564                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 565                         se_num = 0xffffffff;
 566                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 567                         sh_num = 0xffffffff;
 568
 569                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 570                 if (!regs)
 571                         return -ENOMEM;
 572                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 573
 574                 for (i = 0; i < info->read_mmr_reg.count; i++)
 575                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 576                                                       info->read_mmr_reg.dword_offset + i,
 577                                                       &regs[i])) {
 578                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 579                                               info->read_mmr_reg.dword_offset + i);
 580                                 kfree(regs);
 581                                 return -EFAULT;
 582                         }
 583                 n = copy_to_user(out, regs, min(size, alloc_size));
 584                 kfree(regs);
 585                 return n ? -EFAULT : 0;
 586         }
 587         case AMDGPU_INFO_DEV_INFO: {
 588                 struct drm_amdgpu_info_device dev_info = {};
 589                 uint64_t vm_size;
 590
 591                 dev_info.device_id = dev->pdev->device;
 592                 dev_info.chip_rev = adev->rev_id;
 593                 dev_info.external_rev = adev->external_rev_id;
 594                 dev_info.pci_rev = dev->pdev->revision;
 595                 dev_info.family = adev->family;
 596                 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
 597                 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 598                 /* return all clocks in KHz */
 599                 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 600                 if (adev->pm.dpm_enabled) {
 601                         dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 602                         dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 603                 } else {
 604                         dev_info.max_engine_clock = adev->clock.default_sclk * 10;
 605                         dev_info.max_memory_clock = adev->clock.default_mclk * 10;
 606                 }
 607                 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 608                 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
 609                         adev->gfx.config.max_shader_engines;
 610                 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 611                 dev_info._pad = 0;
 612                 dev_info.ids_flags = 0;
 613                 if (adev->flags & AMD_IS_APU)
 614                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 615                 if (amdgpu_sriov_vf(adev))
 616                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 617
 618                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 619                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 620
 621                 /* Older VCE FW versions are buggy and can handle only 40bits */
 622                 if (adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 623                         vm_size = min(vm_size, 1ULL << 40);
 624
 625                 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 626                 dev_info.virtual_address_max =
 627                         min(vm_size, AMDGPU_VA_HOLE_START);
 628
 629                 if (vm_size > AMDGPU_VA_HOLE_START) {
 630                         dev_info.high_va_offset = AMDGPU_VA_HOLE_END;
 631                         dev_info.high_va_max = AMDGPU_VA_HOLE_END | vm_size;
 632                 }
 633                 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 634                 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 635                 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
 636                 dev_info.cu_active_number = adev->gfx.cu_info.number;
 637                 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 638                 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
 639                 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 640                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 641                 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 642                        sizeof(adev->gfx.cu_info.bitmap));
 643                 dev_info.vram_type = adev->gmc.vram_type;
 644                 dev_info.vram_bit_width = adev->gmc.vram_width;
 645                 dev_info.vce_harvest_config = adev->vce.harvest_config;
 646                 dev_info.gc_double_offchip_lds_buf =
 647                         adev->gfx.config.double_offchip_lds_buf;
 648
 649                 if (amdgpu_ngg) {
 650                         dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;
 651                         dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;
 652                         dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;
 653                         dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;
 654                         dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;
 655                         dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;
 656                         dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;
 657                         dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;
 658                 }
 659                 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
 660                 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 661                 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 662                 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 663                 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 664                 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 665                 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 666
 667                 return copy_to_user(out, &dev_info,
 668                                     min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
 669         }
 670         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 671                 unsigned i;
 672                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 673                 struct amd_vce_state *vce_state;
 674
 675                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 676                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 677                         if (vce_state) {
 678                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 679                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 680                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 681                                 vce_clk_table.num_valid_entries++;
 682                         }
 683                 }
 684
 685                 return copy_to_user(out, &vce_clk_table,
 686                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 687         }
 688         case AMDGPU_INFO_VBIOS: {
 689                 uint32_t bios_size = adev->bios_size;
 690
 691                 switch (info->vbios_info.type) {
 692                 case AMDGPU_INFO_VBIOS_SIZE:
 693                         return copy_to_user(out, &bios_size,
 694                                         min((size_t)size, sizeof(bios_size)))
 695                                         ? -EFAULT : 0;
 696                 case AMDGPU_INFO_VBIOS_IMAGE: {
 697                         uint8_t *bios;
 698                         uint32_t bios_offset = info->vbios_info.offset;
 699
 700                         if (bios_offset >= bios_size)
 701                                 return -EINVAL;
 702
 703                         bios = adev->bios + bios_offset;
 704                         return copy_to_user(out, bios,
 705                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 706                                         ? -EFAULT : 0;
 707                 }
 708                 default:
 709                         DRM_DEBUG_KMS("Invalid request %d\n",
 710                                         info->vbios_info.type);
 711                         return -EINVAL;
 712                 }
 713         }
 714         case AMDGPU_INFO_NUM_HANDLES: {
 715                 struct drm_amdgpu_info_num_handles handle;
 716
 717                 switch (info->query_hw_ip.type) {
 718                 case AMDGPU_HW_IP_UVD:
 719                         /* Starting Polaris, we support unlimited UVD handles */
 720                         if (adev->asic_type < CHIP_POLARIS10) {
 721                                 handle.uvd_max_handles = adev->uvd.max_handles;
 722                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 723
 724                                 return copy_to_user(out, &handle,
 725                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 726                         } else {
 727                                 return -ENODATA;
 728                         }
 729
 730                         break;
 731                 default:
 732                         return -EINVAL;
 733                 }
 734         }
 735         case AMDGPU_INFO_SENSOR: {
 736                 if (!adev->pm.dpm_enabled)
 737                         return -ENOENT;
 738
 739                 switch (info->sensor_info.type) {
 740                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 741                         /* get sclk in Mhz */
 742                         if (amdgpu_dpm_read_sensor(adev,
 743                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 744                                                    (void *)&ui32, &ui32_size)) {
 745                                 return -EINVAL;
 746                         }
 747                         ui32 /= 100;
 748                         break;
 749                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 750                         /* get mclk in Mhz */
 751                         if (amdgpu_dpm_read_sensor(adev,
 752                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 753                                                    (void *)&ui32, &ui32_size)) {
 754                                 return -EINVAL;
 755                         }
 756                         ui32 /= 100;
 757                         break;
 758                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 759                         /* get temperature in millidegrees C */
 760                         if (amdgpu_dpm_read_sensor(adev,
 761                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 762                                                    (void *)&ui32, &ui32_size)) {
 763                                 return -EINVAL;
 764                         }
 765                         break;
 766                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 767                         /* get GPU load */
 768                         if (amdgpu_dpm_read_sensor(adev,
 769                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 770                                                    (void *)&ui32, &ui32_size)) {
 771                                 return -EINVAL;
 772                         }
 773                         break;
 774                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 775                         /* get average GPU power */
 776                         if (amdgpu_dpm_read_sensor(adev,
 777                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 778                                                    (void *)&ui32, &ui32_size)) {
 779                                 return -EINVAL;
 780                         }
 781                         ui32 >>= 8;
 782                         break;
 783                 case AMDGPU_INFO_SENSOR_VDDNB:
 784                         /* get VDDNB in millivolts */
 785                         if (amdgpu_dpm_read_sensor(adev,
 786                                                    AMDGPU_PP_SENSOR_VDDNB,
 787                                                    (void *)&ui32, &ui32_size)) {
 788                                 return -EINVAL;
 789                         }
 790                         break;
 791                 case AMDGPU_INFO_SENSOR_VDDGFX:
 792                         /* get VDDGFX in millivolts */
 793                         if (amdgpu_dpm_read_sensor(adev,
 794                                                    AMDGPU_PP_SENSOR_VDDGFX,
 795                                                    (void *)&ui32, &ui32_size)) {
 796                                 return -EINVAL;
 797                         }
 798                         break;
 799                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 800                         /* get stable pstate sclk in Mhz */
 801                         if (amdgpu_dpm_read_sensor(adev,
 802                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 803                                                    (void *)&ui32, &ui32_size)) {
 804                                 return -EINVAL;
 805                         }
 806                         ui32 /= 100;
 807                         break;
 808                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
 809                         /* get stable pstate mclk in Mhz */
 810                         if (amdgpu_dpm_read_sensor(adev,
 811                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 812                                                    (void *)&ui32, &ui32_size)) {
 813                                 return -EINVAL;
 814                         }
 815                         ui32 /= 100;
 816                         break;
 817                 default:
 818                         DRM_DEBUG_KMS("Invalid request %d\n",
 819                                       info->sensor_info.type);
 820                         return -EINVAL;
 821                 }
 822                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 823         }
 824         case AMDGPU_INFO_VRAM_LOST_COUNTER:
 825                 ui32 = atomic_read(&adev->vram_lost_counter);
 826                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 827         default:
 828                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
 829                 return -EINVAL;
 830         }
 831         return 0;
 832 }
 833
 834
 835 /*
 836  * Outdated mess for old drm with Xorg being in charge (void function now).
 837  */
 838 /**
 839  * amdgpu_driver_lastclose_kms - drm callback for last close
 840  *
 841  * @dev: drm dev pointer
 842  *
 843  * Switch vga_switcheroo state after last close (all asics).
 844  */
 845 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
 846 {
 847         drm_fb_helper_lastclose(dev);
 848         vga_switcheroo_process_delayed_switch();
 849 }
 850
 851 /**
 852  * amdgpu_driver_open_kms - drm callback for open
 853  *
 854  * @dev: drm dev pointer
 855  * @file_priv: drm file
 856  *
 857  * On device open, init vm on cayman+ (all asics).
 858  * Returns 0 on success, error on failure.
 859  */
 860 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 861 {
 862         struct amdgpu_device *adev = dev->dev_private;
 863         struct amdgpu_fpriv *fpriv;
 864         int r, pasid;
 865
 866         file_priv->driver_priv = NULL;
 867
 868         r = pm_runtime_get_sync(dev->dev);
 869         if (r < 0)
 870                 return r;
 871
 872         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 873         if (unlikely(!fpriv)) {
 874                 r = -ENOMEM;
 875                 goto out_suspend;
 876         }
 877
 878         pasid = amdgpu_pasid_alloc(16);
 879         if (pasid < 0) {
 880                 dev_warn(adev->dev, "No more PASIDs available!");
 881                 pasid = 0;
 882         }
 883         r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
 884         if (r)
 885                 goto error_pasid;
 886
 887         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
 888         if (!fpriv->prt_va) {
 889                 r = -ENOMEM;
 890                 goto error_vm;
 891         }
 892
 893         if (amdgpu_sriov_vf(adev)) {
 894                 r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va);
 895                 if (r)
 896                         goto error_vm;
 897         }
 898
 899         mutex_init(&fpriv->bo_list_lock);
 900         idr_init(&fpriv->bo_list_handles);
 901
 902         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
 903
 904         file_priv->driver_priv = fpriv;
 905         goto out_suspend;
 906
 907 error_vm:
 908         amdgpu_vm_fini(adev, &fpriv->vm);
 909
 910 error_pasid:
 911         if (pasid)
 912                 amdgpu_pasid_free(pasid);
 913
 914         kfree(fpriv);
 915
 916 out_suspend:
 917         pm_runtime_mark_last_busy(dev->dev);
 918         pm_runtime_put_autosuspend(dev->dev);
 919
 920         return r;
 921 }
 922
 923 /**
 924  * amdgpu_driver_postclose_kms - drm callback for post close
 925  *
 926  * @dev: drm dev pointer
 927  * @file_priv: drm file
 928  *
 929  * On device post close, tear down vm on cayman+ (all asics).
 930  */
 931 void amdgpu_driver_postclose_kms(struct drm_device *dev,
 932                                  struct drm_file *file_priv)
 933 {
 934         struct amdgpu_device *adev = dev->dev_private;
 935         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 936         struct amdgpu_bo_list *list;
 937         struct amdgpu_bo *pd;
 938         unsigned int pasid;
 939         int handle;
 940
 941         if (!fpriv)
 942                 return;
 943
 944         pm_runtime_get_sync(dev->dev);
 945
 946         if (adev->asic_type != CHIP_RAVEN) {
 947                 amdgpu_uvd_free_handles(adev, file_priv);
 948                 amdgpu_vce_free_handles(adev, file_priv);
 949         }
 950
 951         amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
 952
 953         if (amdgpu_sriov_vf(adev)) {
 954                 /* TODO: how to handle reserve failure */
 955                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
 956                 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
 957                 fpriv->csa_va = NULL;
 958                 amdgpu_bo_unreserve(adev->virt.csa_obj);
 959         }
 960
 961         pasid = fpriv->vm.pasid;
 962         pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
 963
 964         amdgpu_vm_fini(adev, &fpriv->vm);
 965         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
 966
 967         if (pasid)
 968                 amdgpu_pasid_free_delayed(pd->tbo.resv, pasid);
 969         amdgpu_bo_unref(&pd);
 970
 971         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
 972                 amdgpu_bo_list_put(list);
 973
 974         idr_destroy(&fpriv->bo_list_handles);
 975         mutex_destroy(&fpriv->bo_list_lock);
 976
 977         kfree(fpriv);
 978         file_priv->driver_priv = NULL;
 979
 980         pm_runtime_mark_last_busy(dev->dev);
 981         pm_runtime_put_autosuspend(dev->dev);
 982 }
 983
 984 /*
 985  * VBlank related functions.
 986  */
 987 /**
 988  * amdgpu_get_vblank_counter_kms - get frame count
 989  *
 990  * @dev: drm dev pointer
 991  * @pipe: crtc to get the frame count from
 992  *
 993  * Gets the frame count on the requested crtc (all asics).
 994  * Returns frame count on success, -EINVAL on failure.
 995  */
 996 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
 997 {
 998         struct amdgpu_device *adev = dev->dev_private;
 999         int vpos, hpos, stat;
1000         u32 count;
1001
1002         if (pipe >= adev->mode_info.num_crtc) {
1003                 DRM_ERROR("Invalid crtc %u\n", pipe);
1004                 return -EINVAL;
1005         }
1006
1007         /* The hw increments its frame counter at start of vsync, not at start
1008          * of vblank, as is required by DRM core vblank counter handling.
1009          * Cook the hw count here to make it appear to the caller as if it
1010          * incremented at start of vblank. We measure distance to start of
1011          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1012          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1013          * result by 1 to give the proper appearance to caller.
1014          */
1015         if (adev->mode_info.crtcs[pipe]) {
1016                 /* Repeat readout if needed to provide stable result if
1017                  * we cross start of vsync during the queries.
1018                  */
1019                 do {
1020                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1021                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1022                          * vpos as distance to start of vblank, instead of
1023                          * regular vertical scanout pos.
1024                          */
1025                         stat = amdgpu_display_get_crtc_scanoutpos(
1026                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1027                                 &vpos, &hpos, NULL, NULL,
1028                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1029                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1030
1031                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1032                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1033                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1034                 } else {
1035                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1036                                       pipe, vpos);
1037
1038                         /* Bump counter if we are at >= leading edge of vblank,
1039                          * but before vsync where vpos would turn negative and
1040                          * the hw counter really increments.
1041                          */
1042                         if (vpos >= 0)
1043                                 count++;
1044                 }
1045         } else {
1046                 /* Fallback to use value as is. */
1047                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1048                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1049         }
1050
1051         return count;
1052 }
1053
1054 /**
1055  * amdgpu_enable_vblank_kms - enable vblank interrupt
1056  *
1057  * @dev: drm dev pointer
1058  * @pipe: crtc to enable vblank interrupt for
1059  *
1060  * Enable the interrupt on the requested crtc (all asics).
1061  * Returns 0 on success, -EINVAL on failure.
1062  */
1063 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1064 {
1065         struct amdgpu_device *adev = dev->dev_private;
1066         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1067
1068         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1069 }
1070
1071 /**
1072  * amdgpu_disable_vblank_kms - disable vblank interrupt
1073  *
1074  * @dev: drm dev pointer
1075  * @pipe: crtc to disable vblank interrupt for
1076  *
1077  * Disable the interrupt on the requested crtc (all asics).
1078  */
1079 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1080 {
1081         struct amdgpu_device *adev = dev->dev_private;
1082         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1083
1084         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1085 }
1086
1087 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
1088         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1089         DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1090         DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1091         DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
1092         DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1093         DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1094         /* KMS */
1095         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1096         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1097         DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1098         DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1099         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1100         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1101         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1102         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1103         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1104         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)
1105 };
1106 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
1107
1108 /*
1109  * Debugfs info
1110  */
1111 #if defined(CONFIG_DEBUG_FS)
1112
1113 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1114 {
1115         struct drm_info_node *node = (struct drm_info_node *) m->private;
1116         struct drm_device *dev = node->minor->dev;
1117         struct amdgpu_device *adev = dev->dev_private;
1118         struct drm_amdgpu_info_firmware fw_info;
1119         struct drm_amdgpu_query_fw query_fw;
1120         struct atom_context *ctx = adev->mode_info.atom_context;
1121         int ret, i;
1122
1123         /* VCE */
1124         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1125         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1126         if (ret)
1127                 return ret;
1128         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1129                    fw_info.feature, fw_info.ver);
1130
1131         /* UVD */
1132         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1133         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1134         if (ret)
1135                 return ret;
1136         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1137                    fw_info.feature, fw_info.ver);
1138
1139         /* GMC */
1140         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1141         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1142         if (ret)
1143                 return ret;
1144         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1145                    fw_info.feature, fw_info.ver);
1146
1147         /* ME */
1148         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1149         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1150         if (ret)
1151                 return ret;
1152         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1153                    fw_info.feature, fw_info.ver);
1154
1155         /* PFP */
1156         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1157         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1158         if (ret)
1159                 return ret;
1160         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1161                    fw_info.feature, fw_info.ver);
1162
1163         /* CE */
1164         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1165         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1166         if (ret)
1167                 return ret;
1168         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1169                    fw_info.feature, fw_info.ver);
1170
1171         /* RLC */
1172         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1173         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1174         if (ret)
1175                 return ret;
1176         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1177                    fw_info.feature, fw_info.ver);
1178
1179         /* RLC SAVE RESTORE LIST CNTL */
1180         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1181         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1182         if (ret)
1183                 return ret;
1184         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1185                    fw_info.feature, fw_info.ver);
1186
1187         /* RLC SAVE RESTORE LIST GPM MEM */
1188         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1189         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1190         if (ret)
1191                 return ret;
1192         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1193                    fw_info.feature, fw_info.ver);
1194
1195         /* RLC SAVE RESTORE LIST SRM MEM */
1196         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1197         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1198         if (ret)
1199                 return ret;
1200         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1201                    fw_info.feature, fw_info.ver);
1202
1203         /* MEC */
1204         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1205         query_fw.index = 0;
1206         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1207         if (ret)
1208                 return ret;
1209         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1210                    fw_info.feature, fw_info.ver);
1211
1212         /* MEC2 */
1213         if (adev->asic_type == CHIP_KAVERI ||
1214             (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
1215                 query_fw.index = 1;
1216                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1217                 if (ret)
1218                         return ret;
1219                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1220                            fw_info.feature, fw_info.ver);
1221         }
1222
1223         /* PSP SOS */
1224         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1225         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1226         if (ret)
1227                 return ret;
1228         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1229                    fw_info.feature, fw_info.ver);
1230
1231
1232         /* PSP ASD */
1233         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1234         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1235         if (ret)
1236                 return ret;
1237         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1238                    fw_info.feature, fw_info.ver);
1239
1240         /* SMC */
1241         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1242         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1243         if (ret)
1244                 return ret;
1245         seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1246                    fw_info.feature, fw_info.ver);
1247
1248         /* SDMA */
1249         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1250         for (i = 0; i < adev->sdma.num_instances; i++) {
1251                 query_fw.index = i;
1252                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1253                 if (ret)
1254                         return ret;
1255                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1256                            i, fw_info.feature, fw_info.ver);
1257         }
1258
1259         /* VCN */
1260         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1261         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1262         if (ret)
1263                 return ret;
1264         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1265                    fw_info.feature, fw_info.ver);
1266
1267
1268         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1269
1270         return 0;
1271 }
1272
1273 static const struct drm_info_list amdgpu_firmware_info_list[] = {
1274         {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1275 };
1276 #endif
1277
1278 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1279 {
1280 #if defined(CONFIG_DEBUG_FS)
1281         return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1282                                         ARRAY_SIZE(amdgpu_firmware_info_list));
1283 #else
1284         return 0;
1285 #endif
1286 }