2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 #include <drm/drm_debugfs.h>
31 #include <drm/amdgpu_drm.h>
32 #include "amdgpu_sched.h"
33 #include "amdgpu_uvd.h"
34 #include "amdgpu_vce.h"
37 #include <linux/vga_switcheroo.h>
38 #include <linux/slab.h>
39 #include <linux/uaccess.h>
40 #include <linux/pci.h>
41 #include <linux/pm_runtime.h>
42 #include "amdgpu_amdkfd.h"
43 #include "amdgpu_gem.h"
44 #include "amdgpu_display.h"
45 #include "amdgpu_ras.h"
47 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
49 struct amdgpu_gpu_instance *gpu_instance;
52 mutex_lock(&mgpu_info.mutex);
54 for (i = 0; i < mgpu_info.num_gpu; i++) {
55 gpu_instance = &(mgpu_info.gpu_ins[i]);
56 if (gpu_instance->adev == adev) {
57 mgpu_info.gpu_ins[i] =
58 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
60 if (adev->flags & AMD_IS_APU)
68 mutex_unlock(&mgpu_info.mutex);
72 * amdgpu_driver_unload_kms - Main unload function for KMS.
74 * @dev: drm dev pointer
76 * This is the main unload function for KMS (all asics).
77 * Returns 0 on success.
79 void amdgpu_driver_unload_kms(struct drm_device *dev)
81 struct amdgpu_device *adev = dev->dev_private;
86 amdgpu_unregister_gpu_instance(adev);
88 if (adev->rmmio == NULL)
91 if (amdgpu_sriov_vf(adev))
92 amdgpu_virt_request_full_gpu(adev, false);
94 if (amdgpu_device_is_px(dev)) {
95 pm_runtime_get_sync(dev->dev);
96 pm_runtime_forbid(dev->dev);
99 amdgpu_acpi_fini(adev);
101 amdgpu_device_fini(adev);
105 dev->dev_private = NULL;
108 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
110 struct amdgpu_gpu_instance *gpu_instance;
112 mutex_lock(&mgpu_info.mutex);
114 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
115 DRM_ERROR("Cannot register more gpu instance\n");
116 mutex_unlock(&mgpu_info.mutex);
120 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
121 gpu_instance->adev = adev;
122 gpu_instance->mgpu_fan_enabled = 0;
125 if (adev->flags & AMD_IS_APU)
128 mgpu_info.num_dgpu++;
130 mutex_unlock(&mgpu_info.mutex);
134 * amdgpu_driver_load_kms - Main load function for KMS.
136 * @dev: drm dev pointer
137 * @flags: device flags
139 * This is the main load function for KMS (all asics).
140 * Returns 0 on success, error on failure.
142 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
144 struct amdgpu_device *adev;
147 #ifdef CONFIG_DRM_AMDGPU_SI
148 if (!amdgpu_si_support) {
149 switch (flags & AMD_ASIC_MASK) {
156 "SI support provided by radeon.\n");
158 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
164 #ifdef CONFIG_DRM_AMDGPU_CIK
165 if (!amdgpu_cik_support) {
166 switch (flags & AMD_ASIC_MASK) {
173 "CIK support provided by radeon.\n");
175 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
182 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
186 dev->dev_private = (void *)adev;
188 if ((amdgpu_runtime_pm != 0) &&
190 (amdgpu_is_atpx_hybrid() ||
191 amdgpu_has_atpx_dgpu_power_cntl()) &&
192 ((flags & AMD_IS_APU) == 0) &&
193 !pci_is_thunderbolt_attached(dev->pdev))
196 /* amdgpu_device_init should report only fatal error
197 * like memory allocation failure or iomapping failure,
198 * or memory manager initialization failure, it must
199 * properly initialize the GPU MC controller and permit
202 r = amdgpu_device_init(adev, dev, dev->pdev, flags);
204 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
208 /* Call ACPI methods: require modeset init
209 * but failure is not fatal
212 acpi_status = amdgpu_acpi_init(adev);
214 dev_dbg(&dev->pdev->dev,
215 "Error during ACPI methods call\n");
218 if (amdgpu_device_is_px(dev)) {
219 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP);
220 pm_runtime_use_autosuspend(dev->dev);
221 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
222 pm_runtime_set_active(dev->dev);
223 pm_runtime_allow(dev->dev);
224 pm_runtime_mark_last_busy(dev->dev);
225 pm_runtime_put_autosuspend(dev->dev);
228 amdgpu_register_gpu_instance(adev);
231 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
232 if (adev->rmmio && amdgpu_device_is_px(dev))
233 pm_runtime_put_noidle(dev->dev);
234 amdgpu_driver_unload_kms(dev);
240 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
241 struct drm_amdgpu_query_fw *query_fw,
242 struct amdgpu_device *adev)
244 switch (query_fw->fw_type) {
245 case AMDGPU_INFO_FW_VCE:
246 fw_info->ver = adev->vce.fw_version;
247 fw_info->feature = adev->vce.fb_version;
249 case AMDGPU_INFO_FW_UVD:
250 fw_info->ver = adev->uvd.fw_version;
251 fw_info->feature = 0;
253 case AMDGPU_INFO_FW_VCN:
254 fw_info->ver = adev->vcn.fw_version;
255 fw_info->feature = 0;
257 case AMDGPU_INFO_FW_GMC:
258 fw_info->ver = adev->gmc.fw_version;
259 fw_info->feature = 0;
261 case AMDGPU_INFO_FW_GFX_ME:
262 fw_info->ver = adev->gfx.me_fw_version;
263 fw_info->feature = adev->gfx.me_feature_version;
265 case AMDGPU_INFO_FW_GFX_PFP:
266 fw_info->ver = adev->gfx.pfp_fw_version;
267 fw_info->feature = adev->gfx.pfp_feature_version;
269 case AMDGPU_INFO_FW_GFX_CE:
270 fw_info->ver = adev->gfx.ce_fw_version;
271 fw_info->feature = adev->gfx.ce_feature_version;
273 case AMDGPU_INFO_FW_GFX_RLC:
274 fw_info->ver = adev->gfx.rlc_fw_version;
275 fw_info->feature = adev->gfx.rlc_feature_version;
277 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
278 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
279 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
281 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
282 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
283 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
285 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
286 fw_info->ver = adev->gfx.rlc_srls_fw_version;
287 fw_info->feature = adev->gfx.rlc_srls_feature_version;
289 case AMDGPU_INFO_FW_GFX_MEC:
290 if (query_fw->index == 0) {
291 fw_info->ver = adev->gfx.mec_fw_version;
292 fw_info->feature = adev->gfx.mec_feature_version;
293 } else if (query_fw->index == 1) {
294 fw_info->ver = adev->gfx.mec2_fw_version;
295 fw_info->feature = adev->gfx.mec2_feature_version;
299 case AMDGPU_INFO_FW_SMC:
300 fw_info->ver = adev->pm.fw_version;
301 fw_info->feature = 0;
303 case AMDGPU_INFO_FW_TA:
304 if (query_fw->index > 1)
306 if (query_fw->index == 0) {
307 fw_info->ver = adev->psp.ta_fw_version;
308 fw_info->feature = adev->psp.ta_xgmi_ucode_version;
310 fw_info->ver = adev->psp.ta_fw_version;
311 fw_info->feature = adev->psp.ta_ras_ucode_version;
314 case AMDGPU_INFO_FW_SDMA:
315 if (query_fw->index >= adev->sdma.num_instances)
317 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
318 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
320 case AMDGPU_INFO_FW_SOS:
321 fw_info->ver = adev->psp.sos_fw_version;
322 fw_info->feature = adev->psp.sos_feature_version;
324 case AMDGPU_INFO_FW_ASD:
325 fw_info->ver = adev->psp.asd_fw_version;
326 fw_info->feature = adev->psp.asd_feature_version;
328 case AMDGPU_INFO_FW_DMCU:
329 fw_info->ver = adev->dm.dmcu_fw_version;
330 fw_info->feature = 0;
338 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
339 struct drm_amdgpu_info *info,
340 struct drm_amdgpu_info_hw_ip *result)
342 uint32_t ib_start_alignment = 0;
343 uint32_t ib_size_alignment = 0;
344 enum amd_ip_block_type type;
345 unsigned int num_rings = 0;
348 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
351 switch (info->query_hw_ip.type) {
352 case AMDGPU_HW_IP_GFX:
353 type = AMD_IP_BLOCK_TYPE_GFX;
354 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
355 if (adev->gfx.gfx_ring[i].sched.ready)
357 ib_start_alignment = 32;
358 ib_size_alignment = 32;
360 case AMDGPU_HW_IP_COMPUTE:
361 type = AMD_IP_BLOCK_TYPE_GFX;
362 for (i = 0; i < adev->gfx.num_compute_rings; i++)
363 if (adev->gfx.compute_ring[i].sched.ready)
365 ib_start_alignment = 32;
366 ib_size_alignment = 32;
368 case AMDGPU_HW_IP_DMA:
369 type = AMD_IP_BLOCK_TYPE_SDMA;
370 for (i = 0; i < adev->sdma.num_instances; i++)
371 if (adev->sdma.instance[i].ring.sched.ready)
373 ib_start_alignment = 256;
374 ib_size_alignment = 4;
376 case AMDGPU_HW_IP_UVD:
377 type = AMD_IP_BLOCK_TYPE_UVD;
378 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
379 if (adev->uvd.harvest_config & (1 << i))
382 if (adev->uvd.inst[i].ring.sched.ready)
385 ib_start_alignment = 64;
386 ib_size_alignment = 64;
388 case AMDGPU_HW_IP_VCE:
389 type = AMD_IP_BLOCK_TYPE_VCE;
390 for (i = 0; i < adev->vce.num_rings; i++)
391 if (adev->vce.ring[i].sched.ready)
393 ib_start_alignment = 4;
394 ib_size_alignment = 1;
396 case AMDGPU_HW_IP_UVD_ENC:
397 type = AMD_IP_BLOCK_TYPE_UVD;
398 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
399 if (adev->uvd.harvest_config & (1 << i))
402 for (j = 0; j < adev->uvd.num_enc_rings; j++)
403 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
406 ib_start_alignment = 64;
407 ib_size_alignment = 64;
409 case AMDGPU_HW_IP_VCN_DEC:
410 type = AMD_IP_BLOCK_TYPE_VCN;
411 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
412 if (adev->uvd.harvest_config & (1 << i))
415 if (adev->vcn.inst[i].ring_dec.sched.ready)
418 ib_start_alignment = 16;
419 ib_size_alignment = 16;
421 case AMDGPU_HW_IP_VCN_ENC:
422 type = AMD_IP_BLOCK_TYPE_VCN;
423 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
424 if (adev->uvd.harvest_config & (1 << i))
427 for (j = 0; j < adev->vcn.num_enc_rings; j++)
428 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
431 ib_start_alignment = 64;
432 ib_size_alignment = 1;
434 case AMDGPU_HW_IP_VCN_JPEG:
435 type = AMD_IP_BLOCK_TYPE_VCN;
436 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
437 if (adev->uvd.harvest_config & (1 << i))
440 if (adev->vcn.inst[i].ring_jpeg.sched.ready)
443 ib_start_alignment = 16;
444 ib_size_alignment = 16;
450 for (i = 0; i < adev->num_ip_blocks; i++)
451 if (adev->ip_blocks[i].version->type == type &&
452 adev->ip_blocks[i].status.valid)
455 if (i == adev->num_ip_blocks)
458 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
461 result->hw_ip_version_major = adev->ip_blocks[i].version->major;
462 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
463 result->capabilities_flags = 0;
464 result->available_rings = (1 << num_rings) - 1;
465 result->ib_start_alignment = ib_start_alignment;
466 result->ib_size_alignment = ib_size_alignment;
471 * Userspace get information ioctl
474 * amdgpu_info_ioctl - answer a device specific request.
476 * @adev: amdgpu device pointer
477 * @data: request object
480 * This function is used to pass device specific parameters to the userspace
481 * drivers. Examples include: pci device id, pipeline parms, tiling params,
483 * Returns 0 on success, -EINVAL on failure.
485 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
487 struct amdgpu_device *adev = dev->dev_private;
488 struct drm_amdgpu_info *info = data;
489 struct amdgpu_mode_info *minfo = &adev->mode_info;
490 void __user *out = (void __user *)(uintptr_t)info->return_pointer;
491 uint32_t size = info->return_size;
492 struct drm_crtc *crtc;
496 int ui32_size = sizeof(ui32);
498 if (!info->return_size || !info->return_pointer)
501 switch (info->query) {
502 case AMDGPU_INFO_ACCEL_WORKING:
503 ui32 = adev->accel_working;
504 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
505 case AMDGPU_INFO_CRTC_FROM_ID:
506 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
507 crtc = (struct drm_crtc *)minfo->crtcs[i];
508 if (crtc && crtc->base.id == info->mode_crtc.id) {
509 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
510 ui32 = amdgpu_crtc->crtc_id;
516 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
519 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
520 case AMDGPU_INFO_HW_IP_INFO: {
521 struct drm_amdgpu_info_hw_ip ip = {};
524 ret = amdgpu_hw_ip_info(adev, info, &ip);
528 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
529 return ret ? -EFAULT : 0;
531 case AMDGPU_INFO_HW_IP_COUNT: {
532 enum amd_ip_block_type type;
535 switch (info->query_hw_ip.type) {
536 case AMDGPU_HW_IP_GFX:
537 type = AMD_IP_BLOCK_TYPE_GFX;
539 case AMDGPU_HW_IP_COMPUTE:
540 type = AMD_IP_BLOCK_TYPE_GFX;
542 case AMDGPU_HW_IP_DMA:
543 type = AMD_IP_BLOCK_TYPE_SDMA;
545 case AMDGPU_HW_IP_UVD:
546 type = AMD_IP_BLOCK_TYPE_UVD;
548 case AMDGPU_HW_IP_VCE:
549 type = AMD_IP_BLOCK_TYPE_VCE;
551 case AMDGPU_HW_IP_UVD_ENC:
552 type = AMD_IP_BLOCK_TYPE_UVD;
554 case AMDGPU_HW_IP_VCN_DEC:
555 case AMDGPU_HW_IP_VCN_ENC:
556 case AMDGPU_HW_IP_VCN_JPEG:
557 type = AMD_IP_BLOCK_TYPE_VCN;
563 for (i = 0; i < adev->num_ip_blocks; i++)
564 if (adev->ip_blocks[i].version->type == type &&
565 adev->ip_blocks[i].status.valid &&
566 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
569 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
571 case AMDGPU_INFO_TIMESTAMP:
572 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
573 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
574 case AMDGPU_INFO_FW_VERSION: {
575 struct drm_amdgpu_info_firmware fw_info;
578 /* We only support one instance of each IP block right now. */
579 if (info->query_fw.ip_instance != 0)
582 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
586 return copy_to_user(out, &fw_info,
587 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
589 case AMDGPU_INFO_NUM_BYTES_MOVED:
590 ui64 = atomic64_read(&adev->num_bytes_moved);
591 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
592 case AMDGPU_INFO_NUM_EVICTIONS:
593 ui64 = atomic64_read(&adev->num_evictions);
594 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
595 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
596 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
597 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
598 case AMDGPU_INFO_VRAM_USAGE:
599 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
600 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
601 case AMDGPU_INFO_VIS_VRAM_USAGE:
602 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
603 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
604 case AMDGPU_INFO_GTT_USAGE:
605 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
606 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
607 case AMDGPU_INFO_GDS_CONFIG: {
608 struct drm_amdgpu_info_gds gds_info;
610 memset(&gds_info, 0, sizeof(gds_info));
611 gds_info.compute_partition_size = adev->gds.gds_size;
612 gds_info.gds_total_size = adev->gds.gds_size;
613 gds_info.gws_per_compute_partition = adev->gds.gws_size;
614 gds_info.oa_per_compute_partition = adev->gds.oa_size;
615 return copy_to_user(out, &gds_info,
616 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
618 case AMDGPU_INFO_VRAM_GTT: {
619 struct drm_amdgpu_info_vram_gtt vram_gtt;
621 vram_gtt.vram_size = adev->gmc.real_vram_size -
622 atomic64_read(&adev->vram_pin_size);
623 vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size -
624 atomic64_read(&adev->visible_pin_size);
625 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
626 vram_gtt.gtt_size *= PAGE_SIZE;
627 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
628 return copy_to_user(out, &vram_gtt,
629 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
631 case AMDGPU_INFO_MEMORY: {
632 struct drm_amdgpu_memory_info mem;
634 memset(&mem, 0, sizeof(mem));
635 mem.vram.total_heap_size = adev->gmc.real_vram_size;
636 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
637 atomic64_read(&adev->vram_pin_size);
638 mem.vram.heap_usage =
639 amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
640 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
642 mem.cpu_accessible_vram.total_heap_size =
643 adev->gmc.visible_vram_size;
644 mem.cpu_accessible_vram.usable_heap_size = adev->gmc.visible_vram_size -
645 atomic64_read(&adev->visible_pin_size);
646 mem.cpu_accessible_vram.heap_usage =
647 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
648 mem.cpu_accessible_vram.max_allocation =
649 mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
651 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size;
652 mem.gtt.total_heap_size *= PAGE_SIZE;
653 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
654 atomic64_read(&adev->gart_pin_size);
656 amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
657 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
659 return copy_to_user(out, &mem,
660 min((size_t)size, sizeof(mem)))
663 case AMDGPU_INFO_READ_MMR_REG: {
664 unsigned n, alloc_size;
666 unsigned se_num = (info->read_mmr_reg.instance >>
667 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
668 AMDGPU_INFO_MMR_SE_INDEX_MASK;
669 unsigned sh_num = (info->read_mmr_reg.instance >>
670 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
671 AMDGPU_INFO_MMR_SH_INDEX_MASK;
673 /* set full masks if the userspace set all bits
674 * in the bitfields */
675 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
677 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
680 if (info->read_mmr_reg.count > 128)
683 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
686 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
688 for (i = 0; i < info->read_mmr_reg.count; i++)
689 if (amdgpu_asic_read_register(adev, se_num, sh_num,
690 info->read_mmr_reg.dword_offset + i,
692 DRM_DEBUG_KMS("unallowed offset %#x\n",
693 info->read_mmr_reg.dword_offset + i);
697 n = copy_to_user(out, regs, min(size, alloc_size));
699 return n ? -EFAULT : 0;
701 case AMDGPU_INFO_DEV_INFO: {
702 struct drm_amdgpu_info_device dev_info = {};
705 dev_info.device_id = dev->pdev->device;
706 dev_info.chip_rev = adev->rev_id;
707 dev_info.external_rev = adev->external_rev_id;
708 dev_info.pci_rev = dev->pdev->revision;
709 dev_info.family = adev->family;
710 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
711 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
712 /* return all clocks in KHz */
713 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
714 if (adev->pm.dpm_enabled) {
715 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
716 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
717 } else if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
718 adev->virt.ops->get_pp_clk) {
719 dev_info.max_engine_clock = amdgpu_virt_get_sclk(adev, false) * 10;
720 dev_info.max_memory_clock = amdgpu_virt_get_mclk(adev, false) * 10;
722 dev_info.max_engine_clock = adev->clock.default_sclk * 10;
723 dev_info.max_memory_clock = adev->clock.default_mclk * 10;
725 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
726 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
727 adev->gfx.config.max_shader_engines;
728 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
730 dev_info.ids_flags = 0;
731 if (adev->flags & AMD_IS_APU)
732 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
733 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
734 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
736 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
737 vm_size -= AMDGPU_VA_RESERVED_SIZE;
739 /* Older VCE FW versions are buggy and can handle only 40bits */
740 if (adev->vce.fw_version &&
741 adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
742 vm_size = min(vm_size, 1ULL << 40);
744 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
745 dev_info.virtual_address_max =
746 min(vm_size, AMDGPU_GMC_HOLE_START);
748 if (vm_size > AMDGPU_GMC_HOLE_START) {
749 dev_info.high_va_offset = AMDGPU_GMC_HOLE_END;
750 dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
752 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
753 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
754 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
755 dev_info.cu_active_number = adev->gfx.cu_info.number;
756 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
757 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
758 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
759 sizeof(adev->gfx.cu_info.ao_cu_bitmap));
760 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
761 sizeof(adev->gfx.cu_info.bitmap));
762 dev_info.vram_type = adev->gmc.vram_type;
763 dev_info.vram_bit_width = adev->gmc.vram_width;
764 dev_info.vce_harvest_config = adev->vce.harvest_config;
765 dev_info.gc_double_offchip_lds_buf =
766 adev->gfx.config.double_offchip_lds_buf;
769 dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;
770 dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;
771 dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;
772 dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;
773 dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;
774 dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;
775 dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;
776 dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;
778 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
779 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
780 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
781 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
782 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
783 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
784 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
786 if (adev->family >= AMDGPU_FAMILY_NV)
787 dev_info.pa_sc_tile_steering_override =
788 adev->gfx.config.pa_sc_tile_steering_override;
790 return copy_to_user(out, &dev_info,
791 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
793 case AMDGPU_INFO_VCE_CLOCK_TABLE: {
795 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
796 struct amd_vce_state *vce_state;
798 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
799 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
801 vce_clk_table.entries[i].sclk = vce_state->sclk;
802 vce_clk_table.entries[i].mclk = vce_state->mclk;
803 vce_clk_table.entries[i].eclk = vce_state->evclk;
804 vce_clk_table.num_valid_entries++;
808 return copy_to_user(out, &vce_clk_table,
809 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
811 case AMDGPU_INFO_VBIOS: {
812 uint32_t bios_size = adev->bios_size;
814 switch (info->vbios_info.type) {
815 case AMDGPU_INFO_VBIOS_SIZE:
816 return copy_to_user(out, &bios_size,
817 min((size_t)size, sizeof(bios_size)))
819 case AMDGPU_INFO_VBIOS_IMAGE: {
821 uint32_t bios_offset = info->vbios_info.offset;
823 if (bios_offset >= bios_size)
826 bios = adev->bios + bios_offset;
827 return copy_to_user(out, bios,
828 min((size_t)size, (size_t)(bios_size - bios_offset)))
832 DRM_DEBUG_KMS("Invalid request %d\n",
833 info->vbios_info.type);
837 case AMDGPU_INFO_NUM_HANDLES: {
838 struct drm_amdgpu_info_num_handles handle;
840 switch (info->query_hw_ip.type) {
841 case AMDGPU_HW_IP_UVD:
842 /* Starting Polaris, we support unlimited UVD handles */
843 if (adev->asic_type < CHIP_POLARIS10) {
844 handle.uvd_max_handles = adev->uvd.max_handles;
845 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
847 return copy_to_user(out, &handle,
848 min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
858 case AMDGPU_INFO_SENSOR: {
859 if (!adev->pm.dpm_enabled)
862 switch (info->sensor_info.type) {
863 case AMDGPU_INFO_SENSOR_GFX_SCLK:
864 /* get sclk in Mhz */
865 if (amdgpu_dpm_read_sensor(adev,
866 AMDGPU_PP_SENSOR_GFX_SCLK,
867 (void *)&ui32, &ui32_size)) {
872 case AMDGPU_INFO_SENSOR_GFX_MCLK:
873 /* get mclk in Mhz */
874 if (amdgpu_dpm_read_sensor(adev,
875 AMDGPU_PP_SENSOR_GFX_MCLK,
876 (void *)&ui32, &ui32_size)) {
881 case AMDGPU_INFO_SENSOR_GPU_TEMP:
882 /* get temperature in millidegrees C */
883 if (amdgpu_dpm_read_sensor(adev,
884 AMDGPU_PP_SENSOR_GPU_TEMP,
885 (void *)&ui32, &ui32_size)) {
889 case AMDGPU_INFO_SENSOR_GPU_LOAD:
891 if (amdgpu_dpm_read_sensor(adev,
892 AMDGPU_PP_SENSOR_GPU_LOAD,
893 (void *)&ui32, &ui32_size)) {
897 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
898 /* get average GPU power */
899 if (amdgpu_dpm_read_sensor(adev,
900 AMDGPU_PP_SENSOR_GPU_POWER,
901 (void *)&ui32, &ui32_size)) {
906 case AMDGPU_INFO_SENSOR_VDDNB:
907 /* get VDDNB in millivolts */
908 if (amdgpu_dpm_read_sensor(adev,
909 AMDGPU_PP_SENSOR_VDDNB,
910 (void *)&ui32, &ui32_size)) {
914 case AMDGPU_INFO_SENSOR_VDDGFX:
915 /* get VDDGFX in millivolts */
916 if (amdgpu_dpm_read_sensor(adev,
917 AMDGPU_PP_SENSOR_VDDGFX,
918 (void *)&ui32, &ui32_size)) {
922 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
923 /* get stable pstate sclk in Mhz */
924 if (amdgpu_dpm_read_sensor(adev,
925 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
926 (void *)&ui32, &ui32_size)) {
931 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
932 /* get stable pstate mclk in Mhz */
933 if (amdgpu_dpm_read_sensor(adev,
934 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
935 (void *)&ui32, &ui32_size)) {
941 DRM_DEBUG_KMS("Invalid request %d\n",
942 info->sensor_info.type);
945 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
947 case AMDGPU_INFO_VRAM_LOST_COUNTER:
948 ui32 = atomic_read(&adev->vram_lost_counter);
949 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
950 case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
951 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
956 ras_mask = (uint64_t)ras->supported << 32 | ras->features;
958 return copy_to_user(out, &ras_mask,
959 min_t(u64, size, sizeof(ras_mask))) ?
963 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
971 * Outdated mess for old drm with Xorg being in charge (void function now).
974 * amdgpu_driver_lastclose_kms - drm callback for last close
976 * @dev: drm dev pointer
978 * Switch vga_switcheroo state after last close (all asics).
980 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
982 drm_fb_helper_lastclose(dev);
983 vga_switcheroo_process_delayed_switch();
987 * amdgpu_driver_open_kms - drm callback for open
989 * @dev: drm dev pointer
990 * @file_priv: drm file
992 * On device open, init vm on cayman+ (all asics).
993 * Returns 0 on success, error on failure.
995 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
997 struct amdgpu_device *adev = dev->dev_private;
998 struct amdgpu_fpriv *fpriv;
1001 /* Ensure IB tests are run on ring */
1002 flush_delayed_work(&adev->delayed_init_work);
1004 file_priv->driver_priv = NULL;
1006 r = pm_runtime_get_sync(dev->dev);
1010 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1011 if (unlikely(!fpriv)) {
1016 pasid = amdgpu_pasid_alloc(16);
1018 dev_warn(adev->dev, "No more PASIDs available!");
1021 r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
1025 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1026 if (!fpriv->prt_va) {
1031 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1032 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1034 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1035 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1040 mutex_init(&fpriv->bo_list_lock);
1041 idr_init(&fpriv->bo_list_handles);
1043 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
1045 file_priv->driver_priv = fpriv;
1049 amdgpu_vm_fini(adev, &fpriv->vm);
1053 amdgpu_pasid_free(pasid);
1058 pm_runtime_mark_last_busy(dev->dev);
1059 pm_runtime_put_autosuspend(dev->dev);
1065 * amdgpu_driver_postclose_kms - drm callback for post close
1067 * @dev: drm dev pointer
1068 * @file_priv: drm file
1070 * On device post close, tear down vm on cayman+ (all asics).
1072 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1073 struct drm_file *file_priv)
1075 struct amdgpu_device *adev = dev->dev_private;
1076 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1077 struct amdgpu_bo_list *list;
1078 struct amdgpu_bo *pd;
1085 pm_runtime_get_sync(dev->dev);
1087 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1088 amdgpu_uvd_free_handles(adev, file_priv);
1089 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1090 amdgpu_vce_free_handles(adev, file_priv);
1092 amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
1094 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1095 /* TODO: how to handle reserve failure */
1096 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1097 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
1098 fpriv->csa_va = NULL;
1099 amdgpu_bo_unreserve(adev->virt.csa_obj);
1102 pasid = fpriv->vm.pasid;
1103 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
1105 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1106 amdgpu_vm_fini(adev, &fpriv->vm);
1109 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1110 amdgpu_bo_unref(&pd);
1112 idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1113 amdgpu_bo_list_put(list);
1115 idr_destroy(&fpriv->bo_list_handles);
1116 mutex_destroy(&fpriv->bo_list_lock);
1119 file_priv->driver_priv = NULL;
1121 pm_runtime_mark_last_busy(dev->dev);
1122 pm_runtime_put_autosuspend(dev->dev);
1126 * VBlank related functions.
1129 * amdgpu_get_vblank_counter_kms - get frame count
1131 * @dev: drm dev pointer
1132 * @pipe: crtc to get the frame count from
1134 * Gets the frame count on the requested crtc (all asics).
1135 * Returns frame count on success, -EINVAL on failure.
1137 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
1139 struct amdgpu_device *adev = dev->dev_private;
1140 int vpos, hpos, stat;
1143 if (pipe >= adev->mode_info.num_crtc) {
1144 DRM_ERROR("Invalid crtc %u\n", pipe);
1148 /* The hw increments its frame counter at start of vsync, not at start
1149 * of vblank, as is required by DRM core vblank counter handling.
1150 * Cook the hw count here to make it appear to the caller as if it
1151 * incremented at start of vblank. We measure distance to start of
1152 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1153 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1154 * result by 1 to give the proper appearance to caller.
1156 if (adev->mode_info.crtcs[pipe]) {
1157 /* Repeat readout if needed to provide stable result if
1158 * we cross start of vsync during the queries.
1161 count = amdgpu_display_vblank_get_counter(adev, pipe);
1162 /* Ask amdgpu_display_get_crtc_scanoutpos to return
1163 * vpos as distance to start of vblank, instead of
1164 * regular vertical scanout pos.
1166 stat = amdgpu_display_get_crtc_scanoutpos(
1167 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1168 &vpos, &hpos, NULL, NULL,
1169 &adev->mode_info.crtcs[pipe]->base.hwmode);
1170 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1172 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1173 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1174 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1176 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1179 /* Bump counter if we are at >= leading edge of vblank,
1180 * but before vsync where vpos would turn negative and
1181 * the hw counter really increments.
1187 /* Fallback to use value as is. */
1188 count = amdgpu_display_vblank_get_counter(adev, pipe);
1189 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1196 * amdgpu_enable_vblank_kms - enable vblank interrupt
1198 * @dev: drm dev pointer
1199 * @pipe: crtc to enable vblank interrupt for
1201 * Enable the interrupt on the requested crtc (all asics).
1202 * Returns 0 on success, -EINVAL on failure.
1204 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1206 struct amdgpu_device *adev = dev->dev_private;
1207 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1209 return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1213 * amdgpu_disable_vblank_kms - disable vblank interrupt
1215 * @dev: drm dev pointer
1216 * @pipe: crtc to disable vblank interrupt for
1218 * Disable the interrupt on the requested crtc (all asics).
1220 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1222 struct amdgpu_device *adev = dev->dev_private;
1223 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1225 amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1228 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
1229 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1230 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1231 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1232 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
1233 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1234 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1236 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1237 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1238 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1239 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1240 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1241 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1242 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1243 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1244 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1245 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)
1247 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
1252 #if defined(CONFIG_DEBUG_FS)
1254 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1256 struct drm_info_node *node = (struct drm_info_node *) m->private;
1257 struct drm_device *dev = node->minor->dev;
1258 struct amdgpu_device *adev = dev->dev_private;
1259 struct drm_amdgpu_info_firmware fw_info;
1260 struct drm_amdgpu_query_fw query_fw;
1261 struct atom_context *ctx = adev->mode_info.atom_context;
1265 query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1266 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1269 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1270 fw_info.feature, fw_info.ver);
1273 query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1274 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1277 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1278 fw_info.feature, fw_info.ver);
1281 query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1282 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1285 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1286 fw_info.feature, fw_info.ver);
1289 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1290 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1293 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1294 fw_info.feature, fw_info.ver);
1297 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1298 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1301 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1302 fw_info.feature, fw_info.ver);
1305 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1306 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1309 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1310 fw_info.feature, fw_info.ver);
1313 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1314 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1317 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1318 fw_info.feature, fw_info.ver);
1320 /* RLC SAVE RESTORE LIST CNTL */
1321 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1322 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1325 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1326 fw_info.feature, fw_info.ver);
1328 /* RLC SAVE RESTORE LIST GPM MEM */
1329 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1330 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1333 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1334 fw_info.feature, fw_info.ver);
1336 /* RLC SAVE RESTORE LIST SRM MEM */
1337 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1338 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1341 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1342 fw_info.feature, fw_info.ver);
1345 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1347 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1350 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1351 fw_info.feature, fw_info.ver);
1354 if (adev->asic_type == CHIP_KAVERI ||
1355 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
1357 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1360 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1361 fw_info.feature, fw_info.ver);
1365 query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1366 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1369 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1370 fw_info.feature, fw_info.ver);
1374 query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1375 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1378 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1379 fw_info.feature, fw_info.ver);
1381 query_fw.fw_type = AMDGPU_INFO_FW_TA;
1382 for (i = 0; i < 2; i++) {
1384 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1387 seq_printf(m, "TA %s feature version: %u, firmware version: 0x%08x\n",
1388 i ? "RAS" : "XGMI", fw_info.feature, fw_info.ver);
1392 query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1393 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1396 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1397 fw_info.feature, fw_info.ver);
1400 query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1401 for (i = 0; i < adev->sdma.num_instances; i++) {
1403 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1406 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1407 i, fw_info.feature, fw_info.ver);
1411 query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1412 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1415 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1416 fw_info.feature, fw_info.ver);
1419 query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1420 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1423 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1424 fw_info.feature, fw_info.ver);
1427 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1432 static const struct drm_info_list amdgpu_firmware_info_list[] = {
1433 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1437 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1439 #if defined(CONFIG_DEBUG_FS)
1440 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1441 ARRAY_SIZE(amdgpu_firmware_info_list));