2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
27 * Kernel port Author: Dave Airlie
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drm_encoder.h>
36 #include <drm/drm_dp_helper.h>
37 #include <drm/drm_fixed.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_fb_helper.h>
40 #include <drm/drm_plane_helper.h>
41 #include <linux/i2c.h>
42 #include <linux/i2c-algo-bit.h>
43 #include <linux/hrtimer.h>
44 #include "amdgpu_irq.h"
46 #include <drm/drm_dp_mst_helper.h>
47 #include "modules/inc/mod_freesync.h"
51 struct amdgpu_encoder;
55 #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
56 #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
57 #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
58 #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
60 #define to_dm_plane_state(x) container_of(x, struct dm_plane_state, base);
62 #define AMDGPU_MAX_HPD_PINS 6
63 #define AMDGPU_MAX_CRTCS 6
64 #define AMDGPU_MAX_PLANES 6
65 #define AMDGPU_MAX_AFMT_BLOCKS 9
67 enum amdgpu_rmx_type {
74 enum amdgpu_underscan_type {
80 #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
81 #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10
90 AMDGPU_HPD_NONE = 0xff,
93 enum amdgpu_crtc_irq {
94 AMDGPU_CRTC_IRQ_VBLANK1 = 0,
95 AMDGPU_CRTC_IRQ_VBLANK2,
96 AMDGPU_CRTC_IRQ_VBLANK3,
97 AMDGPU_CRTC_IRQ_VBLANK4,
98 AMDGPU_CRTC_IRQ_VBLANK5,
99 AMDGPU_CRTC_IRQ_VBLANK6,
100 AMDGPU_CRTC_IRQ_VLINE1,
101 AMDGPU_CRTC_IRQ_VLINE2,
102 AMDGPU_CRTC_IRQ_VLINE3,
103 AMDGPU_CRTC_IRQ_VLINE4,
104 AMDGPU_CRTC_IRQ_VLINE5,
105 AMDGPU_CRTC_IRQ_VLINE6,
106 AMDGPU_CRTC_IRQ_NONE = 0xff
109 enum amdgpu_pageflip_irq {
110 AMDGPU_PAGEFLIP_IRQ_D1 = 0,
111 AMDGPU_PAGEFLIP_IRQ_D2,
112 AMDGPU_PAGEFLIP_IRQ_D3,
113 AMDGPU_PAGEFLIP_IRQ_D4,
114 AMDGPU_PAGEFLIP_IRQ_D5,
115 AMDGPU_PAGEFLIP_IRQ_D6,
116 AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
119 enum amdgpu_flip_status {
122 AMDGPU_FLIP_SUBMITTED
125 #define AMDGPU_MAX_I2C_BUS 16
127 /* amdgpu gpio-based i2c
128 * 1. "mask" reg and bits
129 * grabs the gpio pins for software use
131 * 2. "a" reg and bits
134 * 3. "en" reg and bits
135 * sets the pin direction
137 * 4. "y" reg and bits
141 struct amdgpu_i2c_bus_rec {
143 /* id used by atom */
145 /* id used by atom */
146 enum amdgpu_hpd_id hpd;
147 /* can be used with hw i2c engine */
149 /* uses multi-media i2c engine */
152 uint32_t mask_clk_reg;
153 uint32_t mask_data_reg;
157 uint32_t en_data_reg;
160 uint32_t mask_clk_mask;
161 uint32_t mask_data_mask;
163 uint32_t a_data_mask;
164 uint32_t en_clk_mask;
165 uint32_t en_data_mask;
167 uint32_t y_data_mask;
170 #define AMDGPU_MAX_BIOS_CONNECTOR 16
173 #define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0)
174 #define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1)
175 #define AMDGPU_PLL_USE_REF_DIV (1 << 2)
176 #define AMDGPU_PLL_LEGACY (1 << 3)
177 #define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4)
178 #define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5)
179 #define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6)
180 #define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7)
181 #define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8)
182 #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
183 #define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10)
184 #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
185 #define AMDGPU_PLL_USE_POST_DIV (1 << 12)
186 #define AMDGPU_PLL_IS_LCD (1 << 13)
187 #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
190 /* reference frequency */
191 uint32_t reference_freq;
194 uint32_t reference_div;
197 /* pll in/out limits */
200 uint32_t pll_out_min;
201 uint32_t pll_out_max;
202 uint32_t lcd_pll_out_min;
203 uint32_t lcd_pll_out_max;
207 uint32_t min_ref_div;
208 uint32_t max_ref_div;
209 uint32_t min_post_div;
210 uint32_t max_post_div;
211 uint32_t min_feedback_div;
212 uint32_t max_feedback_div;
213 uint32_t min_frac_feedback_div;
214 uint32_t max_frac_feedback_div;
216 /* flags for the current clock */
223 struct amdgpu_i2c_chan {
224 struct i2c_adapter adapter;
225 struct drm_device *dev;
226 struct i2c_algo_bit_data bit;
227 struct amdgpu_i2c_bus_rec rec;
228 struct drm_dp_aux aux;
238 bool last_buffer_filled_status;
240 struct amdgpu_audio_pin *pin;
246 struct amdgpu_audio_pin {
257 struct amdgpu_audio {
259 struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
263 struct amdgpu_display_funcs {
264 /* display watermarks */
265 void (*bandwidth_update)(struct amdgpu_device *adev);
266 /* get frame count */
267 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
268 /* set backlight level */
269 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
271 /* get backlight level */
272 u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);
274 bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
275 void (*hpd_set_polarity)(struct amdgpu_device *adev,
276 enum amdgpu_hpd_id hpd);
277 u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
279 void (*page_flip)(struct amdgpu_device *adev,
280 int crtc_id, u64 crtc_base, bool async);
281 int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
282 u32 *vbl, u32 *position);
283 /* display topology setup */
284 void (*add_encoder)(struct amdgpu_device *adev,
285 uint32_t encoder_enum,
286 uint32_t supported_device,
288 void (*add_connector)(struct amdgpu_device *adev,
289 uint32_t connector_id,
290 uint32_t supported_device,
292 struct amdgpu_i2c_bus_rec *i2c_bus,
293 uint16_t connector_object_id,
294 struct amdgpu_hpd *hpd,
295 struct amdgpu_router *router);
300 struct amdgpu_framebuffer {
301 struct drm_framebuffer base;
303 /* caching for later use */
307 struct amdgpu_fbdev {
308 struct drm_fb_helper helper;
309 struct amdgpu_framebuffer rfb;
310 struct list_head fbdev_list;
311 struct amdgpu_device *adev;
314 struct amdgpu_mode_info {
315 struct atom_context *atom_context;
316 struct card_info *atom_card_info;
317 bool mode_config_initialized;
318 struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
319 struct drm_plane *planes[AMDGPU_MAX_PLANES];
320 struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
321 /* DVI-I properties */
322 struct drm_property *coherent_mode_property;
323 /* DAC enable load detect */
324 struct drm_property *load_detect_property;
326 struct drm_property *underscan_property;
327 struct drm_property *underscan_hborder_property;
328 struct drm_property *underscan_vborder_property;
330 struct drm_property *audio_property;
332 struct drm_property *dither_property;
333 /* maximum number of bits per channel for monitor color */
334 struct drm_property *max_bpc_property;
335 /* Adaptive Backlight Modulation (power feature) */
336 struct drm_property *abm_level_property;
337 /* hardcoded DFP edid from BIOS */
338 struct edid *bios_hardcoded_edid;
339 int bios_hardcoded_edid_size;
341 /* pointer to fbdev info structure */
342 struct amdgpu_fbdev *rfbdev;
345 /* pointer to backlight encoder */
346 struct amdgpu_encoder *bl_encoder;
347 u8 bl_level; /* saved backlight level */
348 struct amdgpu_audio audio; /* audio stuff */
349 int num_crtc; /* number of crtcs */
350 int num_hpd; /* number of hpd pins */
351 int num_dig; /* number of dig blocks */
353 const struct amdgpu_display_funcs *funcs;
354 const enum drm_plane_type *plane_type;
357 #define AMDGPU_MAX_BL_LEVEL 0xFF
359 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
361 struct amdgpu_backlight_privdata {
362 struct amdgpu_encoder *encoder;
368 struct amdgpu_atom_ss {
370 uint16_t percentage_divider;
382 struct drm_crtc base;
386 uint32_t crtc_offset;
387 struct drm_gem_object *cursor_bo;
388 uint64_t cursor_addr;
395 int max_cursor_width;
396 int max_cursor_height;
397 enum amdgpu_rmx_type rmx_type;
402 struct drm_display_mode native_mode;
405 struct amdgpu_flip_work *pflip_works;
406 enum amdgpu_flip_status pflip_status;
407 int deferred_flip_completion;
408 u64 last_flip_vblank;
410 struct amdgpu_atom_ss ss;
414 u32 pll_reference_div;
417 struct drm_encoder *encoder;
418 struct drm_connector *connector;
423 u32 lb_vblank_lead_lines;
424 struct drm_display_mode hw_mode;
425 /* for virtual dce */
426 struct hrtimer vblank_timer;
427 enum amdgpu_interrupt_state vsync_timer_enabled;
430 struct drm_pending_vblank_event *event;
433 struct amdgpu_encoder_atom_dig {
437 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
440 uint16_t panel_pwr_delay;
443 struct drm_display_mode native_mode;
444 struct backlight_device *bl_dev;
446 uint8_t backlight_level;
448 struct amdgpu_afmt *afmt;
451 struct amdgpu_encoder {
452 struct drm_encoder base;
453 uint32_t encoder_enum;
456 uint32_t active_device;
458 uint32_t pixel_clock;
459 enum amdgpu_rmx_type rmx_type;
460 enum amdgpu_underscan_type underscan_type;
461 uint32_t underscan_hborder;
462 uint32_t underscan_vborder;
463 struct drm_display_mode native_mode;
465 int audio_polling_active;
470 struct amdgpu_connector_atom_dig {
472 u8 dpcd[DP_RECEIVER_CAP_SIZE];
479 struct amdgpu_gpio_rec {
488 enum amdgpu_hpd_id hpd;
490 struct amdgpu_gpio_rec gpio;
493 struct amdgpu_router {
495 struct amdgpu_i2c_bus_rec i2c_info;
500 u8 ddc_mux_control_pin;
505 u8 cd_mux_control_pin;
509 enum amdgpu_connector_audio {
510 AMDGPU_AUDIO_DISABLE = 0,
511 AMDGPU_AUDIO_ENABLE = 1,
512 AMDGPU_AUDIO_AUTO = 2
515 enum amdgpu_connector_dither {
516 AMDGPU_FMT_DITHER_DISABLE = 0,
517 AMDGPU_FMT_DITHER_ENABLE = 1,
520 struct amdgpu_dm_dp_aux {
521 struct drm_dp_aux aux;
522 struct ddc_service *ddc_service;
525 struct amdgpu_i2c_adapter {
526 struct i2c_adapter base;
528 struct ddc_service *ddc_service;
531 #define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux)
533 struct amdgpu_connector {
534 struct drm_connector base;
535 uint32_t connector_id;
537 struct amdgpu_i2c_chan *ddc_bus;
538 /* some systems have an hdmi and vga port with a shared ddc line */
541 /* we need to mind the EDID between detect
542 and get modes due to analog/digital/tvencoder */
545 bool dac_load_detect;
546 bool detected_by_load; /* if the connection status was determined by load */
547 uint16_t connector_object_id;
548 struct amdgpu_hpd hpd;
549 struct amdgpu_router router;
550 struct amdgpu_i2c_chan *router_bus;
551 enum amdgpu_connector_audio audio;
552 enum amdgpu_connector_dither dither;
553 unsigned pixelclock_for_modeset;
556 /* TODO: start to use this struct and remove same field from base one */
557 struct amdgpu_mst_connector {
558 struct amdgpu_connector base;
560 struct drm_dp_mst_topology_mgr mst_mgr;
561 struct amdgpu_dm_dp_aux dm_dp_aux;
562 struct drm_dp_mst_port *port;
563 struct amdgpu_connector *mst_port;
564 bool is_mst_connector;
565 struct amdgpu_encoder *mst_encoder;
568 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
569 ((em) == ATOM_ENCODER_MODE_DP_MST))
571 /* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */
572 #define DRM_SCANOUTPOS_VALID (1 << 0)
573 #define DRM_SCANOUTPOS_IN_VBLANK (1 << 1)
574 #define DRM_SCANOUTPOS_ACCURATE (1 << 2)
575 #define USE_REAL_VBLANKSTART (1 << 30)
576 #define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
578 void amdgpu_link_encoder_connector(struct drm_device *dev);
580 struct drm_connector *
581 amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
582 struct drm_connector *
583 amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
584 bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
587 u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
588 struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder);
590 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
593 void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
595 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
596 unsigned int pipe, unsigned int flags, int *vpos,
597 int *hpos, ktime_t *stime, ktime_t *etime,
598 const struct drm_display_mode *mode);
600 int amdgpu_display_framebuffer_init(struct drm_device *dev,
601 struct amdgpu_framebuffer *rfb,
602 const struct drm_mode_fb_cmd2 *mode_cmd,
603 struct drm_gem_object *obj);
605 int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
607 void amdgpu_enc_destroy(struct drm_encoder *encoder);
608 void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
609 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
610 const struct drm_display_mode *mode,
611 struct drm_display_mode *adjusted_mode);
612 void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
613 struct drm_display_mode *adjusted_mode);
614 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
617 int amdgpu_fbdev_init(struct amdgpu_device *adev);
618 void amdgpu_fbdev_fini(struct amdgpu_device *adev);
619 void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state);
620 int amdgpu_fbdev_total_size(struct amdgpu_device *adev);
621 bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj);
623 int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);
625 /* amdgpu_display.c */
626 void amdgpu_display_print_display_setup(struct drm_device *dev);
627 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev);
628 int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
629 struct drm_modeset_acquire_ctx *ctx);
630 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
631 struct drm_framebuffer *fb,
632 struct drm_pending_vblank_event *event,
633 uint32_t page_flip_flags, uint32_t target,
634 struct drm_modeset_acquire_ctx *ctx);
635 extern const struct drm_mode_config_funcs amdgpu_mode_funcs;