2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "amd_shared.h"
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include "amdgpu_pm.h"
31 #include <drm/amdgpu_drm.h>
32 #include "amdgpu_powerplay.h"
36 static int amdgpu_powerplay_init(struct amdgpu_device *adev)
39 struct amd_powerplay *amd_pp;
41 amd_pp = &(adev->powerplay);
43 if (adev->pp_enabled) {
44 #ifdef CONFIG_DRM_AMD_POWERPLAY
45 struct amd_pp_init *pp_init;
47 pp_init = kzalloc(sizeof(struct amd_pp_init), GFP_KERNEL);
52 pp_init->chip_family = adev->family;
53 pp_init->chip_id = adev->asic_type;
54 pp_init->device = amdgpu_cgs_create_device(adev);
56 ret = amd_powerplay_init(pp_init, amd_pp);
60 amd_pp->pp_handle = (void *)adev;
62 switch (adev->asic_type) {
63 #ifdef CONFIG_DRM_AMDGPU_CIK
66 amd_pp->ip_funcs = &ci_dpm_ip_funcs;
71 amd_pp->ip_funcs = &kv_dpm_ip_funcs;
75 amd_pp->ip_funcs = &iceland_dpm_ip_funcs;
78 amd_pp->ip_funcs = &tonga_dpm_ip_funcs;
81 amd_pp->ip_funcs = &fiji_dpm_ip_funcs;
85 amd_pp->ip_funcs = &cz_dpm_ip_funcs;
95 static int amdgpu_pp_early_init(void *handle)
97 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
100 #ifdef CONFIG_DRM_AMD_POWERPLAY
101 switch (adev->asic_type) {
104 adev->pp_enabled = true;
108 adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true;
112 adev->pp_enabled = (amdgpu_powerplay > 0) ? true : false;
114 /* These chips don't have powerplay implemenations */
122 adev->pp_enabled = false;
126 adev->pp_enabled = false;
129 ret = amdgpu_powerplay_init(adev);
133 if (adev->powerplay.ip_funcs->early_init)
134 ret = adev->powerplay.ip_funcs->early_init(
135 adev->powerplay.pp_handle);
140 static int amdgpu_pp_late_init(void *handle)
143 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
145 if (adev->powerplay.ip_funcs->late_init)
146 ret = adev->powerplay.ip_funcs->late_init(
147 adev->powerplay.pp_handle);
149 #ifdef CONFIG_DRM_AMD_POWERPLAY
150 if (adev->pp_enabled && adev->pm.dpm_enabled) {
151 amdgpu_pm_sysfs_init(adev);
152 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_COMPLETE_INIT, NULL, NULL);
158 static int amdgpu_pp_sw_init(void *handle)
161 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
163 if (adev->powerplay.ip_funcs->sw_init)
164 ret = adev->powerplay.ip_funcs->sw_init(
165 adev->powerplay.pp_handle);
167 #ifdef CONFIG_DRM_AMD_POWERPLAY
168 if (adev->pp_enabled)
169 adev->pm.dpm_enabled = true;
175 static int amdgpu_pp_sw_fini(void *handle)
178 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
180 if (adev->powerplay.ip_funcs->sw_fini)
181 ret = adev->powerplay.ip_funcs->sw_fini(
182 adev->powerplay.pp_handle);
189 static int amdgpu_pp_hw_init(void *handle)
192 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
194 if (adev->pp_enabled && adev->firmware.smu_load)
195 amdgpu_ucode_init_bo(adev);
197 if (adev->powerplay.ip_funcs->hw_init)
198 ret = adev->powerplay.ip_funcs->hw_init(
199 adev->powerplay.pp_handle);
204 static int amdgpu_pp_hw_fini(void *handle)
207 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
209 if (adev->powerplay.ip_funcs->hw_fini)
210 ret = adev->powerplay.ip_funcs->hw_fini(
211 adev->powerplay.pp_handle);
213 if (adev->pp_enabled && adev->firmware.smu_load)
214 amdgpu_ucode_fini_bo(adev);
219 static void amdgpu_pp_late_fini(void *handle)
221 #ifdef CONFIG_DRM_AMD_POWERPLAY
222 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
224 if (adev->pp_enabled) {
225 amdgpu_pm_sysfs_fini(adev);
226 amd_powerplay_fini(adev->powerplay.pp_handle);
229 if (adev->powerplay.ip_funcs->late_fini)
230 adev->powerplay.ip_funcs->late_fini(
231 adev->powerplay.pp_handle);
235 static int amdgpu_pp_suspend(void *handle)
238 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
240 if (adev->powerplay.ip_funcs->suspend)
241 ret = adev->powerplay.ip_funcs->suspend(
242 adev->powerplay.pp_handle);
246 static int amdgpu_pp_resume(void *handle)
249 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
251 if (adev->powerplay.ip_funcs->resume)
252 ret = adev->powerplay.ip_funcs->resume(
253 adev->powerplay.pp_handle);
257 static int amdgpu_pp_set_clockgating_state(void *handle,
258 enum amd_clockgating_state state)
261 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
263 if (adev->powerplay.ip_funcs->set_clockgating_state)
264 ret = adev->powerplay.ip_funcs->set_clockgating_state(
265 adev->powerplay.pp_handle, state);
269 static int amdgpu_pp_set_powergating_state(void *handle,
270 enum amd_powergating_state state)
273 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
275 if (adev->powerplay.ip_funcs->set_powergating_state)
276 ret = adev->powerplay.ip_funcs->set_powergating_state(
277 adev->powerplay.pp_handle, state);
282 static bool amdgpu_pp_is_idle(void *handle)
285 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
287 if (adev->powerplay.ip_funcs->is_idle)
288 ret = adev->powerplay.ip_funcs->is_idle(
289 adev->powerplay.pp_handle);
293 static int amdgpu_pp_wait_for_idle(void *handle)
296 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
298 if (adev->powerplay.ip_funcs->wait_for_idle)
299 ret = adev->powerplay.ip_funcs->wait_for_idle(
300 adev->powerplay.pp_handle);
304 static int amdgpu_pp_soft_reset(void *handle)
307 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
309 if (adev->powerplay.ip_funcs->soft_reset)
310 ret = adev->powerplay.ip_funcs->soft_reset(
311 adev->powerplay.pp_handle);
315 const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
316 .name = "amdgpu_powerplay",
317 .early_init = amdgpu_pp_early_init,
318 .late_init = amdgpu_pp_late_init,
319 .sw_init = amdgpu_pp_sw_init,
320 .sw_fini = amdgpu_pp_sw_fini,
321 .hw_init = amdgpu_pp_hw_init,
322 .hw_fini = amdgpu_pp_hw_fini,
323 .late_fini = amdgpu_pp_late_fini,
324 .suspend = amdgpu_pp_suspend,
325 .resume = amdgpu_pp_resume,
326 .is_idle = amdgpu_pp_is_idle,
327 .wait_for_idle = amdgpu_pp_wait_for_idle,
328 .soft_reset = amdgpu_pp_soft_reset,
329 .set_clockgating_state = amdgpu_pp_set_clockgating_state,
330 .set_powergating_state = amdgpu_pp_set_powergating_state,