drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_psp.h"
  30 #include "amdgpu_ucode.h"
  31 #include "soc15_common.h"
  32 #include "psp_v3_1.h"
  33 #include "psp_v10_0.h"
  34 #include "psp_v11_0.h"
  35
  36 static void psp_set_funcs(struct amdgpu_device *adev);
  37
  38 static int psp_early_init(void *handle)
  39 {
  40         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  41         struct psp_context *psp = &adev->psp;
  42
  43         psp_set_funcs(adev);
  44
  45         switch (adev->asic_type) {
  46         case CHIP_VEGA10:
  47         case CHIP_VEGA12:
  48                 psp_v3_1_set_psp_funcs(psp);
  49                 psp->autoload_supported = false;
  50                 break;
  51         case CHIP_RAVEN:
  52                 psp_v10_0_set_psp_funcs(psp);
  53                 psp->autoload_supported = false;
  54                 break;
  55         case CHIP_VEGA20:
  56         case CHIP_ARCTURUS:
  57                 psp_v11_0_set_psp_funcs(psp);
  58                 psp->autoload_supported = false;
  59                 break;
  60         case CHIP_NAVI10:
  61         case CHIP_NAVI14:
  62         case CHIP_NAVI12:
  63                 psp_v11_0_set_psp_funcs(psp);
  64                 psp->autoload_supported = true;
  65                 break;
  66         default:
  67                 return -EINVAL;
  68         }
  69
  70         psp->adev = adev;
  71
  72         return 0;
  73 }
  74
  75 static int psp_sw_init(void *handle)
  76 {
  77         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  78         struct psp_context *psp = &adev->psp;
  79         int ret;
  80
  81         ret = psp_init_microcode(psp);
  82         if (ret) {
  83                 DRM_ERROR("Failed to load psp firmware!\n");
  84                 return ret;
  85         }
  86
  87         return 0;
  88 }
  89
  90 static int psp_sw_fini(void *handle)
  91 {
  92         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  93
  94         release_firmware(adev->psp.sos_fw);
  95         adev->psp.sos_fw = NULL;
  96         release_firmware(adev->psp.asd_fw);
  97         adev->psp.asd_fw = NULL;
  98         if (adev->psp.ta_fw) {
  99                 release_firmware(adev->psp.ta_fw);
 100                 adev->psp.ta_fw = NULL;
 101         }
 102         return 0;
 103 }
 104
 105 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 106                  uint32_t reg_val, uint32_t mask, bool check_changed)
 107 {
 108         uint32_t val;
 109         int i;
 110         struct amdgpu_device *adev = psp->adev;
 111
 112         for (i = 0; i < adev->usec_timeout; i++) {
 113                 val = RREG32(reg_index);
 114                 if (check_changed) {
 115                         if (val != reg_val)
 116                                 return 0;
 117                 } else {
 118                         if ((val & mask) == reg_val)
 119                                 return 0;
 120                 }
 121                 udelay(1);
 122         }
 123
 124         return -ETIME;
 125 }
 126
 127 static int
 128 psp_cmd_submit_buf(struct psp_context *psp,
 129                    struct amdgpu_firmware_info *ucode,
 130                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 131 {
 132         int ret;
 133         int index;
 134         int timeout = 2000;
 135
 136         mutex_lock(&psp->mutex);
 137
 138         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 139
 140         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 141
 142         index = atomic_inc_return(&psp->fence_value);
 143         ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
 144                              fence_mc_addr, index);
 145         if (ret) {
 146                 atomic_dec(&psp->fence_value);
 147                 mutex_unlock(&psp->mutex);
 148                 return ret;
 149         }
 150
 151         while (*((unsigned int *)psp->fence_buf) != index) {
 152                 if (--timeout == 0)
 153                         break;
 154                 msleep(1);
 155         }
 156
 157         /* In some cases, psp response status is not 0 even there is no
 158          * problem while the command is submitted. Some version of PSP FW
 159          * doesn't write 0 to that field.
 160          * So here we would like to only print a warning instead of an error
 161          * during psp initialization to avoid breaking hw_init and it doesn't
 162          * return -EINVAL.
 163          */
 164         if (psp->cmd_buf_mem->resp.status || !timeout) {
 165                 if (ucode)
 166                         DRM_WARN("failed to load ucode id (%d) ",
 167                                   ucode->ucode_id);
 168                 DRM_WARN("psp command failed and response status is (0x%X)\n",
 169                           psp->cmd_buf_mem->resp.status & GFX_CMD_STATUS_MASK);
 170                 if (!timeout) {
 171                         mutex_unlock(&psp->mutex);
 172                         return -EINVAL;
 173                 }
 174         }
 175
 176         /* get xGMI session id from response buffer */
 177         cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id;
 178
 179         if (ucode) {
 180                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 181                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 182         }
 183         mutex_unlock(&psp->mutex);
 184
 185         return ret;
 186 }
 187
 188 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 189                                  struct psp_gfx_cmd_resp *cmd,
 190                                  uint64_t tmr_mc, uint32_t size)
 191 {
 192         if (psp_support_vmr_ring(psp))
 193                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 194         else
 195                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 196         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 197         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 198         cmd->cmd.cmd_setup_tmr.buf_size = size;
 199 }
 200
 201 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 202                                       uint64_t pri_buf_mc, uint32_t size)
 203 {
 204         cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
 205         cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
 206         cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
 207         cmd->cmd.cmd_load_toc.toc_size = size;
 208 }
 209
 210 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
 211 static int psp_load_toc(struct psp_context *psp,
 212                         uint32_t *tmr_size)
 213 {
 214         int ret;
 215         struct psp_gfx_cmd_resp *cmd;
 216
 217         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 218         if (!cmd)
 219                 return -ENOMEM;
 220         /* Copy toc to psp firmware private buffer */
 221         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 222         memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size);
 223
 224         psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size);
 225
 226         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 227                                  psp->fence_buf_mc_addr);
 228         if (!ret)
 229                 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
 230         kfree(cmd);
 231         return ret;
 232 }
 233
 234 /* Set up Trusted Memory Region */
 235 static int psp_tmr_init(struct psp_context *psp)
 236 {
 237         int ret;
 238         int tmr_size;
 239
 240         /*
 241          * According to HW engineer, they prefer the TMR address be "naturally
 242          * aligned" , e.g. the start address be an integer divide of TMR size.
 243          *
 244          * Note: this memory need be reserved till the driver
 245          * uninitializes.
 246          */
 247         tmr_size = PSP_TMR_SIZE;
 248
 249         /* For ASICs support RLC autoload, psp will parse the toc
 250          * and calculate the total size of TMR needed */
 251         if (psp->toc_start_addr &&
 252             psp->toc_bin_size &&
 253             psp->fw_pri_buf) {
 254                 ret = psp_load_toc(psp, &tmr_size);
 255                 if (ret) {
 256                         DRM_ERROR("Failed to load toc\n");
 257                         return ret;
 258                 }
 259         }
 260
 261         ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
 262                                       AMDGPU_GEM_DOMAIN_VRAM,
 263                                       &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 264
 265         return ret;
 266 }
 267
 268 static int psp_tmr_load(struct psp_context *psp)
 269 {
 270         int ret;
 271         struct psp_gfx_cmd_resp *cmd;
 272
 273         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 274         if (!cmd)
 275                 return -ENOMEM;
 276
 277         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr,
 278                              amdgpu_bo_size(psp->tmr_bo));
 279         DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 280                  amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 281
 282         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 283                                  psp->fence_buf_mc_addr);
 284         if (ret)
 285                 goto failed;
 286
 287         kfree(cmd);
 288
 289         return 0;
 290
 291 failed:
 292         kfree(cmd);
 293         return ret;
 294 }
 295
 296 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 297                                  uint64_t asd_mc, uint64_t asd_mc_shared,
 298                                  uint32_t size, uint32_t shared_size)
 299 {
 300         cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
 301         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
 302         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
 303         cmd->cmd.cmd_load_ta.app_len = size;
 304
 305         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
 306         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
 307         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 308 }
 309
 310 static int psp_asd_init(struct psp_context *psp)
 311 {
 312         int ret;
 313
 314         /*
 315          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 316          * physical) for shared ASD <-> Driver
 317          */
 318         ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
 319                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 320                                       &psp->asd_shared_bo,
 321                                       &psp->asd_shared_mc_addr,
 322                                       &psp->asd_shared_buf);
 323
 324         return ret;
 325 }
 326
 327 static int psp_asd_load(struct psp_context *psp)
 328 {
 329         int ret;
 330         struct psp_gfx_cmd_resp *cmd;
 331
 332         /* If PSP version doesn't match ASD version, asd loading will be failed.
 333          * add workaround to bypass it for sriov now.
 334          * TODO: add version check to make it common
 335          */
 336         if (amdgpu_sriov_vf(psp->adev))
 337                 return 0;
 338
 339         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 340         if (!cmd)
 341                 return -ENOMEM;
 342
 343         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 344         memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
 345
 346         psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
 347                              psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
 348
 349         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 350                                  psp->fence_buf_mc_addr);
 351
 352         kfree(cmd);
 353
 354         return ret;
 355 }
 356
 357 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 358                 uint32_t id, uint32_t value)
 359 {
 360         cmd->cmd_id = GFX_CMD_ID_PROG_REG;
 361         cmd->cmd.cmd_setup_reg_prog.reg_value = value;
 362         cmd->cmd.cmd_setup_reg_prog.reg_id = id;
 363 }
 364
 365 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
 366                 uint32_t value)
 367 {
 368         struct psp_gfx_cmd_resp *cmd = NULL;
 369         int ret = 0;
 370
 371         if (reg >= PSP_REG_LAST)
 372                 return -EINVAL;
 373
 374         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 375         if (!cmd)
 376                 return -ENOMEM;
 377
 378         psp_prep_reg_prog_cmd_buf(cmd, reg, value);
 379         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 380
 381         kfree(cmd);
 382         return ret;
 383 }
 384
 385 static void psp_prep_xgmi_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 386                                           uint64_t xgmi_ta_mc, uint64_t xgmi_mc_shared,
 387                                           uint32_t xgmi_ta_size, uint32_t shared_size)
 388 {
 389         cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
 390         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(xgmi_ta_mc);
 391         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(xgmi_ta_mc);
 392         cmd->cmd.cmd_load_ta.app_len = xgmi_ta_size;
 393
 394         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(xgmi_mc_shared);
 395         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(xgmi_mc_shared);
 396         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 397 }
 398
 399 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
 400 {
 401         int ret;
 402
 403         /*
 404          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 405          * physical) for xgmi ta <-> Driver
 406          */
 407         ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE,
 408                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 409                                       &psp->xgmi_context.xgmi_shared_bo,
 410                                       &psp->xgmi_context.xgmi_shared_mc_addr,
 411                                       &psp->xgmi_context.xgmi_shared_buf);
 412
 413         return ret;
 414 }
 415
 416 static int psp_xgmi_load(struct psp_context *psp)
 417 {
 418         int ret;
 419         struct psp_gfx_cmd_resp *cmd;
 420
 421         /*
 422          * TODO: bypass the loading in sriov for now
 423          */
 424         if (amdgpu_sriov_vf(psp->adev))
 425                 return 0;
 426
 427         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 428         if (!cmd)
 429                 return -ENOMEM;
 430
 431         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 432         memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
 433
 434         psp_prep_xgmi_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
 435                                       psp->xgmi_context.xgmi_shared_mc_addr,
 436                                       psp->ta_xgmi_ucode_size, PSP_XGMI_SHARED_MEM_SIZE);
 437
 438         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 439                                  psp->fence_buf_mc_addr);
 440
 441         if (!ret) {
 442                 psp->xgmi_context.initialized = 1;
 443                 psp->xgmi_context.session_id = cmd->resp.session_id;
 444         }
 445
 446         kfree(cmd);
 447
 448         return ret;
 449 }
 450
 451 static void psp_prep_xgmi_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 452                                             uint32_t xgmi_session_id)
 453 {
 454         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 455         cmd->cmd.cmd_unload_ta.session_id = xgmi_session_id;
 456 }
 457
 458 static int psp_xgmi_unload(struct psp_context *psp)
 459 {
 460         int ret;
 461         struct psp_gfx_cmd_resp *cmd;
 462
 463         /*
 464          * TODO: bypass the unloading in sriov for now
 465          */
 466         if (amdgpu_sriov_vf(psp->adev))
 467                 return 0;
 468
 469         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 470         if (!cmd)
 471                 return -ENOMEM;
 472
 473         psp_prep_xgmi_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);
 474
 475         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 476                                  psp->fence_buf_mc_addr);
 477
 478         kfree(cmd);
 479
 480         return ret;
 481 }
 482
 483 static void psp_prep_xgmi_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 484                                             uint32_t ta_cmd_id,
 485                                             uint32_t xgmi_session_id)
 486 {
 487         cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
 488         cmd->cmd.cmd_invoke_cmd.session_id = xgmi_session_id;
 489         cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
 490         /* Note: cmd_invoke_cmd.buf is not used for now */
 491 }
 492
 493 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
 494 {
 495         int ret;
 496         struct psp_gfx_cmd_resp *cmd;
 497
 498         /*
 499          * TODO: bypass the loading in sriov for now
 500         */
 501         if (amdgpu_sriov_vf(psp->adev))
 502                 return 0;
 503
 504         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 505         if (!cmd)
 506                 return -ENOMEM;
 507
 508         psp_prep_xgmi_ta_invoke_cmd_buf(cmd, ta_cmd_id,
 509                                         psp->xgmi_context.session_id);
 510
 511         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 512                                  psp->fence_buf_mc_addr);
 513
 514         kfree(cmd);
 515
 516         return ret;
 517 }
 518
 519 static int psp_xgmi_terminate(struct psp_context *psp)
 520 {
 521         int ret;
 522
 523         if (!psp->xgmi_context.initialized)
 524                 return 0;
 525
 526         ret = psp_xgmi_unload(psp);
 527         if (ret)
 528                 return ret;
 529
 530         psp->xgmi_context.initialized = 0;
 531
 532         /* free xgmi shared memory */
 533         amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo,
 534                         &psp->xgmi_context.xgmi_shared_mc_addr,
 535                         &psp->xgmi_context.xgmi_shared_buf);
 536
 537         return 0;
 538 }
 539
 540 static int psp_xgmi_initialize(struct psp_context *psp)
 541 {
 542         struct ta_xgmi_shared_memory *xgmi_cmd;
 543         int ret;
 544
 545         if (!psp->adev->psp.ta_fw)
 546                 return -ENOENT;
 547
 548         if (!psp->xgmi_context.initialized) {
 549                 ret = psp_xgmi_init_shared_buf(psp);
 550                 if (ret)
 551                         return ret;
 552         }
 553
 554         /* Load XGMI TA */
 555         ret = psp_xgmi_load(psp);
 556         if (ret)
 557                 return ret;
 558
 559         /* Initialize XGMI session */
 560         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf);
 561         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 562         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
 563
 564         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 565
 566         return ret;
 567 }
 568
 569 // ras begin
 570 static void psp_prep_ras_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 571                 uint64_t ras_ta_mc, uint64_t ras_mc_shared,
 572                 uint32_t ras_ta_size, uint32_t shared_size)
 573 {
 574         cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
 575         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ras_ta_mc);
 576         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ras_ta_mc);
 577         cmd->cmd.cmd_load_ta.app_len = ras_ta_size;
 578
 579         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ras_mc_shared);
 580         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ras_mc_shared);
 581         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 582 }
 583
 584 static int psp_ras_init_shared_buf(struct psp_context *psp)
 585 {
 586         int ret;
 587
 588         /*
 589          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 590          * physical) for ras ta <-> Driver
 591          */
 592         ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE,
 593                         PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 594                         &psp->ras.ras_shared_bo,
 595                         &psp->ras.ras_shared_mc_addr,
 596                         &psp->ras.ras_shared_buf);
 597
 598         return ret;
 599 }
 600
 601 static int psp_ras_load(struct psp_context *psp)
 602 {
 603         int ret;
 604         struct psp_gfx_cmd_resp *cmd;
 605
 606         /*
 607          * TODO: bypass the loading in sriov for now
 608          */
 609         if (amdgpu_sriov_vf(psp->adev))
 610                 return 0;
 611
 612         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 613         if (!cmd)
 614                 return -ENOMEM;
 615
 616         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 617         memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size);
 618
 619         psp_prep_ras_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
 620                         psp->ras.ras_shared_mc_addr,
 621                         psp->ta_ras_ucode_size, PSP_RAS_SHARED_MEM_SIZE);
 622
 623         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 624                         psp->fence_buf_mc_addr);
 625
 626         if (!ret) {
 627                 psp->ras.ras_initialized = 1;
 628                 psp->ras.session_id = cmd->resp.session_id;
 629         }
 630
 631         kfree(cmd);
 632
 633         return ret;
 634 }
 635
 636 static void psp_prep_ras_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 637                                                 uint32_t ras_session_id)
 638 {
 639         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 640         cmd->cmd.cmd_unload_ta.session_id = ras_session_id;
 641 }
 642
 643 static int psp_ras_unload(struct psp_context *psp)
 644 {
 645         int ret;
 646         struct psp_gfx_cmd_resp *cmd;
 647
 648         /*
 649          * TODO: bypass the unloading in sriov for now
 650          */
 651         if (amdgpu_sriov_vf(psp->adev))
 652                 return 0;
 653
 654         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 655         if (!cmd)
 656                 return -ENOMEM;
 657
 658         psp_prep_ras_ta_unload_cmd_buf(cmd, psp->ras.session_id);
 659
 660         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 661                         psp->fence_buf_mc_addr);
 662
 663         kfree(cmd);
 664
 665         return ret;
 666 }
 667
 668 static void psp_prep_ras_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 669                 uint32_t ta_cmd_id,
 670                 uint32_t ras_session_id)
 671 {
 672         cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
 673         cmd->cmd.cmd_invoke_cmd.session_id = ras_session_id;
 674         cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
 675         /* Note: cmd_invoke_cmd.buf is not used for now */
 676 }
 677
 678 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
 679 {
 680         int ret;
 681         struct psp_gfx_cmd_resp *cmd;
 682
 683         /*
 684          * TODO: bypass the loading in sriov for now
 685          */
 686         if (amdgpu_sriov_vf(psp->adev))
 687                 return 0;
 688
 689         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 690         if (!cmd)
 691                 return -ENOMEM;
 692
 693         psp_prep_ras_ta_invoke_cmd_buf(cmd, ta_cmd_id,
 694                         psp->ras.session_id);
 695
 696         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 697                         psp->fence_buf_mc_addr);
 698
 699         kfree(cmd);
 700
 701         return ret;
 702 }
 703
 704 int psp_ras_enable_features(struct psp_context *psp,
 705                 union ta_ras_cmd_input *info, bool enable)
 706 {
 707         struct ta_ras_shared_memory *ras_cmd;
 708         int ret;
 709
 710         if (!psp->ras.ras_initialized)
 711                 return -EINVAL;
 712
 713         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
 714         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
 715
 716         if (enable)
 717                 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
 718         else
 719                 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
 720
 721         ras_cmd->ras_in_message = *info;
 722
 723         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
 724         if (ret)
 725                 return -EINVAL;
 726
 727         return ras_cmd->ras_status;
 728 }
 729
 730 static int psp_ras_terminate(struct psp_context *psp)
 731 {
 732         int ret;
 733
 734         if (!psp->ras.ras_initialized)
 735                 return 0;
 736
 737         ret = psp_ras_unload(psp);
 738         if (ret)
 739                 return ret;
 740
 741         psp->ras.ras_initialized = 0;
 742
 743         /* free ras shared memory */
 744         amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo,
 745                         &psp->ras.ras_shared_mc_addr,
 746                         &psp->ras.ras_shared_buf);
 747
 748         return 0;
 749 }
 750
 751 static int psp_ras_initialize(struct psp_context *psp)
 752 {
 753         int ret;
 754
 755         if (!psp->ras.ras_initialized) {
 756                 ret = psp_ras_init_shared_buf(psp);
 757                 if (ret)
 758                         return ret;
 759         }
 760
 761         ret = psp_ras_load(psp);
 762         if (ret)
 763                 return ret;
 764
 765         return 0;
 766 }
 767 // ras end
 768
 769 static int psp_hw_start(struct psp_context *psp)
 770 {
 771         struct amdgpu_device *adev = psp->adev;
 772         int ret;
 773
 774         if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
 775                 if (psp->kdb_bin_size &&
 776                     (psp->funcs->bootloader_load_kdb != NULL)) {
 777                         ret = psp_bootloader_load_kdb(psp);
 778                         if (ret) {
 779                                 DRM_ERROR("PSP load kdb failed!\n");
 780                                 return ret;
 781                         }
 782                 }
 783
 784                 ret = psp_bootloader_load_sysdrv(psp);
 785                 if (ret) {
 786                         DRM_ERROR("PSP load sysdrv failed!\n");
 787                         return ret;
 788                 }
 789
 790                 ret = psp_bootloader_load_sos(psp);
 791                 if (ret) {
 792                         DRM_ERROR("PSP load sos failed!\n");
 793                         return ret;
 794                 }
 795         }
 796
 797         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
 798         if (ret) {
 799                 DRM_ERROR("PSP create ring failed!\n");
 800                 return ret;
 801         }
 802
 803         ret = psp_tmr_init(psp);
 804         if (ret) {
 805                 DRM_ERROR("PSP tmr init failed!\n");
 806                 return ret;
 807         }
 808
 809         ret = psp_tmr_load(psp);
 810         if (ret) {
 811                 DRM_ERROR("PSP load tmr failed!\n");
 812                 return ret;
 813         }
 814
 815         ret = psp_asd_init(psp);
 816         if (ret) {
 817                 DRM_ERROR("PSP asd init failed!\n");
 818                 return ret;
 819         }
 820
 821         ret = psp_asd_load(psp);
 822         if (ret) {
 823                 DRM_ERROR("PSP load asd failed!\n");
 824                 return ret;
 825         }
 826
 827         if (adev->gmc.xgmi.num_physical_nodes > 1) {
 828                 ret = psp_xgmi_initialize(psp);
 829                 /* Warning the XGMI seesion initialize failure
 830                  * Instead of stop driver initialization
 831                  */
 832                 if (ret)
 833                         dev_err(psp->adev->dev,
 834                                 "XGMI: Failed to initialize XGMI session\n");
 835         }
 836
 837         if (psp->adev->psp.ta_fw) {
 838                 ret = psp_ras_initialize(psp);
 839                 if (ret)
 840                         dev_err(psp->adev->dev,
 841                                         "RAS: Failed to initialize RAS\n");
 842         }
 843
 844         return 0;
 845 }
 846
 847 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
 848                            enum psp_gfx_fw_type *type)
 849 {
 850         switch (ucode->ucode_id) {
 851         case AMDGPU_UCODE_ID_SDMA0:
 852                 *type = GFX_FW_TYPE_SDMA0;
 853                 break;
 854         case AMDGPU_UCODE_ID_SDMA1:
 855                 *type = GFX_FW_TYPE_SDMA1;
 856                 break;
 857         case AMDGPU_UCODE_ID_SDMA2:
 858                 *type = GFX_FW_TYPE_SDMA2;
 859                 break;
 860         case AMDGPU_UCODE_ID_SDMA3:
 861                 *type = GFX_FW_TYPE_SDMA3;
 862                 break;
 863         case AMDGPU_UCODE_ID_SDMA4:
 864                 *type = GFX_FW_TYPE_SDMA4;
 865                 break;
 866         case AMDGPU_UCODE_ID_SDMA5:
 867                 *type = GFX_FW_TYPE_SDMA5;
 868                 break;
 869         case AMDGPU_UCODE_ID_SDMA6:
 870                 *type = GFX_FW_TYPE_SDMA6;
 871                 break;
 872         case AMDGPU_UCODE_ID_SDMA7:
 873                 *type = GFX_FW_TYPE_SDMA7;
 874                 break;
 875         case AMDGPU_UCODE_ID_CP_CE:
 876                 *type = GFX_FW_TYPE_CP_CE;
 877                 break;
 878         case AMDGPU_UCODE_ID_CP_PFP:
 879                 *type = GFX_FW_TYPE_CP_PFP;
 880                 break;
 881         case AMDGPU_UCODE_ID_CP_ME:
 882                 *type = GFX_FW_TYPE_CP_ME;
 883                 break;
 884         case AMDGPU_UCODE_ID_CP_MEC1:
 885                 *type = GFX_FW_TYPE_CP_MEC;
 886                 break;
 887         case AMDGPU_UCODE_ID_CP_MEC1_JT:
 888                 *type = GFX_FW_TYPE_CP_MEC_ME1;
 889                 break;
 890         case AMDGPU_UCODE_ID_CP_MEC2:
 891                 *type = GFX_FW_TYPE_CP_MEC;
 892                 break;
 893         case AMDGPU_UCODE_ID_CP_MEC2_JT:
 894                 *type = GFX_FW_TYPE_CP_MEC_ME2;
 895                 break;
 896         case AMDGPU_UCODE_ID_RLC_G:
 897                 *type = GFX_FW_TYPE_RLC_G;
 898                 break;
 899         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
 900                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
 901                 break;
 902         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
 903                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
 904                 break;
 905         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
 906                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
 907                 break;
 908         case AMDGPU_UCODE_ID_SMC:
 909                 *type = GFX_FW_TYPE_SMU;
 910                 break;
 911         case AMDGPU_UCODE_ID_UVD:
 912                 *type = GFX_FW_TYPE_UVD;
 913                 break;
 914         case AMDGPU_UCODE_ID_UVD1:
 915                 *type = GFX_FW_TYPE_UVD1;
 916                 break;
 917         case AMDGPU_UCODE_ID_VCE:
 918                 *type = GFX_FW_TYPE_VCE;
 919                 break;
 920         case AMDGPU_UCODE_ID_VCN:
 921                 *type = GFX_FW_TYPE_VCN;
 922                 break;
 923         case AMDGPU_UCODE_ID_DMCU_ERAM:
 924                 *type = GFX_FW_TYPE_DMCU_ERAM;
 925                 break;
 926         case AMDGPU_UCODE_ID_DMCU_INTV:
 927                 *type = GFX_FW_TYPE_DMCU_ISR;
 928                 break;
 929         case AMDGPU_UCODE_ID_VCN0_RAM:
 930                 *type = GFX_FW_TYPE_VCN0_RAM;
 931                 break;
 932         case AMDGPU_UCODE_ID_VCN1_RAM:
 933                 *type = GFX_FW_TYPE_VCN1_RAM;
 934                 break;
 935         case AMDGPU_UCODE_ID_MAXIMUM:
 936         default:
 937                 return -EINVAL;
 938         }
 939
 940         return 0;
 941 }
 942
 943 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
 944                                        struct psp_gfx_cmd_resp *cmd)
 945 {
 946         int ret;
 947         uint64_t fw_mem_mc_addr = ucode->mc_addr;
 948
 949         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 950
 951         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 952         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
 953         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
 954         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
 955
 956         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
 957         if (ret)
 958                 DRM_ERROR("Unknown firmware type\n");
 959
 960         return ret;
 961 }
 962
 963 static int psp_execute_np_fw_load(struct psp_context *psp,
 964                                struct amdgpu_firmware_info *ucode)
 965 {
 966         int ret = 0;
 967
 968         ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd);
 969         if (ret)
 970                 return ret;
 971
 972         ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
 973                                  psp->fence_buf_mc_addr);
 974
 975         return ret;
 976 }
 977
 978 static int psp_np_fw_load(struct psp_context *psp)
 979 {
 980         int i, ret;
 981         struct amdgpu_firmware_info *ucode;
 982         struct amdgpu_device* adev = psp->adev;
 983
 984         if (psp->autoload_supported) {
 985                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 986                 if (!ucode->fw)
 987                         goto out;
 988
 989                 ret = psp_execute_np_fw_load(psp, ucode);
 990                 if (ret)
 991                         return ret;
 992         }
 993
 994 out:
 995         for (i = 0; i < adev->firmware.max_ucodes; i++) {
 996                 ucode = &adev->firmware.ucode[i];
 997                 if (!ucode->fw)
 998                         continue;
 999
1000                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
1001                     (psp_smu_reload_quirk(psp) || psp->autoload_supported))
1002                         continue;
1003
1004                 if (amdgpu_sriov_vf(adev) &&
1005                    (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
1006                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
1007                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
1008                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
1009                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
1010                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
1011                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
1012                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
1013                     || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
1014                         /*skip ucode loading in SRIOV VF */
1015                         continue;
1016
1017                 if (psp->autoload_supported &&
1018                     (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
1019                      ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
1020                         /* skip mec JT when autoload is enabled */
1021                         continue;
1022
1023                 ret = psp_execute_np_fw_load(psp, ucode);
1024                 if (ret)
1025                         return ret;
1026
1027                 /* Start rlc autoload after psp recieved all the gfx firmware */
1028                 if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM ||
1029                     (adev->asic_type == CHIP_NAVI12 && ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G)) {
1030                         ret = psp_rlc_autoload(psp);
1031                         if (ret) {
1032                                 DRM_ERROR("Failed to start rlc autoload\n");
1033                                 return ret;
1034                         }
1035                 }
1036 #if 0
1037                 /* check if firmware loaded sucessfully */
1038                 if (!amdgpu_psp_check_fw_loading_status(adev, i))
1039                         return -EINVAL;
1040 #endif
1041         }
1042
1043         return 0;
1044 }
1045
1046 static int psp_load_fw(struct amdgpu_device *adev)
1047 {
1048         int ret;
1049         struct psp_context *psp = &adev->psp;
1050
1051         if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) {
1052                 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
1053                 goto skip_memalloc;
1054         }
1055
1056         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1057         if (!psp->cmd)
1058                 return -ENOMEM;
1059
1060         /* this fw pri bo is not used under SRIOV */
1061         if (!amdgpu_sriov_vf(psp->adev)) {
1062                 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
1063                                               AMDGPU_GEM_DOMAIN_GTT,
1064                                               &psp->fw_pri_bo,
1065                                               &psp->fw_pri_mc_addr,
1066                                               &psp->fw_pri_buf);
1067                 if (ret)
1068                         goto failed;
1069         }
1070
1071         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
1072                                         AMDGPU_GEM_DOMAIN_VRAM,
1073                                         &psp->fence_buf_bo,
1074                                         &psp->fence_buf_mc_addr,
1075                                         &psp->fence_buf);
1076         if (ret)
1077                 goto failed;
1078
1079         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
1080                                       AMDGPU_GEM_DOMAIN_VRAM,
1081                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
1082                                       (void **)&psp->cmd_buf_mem);
1083         if (ret)
1084                 goto failed;
1085
1086         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
1087
1088         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
1089         if (ret) {
1090                 DRM_ERROR("PSP ring init failed!\n");
1091                 goto failed;
1092         }
1093
1094 skip_memalloc:
1095         ret = psp_hw_start(psp);
1096         if (ret)
1097                 goto failed;
1098
1099         ret = psp_np_fw_load(psp);
1100         if (ret)
1101                 goto failed;
1102
1103         return 0;
1104
1105 failed:
1106         /*
1107          * all cleanup jobs (xgmi terminate, ras terminate,
1108          * ring destroy, cmd/fence/fw buffers destory,
1109          * psp->cmd destory) are delayed to psp_hw_fini
1110          */
1111         return ret;
1112 }
1113
1114 static int psp_hw_init(void *handle)
1115 {
1116         int ret;
1117         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1118
1119         mutex_lock(&adev->firmware.mutex);
1120         /*
1121          * This sequence is just used on hw_init only once, no need on
1122          * resume.
1123          */
1124         ret = amdgpu_ucode_init_bo(adev);
1125         if (ret)
1126                 goto failed;
1127
1128         ret = psp_load_fw(adev);
1129         if (ret) {
1130                 DRM_ERROR("PSP firmware loading failed\n");
1131                 goto failed;
1132         }
1133
1134         mutex_unlock(&adev->firmware.mutex);
1135         return 0;
1136
1137 failed:
1138         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
1139         mutex_unlock(&adev->firmware.mutex);
1140         return -EINVAL;
1141 }
1142
1143 static int psp_hw_fini(void *handle)
1144 {
1145         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1146         struct psp_context *psp = &adev->psp;
1147
1148         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1149             psp->xgmi_context.initialized == 1)
1150                 psp_xgmi_terminate(psp);
1151
1152         if (psp->adev->psp.ta_fw)
1153                 psp_ras_terminate(psp);
1154
1155         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
1156
1157         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
1158         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
1159                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
1160         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
1161                               &psp->fence_buf_mc_addr, &psp->fence_buf);
1162         amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr,
1163                               &psp->asd_shared_buf);
1164         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
1165                               (void **)&psp->cmd_buf_mem);
1166
1167         kfree(psp->cmd);
1168         psp->cmd = NULL;
1169
1170         return 0;
1171 }
1172
1173 static int psp_suspend(void *handle)
1174 {
1175         int ret;
1176         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1177         struct psp_context *psp = &adev->psp;
1178
1179         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1180             psp->xgmi_context.initialized == 1) {
1181                 ret = psp_xgmi_terminate(psp);
1182                 if (ret) {
1183                         DRM_ERROR("Failed to terminate xgmi ta\n");
1184                         return ret;
1185                 }
1186         }
1187
1188         if (psp->adev->psp.ta_fw) {
1189                 ret = psp_ras_terminate(psp);
1190                 if (ret) {
1191                         DRM_ERROR("Failed to terminate ras ta\n");
1192                         return ret;
1193                 }
1194         }
1195
1196         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
1197         if (ret) {
1198                 DRM_ERROR("PSP ring stop failed\n");
1199                 return ret;
1200         }
1201
1202         return 0;
1203 }
1204
1205 static int psp_resume(void *handle)
1206 {
1207         int ret;
1208         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1209         struct psp_context *psp = &adev->psp;
1210
1211         DRM_INFO("PSP is resuming...\n");
1212
1213         mutex_lock(&adev->firmware.mutex);
1214
1215         ret = psp_hw_start(psp);
1216         if (ret)
1217                 goto failed;
1218
1219         ret = psp_np_fw_load(psp);
1220         if (ret)
1221                 goto failed;
1222
1223         mutex_unlock(&adev->firmware.mutex);
1224
1225         return 0;
1226
1227 failed:
1228         DRM_ERROR("PSP resume failed\n");
1229         mutex_unlock(&adev->firmware.mutex);
1230         return ret;
1231 }
1232
1233 int psp_gpu_reset(struct amdgpu_device *adev)
1234 {
1235         int ret;
1236
1237         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1238                 return 0;
1239
1240         mutex_lock(&adev->psp.mutex);
1241         ret = psp_mode1_reset(&adev->psp);
1242         mutex_unlock(&adev->psp.mutex);
1243
1244         return ret;
1245 }
1246
1247 int psp_rlc_autoload_start(struct psp_context *psp)
1248 {
1249         int ret;
1250         struct psp_gfx_cmd_resp *cmd;
1251
1252         if (amdgpu_sriov_vf(psp->adev))
1253                 return 0;
1254
1255         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1256         if (!cmd)
1257                 return -ENOMEM;
1258
1259         cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
1260
1261         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1262                                  psp->fence_buf_mc_addr);
1263         kfree(cmd);
1264         return ret;
1265 }
1266
1267 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
1268                         uint64_t cmd_gpu_addr, int cmd_size)
1269 {
1270         struct amdgpu_firmware_info ucode = {0};
1271
1272         ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
1273                 AMDGPU_UCODE_ID_VCN0_RAM;
1274         ucode.mc_addr = cmd_gpu_addr;
1275         ucode.ucode_size = cmd_size;
1276
1277         return psp_execute_np_fw_load(&adev->psp, &ucode);
1278 }
1279
1280 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
1281                                         enum AMDGPU_UCODE_ID ucode_type)
1282 {
1283         struct amdgpu_firmware_info *ucode = NULL;
1284
1285         if (!adev->firmware.fw_size)
1286                 return false;
1287
1288         ucode = &adev->firmware.ucode[ucode_type];
1289         if (!ucode->fw || !ucode->ucode_size)
1290                 return false;
1291
1292         return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
1293 }
1294
1295 static int psp_set_clockgating_state(void *handle,
1296                                      enum amd_clockgating_state state)
1297 {
1298         return 0;
1299 }
1300
1301 static int psp_set_powergating_state(void *handle,
1302                                      enum amd_powergating_state state)
1303 {
1304         return 0;
1305 }
1306
1307 const struct amd_ip_funcs psp_ip_funcs = {
1308         .name = "psp",
1309         .early_init = psp_early_init,
1310         .late_init = NULL,
1311         .sw_init = psp_sw_init,
1312         .sw_fini = psp_sw_fini,
1313         .hw_init = psp_hw_init,
1314         .hw_fini = psp_hw_fini,
1315         .suspend = psp_suspend,
1316         .resume = psp_resume,
1317         .is_idle = NULL,
1318         .check_soft_reset = NULL,
1319         .wait_for_idle = NULL,
1320         .soft_reset = NULL,
1321         .set_clockgating_state = psp_set_clockgating_state,
1322         .set_powergating_state = psp_set_powergating_state,
1323 };
1324
1325 static const struct amdgpu_psp_funcs psp_funcs = {
1326         .check_fw_loading_status = psp_check_fw_loading_status,
1327 };
1328
1329 static void psp_set_funcs(struct amdgpu_device *adev)
1330 {
1331         if (NULL == adev->firmware.funcs)
1332                 adev->firmware.funcs = &psp_funcs;
1333 }
1334
1335 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
1336 {
1337         .type = AMD_IP_BLOCK_TYPE_PSP,
1338         .major = 3,
1339         .minor = 1,
1340         .rev = 0,
1341         .funcs = &psp_ip_funcs,
1342 };
1343
1344 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
1345 {
1346         .type = AMD_IP_BLOCK_TYPE_PSP,
1347         .major = 10,
1348         .minor = 0,
1349         .rev = 0,
1350         .funcs = &psp_ip_funcs,
1351 };
1352
1353 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
1354 {
1355         .type = AMD_IP_BLOCK_TYPE_PSP,
1356         .major = 11,
1357         .minor = 0,
1358         .rev = 0,
1359         .funcs = &psp_ip_funcs,
1360 };