2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/firmware.h>
29 #include "amdgpu_psp.h"
30 #include "amdgpu_ucode.h"
31 #include "soc15_common.h"
33 #include "psp_v10_0.h"
34 #include "psp_v11_0.h"
36 static void psp_set_funcs(struct amdgpu_device *adev);
38 static int psp_early_init(void *handle)
40 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
47 static int psp_sw_init(void *handle)
49 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
50 struct psp_context *psp = &adev->psp;
53 switch (adev->asic_type) {
56 psp_v3_1_set_psp_funcs(psp);
59 psp_v10_0_set_psp_funcs(psp);
62 psp_v11_0_set_psp_funcs(psp);
70 ret = psp_init_microcode(psp);
72 DRM_ERROR("Failed to load psp firmware!\n");
79 static int psp_sw_fini(void *handle)
81 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
83 release_firmware(adev->psp.sos_fw);
84 adev->psp.sos_fw = NULL;
85 release_firmware(adev->psp.asd_fw);
86 adev->psp.asd_fw = NULL;
87 if (adev->psp.ta_fw) {
88 release_firmware(adev->psp.ta_fw);
89 adev->psp.ta_fw = NULL;
94 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
95 uint32_t reg_val, uint32_t mask, bool check_changed)
99 struct amdgpu_device *adev = psp->adev;
101 for (i = 0; i < adev->usec_timeout; i++) {
102 val = RREG32(reg_index);
107 if ((val & mask) == reg_val)
117 psp_cmd_submit_buf(struct psp_context *psp,
118 struct amdgpu_firmware_info *ucode,
119 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
125 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
127 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
129 index = atomic_inc_return(&psp->fence_value);
130 ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
131 fence_mc_addr, index);
133 atomic_dec(&psp->fence_value);
137 while (*((unsigned int *)psp->fence_buf) != index) {
143 /* In some cases, psp response status is not 0 even there is no
144 * problem while the command is submitted. Some version of PSP FW
145 * doesn't write 0 to that field.
146 * So here we would like to only print a warning instead of an error
147 * during psp initialization to avoid breaking hw_init and it doesn't
150 if (psp->cmd_buf_mem->resp.status || !timeout) {
152 DRM_WARN("failed to load ucode id (%d) ",
154 DRM_WARN("psp command failed and response status is (%d)\n",
155 psp->cmd_buf_mem->resp.status);
160 /* get xGMI session id from response buffer */
161 cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id;
164 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
165 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
171 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
172 struct psp_gfx_cmd_resp *cmd,
173 uint64_t tmr_mc, uint32_t size)
175 if (psp_support_vmr_ring(psp))
176 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
178 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
179 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
180 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
181 cmd->cmd.cmd_setup_tmr.buf_size = size;
184 /* Set up Trusted Memory Region */
185 static int psp_tmr_init(struct psp_context *psp)
190 * Allocate 3M memory aligned to 1M from Frame Buffer (local
193 * Note: this memory need be reserved till the driver
196 ret = amdgpu_bo_create_kernel(psp->adev, PSP_TMR_SIZE, 0x100000,
197 AMDGPU_GEM_DOMAIN_VRAM,
198 &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
203 static int psp_tmr_load(struct psp_context *psp)
206 struct psp_gfx_cmd_resp *cmd;
208 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
212 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, PSP_TMR_SIZE);
213 DRM_INFO("reserve 0x%x from 0x%llx for PSP TMR SIZE\n",
214 PSP_TMR_SIZE, psp->tmr_mc_addr);
216 ret = psp_cmd_submit_buf(psp, NULL, cmd,
217 psp->fence_buf_mc_addr);
230 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
231 uint64_t asd_mc, uint64_t asd_mc_shared,
232 uint32_t size, uint32_t shared_size)
234 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
235 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
236 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
237 cmd->cmd.cmd_load_ta.app_len = size;
239 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
240 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
241 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
244 static int psp_asd_init(struct psp_context *psp)
249 * Allocate 16k memory aligned to 4k from Frame Buffer (local
250 * physical) for shared ASD <-> Driver
252 ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
253 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
255 &psp->asd_shared_mc_addr,
256 &psp->asd_shared_buf);
261 static int psp_asd_load(struct psp_context *psp)
264 struct psp_gfx_cmd_resp *cmd;
266 /* If PSP version doesn't match ASD version, asd loading will be failed.
267 * add workaround to bypass it for sriov now.
268 * TODO: add version check to make it common
270 if (amdgpu_sriov_vf(psp->adev))
273 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
277 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
278 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
280 psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
281 psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
283 ret = psp_cmd_submit_buf(psp, NULL, cmd,
284 psp->fence_buf_mc_addr);
291 static void psp_prep_xgmi_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
292 uint64_t xgmi_ta_mc, uint64_t xgmi_mc_shared,
293 uint32_t xgmi_ta_size, uint32_t shared_size)
295 cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
296 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(xgmi_ta_mc);
297 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(xgmi_ta_mc);
298 cmd->cmd.cmd_load_ta.app_len = xgmi_ta_size;
300 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(xgmi_mc_shared);
301 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(xgmi_mc_shared);
302 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
305 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
310 * Allocate 16k memory aligned to 4k from Frame Buffer (local
311 * physical) for xgmi ta <-> Driver
313 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE,
314 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
315 &psp->xgmi_context.xgmi_shared_bo,
316 &psp->xgmi_context.xgmi_shared_mc_addr,
317 &psp->xgmi_context.xgmi_shared_buf);
322 static int psp_xgmi_load(struct psp_context *psp)
325 struct psp_gfx_cmd_resp *cmd;
328 * TODO: bypass the loading in sriov for now
330 if (amdgpu_sriov_vf(psp->adev))
333 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
337 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
338 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
340 psp_prep_xgmi_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
341 psp->xgmi_context.xgmi_shared_mc_addr,
342 psp->ta_xgmi_ucode_size, PSP_XGMI_SHARED_MEM_SIZE);
344 ret = psp_cmd_submit_buf(psp, NULL, cmd,
345 psp->fence_buf_mc_addr);
348 psp->xgmi_context.initialized = 1;
349 psp->xgmi_context.session_id = cmd->resp.session_id;
357 static void psp_prep_xgmi_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
358 uint32_t xgmi_session_id)
360 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
361 cmd->cmd.cmd_unload_ta.session_id = xgmi_session_id;
364 static int psp_xgmi_unload(struct psp_context *psp)
367 struct psp_gfx_cmd_resp *cmd;
370 * TODO: bypass the unloading in sriov for now
372 if (amdgpu_sriov_vf(psp->adev))
375 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
379 psp_prep_xgmi_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);
381 ret = psp_cmd_submit_buf(psp, NULL, cmd,
382 psp->fence_buf_mc_addr);
389 static void psp_prep_xgmi_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
391 uint32_t xgmi_session_id)
393 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
394 cmd->cmd.cmd_invoke_cmd.session_id = xgmi_session_id;
395 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
396 /* Note: cmd_invoke_cmd.buf is not used for now */
399 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
402 struct psp_gfx_cmd_resp *cmd;
405 * TODO: bypass the loading in sriov for now
407 if (amdgpu_sriov_vf(psp->adev))
410 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
414 psp_prep_xgmi_ta_invoke_cmd_buf(cmd, ta_cmd_id,
415 psp->xgmi_context.session_id);
417 ret = psp_cmd_submit_buf(psp, NULL, cmd,
418 psp->fence_buf_mc_addr);
425 static int psp_xgmi_terminate(struct psp_context *psp)
429 if (!psp->xgmi_context.initialized)
432 ret = psp_xgmi_unload(psp);
436 psp->xgmi_context.initialized = 0;
438 /* free xgmi shared memory */
439 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo,
440 &psp->xgmi_context.xgmi_shared_mc_addr,
441 &psp->xgmi_context.xgmi_shared_buf);
446 static int psp_xgmi_initialize(struct psp_context *psp)
448 struct ta_xgmi_shared_memory *xgmi_cmd;
451 if (!psp->adev->psp.ta_fw)
454 if (!psp->xgmi_context.initialized) {
455 ret = psp_xgmi_init_shared_buf(psp);
461 ret = psp_xgmi_load(psp);
465 /* Initialize XGMI session */
466 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf);
467 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
468 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
470 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
476 static void psp_prep_ras_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
477 uint64_t ras_ta_mc, uint64_t ras_mc_shared,
478 uint32_t ras_ta_size, uint32_t shared_size)
480 cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
481 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ras_ta_mc);
482 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ras_ta_mc);
483 cmd->cmd.cmd_load_ta.app_len = ras_ta_size;
485 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ras_mc_shared);
486 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ras_mc_shared);
487 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
490 static int psp_ras_init_shared_buf(struct psp_context *psp)
495 * Allocate 16k memory aligned to 4k from Frame Buffer (local
496 * physical) for ras ta <-> Driver
498 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE,
499 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
500 &psp->ras.ras_shared_bo,
501 &psp->ras.ras_shared_mc_addr,
502 &psp->ras.ras_shared_buf);
507 static int psp_ras_load(struct psp_context *psp)
510 struct psp_gfx_cmd_resp *cmd;
513 * TODO: bypass the loading in sriov for now
515 if (amdgpu_sriov_vf(psp->adev))
518 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
522 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
523 memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size);
525 psp_prep_ras_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
526 psp->ras.ras_shared_mc_addr,
527 psp->ta_ras_ucode_size, PSP_RAS_SHARED_MEM_SIZE);
529 ret = psp_cmd_submit_buf(psp, NULL, cmd,
530 psp->fence_buf_mc_addr);
533 psp->ras.ras_initialized = 1;
534 psp->ras.session_id = cmd->resp.session_id;
542 static void psp_prep_ras_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
543 uint32_t ras_session_id)
545 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
546 cmd->cmd.cmd_unload_ta.session_id = ras_session_id;
549 static int psp_ras_unload(struct psp_context *psp)
552 struct psp_gfx_cmd_resp *cmd;
555 * TODO: bypass the unloading in sriov for now
557 if (amdgpu_sriov_vf(psp->adev))
560 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
564 psp_prep_ras_ta_unload_cmd_buf(cmd, psp->ras.session_id);
566 ret = psp_cmd_submit_buf(psp, NULL, cmd,
567 psp->fence_buf_mc_addr);
574 static void psp_prep_ras_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
576 uint32_t ras_session_id)
578 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
579 cmd->cmd.cmd_invoke_cmd.session_id = ras_session_id;
580 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
581 /* Note: cmd_invoke_cmd.buf is not used for now */
584 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
587 struct psp_gfx_cmd_resp *cmd;
590 * TODO: bypass the loading in sriov for now
592 if (amdgpu_sriov_vf(psp->adev))
595 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
599 psp_prep_ras_ta_invoke_cmd_buf(cmd, ta_cmd_id,
600 psp->ras.session_id);
602 ret = psp_cmd_submit_buf(psp, NULL, cmd,
603 psp->fence_buf_mc_addr);
610 int psp_ras_enable_features(struct psp_context *psp,
611 union ta_ras_cmd_input *info, bool enable)
613 struct ta_ras_shared_memory *ras_cmd;
616 if (!psp->ras.ras_initialized)
619 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
620 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
623 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
625 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
627 ras_cmd->ras_in_message = *info;
629 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
633 return ras_cmd->ras_status;
636 static int psp_ras_terminate(struct psp_context *psp)
640 if (!psp->ras.ras_initialized)
643 ret = psp_ras_unload(psp);
647 psp->ras.ras_initialized = 0;
649 /* free ras shared memory */
650 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo,
651 &psp->ras.ras_shared_mc_addr,
652 &psp->ras.ras_shared_buf);
657 static int psp_ras_initialize(struct psp_context *psp)
661 if (!psp->ras.ras_initialized) {
662 ret = psp_ras_init_shared_buf(psp);
667 ret = psp_ras_load(psp);
675 static int psp_hw_start(struct psp_context *psp)
677 struct amdgpu_device *adev = psp->adev;
680 if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
681 ret = psp_bootloader_load_sysdrv(psp);
683 DRM_ERROR("PSP load sysdrv failed!\n");
687 ret = psp_bootloader_load_sos(psp);
689 DRM_ERROR("PSP load sos failed!\n");
694 ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
696 DRM_ERROR("PSP create ring failed!\n");
700 ret = psp_tmr_load(psp);
702 DRM_ERROR("PSP load tmr failed!\n");
706 ret = psp_asd_load(psp);
708 DRM_ERROR("PSP load asd failed!\n");
712 if (adev->gmc.xgmi.num_physical_nodes > 1) {
713 ret = psp_xgmi_initialize(psp);
714 /* Warning the XGMI seesion initialize failure
715 * Instead of stop driver initialization
718 dev_err(psp->adev->dev,
719 "XGMI: Failed to initialize XGMI session\n");
723 if (psp->adev->psp.ta_fw) {
724 ret = psp_ras_initialize(psp);
726 dev_err(psp->adev->dev,
727 "RAS: Failed to initialize RAS\n");
733 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
734 enum psp_gfx_fw_type *type)
736 switch (ucode->ucode_id) {
737 case AMDGPU_UCODE_ID_SDMA0:
738 *type = GFX_FW_TYPE_SDMA0;
740 case AMDGPU_UCODE_ID_SDMA1:
741 *type = GFX_FW_TYPE_SDMA1;
743 case AMDGPU_UCODE_ID_CP_CE:
744 *type = GFX_FW_TYPE_CP_CE;
746 case AMDGPU_UCODE_ID_CP_PFP:
747 *type = GFX_FW_TYPE_CP_PFP;
749 case AMDGPU_UCODE_ID_CP_ME:
750 *type = GFX_FW_TYPE_CP_ME;
752 case AMDGPU_UCODE_ID_CP_MEC1:
753 *type = GFX_FW_TYPE_CP_MEC;
755 case AMDGPU_UCODE_ID_CP_MEC1_JT:
756 *type = GFX_FW_TYPE_CP_MEC_ME1;
758 case AMDGPU_UCODE_ID_CP_MEC2:
759 *type = GFX_FW_TYPE_CP_MEC;
761 case AMDGPU_UCODE_ID_CP_MEC2_JT:
762 *type = GFX_FW_TYPE_CP_MEC_ME2;
764 case AMDGPU_UCODE_ID_RLC_G:
765 *type = GFX_FW_TYPE_RLC_G;
767 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
768 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
770 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
771 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
773 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
774 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
776 case AMDGPU_UCODE_ID_SMC:
777 *type = GFX_FW_TYPE_SMU;
779 case AMDGPU_UCODE_ID_UVD:
780 *type = GFX_FW_TYPE_UVD;
782 case AMDGPU_UCODE_ID_UVD1:
783 *type = GFX_FW_TYPE_UVD1;
785 case AMDGPU_UCODE_ID_VCE:
786 *type = GFX_FW_TYPE_VCE;
788 case AMDGPU_UCODE_ID_VCN:
789 *type = GFX_FW_TYPE_VCN;
791 case AMDGPU_UCODE_ID_DMCU_ERAM:
792 *type = GFX_FW_TYPE_DMCU_ERAM;
794 case AMDGPU_UCODE_ID_DMCU_INTV:
795 *type = GFX_FW_TYPE_DMCU_ISR;
797 case AMDGPU_UCODE_ID_MAXIMUM:
805 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
806 struct psp_gfx_cmd_resp *cmd)
809 uint64_t fw_mem_mc_addr = ucode->mc_addr;
811 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
813 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
814 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
815 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
816 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
818 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
820 DRM_ERROR("Unknown firmware type\n");
825 static int psp_np_fw_load(struct psp_context *psp)
828 struct amdgpu_firmware_info *ucode;
829 struct amdgpu_device* adev = psp->adev;
831 for (i = 0; i < adev->firmware.max_ucodes; i++) {
832 ucode = &adev->firmware.ucode[i];
836 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
837 psp_smu_reload_quirk(psp))
839 if (amdgpu_sriov_vf(adev) &&
840 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
841 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
842 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
843 /*skip ucode loading in SRIOV VF */
846 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd);
850 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
851 psp->fence_buf_mc_addr);
856 /* check if firmware loaded sucessfully */
857 if (!amdgpu_psp_check_fw_loading_status(adev, i))
865 static int psp_load_fw(struct amdgpu_device *adev)
868 struct psp_context *psp = &adev->psp;
870 if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) {
871 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
875 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
879 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
880 AMDGPU_GEM_DOMAIN_GTT,
882 &psp->fw_pri_mc_addr,
887 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
888 AMDGPU_GEM_DOMAIN_VRAM,
890 &psp->fence_buf_mc_addr,
895 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
896 AMDGPU_GEM_DOMAIN_VRAM,
897 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
898 (void **)&psp->cmd_buf_mem);
902 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
904 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
906 DRM_ERROR("PSP ring init failed!\n");
910 ret = psp_tmr_init(psp);
912 DRM_ERROR("PSP tmr init failed!\n");
916 ret = psp_asd_init(psp);
918 DRM_ERROR("PSP asd init failed!\n");
923 ret = psp_hw_start(psp);
927 ret = psp_np_fw_load(psp);
934 amdgpu_bo_free_kernel(&psp->cmd_buf_bo,
935 &psp->cmd_buf_mc_addr,
936 (void **)&psp->cmd_buf_mem);
938 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
939 &psp->fence_buf_mc_addr, &psp->fence_buf);
941 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
942 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
949 static int psp_hw_init(void *handle)
952 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
954 mutex_lock(&adev->firmware.mutex);
956 * This sequence is just used on hw_init only once, no need on
959 ret = amdgpu_ucode_init_bo(adev);
963 ret = psp_load_fw(adev);
965 DRM_ERROR("PSP firmware loading failed\n");
969 mutex_unlock(&adev->firmware.mutex);
973 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
974 mutex_unlock(&adev->firmware.mutex);
978 static int psp_hw_fini(void *handle)
980 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
981 struct psp_context *psp = &adev->psp;
983 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
984 psp->xgmi_context.initialized == 1)
985 psp_xgmi_terminate(psp);
987 if (psp->adev->psp.ta_fw)
988 psp_ras_terminate(psp);
990 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
992 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
993 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
994 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
995 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
996 &psp->fence_buf_mc_addr, &psp->fence_buf);
997 amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr,
998 &psp->asd_shared_buf);
999 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
1000 (void **)&psp->cmd_buf_mem);
1008 static int psp_suspend(void *handle)
1011 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1012 struct psp_context *psp = &adev->psp;
1014 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1015 psp->xgmi_context.initialized == 1) {
1016 ret = psp_xgmi_terminate(psp);
1018 DRM_ERROR("Failed to terminate xgmi ta\n");
1023 if (psp->adev->psp.ta_fw) {
1024 ret = psp_ras_terminate(psp);
1026 DRM_ERROR("Failed to terminate ras ta\n");
1031 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
1033 DRM_ERROR("PSP ring stop failed\n");
1040 static int psp_resume(void *handle)
1043 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1044 struct psp_context *psp = &adev->psp;
1046 DRM_INFO("PSP is resuming...\n");
1048 mutex_lock(&adev->firmware.mutex);
1050 ret = psp_hw_start(psp);
1054 ret = psp_np_fw_load(psp);
1058 mutex_unlock(&adev->firmware.mutex);
1063 DRM_ERROR("PSP resume failed\n");
1064 mutex_unlock(&adev->firmware.mutex);
1068 int psp_gpu_reset(struct amdgpu_device *adev)
1070 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1073 return psp_mode1_reset(&adev->psp);
1076 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
1077 enum AMDGPU_UCODE_ID ucode_type)
1079 struct amdgpu_firmware_info *ucode = NULL;
1081 if (!adev->firmware.fw_size)
1084 ucode = &adev->firmware.ucode[ucode_type];
1085 if (!ucode->fw || !ucode->ucode_size)
1088 return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
1091 static int psp_set_clockgating_state(void *handle,
1092 enum amd_clockgating_state state)
1097 static int psp_set_powergating_state(void *handle,
1098 enum amd_powergating_state state)
1103 const struct amd_ip_funcs psp_ip_funcs = {
1105 .early_init = psp_early_init,
1107 .sw_init = psp_sw_init,
1108 .sw_fini = psp_sw_fini,
1109 .hw_init = psp_hw_init,
1110 .hw_fini = psp_hw_fini,
1111 .suspend = psp_suspend,
1112 .resume = psp_resume,
1114 .check_soft_reset = NULL,
1115 .wait_for_idle = NULL,
1117 .set_clockgating_state = psp_set_clockgating_state,
1118 .set_powergating_state = psp_set_powergating_state,
1121 static const struct amdgpu_psp_funcs psp_funcs = {
1122 .check_fw_loading_status = psp_check_fw_loading_status,
1125 static void psp_set_funcs(struct amdgpu_device *adev)
1127 if (NULL == adev->firmware.funcs)
1128 adev->firmware.funcs = &psp_funcs;
1131 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
1133 .type = AMD_IP_BLOCK_TYPE_PSP,
1137 .funcs = &psp_ip_funcs,
1140 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
1142 .type = AMD_IP_BLOCK_TYPE_PSP,
1146 .funcs = &psp_ip_funcs,
1149 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
1151 .type = AMD_IP_BLOCK_TYPE_PSP,
1155 .funcs = &psp_ip_funcs,