drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_psp.h"
  30 #include "amdgpu_ucode.h"
  31 #include "soc15_common.h"
  32 #include "psp_v3_1.h"
  33 #include "psp_v10_0.h"
  34 #include "psp_v11_0.h"
  35 #include "psp_v12_0.h"
  36
  37 static void psp_set_funcs(struct amdgpu_device *adev);
  38
  39 static int psp_early_init(void *handle)
  40 {
  41         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  42         struct psp_context *psp = &adev->psp;
  43
  44         psp_set_funcs(adev);
  45
  46         switch (adev->asic_type) {
  47         case CHIP_VEGA10:
  48         case CHIP_VEGA12:
  49                 psp_v3_1_set_psp_funcs(psp);
  50                 psp->autoload_supported = false;
  51                 break;
  52         case CHIP_RAVEN:
  53                 psp_v10_0_set_psp_funcs(psp);
  54                 psp->autoload_supported = false;
  55                 break;
  56         case CHIP_VEGA20:
  57         case CHIP_ARCTURUS:
  58                 psp_v11_0_set_psp_funcs(psp);
  59                 psp->autoload_supported = false;
  60                 break;
  61         case CHIP_NAVI10:
  62         case CHIP_NAVI14:
  63         case CHIP_NAVI12:
  64                 psp_v11_0_set_psp_funcs(psp);
  65                 psp->autoload_supported = true;
  66                 break;
  67         case CHIP_RENOIR:
  68                 psp_v12_0_set_psp_funcs(psp);
  69                 break;
  70         default:
  71                 return -EINVAL;
  72         }
  73
  74         psp->adev = adev;
  75
  76         return 0;
  77 }
  78
  79 static int psp_sw_init(void *handle)
  80 {
  81         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  82         struct psp_context *psp = &adev->psp;
  83         int ret;
  84
  85         ret = psp_init_microcode(psp);
  86         if (ret) {
  87                 DRM_ERROR("Failed to load psp firmware!\n");
  88                 return ret;
  89         }
  90
  91         return 0;
  92 }
  93
  94 static int psp_sw_fini(void *handle)
  95 {
  96         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  97
  98         release_firmware(adev->psp.sos_fw);
  99         adev->psp.sos_fw = NULL;
 100         release_firmware(adev->psp.asd_fw);
 101         adev->psp.asd_fw = NULL;
 102         if (adev->psp.ta_fw) {
 103                 release_firmware(adev->psp.ta_fw);
 104                 adev->psp.ta_fw = NULL;
 105         }
 106         return 0;
 107 }
 108
 109 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 110                  uint32_t reg_val, uint32_t mask, bool check_changed)
 111 {
 112         uint32_t val;
 113         int i;
 114         struct amdgpu_device *adev = psp->adev;
 115
 116         for (i = 0; i < adev->usec_timeout; i++) {
 117                 val = RREG32(reg_index);
 118                 if (check_changed) {
 119                         if (val != reg_val)
 120                                 return 0;
 121                 } else {
 122                         if ((val & mask) == reg_val)
 123                                 return 0;
 124                 }
 125                 udelay(1);
 126         }
 127
 128         return -ETIME;
 129 }
 130
 131 static int
 132 psp_cmd_submit_buf(struct psp_context *psp,
 133                    struct amdgpu_firmware_info *ucode,
 134                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 135 {
 136         int ret;
 137         int index;
 138         int timeout = 2000;
 139
 140         mutex_lock(&psp->mutex);
 141
 142         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 143
 144         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 145
 146         index = atomic_inc_return(&psp->fence_value);
 147         ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
 148                              fence_mc_addr, index);
 149         if (ret) {
 150                 atomic_dec(&psp->fence_value);
 151                 mutex_unlock(&psp->mutex);
 152                 return ret;
 153         }
 154
 155         while (*((unsigned int *)psp->fence_buf) != index) {
 156                 if (--timeout == 0)
 157                         break;
 158                 msleep(1);
 159         }
 160
 161         /* In some cases, psp response status is not 0 even there is no
 162          * problem while the command is submitted. Some version of PSP FW
 163          * doesn't write 0 to that field.
 164          * So here we would like to only print a warning instead of an error
 165          * during psp initialization to avoid breaking hw_init and it doesn't
 166          * return -EINVAL.
 167          */
 168         if (psp->cmd_buf_mem->resp.status || !timeout) {
 169                 if (ucode)
 170                         DRM_WARN("failed to load ucode id (%d) ",
 171                                   ucode->ucode_id);
 172                 DRM_WARN("psp command failed and response status is (0x%X)\n",
 173                           psp->cmd_buf_mem->resp.status & GFX_CMD_STATUS_MASK);
 174                 if (!timeout) {
 175                         mutex_unlock(&psp->mutex);
 176                         return -EINVAL;
 177                 }
 178         }
 179
 180         /* get xGMI session id from response buffer */
 181         cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id;
 182
 183         if (ucode) {
 184                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 185                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 186         }
 187         mutex_unlock(&psp->mutex);
 188
 189         return ret;
 190 }
 191
 192 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 193                                  struct psp_gfx_cmd_resp *cmd,
 194                                  uint64_t tmr_mc, uint32_t size)
 195 {
 196         if (psp_support_vmr_ring(psp))
 197                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 198         else
 199                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 200         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 201         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 202         cmd->cmd.cmd_setup_tmr.buf_size = size;
 203 }
 204
 205 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 206                                       uint64_t pri_buf_mc, uint32_t size)
 207 {
 208         cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
 209         cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
 210         cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
 211         cmd->cmd.cmd_load_toc.toc_size = size;
 212 }
 213
 214 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
 215 static int psp_load_toc(struct psp_context *psp,
 216                         uint32_t *tmr_size)
 217 {
 218         int ret;
 219         struct psp_gfx_cmd_resp *cmd;
 220
 221         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 222         if (!cmd)
 223                 return -ENOMEM;
 224         /* Copy toc to psp firmware private buffer */
 225         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 226         memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size);
 227
 228         psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size);
 229
 230         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 231                                  psp->fence_buf_mc_addr);
 232         if (!ret)
 233                 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
 234         kfree(cmd);
 235         return ret;
 236 }
 237
 238 /* Set up Trusted Memory Region */
 239 static int psp_tmr_init(struct psp_context *psp)
 240 {
 241         int ret;
 242         int tmr_size;
 243
 244         /*
 245          * According to HW engineer, they prefer the TMR address be "naturally
 246          * aligned" , e.g. the start address be an integer divide of TMR size.
 247          *
 248          * Note: this memory need be reserved till the driver
 249          * uninitializes.
 250          */
 251         tmr_size = PSP_TMR_SIZE;
 252
 253         /* For ASICs support RLC autoload, psp will parse the toc
 254          * and calculate the total size of TMR needed */
 255         if (psp->toc_start_addr &&
 256             psp->toc_bin_size &&
 257             psp->fw_pri_buf) {
 258                 ret = psp_load_toc(psp, &tmr_size);
 259                 if (ret) {
 260                         DRM_ERROR("Failed to load toc\n");
 261                         return ret;
 262                 }
 263         }
 264
 265         ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
 266                                       AMDGPU_GEM_DOMAIN_VRAM,
 267                                       &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 268
 269         return ret;
 270 }
 271
 272 static int psp_tmr_load(struct psp_context *psp)
 273 {
 274         int ret;
 275         struct psp_gfx_cmd_resp *cmd;
 276
 277         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 278         if (!cmd)
 279                 return -ENOMEM;
 280
 281         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr,
 282                              amdgpu_bo_size(psp->tmr_bo));
 283         DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 284                  amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 285
 286         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 287                                  psp->fence_buf_mc_addr);
 288         if (ret)
 289                 goto failed;
 290
 291         kfree(cmd);
 292
 293         return 0;
 294
 295 failed:
 296         kfree(cmd);
 297         return ret;
 298 }
 299
 300 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 301                                  uint64_t asd_mc, uint64_t asd_mc_shared,
 302                                  uint32_t size, uint32_t shared_size)
 303 {
 304         cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
 305         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
 306         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
 307         cmd->cmd.cmd_load_ta.app_len = size;
 308
 309         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
 310         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
 311         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 312 }
 313
 314 static int psp_asd_init(struct psp_context *psp)
 315 {
 316         int ret;
 317
 318         /*
 319          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 320          * physical) for shared ASD <-> Driver
 321          */
 322         ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
 323                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 324                                       &psp->asd_shared_bo,
 325                                       &psp->asd_shared_mc_addr,
 326                                       &psp->asd_shared_buf);
 327
 328         return ret;
 329 }
 330
 331 static int psp_asd_load(struct psp_context *psp)
 332 {
 333         int ret;
 334         struct psp_gfx_cmd_resp *cmd;
 335
 336         /* If PSP version doesn't match ASD version, asd loading will be failed.
 337          * add workaround to bypass it for sriov now.
 338          * TODO: add version check to make it common
 339          */
 340         if (amdgpu_sriov_vf(psp->adev))
 341                 return 0;
 342
 343         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 344         if (!cmd)
 345                 return -ENOMEM;
 346
 347         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 348         memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
 349
 350         psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
 351                              psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
 352
 353         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 354                                  psp->fence_buf_mc_addr);
 355
 356         kfree(cmd);
 357
 358         return ret;
 359 }
 360
 361 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 362                 uint32_t id, uint32_t value)
 363 {
 364         cmd->cmd_id = GFX_CMD_ID_PROG_REG;
 365         cmd->cmd.cmd_setup_reg_prog.reg_value = value;
 366         cmd->cmd.cmd_setup_reg_prog.reg_id = id;
 367 }
 368
 369 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
 370                 uint32_t value)
 371 {
 372         struct psp_gfx_cmd_resp *cmd = NULL;
 373         int ret = 0;
 374
 375         if (reg >= PSP_REG_LAST)
 376                 return -EINVAL;
 377
 378         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 379         if (!cmd)
 380                 return -ENOMEM;
 381
 382         psp_prep_reg_prog_cmd_buf(cmd, reg, value);
 383         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 384
 385         kfree(cmd);
 386         return ret;
 387 }
 388
 389 static void psp_prep_xgmi_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 390                                           uint64_t xgmi_ta_mc, uint64_t xgmi_mc_shared,
 391                                           uint32_t xgmi_ta_size, uint32_t shared_size)
 392 {
 393         cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
 394         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(xgmi_ta_mc);
 395         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(xgmi_ta_mc);
 396         cmd->cmd.cmd_load_ta.app_len = xgmi_ta_size;
 397
 398         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(xgmi_mc_shared);
 399         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(xgmi_mc_shared);
 400         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 401 }
 402
 403 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
 404 {
 405         int ret;
 406
 407         /*
 408          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 409          * physical) for xgmi ta <-> Driver
 410          */
 411         ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE,
 412                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 413                                       &psp->xgmi_context.xgmi_shared_bo,
 414                                       &psp->xgmi_context.xgmi_shared_mc_addr,
 415                                       &psp->xgmi_context.xgmi_shared_buf);
 416
 417         return ret;
 418 }
 419
 420 static int psp_xgmi_load(struct psp_context *psp)
 421 {
 422         int ret;
 423         struct psp_gfx_cmd_resp *cmd;
 424
 425         /*
 426          * TODO: bypass the loading in sriov for now
 427          */
 428         if (amdgpu_sriov_vf(psp->adev))
 429                 return 0;
 430
 431         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 432         if (!cmd)
 433                 return -ENOMEM;
 434
 435         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 436         memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
 437
 438         psp_prep_xgmi_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
 439                                       psp->xgmi_context.xgmi_shared_mc_addr,
 440                                       psp->ta_xgmi_ucode_size, PSP_XGMI_SHARED_MEM_SIZE);
 441
 442         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 443                                  psp->fence_buf_mc_addr);
 444
 445         if (!ret) {
 446                 psp->xgmi_context.initialized = 1;
 447                 psp->xgmi_context.session_id = cmd->resp.session_id;
 448         }
 449
 450         kfree(cmd);
 451
 452         return ret;
 453 }
 454
 455 static void psp_prep_xgmi_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 456                                             uint32_t xgmi_session_id)
 457 {
 458         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 459         cmd->cmd.cmd_unload_ta.session_id = xgmi_session_id;
 460 }
 461
 462 static int psp_xgmi_unload(struct psp_context *psp)
 463 {
 464         int ret;
 465         struct psp_gfx_cmd_resp *cmd;
 466
 467         /*
 468          * TODO: bypass the unloading in sriov for now
 469          */
 470         if (amdgpu_sriov_vf(psp->adev))
 471                 return 0;
 472
 473         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 474         if (!cmd)
 475                 return -ENOMEM;
 476
 477         psp_prep_xgmi_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);
 478
 479         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 480                                  psp->fence_buf_mc_addr);
 481
 482         kfree(cmd);
 483
 484         return ret;
 485 }
 486
 487 static void psp_prep_xgmi_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 488                                             uint32_t ta_cmd_id,
 489                                             uint32_t xgmi_session_id)
 490 {
 491         cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
 492         cmd->cmd.cmd_invoke_cmd.session_id = xgmi_session_id;
 493         cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
 494         /* Note: cmd_invoke_cmd.buf is not used for now */
 495 }
 496
 497 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
 498 {
 499         int ret;
 500         struct psp_gfx_cmd_resp *cmd;
 501
 502         /*
 503          * TODO: bypass the loading in sriov for now
 504         */
 505         if (amdgpu_sriov_vf(psp->adev))
 506                 return 0;
 507
 508         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 509         if (!cmd)
 510                 return -ENOMEM;
 511
 512         psp_prep_xgmi_ta_invoke_cmd_buf(cmd, ta_cmd_id,
 513                                         psp->xgmi_context.session_id);
 514
 515         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 516                                  psp->fence_buf_mc_addr);
 517
 518         kfree(cmd);
 519
 520         return ret;
 521 }
 522
 523 static int psp_xgmi_terminate(struct psp_context *psp)
 524 {
 525         int ret;
 526
 527         if (!psp->xgmi_context.initialized)
 528                 return 0;
 529
 530         ret = psp_xgmi_unload(psp);
 531         if (ret)
 532                 return ret;
 533
 534         psp->xgmi_context.initialized = 0;
 535
 536         /* free xgmi shared memory */
 537         amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo,
 538                         &psp->xgmi_context.xgmi_shared_mc_addr,
 539                         &psp->xgmi_context.xgmi_shared_buf);
 540
 541         return 0;
 542 }
 543
 544 static int psp_xgmi_initialize(struct psp_context *psp)
 545 {
 546         struct ta_xgmi_shared_memory *xgmi_cmd;
 547         int ret;
 548
 549         if (!psp->adev->psp.ta_fw)
 550                 return -ENOENT;
 551
 552         if (!psp->xgmi_context.initialized) {
 553                 ret = psp_xgmi_init_shared_buf(psp);
 554                 if (ret)
 555                         return ret;
 556         }
 557
 558         /* Load XGMI TA */
 559         ret = psp_xgmi_load(psp);
 560         if (ret)
 561                 return ret;
 562
 563         /* Initialize XGMI session */
 564         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf);
 565         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 566         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
 567
 568         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 569
 570         return ret;
 571 }
 572
 573 // ras begin
 574 static void psp_prep_ras_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 575                 uint64_t ras_ta_mc, uint64_t ras_mc_shared,
 576                 uint32_t ras_ta_size, uint32_t shared_size)
 577 {
 578         cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
 579         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ras_ta_mc);
 580         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ras_ta_mc);
 581         cmd->cmd.cmd_load_ta.app_len = ras_ta_size;
 582
 583         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ras_mc_shared);
 584         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ras_mc_shared);
 585         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 586 }
 587
 588 static int psp_ras_init_shared_buf(struct psp_context *psp)
 589 {
 590         int ret;
 591
 592         /*
 593          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 594          * physical) for ras ta <-> Driver
 595          */
 596         ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE,
 597                         PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 598                         &psp->ras.ras_shared_bo,
 599                         &psp->ras.ras_shared_mc_addr,
 600                         &psp->ras.ras_shared_buf);
 601
 602         return ret;
 603 }
 604
 605 static int psp_ras_load(struct psp_context *psp)
 606 {
 607         int ret;
 608         struct psp_gfx_cmd_resp *cmd;
 609
 610         /*
 611          * TODO: bypass the loading in sriov for now
 612          */
 613         if (amdgpu_sriov_vf(psp->adev))
 614                 return 0;
 615
 616         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 617         if (!cmd)
 618                 return -ENOMEM;
 619
 620         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 621         memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size);
 622
 623         psp_prep_ras_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
 624                         psp->ras.ras_shared_mc_addr,
 625                         psp->ta_ras_ucode_size, PSP_RAS_SHARED_MEM_SIZE);
 626
 627         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 628                         psp->fence_buf_mc_addr);
 629
 630         if (!ret) {
 631                 psp->ras.ras_initialized = 1;
 632                 psp->ras.session_id = cmd->resp.session_id;
 633         }
 634
 635         kfree(cmd);
 636
 637         return ret;
 638 }
 639
 640 static void psp_prep_ras_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 641                                                 uint32_t ras_session_id)
 642 {
 643         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 644         cmd->cmd.cmd_unload_ta.session_id = ras_session_id;
 645 }
 646
 647 static int psp_ras_unload(struct psp_context *psp)
 648 {
 649         int ret;
 650         struct psp_gfx_cmd_resp *cmd;
 651
 652         /*
 653          * TODO: bypass the unloading in sriov for now
 654          */
 655         if (amdgpu_sriov_vf(psp->adev))
 656                 return 0;
 657
 658         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 659         if (!cmd)
 660                 return -ENOMEM;
 661
 662         psp_prep_ras_ta_unload_cmd_buf(cmd, psp->ras.session_id);
 663
 664         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 665                         psp->fence_buf_mc_addr);
 666
 667         kfree(cmd);
 668
 669         return ret;
 670 }
 671
 672 static void psp_prep_ras_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 673                 uint32_t ta_cmd_id,
 674                 uint32_t ras_session_id)
 675 {
 676         cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
 677         cmd->cmd.cmd_invoke_cmd.session_id = ras_session_id;
 678         cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
 679         /* Note: cmd_invoke_cmd.buf is not used for now */
 680 }
 681
 682 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
 683 {
 684         int ret;
 685         struct psp_gfx_cmd_resp *cmd;
 686
 687         /*
 688          * TODO: bypass the loading in sriov for now
 689          */
 690         if (amdgpu_sriov_vf(psp->adev))
 691                 return 0;
 692
 693         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 694         if (!cmd)
 695                 return -ENOMEM;
 696
 697         psp_prep_ras_ta_invoke_cmd_buf(cmd, ta_cmd_id,
 698                         psp->ras.session_id);
 699
 700         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 701                         psp->fence_buf_mc_addr);
 702
 703         kfree(cmd);
 704
 705         return ret;
 706 }
 707
 708 int psp_ras_enable_features(struct psp_context *psp,
 709                 union ta_ras_cmd_input *info, bool enable)
 710 {
 711         struct ta_ras_shared_memory *ras_cmd;
 712         int ret;
 713
 714         if (!psp->ras.ras_initialized)
 715                 return -EINVAL;
 716
 717         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
 718         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
 719
 720         if (enable)
 721                 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
 722         else
 723                 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
 724
 725         ras_cmd->ras_in_message = *info;
 726
 727         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
 728         if (ret)
 729                 return -EINVAL;
 730
 731         return ras_cmd->ras_status;
 732 }
 733
 734 static int psp_ras_terminate(struct psp_context *psp)
 735 {
 736         int ret;
 737
 738         if (!psp->ras.ras_initialized)
 739                 return 0;
 740
 741         ret = psp_ras_unload(psp);
 742         if (ret)
 743                 return ret;
 744
 745         psp->ras.ras_initialized = 0;
 746
 747         /* free ras shared memory */
 748         amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo,
 749                         &psp->ras.ras_shared_mc_addr,
 750                         &psp->ras.ras_shared_buf);
 751
 752         return 0;
 753 }
 754
 755 static int psp_ras_initialize(struct psp_context *psp)
 756 {
 757         int ret;
 758
 759         if (!psp->ras.ras_initialized) {
 760                 ret = psp_ras_init_shared_buf(psp);
 761                 if (ret)
 762                         return ret;
 763         }
 764
 765         ret = psp_ras_load(psp);
 766         if (ret)
 767                 return ret;
 768
 769         return 0;
 770 }
 771 // ras end
 772
 773 static int psp_hw_start(struct psp_context *psp)
 774 {
 775         struct amdgpu_device *adev = psp->adev;
 776         int ret;
 777
 778         if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
 779                 if (psp->kdb_bin_size &&
 780                     (psp->funcs->bootloader_load_kdb != NULL)) {
 781                         ret = psp_bootloader_load_kdb(psp);
 782                         if (ret) {
 783                                 DRM_ERROR("PSP load kdb failed!\n");
 784                                 return ret;
 785                         }
 786                 }
 787
 788                 ret = psp_bootloader_load_sysdrv(psp);
 789                 if (ret) {
 790                         DRM_ERROR("PSP load sysdrv failed!\n");
 791                         return ret;
 792                 }
 793
 794                 ret = psp_bootloader_load_sos(psp);
 795                 if (ret) {
 796                         DRM_ERROR("PSP load sos failed!\n");
 797                         return ret;
 798                 }
 799         }
 800
 801         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
 802         if (ret) {
 803                 DRM_ERROR("PSP create ring failed!\n");
 804                 return ret;
 805         }
 806
 807         ret = psp_tmr_init(psp);
 808         if (ret) {
 809                 DRM_ERROR("PSP tmr init failed!\n");
 810                 return ret;
 811         }
 812
 813         ret = psp_tmr_load(psp);
 814         if (ret) {
 815                 DRM_ERROR("PSP load tmr failed!\n");
 816                 return ret;
 817         }
 818
 819         ret = psp_asd_init(psp);
 820         if (ret) {
 821                 DRM_ERROR("PSP asd init failed!\n");
 822                 return ret;
 823         }
 824
 825         ret = psp_asd_load(psp);
 826         if (ret) {
 827                 DRM_ERROR("PSP load asd failed!\n");
 828                 return ret;
 829         }
 830
 831         if (adev->gmc.xgmi.num_physical_nodes > 1) {
 832                 ret = psp_xgmi_initialize(psp);
 833                 /* Warning the XGMI seesion initialize failure
 834                  * Instead of stop driver initialization
 835                  */
 836                 if (ret)
 837                         dev_err(psp->adev->dev,
 838                                 "XGMI: Failed to initialize XGMI session\n");
 839         }
 840
 841         if (psp->adev->psp.ta_fw) {
 842                 ret = psp_ras_initialize(psp);
 843                 if (ret)
 844                         dev_err(psp->adev->dev,
 845                                         "RAS: Failed to initialize RAS\n");
 846         }
 847
 848         return 0;
 849 }
 850
 851 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
 852                            enum psp_gfx_fw_type *type)
 853 {
 854         switch (ucode->ucode_id) {
 855         case AMDGPU_UCODE_ID_SDMA0:
 856                 *type = GFX_FW_TYPE_SDMA0;
 857                 break;
 858         case AMDGPU_UCODE_ID_SDMA1:
 859                 *type = GFX_FW_TYPE_SDMA1;
 860                 break;
 861         case AMDGPU_UCODE_ID_SDMA2:
 862                 *type = GFX_FW_TYPE_SDMA2;
 863                 break;
 864         case AMDGPU_UCODE_ID_SDMA3:
 865                 *type = GFX_FW_TYPE_SDMA3;
 866                 break;
 867         case AMDGPU_UCODE_ID_SDMA4:
 868                 *type = GFX_FW_TYPE_SDMA4;
 869                 break;
 870         case AMDGPU_UCODE_ID_SDMA5:
 871                 *type = GFX_FW_TYPE_SDMA5;
 872                 break;
 873         case AMDGPU_UCODE_ID_SDMA6:
 874                 *type = GFX_FW_TYPE_SDMA6;
 875                 break;
 876         case AMDGPU_UCODE_ID_SDMA7:
 877                 *type = GFX_FW_TYPE_SDMA7;
 878                 break;
 879         case AMDGPU_UCODE_ID_CP_CE:
 880                 *type = GFX_FW_TYPE_CP_CE;
 881                 break;
 882         case AMDGPU_UCODE_ID_CP_PFP:
 883                 *type = GFX_FW_TYPE_CP_PFP;
 884                 break;
 885         case AMDGPU_UCODE_ID_CP_ME:
 886                 *type = GFX_FW_TYPE_CP_ME;
 887                 break;
 888         case AMDGPU_UCODE_ID_CP_MEC1:
 889                 *type = GFX_FW_TYPE_CP_MEC;
 890                 break;
 891         case AMDGPU_UCODE_ID_CP_MEC1_JT:
 892                 *type = GFX_FW_TYPE_CP_MEC_ME1;
 893                 break;
 894         case AMDGPU_UCODE_ID_CP_MEC2:
 895                 *type = GFX_FW_TYPE_CP_MEC;
 896                 break;
 897         case AMDGPU_UCODE_ID_CP_MEC2_JT:
 898                 *type = GFX_FW_TYPE_CP_MEC_ME2;
 899                 break;
 900         case AMDGPU_UCODE_ID_RLC_G:
 901                 *type = GFX_FW_TYPE_RLC_G;
 902                 break;
 903         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
 904                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
 905                 break;
 906         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
 907                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
 908                 break;
 909         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
 910                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
 911                 break;
 912         case AMDGPU_UCODE_ID_SMC:
 913                 *type = GFX_FW_TYPE_SMU;
 914                 break;
 915         case AMDGPU_UCODE_ID_UVD:
 916                 *type = GFX_FW_TYPE_UVD;
 917                 break;
 918         case AMDGPU_UCODE_ID_UVD1:
 919                 *type = GFX_FW_TYPE_UVD1;
 920                 break;
 921         case AMDGPU_UCODE_ID_VCE:
 922                 *type = GFX_FW_TYPE_VCE;
 923                 break;
 924         case AMDGPU_UCODE_ID_VCN:
 925                 *type = GFX_FW_TYPE_VCN;
 926                 break;
 927         case AMDGPU_UCODE_ID_DMCU_ERAM:
 928                 *type = GFX_FW_TYPE_DMCU_ERAM;
 929                 break;
 930         case AMDGPU_UCODE_ID_DMCU_INTV:
 931                 *type = GFX_FW_TYPE_DMCU_ISR;
 932                 break;
 933         case AMDGPU_UCODE_ID_VCN0_RAM:
 934                 *type = GFX_FW_TYPE_VCN0_RAM;
 935                 break;
 936         case AMDGPU_UCODE_ID_VCN1_RAM:
 937                 *type = GFX_FW_TYPE_VCN1_RAM;
 938                 break;
 939         case AMDGPU_UCODE_ID_MAXIMUM:
 940         default:
 941                 return -EINVAL;
 942         }
 943
 944         return 0;
 945 }
 946
 947 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
 948                                        struct psp_gfx_cmd_resp *cmd)
 949 {
 950         int ret;
 951         uint64_t fw_mem_mc_addr = ucode->mc_addr;
 952
 953         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 954
 955         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 956         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
 957         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
 958         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
 959
 960         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
 961         if (ret)
 962                 DRM_ERROR("Unknown firmware type\n");
 963
 964         return ret;
 965 }
 966
 967 static int psp_execute_np_fw_load(struct psp_context *psp,
 968                                struct amdgpu_firmware_info *ucode)
 969 {
 970         int ret = 0;
 971
 972         ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd);
 973         if (ret)
 974                 return ret;
 975
 976         ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
 977                                  psp->fence_buf_mc_addr);
 978
 979         return ret;
 980 }
 981
 982 static int psp_np_fw_load(struct psp_context *psp)
 983 {
 984         int i, ret;
 985         struct amdgpu_firmware_info *ucode;
 986         struct amdgpu_device* adev = psp->adev;
 987
 988         if (psp->autoload_supported) {
 989                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 990                 if (!ucode->fw)
 991                         goto out;
 992
 993                 ret = psp_execute_np_fw_load(psp, ucode);
 994                 if (ret)
 995                         return ret;
 996         }
 997
 998 out:
 999         for (i = 0; i < adev->firmware.max_ucodes; i++) {
1000                 ucode = &adev->firmware.ucode[i];
1001                 if (!ucode->fw)
1002                         continue;
1003
1004                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
1005                     (psp_smu_reload_quirk(psp) || psp->autoload_supported))
1006                         continue;
1007
1008                 if (amdgpu_sriov_vf(adev) &&
1009                    (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
1010                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
1011                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
1012                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
1013                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
1014                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
1015                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
1016                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
1017                     || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
1018                         /*skip ucode loading in SRIOV VF */
1019                         continue;
1020
1021                 if (psp->autoload_supported &&
1022                     (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
1023                      ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
1024                         /* skip mec JT when autoload is enabled */
1025                         continue;
1026
1027                 ret = psp_execute_np_fw_load(psp, ucode);
1028                 if (ret)
1029                         return ret;
1030
1031                 /* Start rlc autoload after psp recieved all the gfx firmware */
1032                 if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM ||
1033                     (adev->asic_type == CHIP_NAVI12 && ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G)) {
1034                         ret = psp_rlc_autoload(psp);
1035                         if (ret) {
1036                                 DRM_ERROR("Failed to start rlc autoload\n");
1037                                 return ret;
1038                         }
1039                 }
1040 #if 0
1041                 /* check if firmware loaded sucessfully */
1042                 if (!amdgpu_psp_check_fw_loading_status(adev, i))
1043                         return -EINVAL;
1044 #endif
1045         }
1046
1047         return 0;
1048 }
1049
1050 static int psp_load_fw(struct amdgpu_device *adev)
1051 {
1052         int ret;
1053         struct psp_context *psp = &adev->psp;
1054
1055         if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) {
1056                 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
1057                 goto skip_memalloc;
1058         }
1059
1060         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1061         if (!psp->cmd)
1062                 return -ENOMEM;
1063
1064         /* this fw pri bo is not used under SRIOV */
1065         if (!amdgpu_sriov_vf(psp->adev)) {
1066                 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
1067                                               AMDGPU_GEM_DOMAIN_GTT,
1068                                               &psp->fw_pri_bo,
1069                                               &psp->fw_pri_mc_addr,
1070                                               &psp->fw_pri_buf);
1071                 if (ret)
1072                         goto failed;
1073         }
1074
1075         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
1076                                         AMDGPU_GEM_DOMAIN_VRAM,
1077                                         &psp->fence_buf_bo,
1078                                         &psp->fence_buf_mc_addr,
1079                                         &psp->fence_buf);
1080         if (ret)
1081                 goto failed;
1082
1083         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
1084                                       AMDGPU_GEM_DOMAIN_VRAM,
1085                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
1086                                       (void **)&psp->cmd_buf_mem);
1087         if (ret)
1088                 goto failed;
1089
1090         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
1091
1092         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
1093         if (ret) {
1094                 DRM_ERROR("PSP ring init failed!\n");
1095                 goto failed;
1096         }
1097
1098 skip_memalloc:
1099         ret = psp_hw_start(psp);
1100         if (ret)
1101                 goto failed;
1102
1103         ret = psp_np_fw_load(psp);
1104         if (ret)
1105                 goto failed;
1106
1107         return 0;
1108
1109 failed:
1110         /*
1111          * all cleanup jobs (xgmi terminate, ras terminate,
1112          * ring destroy, cmd/fence/fw buffers destory,
1113          * psp->cmd destory) are delayed to psp_hw_fini
1114          */
1115         return ret;
1116 }
1117
1118 static int psp_hw_init(void *handle)
1119 {
1120         int ret;
1121         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1122
1123         mutex_lock(&adev->firmware.mutex);
1124         /*
1125          * This sequence is just used on hw_init only once, no need on
1126          * resume.
1127          */
1128         ret = amdgpu_ucode_init_bo(adev);
1129         if (ret)
1130                 goto failed;
1131
1132         ret = psp_load_fw(adev);
1133         if (ret) {
1134                 DRM_ERROR("PSP firmware loading failed\n");
1135                 goto failed;
1136         }
1137
1138         mutex_unlock(&adev->firmware.mutex);
1139         return 0;
1140
1141 failed:
1142         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
1143         mutex_unlock(&adev->firmware.mutex);
1144         return -EINVAL;
1145 }
1146
1147 static int psp_hw_fini(void *handle)
1148 {
1149         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1150         struct psp_context *psp = &adev->psp;
1151
1152         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1153             psp->xgmi_context.initialized == 1)
1154                 psp_xgmi_terminate(psp);
1155
1156         if (psp->adev->psp.ta_fw)
1157                 psp_ras_terminate(psp);
1158
1159         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
1160
1161         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
1162         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
1163                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
1164         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
1165                               &psp->fence_buf_mc_addr, &psp->fence_buf);
1166         amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr,
1167                               &psp->asd_shared_buf);
1168         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
1169                               (void **)&psp->cmd_buf_mem);
1170
1171         kfree(psp->cmd);
1172         psp->cmd = NULL;
1173
1174         return 0;
1175 }
1176
1177 static int psp_suspend(void *handle)
1178 {
1179         int ret;
1180         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1181         struct psp_context *psp = &adev->psp;
1182
1183         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1184             psp->xgmi_context.initialized == 1) {
1185                 ret = psp_xgmi_terminate(psp);
1186                 if (ret) {
1187                         DRM_ERROR("Failed to terminate xgmi ta\n");
1188                         return ret;
1189                 }
1190         }
1191
1192         if (psp->adev->psp.ta_fw) {
1193                 ret = psp_ras_terminate(psp);
1194                 if (ret) {
1195                         DRM_ERROR("Failed to terminate ras ta\n");
1196                         return ret;
1197                 }
1198         }
1199
1200         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
1201         if (ret) {
1202                 DRM_ERROR("PSP ring stop failed\n");
1203                 return ret;
1204         }
1205
1206         return 0;
1207 }
1208
1209 static int psp_resume(void *handle)
1210 {
1211         int ret;
1212         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1213         struct psp_context *psp = &adev->psp;
1214
1215         DRM_INFO("PSP is resuming...\n");
1216
1217         mutex_lock(&adev->firmware.mutex);
1218
1219         ret = psp_hw_start(psp);
1220         if (ret)
1221                 goto failed;
1222
1223         ret = psp_np_fw_load(psp);
1224         if (ret)
1225                 goto failed;
1226
1227         mutex_unlock(&adev->firmware.mutex);
1228
1229         return 0;
1230
1231 failed:
1232         DRM_ERROR("PSP resume failed\n");
1233         mutex_unlock(&adev->firmware.mutex);
1234         return ret;
1235 }
1236
1237 int psp_gpu_reset(struct amdgpu_device *adev)
1238 {
1239         int ret;
1240
1241         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1242                 return 0;
1243
1244         mutex_lock(&adev->psp.mutex);
1245         ret = psp_mode1_reset(&adev->psp);
1246         mutex_unlock(&adev->psp.mutex);
1247
1248         return ret;
1249 }
1250
1251 int psp_rlc_autoload_start(struct psp_context *psp)
1252 {
1253         int ret;
1254         struct psp_gfx_cmd_resp *cmd;
1255
1256         if (amdgpu_sriov_vf(psp->adev))
1257                 return 0;
1258
1259         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1260         if (!cmd)
1261                 return -ENOMEM;
1262
1263         cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
1264
1265         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1266                                  psp->fence_buf_mc_addr);
1267         kfree(cmd);
1268         return ret;
1269 }
1270
1271 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
1272                         uint64_t cmd_gpu_addr, int cmd_size)
1273 {
1274         struct amdgpu_firmware_info ucode = {0};
1275
1276         ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
1277                 AMDGPU_UCODE_ID_VCN0_RAM;
1278         ucode.mc_addr = cmd_gpu_addr;
1279         ucode.ucode_size = cmd_size;
1280
1281         return psp_execute_np_fw_load(&adev->psp, &ucode);
1282 }
1283
1284 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
1285                                         enum AMDGPU_UCODE_ID ucode_type)
1286 {
1287         struct amdgpu_firmware_info *ucode = NULL;
1288
1289         if (!adev->firmware.fw_size)
1290                 return false;
1291
1292         ucode = &adev->firmware.ucode[ucode_type];
1293         if (!ucode->fw || !ucode->ucode_size)
1294                 return false;
1295
1296         return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
1297 }
1298
1299 static int psp_set_clockgating_state(void *handle,
1300                                      enum amd_clockgating_state state)
1301 {
1302         return 0;
1303 }
1304
1305 static int psp_set_powergating_state(void *handle,
1306                                      enum amd_powergating_state state)
1307 {
1308         return 0;
1309 }
1310
1311 const struct amd_ip_funcs psp_ip_funcs = {
1312         .name = "psp",
1313         .early_init = psp_early_init,
1314         .late_init = NULL,
1315         .sw_init = psp_sw_init,
1316         .sw_fini = psp_sw_fini,
1317         .hw_init = psp_hw_init,
1318         .hw_fini = psp_hw_fini,
1319         .suspend = psp_suspend,
1320         .resume = psp_resume,
1321         .is_idle = NULL,
1322         .check_soft_reset = NULL,
1323         .wait_for_idle = NULL,
1324         .soft_reset = NULL,
1325         .set_clockgating_state = psp_set_clockgating_state,
1326         .set_powergating_state = psp_set_powergating_state,
1327 };
1328
1329 static const struct amdgpu_psp_funcs psp_funcs = {
1330         .check_fw_loading_status = psp_check_fw_loading_status,
1331 };
1332
1333 static void psp_set_funcs(struct amdgpu_device *adev)
1334 {
1335         if (NULL == adev->firmware.funcs)
1336                 adev->firmware.funcs = &psp_funcs;
1337 }
1338
1339 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
1340 {
1341         .type = AMD_IP_BLOCK_TYPE_PSP,
1342         .major = 3,
1343         .minor = 1,
1344         .rev = 0,
1345         .funcs = &psp_ip_funcs,
1346 };
1347
1348 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
1349 {
1350         .type = AMD_IP_BLOCK_TYPE_PSP,
1351         .major = 10,
1352         .minor = 0,
1353         .rev = 0,
1354         .funcs = &psp_ip_funcs,
1355 };
1356
1357 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
1358 {
1359         .type = AMD_IP_BLOCK_TYPE_PSP,
1360         .major = 11,
1361         .minor = 0,
1362         .rev = 0,
1363         .funcs = &psp_ip_funcs,
1364 };
1365
1366 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
1367 {
1368         .type = AMD_IP_BLOCK_TYPE_PSP,
1369         .major = 12,
1370         .minor = 0,
1371         .rev = 0,
1372         .funcs = &psp_ip_funcs,
1373 };