drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_psp.h"
  30 #include "amdgpu_ucode.h"
  31 #include "soc15_common.h"
  32 #include "psp_v3_1.h"
  33 #include "psp_v10_0.h"
  34 #include "psp_v11_0.h"
  35 #include "psp_v12_0.h"
  36
  37 #include "amdgpu_ras.h"
  38
  39 static void psp_set_funcs(struct amdgpu_device *adev);
  40
  41 static int psp_early_init(void *handle)
  42 {
  43         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  44         struct psp_context *psp = &adev->psp;
  45
  46         psp_set_funcs(adev);
  47
  48         switch (adev->asic_type) {
  49         case CHIP_VEGA10:
  50         case CHIP_VEGA12:
  51                 psp_v3_1_set_psp_funcs(psp);
  52                 psp->autoload_supported = false;
  53                 break;
  54         case CHIP_RAVEN:
  55                 psp_v10_0_set_psp_funcs(psp);
  56                 psp->autoload_supported = false;
  57                 break;
  58         case CHIP_VEGA20:
  59         case CHIP_ARCTURUS:
  60                 psp_v11_0_set_psp_funcs(psp);
  61                 psp->autoload_supported = false;
  62                 break;
  63         case CHIP_NAVI10:
  64         case CHIP_NAVI14:
  65         case CHIP_NAVI12:
  66                 psp_v11_0_set_psp_funcs(psp);
  67                 psp->autoload_supported = true;
  68                 break;
  69         case CHIP_RENOIR:
  70                 psp_v12_0_set_psp_funcs(psp);
  71                 break;
  72         default:
  73                 return -EINVAL;
  74         }
  75
  76         psp->adev = adev;
  77
  78         return 0;
  79 }
  80
  81 static int psp_sw_init(void *handle)
  82 {
  83         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  84         struct psp_context *psp = &adev->psp;
  85         int ret;
  86
  87         ret = psp_init_microcode(psp);
  88         if (ret) {
  89                 DRM_ERROR("Failed to load psp firmware!\n");
  90                 return ret;
  91         }
  92
  93         ret = psp_mem_training_init(psp);
  94         if (ret) {
  95                 DRM_ERROR("Failed to initialize memory training!\n");
  96                 return ret;
  97         }
  98         ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
  99         if (ret) {
 100                 DRM_ERROR("Failed to process memory training!\n");
 101                 return ret;
 102         }
 103
 104         return 0;
 105 }
 106
 107 static int psp_sw_fini(void *handle)
 108 {
 109         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 110
 111         psp_mem_training_fini(&adev->psp);
 112         release_firmware(adev->psp.sos_fw);
 113         adev->psp.sos_fw = NULL;
 114         release_firmware(adev->psp.asd_fw);
 115         adev->psp.asd_fw = NULL;
 116         if (adev->psp.ta_fw) {
 117                 release_firmware(adev->psp.ta_fw);
 118                 adev->psp.ta_fw = NULL;
 119         }
 120         return 0;
 121 }
 122
 123 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 124                  uint32_t reg_val, uint32_t mask, bool check_changed)
 125 {
 126         uint32_t val;
 127         int i;
 128         struct amdgpu_device *adev = psp->adev;
 129
 130         for (i = 0; i < adev->usec_timeout; i++) {
 131                 val = RREG32(reg_index);
 132                 if (check_changed) {
 133                         if (val != reg_val)
 134                                 return 0;
 135                 } else {
 136                         if ((val & mask) == reg_val)
 137                                 return 0;
 138                 }
 139                 udelay(1);
 140         }
 141
 142         return -ETIME;
 143 }
 144
 145 static int
 146 psp_cmd_submit_buf(struct psp_context *psp,
 147                    struct amdgpu_firmware_info *ucode,
 148                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 149 {
 150         int ret;
 151         int index;
 152         int timeout = 2000;
 153
 154         mutex_lock(&psp->mutex);
 155
 156         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 157
 158         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 159
 160         index = atomic_inc_return(&psp->fence_value);
 161         ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
 162         if (ret) {
 163                 atomic_dec(&psp->fence_value);
 164                 mutex_unlock(&psp->mutex);
 165                 return ret;
 166         }
 167
 168         amdgpu_asic_invalidate_hdp(psp->adev, NULL);
 169         while (*((unsigned int *)psp->fence_buf) != index) {
 170                 if (--timeout == 0)
 171                         break;
 172                 /*
 173                  * Shouldn't wait for timeout when err_event_athub occurs,
 174                  * because gpu reset thread triggered and lock resource should
 175                  * be released for psp resume sequence.
 176                  */
 177                 if (amdgpu_ras_intr_triggered())
 178                         break;
 179                 msleep(1);
 180                 amdgpu_asic_invalidate_hdp(psp->adev, NULL);
 181         }
 182
 183         /* In some cases, psp response status is not 0 even there is no
 184          * problem while the command is submitted. Some version of PSP FW
 185          * doesn't write 0 to that field.
 186          * So here we would like to only print a warning instead of an error
 187          * during psp initialization to avoid breaking hw_init and it doesn't
 188          * return -EINVAL.
 189          */
 190         if (psp->cmd_buf_mem->resp.status || !timeout) {
 191                 if (ucode)
 192                         DRM_WARN("failed to load ucode id (%d) ",
 193                                   ucode->ucode_id);
 194                 DRM_DEBUG_DRIVER("psp command (0x%X) failed and response status is (0x%X)\n",
 195                          psp->cmd_buf_mem->cmd_id,
 196                          psp->cmd_buf_mem->resp.status & GFX_CMD_STATUS_MASK);
 197                 if (!timeout) {
 198                         mutex_unlock(&psp->mutex);
 199                         return -EINVAL;
 200                 }
 201         }
 202
 203         /* get xGMI session id from response buffer */
 204         cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id;
 205
 206         if (ucode) {
 207                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 208                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 209         }
 210         mutex_unlock(&psp->mutex);
 211
 212         return ret;
 213 }
 214
 215 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 216                                  struct psp_gfx_cmd_resp *cmd,
 217                                  uint64_t tmr_mc, uint32_t size)
 218 {
 219         if (psp_support_vmr_ring(psp))
 220                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 221         else
 222                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 223         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 224         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 225         cmd->cmd.cmd_setup_tmr.buf_size = size;
 226 }
 227
 228 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 229                                       uint64_t pri_buf_mc, uint32_t size)
 230 {
 231         cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
 232         cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
 233         cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
 234         cmd->cmd.cmd_load_toc.toc_size = size;
 235 }
 236
 237 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
 238 static int psp_load_toc(struct psp_context *psp,
 239                         uint32_t *tmr_size)
 240 {
 241         int ret;
 242         struct psp_gfx_cmd_resp *cmd;
 243
 244         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 245         if (!cmd)
 246                 return -ENOMEM;
 247         /* Copy toc to psp firmware private buffer */
 248         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 249         memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size);
 250
 251         psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size);
 252
 253         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 254                                  psp->fence_buf_mc_addr);
 255         if (!ret)
 256                 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
 257         kfree(cmd);
 258         return ret;
 259 }
 260
 261 /* Set up Trusted Memory Region */
 262 static int psp_tmr_init(struct psp_context *psp)
 263 {
 264         int ret;
 265         int tmr_size;
 266         void *tmr_buf;
 267         void **pptr;
 268
 269         /*
 270          * According to HW engineer, they prefer the TMR address be "naturally
 271          * aligned" , e.g. the start address be an integer divide of TMR size.
 272          *
 273          * Note: this memory need be reserved till the driver
 274          * uninitializes.
 275          */
 276         tmr_size = PSP_TMR_SIZE;
 277
 278         /* For ASICs support RLC autoload, psp will parse the toc
 279          * and calculate the total size of TMR needed */
 280         if (!amdgpu_sriov_vf(psp->adev) &&
 281             psp->toc_start_addr &&
 282             psp->toc_bin_size &&
 283             psp->fw_pri_buf) {
 284                 ret = psp_load_toc(psp, &tmr_size);
 285                 if (ret) {
 286                         DRM_ERROR("Failed to load toc\n");
 287                         return ret;
 288                 }
 289         }
 290
 291         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 292         ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
 293                                       AMDGPU_GEM_DOMAIN_VRAM,
 294                                       &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 295
 296         return ret;
 297 }
 298
 299 static int psp_tmr_load(struct psp_context *psp)
 300 {
 301         int ret;
 302         struct psp_gfx_cmd_resp *cmd;
 303
 304         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 305         if (!cmd)
 306                 return -ENOMEM;
 307
 308         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr,
 309                              amdgpu_bo_size(psp->tmr_bo));
 310         DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 311                  amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 312
 313         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 314                                  psp->fence_buf_mc_addr);
 315
 316         kfree(cmd);
 317
 318         return ret;
 319 }
 320
 321 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 322                                  uint64_t asd_mc, uint64_t asd_mc_shared,
 323                                  uint32_t size, uint32_t shared_size)
 324 {
 325         cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
 326         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
 327         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
 328         cmd->cmd.cmd_load_ta.app_len = size;
 329
 330         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
 331         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
 332         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 333 }
 334
 335 static int psp_asd_init(struct psp_context *psp)
 336 {
 337         int ret;
 338
 339         /*
 340          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 341          * physical) for shared ASD <-> Driver
 342          */
 343         ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
 344                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 345                                       &psp->asd_shared_bo,
 346                                       &psp->asd_shared_mc_addr,
 347                                       &psp->asd_shared_buf);
 348
 349         return ret;
 350 }
 351
 352 static int psp_asd_load(struct psp_context *psp)
 353 {
 354         int ret;
 355         struct psp_gfx_cmd_resp *cmd;
 356
 357         /* If PSP version doesn't match ASD version, asd loading will be failed.
 358          * add workaround to bypass it for sriov now.
 359          * TODO: add version check to make it common
 360          */
 361         if (amdgpu_sriov_vf(psp->adev))
 362                 return 0;
 363
 364         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 365         if (!cmd)
 366                 return -ENOMEM;
 367
 368         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 369         memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
 370
 371         psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
 372                              psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
 373
 374         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 375                                  psp->fence_buf_mc_addr);
 376
 377         kfree(cmd);
 378
 379         return ret;
 380 }
 381
 382 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 383                 uint32_t id, uint32_t value)
 384 {
 385         cmd->cmd_id = GFX_CMD_ID_PROG_REG;
 386         cmd->cmd.cmd_setup_reg_prog.reg_value = value;
 387         cmd->cmd.cmd_setup_reg_prog.reg_id = id;
 388 }
 389
 390 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
 391                 uint32_t value)
 392 {
 393         struct psp_gfx_cmd_resp *cmd = NULL;
 394         int ret = 0;
 395
 396         if (reg >= PSP_REG_LAST)
 397                 return -EINVAL;
 398
 399         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 400         if (!cmd)
 401                 return -ENOMEM;
 402
 403         psp_prep_reg_prog_cmd_buf(cmd, reg, value);
 404         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 405
 406         kfree(cmd);
 407         return ret;
 408 }
 409
 410 static void psp_prep_xgmi_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 411                                           uint64_t xgmi_ta_mc, uint64_t xgmi_mc_shared,
 412                                           uint32_t xgmi_ta_size, uint32_t shared_size)
 413 {
 414         cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
 415         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(xgmi_ta_mc);
 416         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(xgmi_ta_mc);
 417         cmd->cmd.cmd_load_ta.app_len = xgmi_ta_size;
 418
 419         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(xgmi_mc_shared);
 420         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(xgmi_mc_shared);
 421         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 422 }
 423
 424 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
 425 {
 426         int ret;
 427
 428         /*
 429          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 430          * physical) for xgmi ta <-> Driver
 431          */
 432         ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE,
 433                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 434                                       &psp->xgmi_context.xgmi_shared_bo,
 435                                       &psp->xgmi_context.xgmi_shared_mc_addr,
 436                                       &psp->xgmi_context.xgmi_shared_buf);
 437
 438         return ret;
 439 }
 440
 441 static int psp_xgmi_load(struct psp_context *psp)
 442 {
 443         int ret;
 444         struct psp_gfx_cmd_resp *cmd;
 445
 446         /*
 447          * TODO: bypass the loading in sriov for now
 448          */
 449         if (amdgpu_sriov_vf(psp->adev))
 450                 return 0;
 451
 452         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 453         if (!cmd)
 454                 return -ENOMEM;
 455
 456         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 457         memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
 458
 459         psp_prep_xgmi_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
 460                                       psp->xgmi_context.xgmi_shared_mc_addr,
 461                                       psp->ta_xgmi_ucode_size, PSP_XGMI_SHARED_MEM_SIZE);
 462
 463         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 464                                  psp->fence_buf_mc_addr);
 465
 466         if (!ret) {
 467                 psp->xgmi_context.initialized = 1;
 468                 psp->xgmi_context.session_id = cmd->resp.session_id;
 469         }
 470
 471         kfree(cmd);
 472
 473         return ret;
 474 }
 475
 476 static void psp_prep_xgmi_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 477                                             uint32_t xgmi_session_id)
 478 {
 479         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 480         cmd->cmd.cmd_unload_ta.session_id = xgmi_session_id;
 481 }
 482
 483 static int psp_xgmi_unload(struct psp_context *psp)
 484 {
 485         int ret;
 486         struct psp_gfx_cmd_resp *cmd;
 487
 488         /*
 489          * TODO: bypass the unloading in sriov for now
 490          */
 491         if (amdgpu_sriov_vf(psp->adev))
 492                 return 0;
 493
 494         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 495         if (!cmd)
 496                 return -ENOMEM;
 497
 498         psp_prep_xgmi_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);
 499
 500         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 501                                  psp->fence_buf_mc_addr);
 502
 503         kfree(cmd);
 504
 505         return ret;
 506 }
 507
 508 static void psp_prep_xgmi_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 509                                             uint32_t ta_cmd_id,
 510                                             uint32_t xgmi_session_id)
 511 {
 512         cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
 513         cmd->cmd.cmd_invoke_cmd.session_id = xgmi_session_id;
 514         cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
 515         /* Note: cmd_invoke_cmd.buf is not used for now */
 516 }
 517
 518 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
 519 {
 520         int ret;
 521         struct psp_gfx_cmd_resp *cmd;
 522
 523         /*
 524          * TODO: bypass the loading in sriov for now
 525         */
 526         if (amdgpu_sriov_vf(psp->adev))
 527                 return 0;
 528
 529         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 530         if (!cmd)
 531                 return -ENOMEM;
 532
 533         psp_prep_xgmi_ta_invoke_cmd_buf(cmd, ta_cmd_id,
 534                                         psp->xgmi_context.session_id);
 535
 536         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 537                                  psp->fence_buf_mc_addr);
 538
 539         kfree(cmd);
 540
 541         return ret;
 542 }
 543
 544 static int psp_xgmi_terminate(struct psp_context *psp)
 545 {
 546         int ret;
 547
 548         if (!psp->xgmi_context.initialized)
 549                 return 0;
 550
 551         ret = psp_xgmi_unload(psp);
 552         if (ret)
 553                 return ret;
 554
 555         psp->xgmi_context.initialized = 0;
 556
 557         /* free xgmi shared memory */
 558         amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo,
 559                         &psp->xgmi_context.xgmi_shared_mc_addr,
 560                         &psp->xgmi_context.xgmi_shared_buf);
 561
 562         return 0;
 563 }
 564
 565 static int psp_xgmi_initialize(struct psp_context *psp)
 566 {
 567         struct ta_xgmi_shared_memory *xgmi_cmd;
 568         int ret;
 569
 570         if (!psp->adev->psp.ta_fw ||
 571             !psp->adev->psp.ta_xgmi_ucode_size ||
 572             !psp->adev->psp.ta_xgmi_start_addr)
 573                 return -ENOENT;
 574
 575         if (!psp->xgmi_context.initialized) {
 576                 ret = psp_xgmi_init_shared_buf(psp);
 577                 if (ret)
 578                         return ret;
 579         }
 580
 581         /* Load XGMI TA */
 582         ret = psp_xgmi_load(psp);
 583         if (ret)
 584                 return ret;
 585
 586         /* Initialize XGMI session */
 587         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf);
 588         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 589         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
 590
 591         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 592
 593         return ret;
 594 }
 595
 596 // ras begin
 597 static void psp_prep_ras_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 598                 uint64_t ras_ta_mc, uint64_t ras_mc_shared,
 599                 uint32_t ras_ta_size, uint32_t shared_size)
 600 {
 601         cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
 602         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ras_ta_mc);
 603         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ras_ta_mc);
 604         cmd->cmd.cmd_load_ta.app_len = ras_ta_size;
 605
 606         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ras_mc_shared);
 607         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ras_mc_shared);
 608         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 609 }
 610
 611 static int psp_ras_init_shared_buf(struct psp_context *psp)
 612 {
 613         int ret;
 614
 615         /*
 616          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 617          * physical) for ras ta <-> Driver
 618          */
 619         ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE,
 620                         PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 621                         &psp->ras.ras_shared_bo,
 622                         &psp->ras.ras_shared_mc_addr,
 623                         &psp->ras.ras_shared_buf);
 624
 625         return ret;
 626 }
 627
 628 static int psp_ras_load(struct psp_context *psp)
 629 {
 630         int ret;
 631         struct psp_gfx_cmd_resp *cmd;
 632
 633         /*
 634          * TODO: bypass the loading in sriov for now
 635          */
 636         if (amdgpu_sriov_vf(psp->adev))
 637                 return 0;
 638
 639         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 640         if (!cmd)
 641                 return -ENOMEM;
 642
 643         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 644         memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size);
 645
 646         psp_prep_ras_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
 647                         psp->ras.ras_shared_mc_addr,
 648                         psp->ta_ras_ucode_size, PSP_RAS_SHARED_MEM_SIZE);
 649
 650         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 651                         psp->fence_buf_mc_addr);
 652
 653         if (!ret) {
 654                 psp->ras.ras_initialized = 1;
 655                 psp->ras.session_id = cmd->resp.session_id;
 656         }
 657
 658         kfree(cmd);
 659
 660         return ret;
 661 }
 662
 663 static void psp_prep_ras_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 664                                                 uint32_t ras_session_id)
 665 {
 666         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 667         cmd->cmd.cmd_unload_ta.session_id = ras_session_id;
 668 }
 669
 670 static int psp_ras_unload(struct psp_context *psp)
 671 {
 672         int ret;
 673         struct psp_gfx_cmd_resp *cmd;
 674
 675         /*
 676          * TODO: bypass the unloading in sriov for now
 677          */
 678         if (amdgpu_sriov_vf(psp->adev))
 679                 return 0;
 680
 681         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 682         if (!cmd)
 683                 return -ENOMEM;
 684
 685         psp_prep_ras_ta_unload_cmd_buf(cmd, psp->ras.session_id);
 686
 687         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 688                         psp->fence_buf_mc_addr);
 689
 690         kfree(cmd);
 691
 692         return ret;
 693 }
 694
 695 static void psp_prep_ras_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 696                 uint32_t ta_cmd_id,
 697                 uint32_t ras_session_id)
 698 {
 699         cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
 700         cmd->cmd.cmd_invoke_cmd.session_id = ras_session_id;
 701         cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
 702         /* Note: cmd_invoke_cmd.buf is not used for now */
 703 }
 704
 705 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
 706 {
 707         int ret;
 708         struct psp_gfx_cmd_resp *cmd;
 709
 710         /*
 711          * TODO: bypass the loading in sriov for now
 712          */
 713         if (amdgpu_sriov_vf(psp->adev))
 714                 return 0;
 715
 716         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 717         if (!cmd)
 718                 return -ENOMEM;
 719
 720         psp_prep_ras_ta_invoke_cmd_buf(cmd, ta_cmd_id,
 721                         psp->ras.session_id);
 722
 723         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 724                         psp->fence_buf_mc_addr);
 725
 726         kfree(cmd);
 727
 728         return ret;
 729 }
 730
 731 int psp_ras_enable_features(struct psp_context *psp,
 732                 union ta_ras_cmd_input *info, bool enable)
 733 {
 734         struct ta_ras_shared_memory *ras_cmd;
 735         int ret;
 736
 737         if (!psp->ras.ras_initialized)
 738                 return -EINVAL;
 739
 740         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
 741         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
 742
 743         if (enable)
 744                 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
 745         else
 746                 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
 747
 748         ras_cmd->ras_in_message = *info;
 749
 750         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
 751         if (ret)
 752                 return -EINVAL;
 753
 754         return ras_cmd->ras_status;
 755 }
 756
 757 static int psp_ras_terminate(struct psp_context *psp)
 758 {
 759         int ret;
 760
 761         if (!psp->ras.ras_initialized)
 762                 return 0;
 763
 764         ret = psp_ras_unload(psp);
 765         if (ret)
 766                 return ret;
 767
 768         psp->ras.ras_initialized = 0;
 769
 770         /* free ras shared memory */
 771         amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo,
 772                         &psp->ras.ras_shared_mc_addr,
 773                         &psp->ras.ras_shared_buf);
 774
 775         return 0;
 776 }
 777
 778 static int psp_ras_initialize(struct psp_context *psp)
 779 {
 780         int ret;
 781
 782         if (!psp->adev->psp.ta_ras_ucode_size ||
 783             !psp->adev->psp.ta_ras_start_addr) {
 784                 dev_warn(psp->adev->dev, "RAS: ras ta ucode is not available\n");
 785                 return 0;
 786         }
 787
 788         if (!psp->ras.ras_initialized) {
 789                 ret = psp_ras_init_shared_buf(psp);
 790                 if (ret)
 791                         return ret;
 792         }
 793
 794         ret = psp_ras_load(psp);
 795         if (ret)
 796                 return ret;
 797
 798         return 0;
 799 }
 800 // ras end
 801
 802 // HDCP start
 803 static void psp_prep_hdcp_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 804                                           uint64_t hdcp_ta_mc,
 805                                           uint64_t hdcp_mc_shared,
 806                                           uint32_t hdcp_ta_size,
 807                                           uint32_t shared_size)
 808 {
 809         cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
 810         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(hdcp_ta_mc);
 811         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(hdcp_ta_mc);
 812         cmd->cmd.cmd_load_ta.app_len = hdcp_ta_size;
 813
 814         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
 815                 lower_32_bits(hdcp_mc_shared);
 816         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
 817                 upper_32_bits(hdcp_mc_shared);
 818         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 819 }
 820
 821 static int psp_hdcp_init_shared_buf(struct psp_context *psp)
 822 {
 823         int ret;
 824
 825         /*
 826          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 827          * physical) for hdcp ta <-> Driver
 828          */
 829         ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE,
 830                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 831                                       &psp->hdcp_context.hdcp_shared_bo,
 832                                       &psp->hdcp_context.hdcp_shared_mc_addr,
 833                                       &psp->hdcp_context.hdcp_shared_buf);
 834
 835         return ret;
 836 }
 837
 838 static int psp_hdcp_load(struct psp_context *psp)
 839 {
 840         int ret;
 841         struct psp_gfx_cmd_resp *cmd;
 842
 843         /*
 844          * TODO: bypass the loading in sriov for now
 845          */
 846         if (amdgpu_sriov_vf(psp->adev))
 847                 return 0;
 848
 849         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 850         if (!cmd)
 851                 return -ENOMEM;
 852
 853         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 854         memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr,
 855                psp->ta_hdcp_ucode_size);
 856
 857         psp_prep_hdcp_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
 858                                       psp->hdcp_context.hdcp_shared_mc_addr,
 859                                       psp->ta_hdcp_ucode_size,
 860                                       PSP_HDCP_SHARED_MEM_SIZE);
 861
 862         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 863
 864         if (!ret) {
 865                 psp->hdcp_context.hdcp_initialized = 1;
 866                 psp->hdcp_context.session_id = cmd->resp.session_id;
 867         }
 868
 869         kfree(cmd);
 870
 871         return ret;
 872 }
 873 static int psp_hdcp_initialize(struct psp_context *psp)
 874 {
 875         int ret;
 876
 877         if (!psp->adev->psp.ta_hdcp_ucode_size ||
 878             !psp->adev->psp.ta_hdcp_start_addr) {
 879                 dev_warn(psp->adev->dev, "HDCP: hdcp ta ucode is not available\n");
 880                 return 0;
 881         }
 882
 883         if (!psp->hdcp_context.hdcp_initialized) {
 884                 ret = psp_hdcp_init_shared_buf(psp);
 885                 if (ret)
 886                         return ret;
 887         }
 888
 889         ret = psp_hdcp_load(psp);
 890         if (ret)
 891                 return ret;
 892
 893         return 0;
 894 }
 895 static void psp_prep_hdcp_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 896                                             uint32_t hdcp_session_id)
 897 {
 898         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 899         cmd->cmd.cmd_unload_ta.session_id = hdcp_session_id;
 900 }
 901
 902 static int psp_hdcp_unload(struct psp_context *psp)
 903 {
 904         int ret;
 905         struct psp_gfx_cmd_resp *cmd;
 906
 907         /*
 908          * TODO: bypass the unloading in sriov for now
 909          */
 910         if (amdgpu_sriov_vf(psp->adev))
 911                 return 0;
 912
 913         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 914         if (!cmd)
 915                 return -ENOMEM;
 916
 917         psp_prep_hdcp_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id);
 918
 919         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 920
 921         kfree(cmd);
 922
 923         return ret;
 924 }
 925
 926 static void psp_prep_hdcp_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 927                                             uint32_t ta_cmd_id,
 928                                             uint32_t hdcp_session_id)
 929 {
 930         cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
 931         cmd->cmd.cmd_invoke_cmd.session_id = hdcp_session_id;
 932         cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
 933         /* Note: cmd_invoke_cmd.buf is not used for now */
 934 }
 935
 936 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
 937 {
 938         int ret;
 939         struct psp_gfx_cmd_resp *cmd;
 940
 941         /*
 942          * TODO: bypass the loading in sriov for now
 943          */
 944         if (amdgpu_sriov_vf(psp->adev))
 945                 return 0;
 946
 947         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 948         if (!cmd)
 949                 return -ENOMEM;
 950
 951         psp_prep_hdcp_ta_invoke_cmd_buf(cmd, ta_cmd_id,
 952                                         psp->hdcp_context.session_id);
 953
 954         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 955
 956         kfree(cmd);
 957
 958         return ret;
 959 }
 960
 961 static int psp_hdcp_terminate(struct psp_context *psp)
 962 {
 963         int ret;
 964
 965         if (!psp->hdcp_context.hdcp_initialized)
 966                 return 0;
 967
 968         ret = psp_hdcp_unload(psp);
 969         if (ret)
 970                 return ret;
 971
 972         psp->hdcp_context.hdcp_initialized = 0;
 973
 974         /* free hdcp shared memory */
 975         amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo,
 976                               &psp->hdcp_context.hdcp_shared_mc_addr,
 977                               &psp->hdcp_context.hdcp_shared_buf);
 978
 979         return 0;
 980 }
 981 // HDCP end
 982
 983 // DTM start
 984 static void psp_prep_dtm_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 985                                          uint64_t dtm_ta_mc,
 986                                          uint64_t dtm_mc_shared,
 987                                          uint32_t dtm_ta_size,
 988                                          uint32_t shared_size)
 989 {
 990         cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
 991         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(dtm_ta_mc);
 992         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(dtm_ta_mc);
 993         cmd->cmd.cmd_load_ta.app_len = dtm_ta_size;
 994
 995         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(dtm_mc_shared);
 996         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(dtm_mc_shared);
 997         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 998 }
 999
1000 static int psp_dtm_init_shared_buf(struct psp_context *psp)
1001 {
1002         int ret;
1003
1004         /*
1005          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1006          * physical) for dtm ta <-> Driver
1007          */
1008         ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE,
1009                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1010                                       &psp->dtm_context.dtm_shared_bo,
1011                                       &psp->dtm_context.dtm_shared_mc_addr,
1012                                       &psp->dtm_context.dtm_shared_buf);
1013
1014         return ret;
1015 }
1016
1017 static int psp_dtm_load(struct psp_context *psp)
1018 {
1019         int ret;
1020         struct psp_gfx_cmd_resp *cmd;
1021
1022         /*
1023          * TODO: bypass the loading in sriov for now
1024          */
1025         if (amdgpu_sriov_vf(psp->adev))
1026                 return 0;
1027
1028         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1029         if (!cmd)
1030                 return -ENOMEM;
1031
1032         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1033         memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size);
1034
1035         psp_prep_dtm_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
1036                                      psp->dtm_context.dtm_shared_mc_addr,
1037                                      psp->ta_dtm_ucode_size,
1038                                      PSP_DTM_SHARED_MEM_SIZE);
1039
1040         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1041
1042         if (!ret) {
1043                 psp->dtm_context.dtm_initialized = 1;
1044                 psp->dtm_context.session_id = cmd->resp.session_id;
1045         }
1046
1047         kfree(cmd);
1048
1049         return ret;
1050 }
1051
1052 static int psp_dtm_initialize(struct psp_context *psp)
1053 {
1054         int ret;
1055
1056         if (!psp->adev->psp.ta_dtm_ucode_size ||
1057             !psp->adev->psp.ta_dtm_start_addr) {
1058                 dev_warn(psp->adev->dev, "DTM: dtm ta ucode is not available\n");
1059                 return 0;
1060         }
1061
1062         if (!psp->dtm_context.dtm_initialized) {
1063                 ret = psp_dtm_init_shared_buf(psp);
1064                 if (ret)
1065                         return ret;
1066         }
1067
1068         ret = psp_dtm_load(psp);
1069         if (ret)
1070                 return ret;
1071
1072         return 0;
1073 }
1074
1075 static void psp_prep_dtm_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1076                                            uint32_t ta_cmd_id,
1077                                            uint32_t dtm_session_id)
1078 {
1079         cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
1080         cmd->cmd.cmd_invoke_cmd.session_id = dtm_session_id;
1081         cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
1082         /* Note: cmd_invoke_cmd.buf is not used for now */
1083 }
1084
1085 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1086 {
1087         int ret;
1088         struct psp_gfx_cmd_resp *cmd;
1089
1090         /*
1091          * TODO: bypass the loading in sriov for now
1092          */
1093         if (amdgpu_sriov_vf(psp->adev))
1094                 return 0;
1095
1096         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1097         if (!cmd)
1098                 return -ENOMEM;
1099
1100         psp_prep_dtm_ta_invoke_cmd_buf(cmd, ta_cmd_id,
1101                                        psp->dtm_context.session_id);
1102
1103         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1104
1105         kfree(cmd);
1106
1107         return ret;
1108 }
1109
1110 static int psp_dtm_terminate(struct psp_context *psp)
1111 {
1112         int ret;
1113
1114         if (!psp->dtm_context.dtm_initialized)
1115                 return 0;
1116
1117         ret = psp_hdcp_unload(psp);
1118         if (ret)
1119                 return ret;
1120
1121         psp->dtm_context.dtm_initialized = 0;
1122
1123         /* free hdcp shared memory */
1124         amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo,
1125                               &psp->dtm_context.dtm_shared_mc_addr,
1126                               &psp->dtm_context.dtm_shared_buf);
1127
1128         return 0;
1129 }
1130 // DTM end
1131
1132 static int psp_hw_start(struct psp_context *psp)
1133 {
1134         struct amdgpu_device *adev = psp->adev;
1135         int ret;
1136
1137         if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
1138                 if (psp->kdb_bin_size &&
1139                     (psp->funcs->bootloader_load_kdb != NULL)) {
1140                         ret = psp_bootloader_load_kdb(psp);
1141                         if (ret) {
1142                                 DRM_ERROR("PSP load kdb failed!\n");
1143                                 return ret;
1144                         }
1145                 }
1146
1147                 ret = psp_bootloader_load_sysdrv(psp);
1148                 if (ret) {
1149                         DRM_ERROR("PSP load sysdrv failed!\n");
1150                         return ret;
1151                 }
1152
1153                 ret = psp_bootloader_load_sos(psp);
1154                 if (ret) {
1155                         DRM_ERROR("PSP load sos failed!\n");
1156                         return ret;
1157                 }
1158         }
1159
1160         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
1161         if (ret) {
1162                 DRM_ERROR("PSP create ring failed!\n");
1163                 return ret;
1164         }
1165
1166         ret = psp_tmr_init(psp);
1167         if (ret) {
1168                 DRM_ERROR("PSP tmr init failed!\n");
1169                 return ret;
1170         }
1171
1172         ret = psp_tmr_load(psp);
1173         if (ret) {
1174                 DRM_ERROR("PSP load tmr failed!\n");
1175                 return ret;
1176         }
1177
1178         ret = psp_asd_init(psp);
1179         if (ret) {
1180                 DRM_ERROR("PSP asd init failed!\n");
1181                 return ret;
1182         }
1183
1184         ret = psp_asd_load(psp);
1185         if (ret) {
1186                 DRM_ERROR("PSP load asd failed!\n");
1187                 return ret;
1188         }
1189
1190         if (adev->gmc.xgmi.num_physical_nodes > 1) {
1191                 ret = psp_xgmi_initialize(psp);
1192                 /* Warning the XGMI seesion initialize failure
1193                  * Instead of stop driver initialization
1194                  */
1195                 if (ret)
1196                         dev_err(psp->adev->dev,
1197                                 "XGMI: Failed to initialize XGMI session\n");
1198         }
1199
1200         if (psp->adev->psp.ta_fw) {
1201                 ret = psp_ras_initialize(psp);
1202                 if (ret)
1203                         dev_err(psp->adev->dev,
1204                                         "RAS: Failed to initialize RAS\n");
1205
1206                 ret = psp_hdcp_initialize(psp);
1207                 if (ret)
1208                         dev_err(psp->adev->dev,
1209                                 "HDCP: Failed to initialize HDCP\n");
1210
1211                 ret = psp_dtm_initialize(psp);
1212                 if (ret)
1213                         dev_err(psp->adev->dev,
1214                                 "DTM: Failed to initialize DTM\n");
1215         }
1216
1217         return 0;
1218 }
1219
1220 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
1221                            enum psp_gfx_fw_type *type)
1222 {
1223         switch (ucode->ucode_id) {
1224         case AMDGPU_UCODE_ID_SDMA0:
1225                 *type = GFX_FW_TYPE_SDMA0;
1226                 break;
1227         case AMDGPU_UCODE_ID_SDMA1:
1228                 *type = GFX_FW_TYPE_SDMA1;
1229                 break;
1230         case AMDGPU_UCODE_ID_SDMA2:
1231                 *type = GFX_FW_TYPE_SDMA2;
1232                 break;
1233         case AMDGPU_UCODE_ID_SDMA3:
1234                 *type = GFX_FW_TYPE_SDMA3;
1235                 break;
1236         case AMDGPU_UCODE_ID_SDMA4:
1237                 *type = GFX_FW_TYPE_SDMA4;
1238                 break;
1239         case AMDGPU_UCODE_ID_SDMA5:
1240                 *type = GFX_FW_TYPE_SDMA5;
1241                 break;
1242         case AMDGPU_UCODE_ID_SDMA6:
1243                 *type = GFX_FW_TYPE_SDMA6;
1244                 break;
1245         case AMDGPU_UCODE_ID_SDMA7:
1246                 *type = GFX_FW_TYPE_SDMA7;
1247                 break;
1248         case AMDGPU_UCODE_ID_CP_CE:
1249                 *type = GFX_FW_TYPE_CP_CE;
1250                 break;
1251         case AMDGPU_UCODE_ID_CP_PFP:
1252                 *type = GFX_FW_TYPE_CP_PFP;
1253                 break;
1254         case AMDGPU_UCODE_ID_CP_ME:
1255                 *type = GFX_FW_TYPE_CP_ME;
1256                 break;
1257         case AMDGPU_UCODE_ID_CP_MEC1:
1258                 *type = GFX_FW_TYPE_CP_MEC;
1259                 break;
1260         case AMDGPU_UCODE_ID_CP_MEC1_JT:
1261                 *type = GFX_FW_TYPE_CP_MEC_ME1;
1262                 break;
1263         case AMDGPU_UCODE_ID_CP_MEC2:
1264                 *type = GFX_FW_TYPE_CP_MEC;
1265                 break;
1266         case AMDGPU_UCODE_ID_CP_MEC2_JT:
1267                 *type = GFX_FW_TYPE_CP_MEC_ME2;
1268                 break;
1269         case AMDGPU_UCODE_ID_RLC_G:
1270                 *type = GFX_FW_TYPE_RLC_G;
1271                 break;
1272         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
1273                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
1274                 break;
1275         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
1276                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
1277                 break;
1278         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
1279                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
1280                 break;
1281         case AMDGPU_UCODE_ID_SMC:
1282                 *type = GFX_FW_TYPE_SMU;
1283                 break;
1284         case AMDGPU_UCODE_ID_UVD:
1285                 *type = GFX_FW_TYPE_UVD;
1286                 break;
1287         case AMDGPU_UCODE_ID_UVD1:
1288                 *type = GFX_FW_TYPE_UVD1;
1289                 break;
1290         case AMDGPU_UCODE_ID_VCE:
1291                 *type = GFX_FW_TYPE_VCE;
1292                 break;
1293         case AMDGPU_UCODE_ID_VCN:
1294                 *type = GFX_FW_TYPE_VCN;
1295                 break;
1296         case AMDGPU_UCODE_ID_DMCU_ERAM:
1297                 *type = GFX_FW_TYPE_DMCU_ERAM;
1298                 break;
1299         case AMDGPU_UCODE_ID_DMCU_INTV:
1300                 *type = GFX_FW_TYPE_DMCU_ISR;
1301                 break;
1302         case AMDGPU_UCODE_ID_VCN0_RAM:
1303                 *type = GFX_FW_TYPE_VCN0_RAM;
1304                 break;
1305         case AMDGPU_UCODE_ID_VCN1_RAM:
1306                 *type = GFX_FW_TYPE_VCN1_RAM;
1307                 break;
1308         case AMDGPU_UCODE_ID_DMCUB:
1309                 *type = GFX_FW_TYPE_DMUB;
1310                 break;
1311         case AMDGPU_UCODE_ID_MAXIMUM:
1312         default:
1313                 return -EINVAL;
1314         }
1315
1316         return 0;
1317 }
1318
1319 static void psp_print_fw_hdr(struct psp_context *psp,
1320                              struct amdgpu_firmware_info *ucode)
1321 {
1322         struct amdgpu_device *adev = psp->adev;
1323         struct common_firmware_header *hdr;
1324
1325         switch (ucode->ucode_id) {
1326         case AMDGPU_UCODE_ID_SDMA0:
1327         case AMDGPU_UCODE_ID_SDMA1:
1328         case AMDGPU_UCODE_ID_SDMA2:
1329         case AMDGPU_UCODE_ID_SDMA3:
1330         case AMDGPU_UCODE_ID_SDMA4:
1331         case AMDGPU_UCODE_ID_SDMA5:
1332         case AMDGPU_UCODE_ID_SDMA6:
1333         case AMDGPU_UCODE_ID_SDMA7:
1334                 hdr = (struct common_firmware_header *)
1335                         adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
1336                 amdgpu_ucode_print_sdma_hdr(hdr);
1337                 break;
1338         case AMDGPU_UCODE_ID_CP_CE:
1339                 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
1340                 amdgpu_ucode_print_gfx_hdr(hdr);
1341                 break;
1342         case AMDGPU_UCODE_ID_CP_PFP:
1343                 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
1344                 amdgpu_ucode_print_gfx_hdr(hdr);
1345                 break;
1346         case AMDGPU_UCODE_ID_CP_ME:
1347                 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
1348                 amdgpu_ucode_print_gfx_hdr(hdr);
1349                 break;
1350         case AMDGPU_UCODE_ID_CP_MEC1:
1351                 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
1352                 amdgpu_ucode_print_gfx_hdr(hdr);
1353                 break;
1354         case AMDGPU_UCODE_ID_RLC_G:
1355                 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
1356                 amdgpu_ucode_print_rlc_hdr(hdr);
1357                 break;
1358         case AMDGPU_UCODE_ID_SMC:
1359                 hdr = (struct common_firmware_header *)adev->pm.fw->data;
1360                 amdgpu_ucode_print_smc_hdr(hdr);
1361                 break;
1362         default:
1363                 break;
1364         }
1365 }
1366
1367 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
1368                                        struct psp_gfx_cmd_resp *cmd)
1369 {
1370         int ret;
1371         uint64_t fw_mem_mc_addr = ucode->mc_addr;
1372
1373         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
1374
1375         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
1376         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
1377         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
1378         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
1379
1380         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
1381         if (ret)
1382                 DRM_ERROR("Unknown firmware type\n");
1383
1384         return ret;
1385 }
1386
1387 static int psp_execute_np_fw_load(struct psp_context *psp,
1388                                struct amdgpu_firmware_info *ucode)
1389 {
1390         int ret = 0;
1391
1392         ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd);
1393         if (ret)
1394                 return ret;
1395
1396         ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
1397                                  psp->fence_buf_mc_addr);
1398
1399         return ret;
1400 }
1401
1402 static int psp_np_fw_load(struct psp_context *psp)
1403 {
1404         int i, ret;
1405         struct amdgpu_firmware_info *ucode;
1406         struct amdgpu_device* adev = psp->adev;
1407
1408         if (psp->autoload_supported) {
1409                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
1410                 if (!ucode->fw)
1411                         goto out;
1412
1413                 ret = psp_execute_np_fw_load(psp, ucode);
1414                 if (ret)
1415                         return ret;
1416         }
1417
1418 out:
1419         for (i = 0; i < adev->firmware.max_ucodes; i++) {
1420                 ucode = &adev->firmware.ucode[i];
1421                 if (!ucode->fw)
1422                         continue;
1423
1424                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
1425                     (psp_smu_reload_quirk(psp) || psp->autoload_supported))
1426                         continue;
1427
1428                 if (amdgpu_sriov_vf(adev) &&
1429                    (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
1430                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
1431                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
1432                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
1433                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
1434                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
1435                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
1436                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
1437                     || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
1438                         /*skip ucode loading in SRIOV VF */
1439                         continue;
1440
1441                 if (psp->autoload_supported &&
1442                     (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
1443                      ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
1444                         /* skip mec JT when autoload is enabled */
1445                         continue;
1446
1447                 psp_print_fw_hdr(psp, ucode);
1448
1449                 ret = psp_execute_np_fw_load(psp, ucode);
1450                 if (ret)
1451                         return ret;
1452
1453                 /* Start rlc autoload after psp recieved all the gfx firmware */
1454                 if (psp->autoload_supported && ucode->ucode_id ==
1455                         AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
1456                         ret = psp_rlc_autoload(psp);
1457                         if (ret) {
1458                                 DRM_ERROR("Failed to start rlc autoload\n");
1459                                 return ret;
1460                         }
1461                 }
1462 #if 0
1463                 /* check if firmware loaded sucessfully */
1464                 if (!amdgpu_psp_check_fw_loading_status(adev, i))
1465                         return -EINVAL;
1466 #endif
1467         }
1468
1469         return 0;
1470 }
1471
1472 static int psp_load_fw(struct amdgpu_device *adev)
1473 {
1474         int ret;
1475         struct psp_context *psp = &adev->psp;
1476
1477         if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) {
1478                 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
1479                 goto skip_memalloc;
1480         }
1481
1482         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1483         if (!psp->cmd)
1484                 return -ENOMEM;
1485
1486         /* this fw pri bo is not used under SRIOV */
1487         if (!amdgpu_sriov_vf(psp->adev)) {
1488                 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
1489                                               AMDGPU_GEM_DOMAIN_GTT,
1490                                               &psp->fw_pri_bo,
1491                                               &psp->fw_pri_mc_addr,
1492                                               &psp->fw_pri_buf);
1493                 if (ret)
1494                         goto failed;
1495         }
1496
1497         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
1498                                         AMDGPU_GEM_DOMAIN_VRAM,
1499                                         &psp->fence_buf_bo,
1500                                         &psp->fence_buf_mc_addr,
1501                                         &psp->fence_buf);
1502         if (ret)
1503                 goto failed;
1504
1505         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
1506                                       AMDGPU_GEM_DOMAIN_VRAM,
1507                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
1508                                       (void **)&psp->cmd_buf_mem);
1509         if (ret)
1510                 goto failed;
1511
1512         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
1513
1514         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
1515         if (ret) {
1516                 DRM_ERROR("PSP ring init failed!\n");
1517                 goto failed;
1518         }
1519
1520 skip_memalloc:
1521         ret = psp_hw_start(psp);
1522         if (ret)
1523                 goto failed;
1524
1525         ret = psp_np_fw_load(psp);
1526         if (ret)
1527                 goto failed;
1528
1529         return 0;
1530
1531 failed:
1532         /*
1533          * all cleanup jobs (xgmi terminate, ras terminate,
1534          * ring destroy, cmd/fence/fw buffers destory,
1535          * psp->cmd destory) are delayed to psp_hw_fini
1536          */
1537         return ret;
1538 }
1539
1540 static int psp_hw_init(void *handle)
1541 {
1542         int ret;
1543         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1544
1545         mutex_lock(&adev->firmware.mutex);
1546         /*
1547          * This sequence is just used on hw_init only once, no need on
1548          * resume.
1549          */
1550         ret = amdgpu_ucode_init_bo(adev);
1551         if (ret)
1552                 goto failed;
1553
1554         ret = psp_load_fw(adev);
1555         if (ret) {
1556                 DRM_ERROR("PSP firmware loading failed\n");
1557                 goto failed;
1558         }
1559
1560         mutex_unlock(&adev->firmware.mutex);
1561         return 0;
1562
1563 failed:
1564         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
1565         mutex_unlock(&adev->firmware.mutex);
1566         return -EINVAL;
1567 }
1568
1569 static int psp_hw_fini(void *handle)
1570 {
1571         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1572         struct psp_context *psp = &adev->psp;
1573         void *tmr_buf;
1574         void **pptr;
1575
1576         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1577             psp->xgmi_context.initialized == 1)
1578                 psp_xgmi_terminate(psp);
1579
1580         if (psp->adev->psp.ta_fw) {
1581                 psp_ras_terminate(psp);
1582                 psp_dtm_terminate(psp);
1583                 psp_hdcp_terminate(psp);
1584         }
1585
1586         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
1587
1588         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
1589         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
1590         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
1591                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
1592         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
1593                               &psp->fence_buf_mc_addr, &psp->fence_buf);
1594         amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr,
1595                               &psp->asd_shared_buf);
1596         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
1597                               (void **)&psp->cmd_buf_mem);
1598
1599         kfree(psp->cmd);
1600         psp->cmd = NULL;
1601
1602         return 0;
1603 }
1604
1605 static int psp_suspend(void *handle)
1606 {
1607         int ret;
1608         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1609         struct psp_context *psp = &adev->psp;
1610
1611         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1612             psp->xgmi_context.initialized == 1) {
1613                 ret = psp_xgmi_terminate(psp);
1614                 if (ret) {
1615                         DRM_ERROR("Failed to terminate xgmi ta\n");
1616                         return ret;
1617                 }
1618         }
1619
1620         if (psp->adev->psp.ta_fw) {
1621                 ret = psp_ras_terminate(psp);
1622                 if (ret) {
1623                         DRM_ERROR("Failed to terminate ras ta\n");
1624                         return ret;
1625                 }
1626                 ret = psp_hdcp_terminate(psp);
1627                 if (ret) {
1628                         DRM_ERROR("Failed to terminate hdcp ta\n");
1629                         return ret;
1630                 }
1631                 ret = psp_dtm_terminate(psp);
1632                 if (ret) {
1633                         DRM_ERROR("Failed to terminate dtm ta\n");
1634                         return ret;
1635                 }
1636         }
1637
1638         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
1639         if (ret) {
1640                 DRM_ERROR("PSP ring stop failed\n");
1641                 return ret;
1642         }
1643
1644         return 0;
1645 }
1646
1647 static int psp_resume(void *handle)
1648 {
1649         int ret;
1650         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1651         struct psp_context *psp = &adev->psp;
1652
1653         DRM_INFO("PSP is resuming...\n");
1654
1655         ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
1656         if (ret) {
1657                 DRM_ERROR("Failed to process memory training!\n");
1658                 return ret;
1659         }
1660
1661         mutex_lock(&adev->firmware.mutex);
1662
1663         ret = psp_hw_start(psp);
1664         if (ret)
1665                 goto failed;
1666
1667         ret = psp_np_fw_load(psp);
1668         if (ret)
1669                 goto failed;
1670
1671         mutex_unlock(&adev->firmware.mutex);
1672
1673         return 0;
1674
1675 failed:
1676         DRM_ERROR("PSP resume failed\n");
1677         mutex_unlock(&adev->firmware.mutex);
1678         return ret;
1679 }
1680
1681 int psp_gpu_reset(struct amdgpu_device *adev)
1682 {
1683         int ret;
1684
1685         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1686                 return 0;
1687
1688         mutex_lock(&adev->psp.mutex);
1689         ret = psp_mode1_reset(&adev->psp);
1690         mutex_unlock(&adev->psp.mutex);
1691
1692         return ret;
1693 }
1694
1695 int psp_rlc_autoload_start(struct psp_context *psp)
1696 {
1697         int ret;
1698         struct psp_gfx_cmd_resp *cmd;
1699
1700         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1701         if (!cmd)
1702                 return -ENOMEM;
1703
1704         cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
1705
1706         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1707                                  psp->fence_buf_mc_addr);
1708         kfree(cmd);
1709         return ret;
1710 }
1711
1712 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
1713                         uint64_t cmd_gpu_addr, int cmd_size)
1714 {
1715         struct amdgpu_firmware_info ucode = {0};
1716
1717         ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
1718                 AMDGPU_UCODE_ID_VCN0_RAM;
1719         ucode.mc_addr = cmd_gpu_addr;
1720         ucode.ucode_size = cmd_size;
1721
1722         return psp_execute_np_fw_load(&adev->psp, &ucode);
1723 }
1724
1725 int psp_ring_cmd_submit(struct psp_context *psp,
1726                         uint64_t cmd_buf_mc_addr,
1727                         uint64_t fence_mc_addr,
1728                         int index)
1729 {
1730         unsigned int psp_write_ptr_reg = 0;
1731         struct psp_gfx_rb_frame *write_frame;
1732         struct psp_ring *ring = &psp->km_ring;
1733         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
1734         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
1735                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
1736         struct amdgpu_device *adev = psp->adev;
1737         uint32_t ring_size_dw = ring->ring_size / 4;
1738         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
1739
1740         /* KM (GPCOM) prepare write pointer */
1741         psp_write_ptr_reg = psp_ring_get_wptr(psp);
1742
1743         /* Update KM RB frame pointer to new frame */
1744         /* write_frame ptr increments by size of rb_frame in bytes */
1745         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
1746         if ((psp_write_ptr_reg % ring_size_dw) == 0)
1747                 write_frame = ring_buffer_start;
1748         else
1749                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
1750         /* Check invalid write_frame ptr address */
1751         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
1752                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
1753                           ring_buffer_start, ring_buffer_end, write_frame);
1754                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
1755                 return -EINVAL;
1756         }
1757
1758         /* Initialize KM RB frame */
1759         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
1760
1761         /* Update KM RB frame */
1762         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
1763         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
1764         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
1765         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
1766         write_frame->fence_value = index;
1767         amdgpu_asic_flush_hdp(adev, NULL);
1768
1769         /* Update the write Pointer in DWORDs */
1770         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
1771         psp_ring_set_wptr(psp, psp_write_ptr_reg);
1772         return 0;
1773 }
1774
1775 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
1776                                         enum AMDGPU_UCODE_ID ucode_type)
1777 {
1778         struct amdgpu_firmware_info *ucode = NULL;
1779
1780         if (!adev->firmware.fw_size)
1781                 return false;
1782
1783         ucode = &adev->firmware.ucode[ucode_type];
1784         if (!ucode->fw || !ucode->ucode_size)
1785                 return false;
1786
1787         return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
1788 }
1789
1790 static int psp_set_clockgating_state(void *handle,
1791                                      enum amd_clockgating_state state)
1792 {
1793         return 0;
1794 }
1795
1796 static int psp_set_powergating_state(void *handle,
1797                                      enum amd_powergating_state state)
1798 {
1799         return 0;
1800 }
1801
1802 const struct amd_ip_funcs psp_ip_funcs = {
1803         .name = "psp",
1804         .early_init = psp_early_init,
1805         .late_init = NULL,
1806         .sw_init = psp_sw_init,
1807         .sw_fini = psp_sw_fini,
1808         .hw_init = psp_hw_init,
1809         .hw_fini = psp_hw_fini,
1810         .suspend = psp_suspend,
1811         .resume = psp_resume,
1812         .is_idle = NULL,
1813         .check_soft_reset = NULL,
1814         .wait_for_idle = NULL,
1815         .soft_reset = NULL,
1816         .set_clockgating_state = psp_set_clockgating_state,
1817         .set_powergating_state = psp_set_powergating_state,
1818 };
1819
1820 static const struct amdgpu_psp_funcs psp_funcs = {
1821         .check_fw_loading_status = psp_check_fw_loading_status,
1822 };
1823
1824 static void psp_set_funcs(struct amdgpu_device *adev)
1825 {
1826         if (NULL == adev->firmware.funcs)
1827                 adev->firmware.funcs = &psp_funcs;
1828 }
1829
1830 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
1831 {
1832         .type = AMD_IP_BLOCK_TYPE_PSP,
1833         .major = 3,
1834         .minor = 1,
1835         .rev = 0,
1836         .funcs = &psp_ip_funcs,
1837 };
1838
1839 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
1840 {
1841         .type = AMD_IP_BLOCK_TYPE_PSP,
1842         .major = 10,
1843         .minor = 0,
1844         .rev = 0,
1845         .funcs = &psp_ip_funcs,
1846 };
1847
1848 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
1849 {
1850         .type = AMD_IP_BLOCK_TYPE_PSP,
1851         .major = 11,
1852         .minor = 0,
1853         .rev = 0,
1854         .funcs = &psp_ip_funcs,
1855 };
1856
1857 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
1858 {
1859         .type = AMD_IP_BLOCK_TYPE_PSP,
1860         .major = 12,
1861         .minor = 0,
1862         .rev = 0,
1863         .funcs = &psp_ip_funcs,
1864 };