drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_psp.h"
  30 #include "amdgpu_ucode.h"
  31 #include "soc15_common.h"
  32 #include "psp_v3_1.h"
  33 #include "psp_v10_0.h"
  34 #include "psp_v11_0.h"
  35
  36 static void psp_set_funcs(struct amdgpu_device *adev);
  37
  38 static int psp_early_init(void *handle)
  39 {
  40         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  41         struct psp_context *psp = &adev->psp;
  42
  43         psp_set_funcs(adev);
  44
  45         switch (adev->asic_type) {
  46         case CHIP_VEGA10:
  47         case CHIP_VEGA12:
  48                 psp_v3_1_set_psp_funcs(psp);
  49                 psp->autoload_supported = false;
  50                 break;
  51         case CHIP_RAVEN:
  52                 psp_v10_0_set_psp_funcs(psp);
  53                 psp->autoload_supported = false;
  54                 break;
  55         case CHIP_VEGA20:
  56                 psp_v11_0_set_psp_funcs(psp);
  57                 psp->autoload_supported = false;
  58                 break;
  59         case CHIP_NAVI10:
  60                 psp_v11_0_set_psp_funcs(psp);
  61                 psp->autoload_supported = true;
  62                 break;
  63         default:
  64                 return -EINVAL;
  65         }
  66
  67         psp->adev = adev;
  68
  69         return 0;
  70 }
  71
  72 static int psp_sw_init(void *handle)
  73 {
  74         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  75         struct psp_context *psp = &adev->psp;
  76         int ret;
  77
  78         ret = psp_init_microcode(psp);
  79         if (ret) {
  80                 DRM_ERROR("Failed to load psp firmware!\n");
  81                 return ret;
  82         }
  83
  84         return 0;
  85 }
  86
  87 static int psp_sw_fini(void *handle)
  88 {
  89         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  90
  91         release_firmware(adev->psp.sos_fw);
  92         adev->psp.sos_fw = NULL;
  93         release_firmware(adev->psp.asd_fw);
  94         adev->psp.asd_fw = NULL;
  95         if (adev->psp.ta_fw) {
  96                 release_firmware(adev->psp.ta_fw);
  97                 adev->psp.ta_fw = NULL;
  98         }
  99         return 0;
 100 }
 101
 102 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 103                  uint32_t reg_val, uint32_t mask, bool check_changed)
 104 {
 105         uint32_t val;
 106         int i;
 107         struct amdgpu_device *adev = psp->adev;
 108
 109         for (i = 0; i < adev->usec_timeout; i++) {
 110                 val = RREG32(reg_index);
 111                 if (check_changed) {
 112                         if (val != reg_val)
 113                                 return 0;
 114                 } else {
 115                         if ((val & mask) == reg_val)
 116                                 return 0;
 117                 }
 118                 udelay(1);
 119         }
 120
 121         return -ETIME;
 122 }
 123
 124 static int
 125 psp_cmd_submit_buf(struct psp_context *psp,
 126                    struct amdgpu_firmware_info *ucode,
 127                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 128 {
 129         int ret;
 130         int index;
 131         int timeout = 2000;
 132
 133         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 134
 135         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 136
 137         index = atomic_inc_return(&psp->fence_value);
 138         ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
 139                              fence_mc_addr, index);
 140         if (ret) {
 141                 atomic_dec(&psp->fence_value);
 142                 return ret;
 143         }
 144
 145         while (*((unsigned int *)psp->fence_buf) != index) {
 146                 if (--timeout == 0)
 147                         break;
 148                 msleep(1);
 149         }
 150
 151         /* In some cases, psp response status is not 0 even there is no
 152          * problem while the command is submitted. Some version of PSP FW
 153          * doesn't write 0 to that field.
 154          * So here we would like to only print a warning instead of an error
 155          * during psp initialization to avoid breaking hw_init and it doesn't
 156          * return -EINVAL.
 157          */
 158         if (psp->cmd_buf_mem->resp.status || !timeout) {
 159                 if (ucode)
 160                         DRM_WARN("failed to load ucode id (%d) ",
 161                                   ucode->ucode_id);
 162                 DRM_WARN("psp command failed and response status is (%d)\n",
 163                           psp->cmd_buf_mem->resp.status);
 164                 if (!timeout)
 165                         return -EINVAL;
 166         }
 167
 168         /* get xGMI session id from response buffer */
 169         cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id;
 170
 171         if (ucode) {
 172                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 173                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 174         }
 175
 176         return ret;
 177 }
 178
 179 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 180                                  struct psp_gfx_cmd_resp *cmd,
 181                                  uint64_t tmr_mc, uint32_t size)
 182 {
 183         if (psp_support_vmr_ring(psp))
 184                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 185         else
 186                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 187         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 188         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 189         cmd->cmd.cmd_setup_tmr.buf_size = size;
 190 }
 191
 192 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 193                                       uint64_t pri_buf_mc, uint32_t size)
 194 {
 195         cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
 196         cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
 197         cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
 198         cmd->cmd.cmd_load_toc.toc_size = size;
 199 }
 200
 201 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
 202 static int psp_load_toc(struct psp_context *psp,
 203                         uint32_t *tmr_size)
 204 {
 205         int ret;
 206         struct psp_gfx_cmd_resp *cmd;
 207
 208         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 209         if (!cmd)
 210                 return -ENOMEM;
 211         /* Copy toc to psp firmware private buffer */
 212         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 213         memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size);
 214
 215         psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size);
 216
 217         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 218                                  psp->fence_buf_mc_addr);
 219         if (!ret)
 220                 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
 221         kfree(cmd);
 222         return ret;
 223 }
 224
 225 /* Set up Trusted Memory Region */
 226 static int psp_tmr_init(struct psp_context *psp)
 227 {
 228         int ret;
 229         int tmr_size;
 230
 231         /*
 232          * According to HW engineer, they prefer the TMR address be "naturally
 233          * aligned" , e.g. the start address be an integer divide of TMR size.
 234          *
 235          * Note: this memory need be reserved till the driver
 236          * uninitializes.
 237          */
 238         tmr_size = PSP_TMR_SIZE;
 239
 240         /* For ASICs support RLC autoload, psp will parse the toc
 241          * and calculate the total size of TMR needed */
 242         if (psp->toc_start_addr &&
 243             psp->toc_bin_size &&
 244             psp->fw_pri_buf) {
 245                 ret = psp_load_toc(psp, &tmr_size);
 246                 if (ret) {
 247                         DRM_ERROR("Failed to load toc\n");
 248                         return ret;
 249                 }
 250         }
 251
 252         ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
 253                                       AMDGPU_GEM_DOMAIN_VRAM,
 254                                       &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 255
 256         return ret;
 257 }
 258
 259 static int psp_tmr_load(struct psp_context *psp)
 260 {
 261         int ret;
 262         struct psp_gfx_cmd_resp *cmd;
 263
 264         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 265         if (!cmd)
 266                 return -ENOMEM;
 267
 268         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr,
 269                              amdgpu_bo_size(psp->tmr_bo));
 270         DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 271                  amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 272
 273         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 274                                  psp->fence_buf_mc_addr);
 275         if (ret)
 276                 goto failed;
 277
 278         kfree(cmd);
 279
 280         return 0;
 281
 282 failed:
 283         kfree(cmd);
 284         return ret;
 285 }
 286
 287 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 288                                  uint64_t asd_mc, uint64_t asd_mc_shared,
 289                                  uint32_t size, uint32_t shared_size)
 290 {
 291         cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
 292         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
 293         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
 294         cmd->cmd.cmd_load_ta.app_len = size;
 295
 296         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
 297         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
 298         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 299 }
 300
 301 static int psp_asd_init(struct psp_context *psp)
 302 {
 303         int ret;
 304
 305         /*
 306          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 307          * physical) for shared ASD <-> Driver
 308          */
 309         ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
 310                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 311                                       &psp->asd_shared_bo,
 312                                       &psp->asd_shared_mc_addr,
 313                                       &psp->asd_shared_buf);
 314
 315         return ret;
 316 }
 317
 318 static int psp_asd_load(struct psp_context *psp)
 319 {
 320         int ret;
 321         struct psp_gfx_cmd_resp *cmd;
 322
 323         /* If PSP version doesn't match ASD version, asd loading will be failed.
 324          * add workaround to bypass it for sriov now.
 325          * TODO: add version check to make it common
 326          */
 327         if (amdgpu_sriov_vf(psp->adev))
 328                 return 0;
 329
 330         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 331         if (!cmd)
 332                 return -ENOMEM;
 333
 334         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 335         memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
 336
 337         psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
 338                              psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
 339
 340         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 341                                  psp->fence_buf_mc_addr);
 342
 343         kfree(cmd);
 344
 345         return ret;
 346 }
 347
 348 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 349                 uint32_t id, uint32_t value)
 350 {
 351         cmd->cmd_id = GFX_CMD_ID_PROG_REG;
 352         cmd->cmd.cmd_setup_reg_prog.reg_value = value;
 353         cmd->cmd.cmd_setup_reg_prog.reg_id = id;
 354 }
 355
 356 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
 357                 uint32_t value)
 358 {
 359         struct psp_gfx_cmd_resp *cmd = NULL;
 360         int ret = 0;
 361
 362         if (reg >= PSP_REG_LAST)
 363                 return -EINVAL;
 364
 365         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 366         if (!cmd)
 367                 return -ENOMEM;
 368
 369         psp_prep_reg_prog_cmd_buf(cmd, reg, value);
 370         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 371
 372         kfree(cmd);
 373         return ret;
 374 }
 375
 376 static void psp_prep_xgmi_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 377                                           uint64_t xgmi_ta_mc, uint64_t xgmi_mc_shared,
 378                                           uint32_t xgmi_ta_size, uint32_t shared_size)
 379 {
 380         cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
 381         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(xgmi_ta_mc);
 382         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(xgmi_ta_mc);
 383         cmd->cmd.cmd_load_ta.app_len = xgmi_ta_size;
 384
 385         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(xgmi_mc_shared);
 386         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(xgmi_mc_shared);
 387         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 388 }
 389
 390 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
 391 {
 392         int ret;
 393
 394         /*
 395          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 396          * physical) for xgmi ta <-> Driver
 397          */
 398         ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE,
 399                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 400                                       &psp->xgmi_context.xgmi_shared_bo,
 401                                       &psp->xgmi_context.xgmi_shared_mc_addr,
 402                                       &psp->xgmi_context.xgmi_shared_buf);
 403
 404         return ret;
 405 }
 406
 407 static int psp_xgmi_load(struct psp_context *psp)
 408 {
 409         int ret;
 410         struct psp_gfx_cmd_resp *cmd;
 411
 412         /*
 413          * TODO: bypass the loading in sriov for now
 414          */
 415         if (amdgpu_sriov_vf(psp->adev))
 416                 return 0;
 417
 418         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 419         if (!cmd)
 420                 return -ENOMEM;
 421
 422         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 423         memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
 424
 425         psp_prep_xgmi_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
 426                                       psp->xgmi_context.xgmi_shared_mc_addr,
 427                                       psp->ta_xgmi_ucode_size, PSP_XGMI_SHARED_MEM_SIZE);
 428
 429         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 430                                  psp->fence_buf_mc_addr);
 431
 432         if (!ret) {
 433                 psp->xgmi_context.initialized = 1;
 434                 psp->xgmi_context.session_id = cmd->resp.session_id;
 435         }
 436
 437         kfree(cmd);
 438
 439         return ret;
 440 }
 441
 442 static void psp_prep_xgmi_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 443                                             uint32_t xgmi_session_id)
 444 {
 445         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 446         cmd->cmd.cmd_unload_ta.session_id = xgmi_session_id;
 447 }
 448
 449 static int psp_xgmi_unload(struct psp_context *psp)
 450 {
 451         int ret;
 452         struct psp_gfx_cmd_resp *cmd;
 453
 454         /*
 455          * TODO: bypass the unloading in sriov for now
 456          */
 457         if (amdgpu_sriov_vf(psp->adev))
 458                 return 0;
 459
 460         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 461         if (!cmd)
 462                 return -ENOMEM;
 463
 464         psp_prep_xgmi_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);
 465
 466         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 467                                  psp->fence_buf_mc_addr);
 468
 469         kfree(cmd);
 470
 471         return ret;
 472 }
 473
 474 static void psp_prep_xgmi_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 475                                             uint32_t ta_cmd_id,
 476                                             uint32_t xgmi_session_id)
 477 {
 478         cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
 479         cmd->cmd.cmd_invoke_cmd.session_id = xgmi_session_id;
 480         cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
 481         /* Note: cmd_invoke_cmd.buf is not used for now */
 482 }
 483
 484 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
 485 {
 486         int ret;
 487         struct psp_gfx_cmd_resp *cmd;
 488
 489         /*
 490          * TODO: bypass the loading in sriov for now
 491         */
 492         if (amdgpu_sriov_vf(psp->adev))
 493                 return 0;
 494
 495         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 496         if (!cmd)
 497                 return -ENOMEM;
 498
 499         psp_prep_xgmi_ta_invoke_cmd_buf(cmd, ta_cmd_id,
 500                                         psp->xgmi_context.session_id);
 501
 502         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 503                                  psp->fence_buf_mc_addr);
 504
 505         kfree(cmd);
 506
 507         return ret;
 508 }
 509
 510 static int psp_xgmi_terminate(struct psp_context *psp)
 511 {
 512         int ret;
 513
 514         if (!psp->xgmi_context.initialized)
 515                 return 0;
 516
 517         ret = psp_xgmi_unload(psp);
 518         if (ret)
 519                 return ret;
 520
 521         psp->xgmi_context.initialized = 0;
 522
 523         /* free xgmi shared memory */
 524         amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo,
 525                         &psp->xgmi_context.xgmi_shared_mc_addr,
 526                         &psp->xgmi_context.xgmi_shared_buf);
 527
 528         return 0;
 529 }
 530
 531 static int psp_xgmi_initialize(struct psp_context *psp)
 532 {
 533         struct ta_xgmi_shared_memory *xgmi_cmd;
 534         int ret;
 535
 536         if (!psp->adev->psp.ta_fw)
 537                 return -ENOENT;
 538
 539         if (!psp->xgmi_context.initialized) {
 540                 ret = psp_xgmi_init_shared_buf(psp);
 541                 if (ret)
 542                         return ret;
 543         }
 544
 545         /* Load XGMI TA */
 546         ret = psp_xgmi_load(psp);
 547         if (ret)
 548                 return ret;
 549
 550         /* Initialize XGMI session */
 551         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf);
 552         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 553         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
 554
 555         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 556
 557         return ret;
 558 }
 559
 560 // ras begin
 561 static void psp_prep_ras_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 562                 uint64_t ras_ta_mc, uint64_t ras_mc_shared,
 563                 uint32_t ras_ta_size, uint32_t shared_size)
 564 {
 565         cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
 566         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ras_ta_mc);
 567         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ras_ta_mc);
 568         cmd->cmd.cmd_load_ta.app_len = ras_ta_size;
 569
 570         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ras_mc_shared);
 571         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ras_mc_shared);
 572         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 573 }
 574
 575 static int psp_ras_init_shared_buf(struct psp_context *psp)
 576 {
 577         int ret;
 578
 579         /*
 580          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 581          * physical) for ras ta <-> Driver
 582          */
 583         ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE,
 584                         PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 585                         &psp->ras.ras_shared_bo,
 586                         &psp->ras.ras_shared_mc_addr,
 587                         &psp->ras.ras_shared_buf);
 588
 589         return ret;
 590 }
 591
 592 static int psp_ras_load(struct psp_context *psp)
 593 {
 594         int ret;
 595         struct psp_gfx_cmd_resp *cmd;
 596
 597         /*
 598          * TODO: bypass the loading in sriov for now
 599          */
 600         if (amdgpu_sriov_vf(psp->adev))
 601                 return 0;
 602
 603         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 604         if (!cmd)
 605                 return -ENOMEM;
 606
 607         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 608         memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size);
 609
 610         psp_prep_ras_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
 611                         psp->ras.ras_shared_mc_addr,
 612                         psp->ta_ras_ucode_size, PSP_RAS_SHARED_MEM_SIZE);
 613
 614         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 615                         psp->fence_buf_mc_addr);
 616
 617         if (!ret) {
 618                 psp->ras.ras_initialized = 1;
 619                 psp->ras.session_id = cmd->resp.session_id;
 620         }
 621
 622         kfree(cmd);
 623
 624         return ret;
 625 }
 626
 627 static void psp_prep_ras_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 628                                                 uint32_t ras_session_id)
 629 {
 630         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 631         cmd->cmd.cmd_unload_ta.session_id = ras_session_id;
 632 }
 633
 634 static int psp_ras_unload(struct psp_context *psp)
 635 {
 636         int ret;
 637         struct psp_gfx_cmd_resp *cmd;
 638
 639         /*
 640          * TODO: bypass the unloading in sriov for now
 641          */
 642         if (amdgpu_sriov_vf(psp->adev))
 643                 return 0;
 644
 645         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 646         if (!cmd)
 647                 return -ENOMEM;
 648
 649         psp_prep_ras_ta_unload_cmd_buf(cmd, psp->ras.session_id);
 650
 651         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 652                         psp->fence_buf_mc_addr);
 653
 654         kfree(cmd);
 655
 656         return ret;
 657 }
 658
 659 static void psp_prep_ras_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 660                 uint32_t ta_cmd_id,
 661                 uint32_t ras_session_id)
 662 {
 663         cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
 664         cmd->cmd.cmd_invoke_cmd.session_id = ras_session_id;
 665         cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
 666         /* Note: cmd_invoke_cmd.buf is not used for now */
 667 }
 668
 669 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
 670 {
 671         int ret;
 672         struct psp_gfx_cmd_resp *cmd;
 673
 674         /*
 675          * TODO: bypass the loading in sriov for now
 676          */
 677         if (amdgpu_sriov_vf(psp->adev))
 678                 return 0;
 679
 680         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 681         if (!cmd)
 682                 return -ENOMEM;
 683
 684         psp_prep_ras_ta_invoke_cmd_buf(cmd, ta_cmd_id,
 685                         psp->ras.session_id);
 686
 687         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 688                         psp->fence_buf_mc_addr);
 689
 690         kfree(cmd);
 691
 692         return ret;
 693 }
 694
 695 int psp_ras_enable_features(struct psp_context *psp,
 696                 union ta_ras_cmd_input *info, bool enable)
 697 {
 698         struct ta_ras_shared_memory *ras_cmd;
 699         int ret;
 700
 701         if (!psp->ras.ras_initialized)
 702                 return -EINVAL;
 703
 704         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
 705         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
 706
 707         if (enable)
 708                 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
 709         else
 710                 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
 711
 712         ras_cmd->ras_in_message = *info;
 713
 714         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
 715         if (ret)
 716                 return -EINVAL;
 717
 718         return ras_cmd->ras_status;
 719 }
 720
 721 static int psp_ras_terminate(struct psp_context *psp)
 722 {
 723         int ret;
 724
 725         if (!psp->ras.ras_initialized)
 726                 return 0;
 727
 728         ret = psp_ras_unload(psp);
 729         if (ret)
 730                 return ret;
 731
 732         psp->ras.ras_initialized = 0;
 733
 734         /* free ras shared memory */
 735         amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo,
 736                         &psp->ras.ras_shared_mc_addr,
 737                         &psp->ras.ras_shared_buf);
 738
 739         return 0;
 740 }
 741
 742 static int psp_ras_initialize(struct psp_context *psp)
 743 {
 744         int ret;
 745
 746         if (!psp->ras.ras_initialized) {
 747                 ret = psp_ras_init_shared_buf(psp);
 748                 if (ret)
 749                         return ret;
 750         }
 751
 752         ret = psp_ras_load(psp);
 753         if (ret)
 754                 return ret;
 755
 756         return 0;
 757 }
 758 // ras end
 759
 760 static int psp_hw_start(struct psp_context *psp)
 761 {
 762         struct amdgpu_device *adev = psp->adev;
 763         int ret;
 764
 765         if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
 766                 ret = psp_bootloader_load_sysdrv(psp);
 767                 if (ret) {
 768                         DRM_ERROR("PSP load sysdrv failed!\n");
 769                         return ret;
 770                 }
 771
 772                 ret = psp_bootloader_load_sos(psp);
 773                 if (ret) {
 774                         DRM_ERROR("PSP load sos failed!\n");
 775                         return ret;
 776                 }
 777         }
 778
 779         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
 780         if (ret) {
 781                 DRM_ERROR("PSP create ring failed!\n");
 782                 return ret;
 783         }
 784
 785         ret = psp_tmr_init(psp);
 786         if (ret) {
 787                 DRM_ERROR("PSP tmr init failed!\n");
 788                 return ret;
 789         }
 790
 791         ret = psp_tmr_load(psp);
 792         if (ret) {
 793                 DRM_ERROR("PSP load tmr failed!\n");
 794                 return ret;
 795         }
 796
 797         ret = psp_asd_init(psp);
 798         if (ret) {
 799                 DRM_ERROR("PSP asd init failed!\n");
 800                 return ret;
 801         }
 802
 803         ret = psp_asd_load(psp);
 804         if (ret) {
 805                 DRM_ERROR("PSP load asd failed!\n");
 806                 return ret;
 807         }
 808
 809         if (adev->gmc.xgmi.num_physical_nodes > 1) {
 810                 ret = psp_xgmi_initialize(psp);
 811                 /* Warning the XGMI seesion initialize failure
 812                  * Instead of stop driver initialization
 813                  */
 814                 if (ret)
 815                         dev_err(psp->adev->dev,
 816                                 "XGMI: Failed to initialize XGMI session\n");
 817         }
 818
 819
 820         if (psp->adev->psp.ta_fw) {
 821                 ret = psp_ras_initialize(psp);
 822                 if (ret)
 823                         dev_err(psp->adev->dev,
 824                                         "RAS: Failed to initialize RAS\n");
 825         }
 826
 827         return 0;
 828 }
 829
 830 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
 831                            enum psp_gfx_fw_type *type)
 832 {
 833         switch (ucode->ucode_id) {
 834         case AMDGPU_UCODE_ID_SDMA0:
 835                 *type = GFX_FW_TYPE_SDMA0;
 836                 break;
 837         case AMDGPU_UCODE_ID_SDMA1:
 838                 *type = GFX_FW_TYPE_SDMA1;
 839                 break;
 840         case AMDGPU_UCODE_ID_CP_CE:
 841                 *type = GFX_FW_TYPE_CP_CE;
 842                 break;
 843         case AMDGPU_UCODE_ID_CP_PFP:
 844                 *type = GFX_FW_TYPE_CP_PFP;
 845                 break;
 846         case AMDGPU_UCODE_ID_CP_ME:
 847                 *type = GFX_FW_TYPE_CP_ME;
 848                 break;
 849         case AMDGPU_UCODE_ID_CP_MEC1:
 850                 *type = GFX_FW_TYPE_CP_MEC;
 851                 break;
 852         case AMDGPU_UCODE_ID_CP_MEC1_JT:
 853                 *type = GFX_FW_TYPE_CP_MEC_ME1;
 854                 break;
 855         case AMDGPU_UCODE_ID_CP_MEC2:
 856                 *type = GFX_FW_TYPE_CP_MEC;
 857                 break;
 858         case AMDGPU_UCODE_ID_CP_MEC2_JT:
 859                 *type = GFX_FW_TYPE_CP_MEC_ME2;
 860                 break;
 861         case AMDGPU_UCODE_ID_RLC_G:
 862                 *type = GFX_FW_TYPE_RLC_G;
 863                 break;
 864         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
 865                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
 866                 break;
 867         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
 868                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
 869                 break;
 870         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
 871                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
 872                 break;
 873         case AMDGPU_UCODE_ID_SMC:
 874                 *type = GFX_FW_TYPE_SMU;
 875                 break;
 876         case AMDGPU_UCODE_ID_UVD:
 877                 *type = GFX_FW_TYPE_UVD;
 878                 break;
 879         case AMDGPU_UCODE_ID_UVD1:
 880                 *type = GFX_FW_TYPE_UVD1;
 881                 break;
 882         case AMDGPU_UCODE_ID_VCE:
 883                 *type = GFX_FW_TYPE_VCE;
 884                 break;
 885         case AMDGPU_UCODE_ID_VCN:
 886                 *type = GFX_FW_TYPE_VCN;
 887                 break;
 888         case AMDGPU_UCODE_ID_DMCU_ERAM:
 889                 *type = GFX_FW_TYPE_DMCU_ERAM;
 890                 break;
 891         case AMDGPU_UCODE_ID_DMCU_INTV:
 892                 *type = GFX_FW_TYPE_DMCU_ISR;
 893                 break;
 894         case AMDGPU_UCODE_ID_VCN0_RAM:
 895                 *type = GFX_FW_TYPE_VCN0_RAM;
 896                 break;
 897         case AMDGPU_UCODE_ID_VCN1_RAM:
 898                 *type = GFX_FW_TYPE_VCN1_RAM;
 899                 break;
 900         case AMDGPU_UCODE_ID_MAXIMUM:
 901         default:
 902                 return -EINVAL;
 903         }
 904
 905         return 0;
 906 }
 907
 908 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
 909                                        struct psp_gfx_cmd_resp *cmd)
 910 {
 911         int ret;
 912         uint64_t fw_mem_mc_addr = ucode->mc_addr;
 913
 914         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 915
 916         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 917         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
 918         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
 919         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
 920
 921         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
 922         if (ret)
 923                 DRM_ERROR("Unknown firmware type\n");
 924
 925         return ret;
 926 }
 927
 928 static int psp_execute_np_fw_load(struct psp_context *psp,
 929                                struct amdgpu_firmware_info *ucode)
 930 {
 931         int ret = 0;
 932
 933         ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd);
 934         if (ret)
 935                 return ret;
 936
 937         ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
 938                                  psp->fence_buf_mc_addr);
 939
 940         return ret;
 941 }
 942
 943 static int psp_np_fw_load(struct psp_context *psp)
 944 {
 945         int i, ret;
 946         struct amdgpu_firmware_info *ucode;
 947         struct amdgpu_device* adev = psp->adev;
 948
 949         if (psp->autoload_supported) {
 950                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 951                 if (!ucode->fw)
 952                         goto out;
 953
 954                 ret = psp_execute_np_fw_load(psp, ucode);
 955                 if (ret)
 956                         return ret;
 957         }
 958
 959 out:
 960         for (i = 0; i < adev->firmware.max_ucodes; i++) {
 961                 ucode = &adev->firmware.ucode[i];
 962                 if (!ucode->fw)
 963                         continue;
 964
 965                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
 966                     (psp_smu_reload_quirk(psp) || psp->autoload_supported))
 967                         continue;
 968                 if (amdgpu_sriov_vf(adev) &&
 969                    (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
 970                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
 971                     || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
 972                         /*skip ucode loading in SRIOV VF */
 973                         continue;
 974                 if (psp->autoload_supported &&
 975                     (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
 976                      ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
 977                         /* skip mec JT when autoload is enabled */
 978                         continue;
 979
 980                 ret = psp_execute_np_fw_load(psp, ucode);
 981                 if (ret)
 982                         return ret;
 983
 984                 /* Start rlc autoload after psp recieved all the gfx firmware */
 985                 if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
 986                         ret = psp_rlc_autoload(psp);
 987                         if (ret) {
 988                                 DRM_ERROR("Failed to start rlc autoload\n");
 989                                 return ret;
 990                         }
 991                 }
 992 #if 0
 993                 /* check if firmware loaded sucessfully */
 994                 if (!amdgpu_psp_check_fw_loading_status(adev, i))
 995                         return -EINVAL;
 996 #endif
 997         }
 998
 999         return 0;
1000 }
1001
1002 static int psp_load_fw(struct amdgpu_device *adev)
1003 {
1004         int ret;
1005         struct psp_context *psp = &adev->psp;
1006
1007         if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) {
1008                 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
1009                 goto skip_memalloc;
1010         }
1011
1012         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1013         if (!psp->cmd)
1014                 return -ENOMEM;
1015
1016         /* this fw pri bo is not used under SRIOV */
1017         if (!amdgpu_sriov_vf(psp->adev)) {
1018                 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
1019                                               AMDGPU_GEM_DOMAIN_GTT,
1020                                               &psp->fw_pri_bo,
1021                                               &psp->fw_pri_mc_addr,
1022                                               &psp->fw_pri_buf);
1023                 if (ret)
1024                         goto failed;
1025         }
1026
1027         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
1028                                         AMDGPU_GEM_DOMAIN_VRAM,
1029                                         &psp->fence_buf_bo,
1030                                         &psp->fence_buf_mc_addr,
1031                                         &psp->fence_buf);
1032         if (ret)
1033                 goto failed;
1034
1035         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
1036                                       AMDGPU_GEM_DOMAIN_VRAM,
1037                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
1038                                       (void **)&psp->cmd_buf_mem);
1039         if (ret)
1040                 goto failed;
1041
1042         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
1043
1044         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
1045         if (ret) {
1046                 DRM_ERROR("PSP ring init failed!\n");
1047                 goto failed;
1048         }
1049
1050 skip_memalloc:
1051         ret = psp_hw_start(psp);
1052         if (ret)
1053                 goto failed;
1054
1055         ret = psp_np_fw_load(psp);
1056         if (ret)
1057                 goto failed;
1058
1059         return 0;
1060
1061 failed:
1062         /*
1063          * all cleanup jobs (xgmi terminate, ras terminate,
1064          * ring destroy, cmd/fence/fw buffers destory,
1065          * psp->cmd destory) are delayed to psp_hw_fini
1066          */
1067         return ret;
1068 }
1069
1070 static int psp_hw_init(void *handle)
1071 {
1072         int ret;
1073         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1074
1075         mutex_lock(&adev->firmware.mutex);
1076         /*
1077          * This sequence is just used on hw_init only once, no need on
1078          * resume.
1079          */
1080         ret = amdgpu_ucode_init_bo(adev);
1081         if (ret)
1082                 goto failed;
1083
1084         ret = psp_load_fw(adev);
1085         if (ret) {
1086                 DRM_ERROR("PSP firmware loading failed\n");
1087                 goto failed;
1088         }
1089
1090         mutex_unlock(&adev->firmware.mutex);
1091         return 0;
1092
1093 failed:
1094         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
1095         mutex_unlock(&adev->firmware.mutex);
1096         return -EINVAL;
1097 }
1098
1099 static int psp_hw_fini(void *handle)
1100 {
1101         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1102         struct psp_context *psp = &adev->psp;
1103
1104         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1105             psp->xgmi_context.initialized == 1)
1106                 psp_xgmi_terminate(psp);
1107
1108         if (psp->adev->psp.ta_fw)
1109                 psp_ras_terminate(psp);
1110
1111         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
1112
1113         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
1114         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
1115                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
1116         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
1117                               &psp->fence_buf_mc_addr, &psp->fence_buf);
1118         amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr,
1119                               &psp->asd_shared_buf);
1120         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
1121                               (void **)&psp->cmd_buf_mem);
1122
1123         kfree(psp->cmd);
1124         psp->cmd = NULL;
1125
1126         return 0;
1127 }
1128
1129 static int psp_suspend(void *handle)
1130 {
1131         int ret;
1132         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1133         struct psp_context *psp = &adev->psp;
1134
1135         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1136             psp->xgmi_context.initialized == 1) {
1137                 ret = psp_xgmi_terminate(psp);
1138                 if (ret) {
1139                         DRM_ERROR("Failed to terminate xgmi ta\n");
1140                         return ret;
1141                 }
1142         }
1143
1144         if (psp->adev->psp.ta_fw) {
1145                 ret = psp_ras_terminate(psp);
1146                 if (ret) {
1147                         DRM_ERROR("Failed to terminate ras ta\n");
1148                         return ret;
1149                 }
1150         }
1151
1152         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
1153         if (ret) {
1154                 DRM_ERROR("PSP ring stop failed\n");
1155                 return ret;
1156         }
1157
1158         return 0;
1159 }
1160
1161 static int psp_resume(void *handle)
1162 {
1163         int ret;
1164         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1165         struct psp_context *psp = &adev->psp;
1166
1167         DRM_INFO("PSP is resuming...\n");
1168
1169         mutex_lock(&adev->firmware.mutex);
1170
1171         ret = psp_hw_start(psp);
1172         if (ret)
1173                 goto failed;
1174
1175         ret = psp_np_fw_load(psp);
1176         if (ret)
1177                 goto failed;
1178
1179         mutex_unlock(&adev->firmware.mutex);
1180
1181         return 0;
1182
1183 failed:
1184         DRM_ERROR("PSP resume failed\n");
1185         mutex_unlock(&adev->firmware.mutex);
1186         return ret;
1187 }
1188
1189 int psp_gpu_reset(struct amdgpu_device *adev)
1190 {
1191         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1192                 return 0;
1193
1194         return psp_mode1_reset(&adev->psp);
1195 }
1196
1197 int psp_rlc_autoload_start(struct psp_context *psp)
1198 {
1199         int ret;
1200         struct psp_gfx_cmd_resp *cmd;
1201
1202         if (amdgpu_sriov_vf(psp->adev))
1203                 return 0;
1204
1205         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1206         if (!cmd)
1207                 return -ENOMEM;
1208
1209         cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
1210
1211         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1212                                  psp->fence_buf_mc_addr);
1213         kfree(cmd);
1214         return ret;
1215 }
1216
1217 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
1218                         uint64_t cmd_gpu_addr, int cmd_size)
1219 {
1220         struct amdgpu_firmware_info ucode = {0};
1221
1222         ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
1223                 AMDGPU_UCODE_ID_VCN0_RAM;
1224         ucode.mc_addr = cmd_gpu_addr;
1225         ucode.ucode_size = cmd_size;
1226
1227         return psp_execute_np_fw_load(&adev->psp, &ucode);
1228 }
1229
1230 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
1231                                         enum AMDGPU_UCODE_ID ucode_type)
1232 {
1233         struct amdgpu_firmware_info *ucode = NULL;
1234
1235         if (!adev->firmware.fw_size)
1236                 return false;
1237
1238         ucode = &adev->firmware.ucode[ucode_type];
1239         if (!ucode->fw || !ucode->ucode_size)
1240                 return false;
1241
1242         return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
1243 }
1244
1245 static int psp_set_clockgating_state(void *handle,
1246                                      enum amd_clockgating_state state)
1247 {
1248         return 0;
1249 }
1250
1251 static int psp_set_powergating_state(void *handle,
1252                                      enum amd_powergating_state state)
1253 {
1254         return 0;
1255 }
1256
1257 const struct amd_ip_funcs psp_ip_funcs = {
1258         .name = "psp",
1259         .early_init = psp_early_init,
1260         .late_init = NULL,
1261         .sw_init = psp_sw_init,
1262         .sw_fini = psp_sw_fini,
1263         .hw_init = psp_hw_init,
1264         .hw_fini = psp_hw_fini,
1265         .suspend = psp_suspend,
1266         .resume = psp_resume,
1267         .is_idle = NULL,
1268         .check_soft_reset = NULL,
1269         .wait_for_idle = NULL,
1270         .soft_reset = NULL,
1271         .set_clockgating_state = psp_set_clockgating_state,
1272         .set_powergating_state = psp_set_powergating_state,
1273 };
1274
1275 static const struct amdgpu_psp_funcs psp_funcs = {
1276         .check_fw_loading_status = psp_check_fw_loading_status,
1277 };
1278
1279 static void psp_set_funcs(struct amdgpu_device *adev)
1280 {
1281         if (NULL == adev->firmware.funcs)
1282                 adev->firmware.funcs = &psp_funcs;
1283 }
1284
1285 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
1286 {
1287         .type = AMD_IP_BLOCK_TYPE_PSP,
1288         .major = 3,
1289         .minor = 1,
1290         .rev = 0,
1291         .funcs = &psp_ip_funcs,
1292 };
1293
1294 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
1295 {
1296         .type = AMD_IP_BLOCK_TYPE_PSP,
1297         .major = 10,
1298         .minor = 0,
1299         .rev = 0,
1300         .funcs = &psp_ip_funcs,
1301 };
1302
1303 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
1304 {
1305         .type = AMD_IP_BLOCK_TYPE_PSP,
1306         .major = 11,
1307         .minor = 0,
1308         .rev = 0,
1309         .funcs = &psp_ip_funcs,
1310 };