2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/firmware.h>
29 #include "amdgpu_psp.h"
30 #include "amdgpu_ucode.h"
31 #include "soc15_common.h"
33 #include "psp_v10_0.h"
34 #include "psp_v11_0.h"
35 #include "psp_v12_0.h"
37 static void psp_set_funcs(struct amdgpu_device *adev);
39 static int psp_early_init(void *handle)
41 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
42 struct psp_context *psp = &adev->psp;
46 switch (adev->asic_type) {
49 psp_v3_1_set_psp_funcs(psp);
50 psp->autoload_supported = false;
53 psp_v10_0_set_psp_funcs(psp);
54 psp->autoload_supported = false;
58 psp_v11_0_set_psp_funcs(psp);
59 psp->autoload_supported = false;
64 psp_v11_0_set_psp_funcs(psp);
65 psp->autoload_supported = true;
68 psp_v12_0_set_psp_funcs(psp);
79 static int psp_sw_init(void *handle)
81 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
82 struct psp_context *psp = &adev->psp;
85 ret = psp_init_microcode(psp);
87 DRM_ERROR("Failed to load psp firmware!\n");
94 static int psp_sw_fini(void *handle)
96 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
98 release_firmware(adev->psp.sos_fw);
99 adev->psp.sos_fw = NULL;
100 release_firmware(adev->psp.asd_fw);
101 adev->psp.asd_fw = NULL;
102 if (adev->psp.ta_fw) {
103 release_firmware(adev->psp.ta_fw);
104 adev->psp.ta_fw = NULL;
109 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
110 uint32_t reg_val, uint32_t mask, bool check_changed)
114 struct amdgpu_device *adev = psp->adev;
116 for (i = 0; i < adev->usec_timeout; i++) {
117 val = RREG32(reg_index);
122 if ((val & mask) == reg_val)
132 psp_cmd_submit_buf(struct psp_context *psp,
133 struct amdgpu_firmware_info *ucode,
134 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
140 mutex_lock(&psp->mutex);
142 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
144 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
146 index = atomic_inc_return(&psp->fence_value);
147 ret = psp_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
149 atomic_dec(&psp->fence_value);
150 mutex_unlock(&psp->mutex);
154 while (*((unsigned int *)psp->fence_buf) != index) {
160 /* In some cases, psp response status is not 0 even there is no
161 * problem while the command is submitted. Some version of PSP FW
162 * doesn't write 0 to that field.
163 * So here we would like to only print a warning instead of an error
164 * during psp initialization to avoid breaking hw_init and it doesn't
167 if (psp->cmd_buf_mem->resp.status || !timeout) {
169 DRM_WARN("failed to load ucode id (%d) ",
171 DRM_WARN("psp command failed and response status is (0x%X)\n",
172 psp->cmd_buf_mem->resp.status & GFX_CMD_STATUS_MASK);
174 mutex_unlock(&psp->mutex);
179 /* get xGMI session id from response buffer */
180 cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id;
183 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
184 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
186 mutex_unlock(&psp->mutex);
191 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
192 struct psp_gfx_cmd_resp *cmd,
193 uint64_t tmr_mc, uint32_t size)
195 if (psp_support_vmr_ring(psp))
196 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
198 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
199 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
200 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
201 cmd->cmd.cmd_setup_tmr.buf_size = size;
204 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
205 uint64_t pri_buf_mc, uint32_t size)
207 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
208 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
209 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
210 cmd->cmd.cmd_load_toc.toc_size = size;
213 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
214 static int psp_load_toc(struct psp_context *psp,
218 struct psp_gfx_cmd_resp *cmd;
220 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
223 /* Copy toc to psp firmware private buffer */
224 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
225 memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size);
227 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size);
229 ret = psp_cmd_submit_buf(psp, NULL, cmd,
230 psp->fence_buf_mc_addr);
232 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
237 /* Set up Trusted Memory Region */
238 static int psp_tmr_init(struct psp_context *psp)
246 * According to HW engineer, they prefer the TMR address be "naturally
247 * aligned" , e.g. the start address be an integer divide of TMR size.
249 * Note: this memory need be reserved till the driver
252 tmr_size = PSP_TMR_SIZE;
254 /* For ASICs support RLC autoload, psp will parse the toc
255 * and calculate the total size of TMR needed */
256 if (psp->toc_start_addr &&
259 ret = psp_load_toc(psp, &tmr_size);
261 DRM_ERROR("Failed to load toc\n");
266 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
267 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
268 AMDGPU_GEM_DOMAIN_VRAM,
269 &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
274 static int psp_tmr_load(struct psp_context *psp)
277 struct psp_gfx_cmd_resp *cmd;
279 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
283 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr,
284 amdgpu_bo_size(psp->tmr_bo));
285 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
286 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
288 ret = psp_cmd_submit_buf(psp, NULL, cmd,
289 psp->fence_buf_mc_addr);
302 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
303 uint64_t asd_mc, uint64_t asd_mc_shared,
304 uint32_t size, uint32_t shared_size)
306 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
307 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
308 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
309 cmd->cmd.cmd_load_ta.app_len = size;
311 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
312 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
313 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
316 static int psp_asd_init(struct psp_context *psp)
321 * Allocate 16k memory aligned to 4k from Frame Buffer (local
322 * physical) for shared ASD <-> Driver
324 ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
325 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
327 &psp->asd_shared_mc_addr,
328 &psp->asd_shared_buf);
333 static int psp_asd_load(struct psp_context *psp)
336 struct psp_gfx_cmd_resp *cmd;
338 /* If PSP version doesn't match ASD version, asd loading will be failed.
339 * add workaround to bypass it for sriov now.
340 * TODO: add version check to make it common
342 if (amdgpu_sriov_vf(psp->adev))
345 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
349 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
350 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
352 psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
353 psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
355 ret = psp_cmd_submit_buf(psp, NULL, cmd,
356 psp->fence_buf_mc_addr);
363 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
364 uint32_t id, uint32_t value)
366 cmd->cmd_id = GFX_CMD_ID_PROG_REG;
367 cmd->cmd.cmd_setup_reg_prog.reg_value = value;
368 cmd->cmd.cmd_setup_reg_prog.reg_id = id;
371 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
374 struct psp_gfx_cmd_resp *cmd = NULL;
377 if (reg >= PSP_REG_LAST)
380 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
384 psp_prep_reg_prog_cmd_buf(cmd, reg, value);
385 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
391 static void psp_prep_xgmi_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
392 uint64_t xgmi_ta_mc, uint64_t xgmi_mc_shared,
393 uint32_t xgmi_ta_size, uint32_t shared_size)
395 cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
396 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(xgmi_ta_mc);
397 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(xgmi_ta_mc);
398 cmd->cmd.cmd_load_ta.app_len = xgmi_ta_size;
400 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(xgmi_mc_shared);
401 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(xgmi_mc_shared);
402 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
405 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
410 * Allocate 16k memory aligned to 4k from Frame Buffer (local
411 * physical) for xgmi ta <-> Driver
413 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE,
414 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
415 &psp->xgmi_context.xgmi_shared_bo,
416 &psp->xgmi_context.xgmi_shared_mc_addr,
417 &psp->xgmi_context.xgmi_shared_buf);
422 static int psp_xgmi_load(struct psp_context *psp)
425 struct psp_gfx_cmd_resp *cmd;
428 * TODO: bypass the loading in sriov for now
430 if (amdgpu_sriov_vf(psp->adev))
433 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
437 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
438 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
440 psp_prep_xgmi_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
441 psp->xgmi_context.xgmi_shared_mc_addr,
442 psp->ta_xgmi_ucode_size, PSP_XGMI_SHARED_MEM_SIZE);
444 ret = psp_cmd_submit_buf(psp, NULL, cmd,
445 psp->fence_buf_mc_addr);
448 psp->xgmi_context.initialized = 1;
449 psp->xgmi_context.session_id = cmd->resp.session_id;
457 static void psp_prep_xgmi_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
458 uint32_t xgmi_session_id)
460 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
461 cmd->cmd.cmd_unload_ta.session_id = xgmi_session_id;
464 static int psp_xgmi_unload(struct psp_context *psp)
467 struct psp_gfx_cmd_resp *cmd;
470 * TODO: bypass the unloading in sriov for now
472 if (amdgpu_sriov_vf(psp->adev))
475 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
479 psp_prep_xgmi_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);
481 ret = psp_cmd_submit_buf(psp, NULL, cmd,
482 psp->fence_buf_mc_addr);
489 static void psp_prep_xgmi_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
491 uint32_t xgmi_session_id)
493 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
494 cmd->cmd.cmd_invoke_cmd.session_id = xgmi_session_id;
495 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
496 /* Note: cmd_invoke_cmd.buf is not used for now */
499 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
502 struct psp_gfx_cmd_resp *cmd;
505 * TODO: bypass the loading in sriov for now
507 if (amdgpu_sriov_vf(psp->adev))
510 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
514 psp_prep_xgmi_ta_invoke_cmd_buf(cmd, ta_cmd_id,
515 psp->xgmi_context.session_id);
517 ret = psp_cmd_submit_buf(psp, NULL, cmd,
518 psp->fence_buf_mc_addr);
525 static int psp_xgmi_terminate(struct psp_context *psp)
529 if (!psp->xgmi_context.initialized)
532 ret = psp_xgmi_unload(psp);
536 psp->xgmi_context.initialized = 0;
538 /* free xgmi shared memory */
539 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo,
540 &psp->xgmi_context.xgmi_shared_mc_addr,
541 &psp->xgmi_context.xgmi_shared_buf);
546 static int psp_xgmi_initialize(struct psp_context *psp)
548 struct ta_xgmi_shared_memory *xgmi_cmd;
551 if (!psp->adev->psp.ta_fw)
554 if (!psp->xgmi_context.initialized) {
555 ret = psp_xgmi_init_shared_buf(psp);
561 ret = psp_xgmi_load(psp);
565 /* Initialize XGMI session */
566 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf);
567 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
568 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
570 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
576 static void psp_prep_ras_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
577 uint64_t ras_ta_mc, uint64_t ras_mc_shared,
578 uint32_t ras_ta_size, uint32_t shared_size)
580 cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
581 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ras_ta_mc);
582 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ras_ta_mc);
583 cmd->cmd.cmd_load_ta.app_len = ras_ta_size;
585 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ras_mc_shared);
586 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ras_mc_shared);
587 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
590 static int psp_ras_init_shared_buf(struct psp_context *psp)
595 * Allocate 16k memory aligned to 4k from Frame Buffer (local
596 * physical) for ras ta <-> Driver
598 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE,
599 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
600 &psp->ras.ras_shared_bo,
601 &psp->ras.ras_shared_mc_addr,
602 &psp->ras.ras_shared_buf);
607 static int psp_ras_load(struct psp_context *psp)
610 struct psp_gfx_cmd_resp *cmd;
613 * TODO: bypass the loading in sriov for now
615 if (amdgpu_sriov_vf(psp->adev))
618 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
622 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
623 memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size);
625 psp_prep_ras_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
626 psp->ras.ras_shared_mc_addr,
627 psp->ta_ras_ucode_size, PSP_RAS_SHARED_MEM_SIZE);
629 ret = psp_cmd_submit_buf(psp, NULL, cmd,
630 psp->fence_buf_mc_addr);
633 psp->ras.ras_initialized = 1;
634 psp->ras.session_id = cmd->resp.session_id;
642 static void psp_prep_ras_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
643 uint32_t ras_session_id)
645 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
646 cmd->cmd.cmd_unload_ta.session_id = ras_session_id;
649 static int psp_ras_unload(struct psp_context *psp)
652 struct psp_gfx_cmd_resp *cmd;
655 * TODO: bypass the unloading in sriov for now
657 if (amdgpu_sriov_vf(psp->adev))
660 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
664 psp_prep_ras_ta_unload_cmd_buf(cmd, psp->ras.session_id);
666 ret = psp_cmd_submit_buf(psp, NULL, cmd,
667 psp->fence_buf_mc_addr);
674 static void psp_prep_ras_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
676 uint32_t ras_session_id)
678 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
679 cmd->cmd.cmd_invoke_cmd.session_id = ras_session_id;
680 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
681 /* Note: cmd_invoke_cmd.buf is not used for now */
684 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
687 struct psp_gfx_cmd_resp *cmd;
690 * TODO: bypass the loading in sriov for now
692 if (amdgpu_sriov_vf(psp->adev))
695 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
699 psp_prep_ras_ta_invoke_cmd_buf(cmd, ta_cmd_id,
700 psp->ras.session_id);
702 ret = psp_cmd_submit_buf(psp, NULL, cmd,
703 psp->fence_buf_mc_addr);
710 int psp_ras_enable_features(struct psp_context *psp,
711 union ta_ras_cmd_input *info, bool enable)
713 struct ta_ras_shared_memory *ras_cmd;
716 if (!psp->ras.ras_initialized)
719 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
720 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
723 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
725 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
727 ras_cmd->ras_in_message = *info;
729 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
733 return ras_cmd->ras_status;
736 static int psp_ras_terminate(struct psp_context *psp)
740 if (!psp->ras.ras_initialized)
743 ret = psp_ras_unload(psp);
747 psp->ras.ras_initialized = 0;
749 /* free ras shared memory */
750 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo,
751 &psp->ras.ras_shared_mc_addr,
752 &psp->ras.ras_shared_buf);
757 static int psp_ras_initialize(struct psp_context *psp)
761 if (!psp->ras.ras_initialized) {
762 ret = psp_ras_init_shared_buf(psp);
767 ret = psp_ras_load(psp);
775 static int psp_hw_start(struct psp_context *psp)
777 struct amdgpu_device *adev = psp->adev;
780 if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
781 if (psp->kdb_bin_size &&
782 (psp->funcs->bootloader_load_kdb != NULL)) {
783 ret = psp_bootloader_load_kdb(psp);
785 DRM_ERROR("PSP load kdb failed!\n");
790 ret = psp_bootloader_load_sysdrv(psp);
792 DRM_ERROR("PSP load sysdrv failed!\n");
796 ret = psp_bootloader_load_sos(psp);
798 DRM_ERROR("PSP load sos failed!\n");
803 ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
805 DRM_ERROR("PSP create ring failed!\n");
809 ret = psp_tmr_init(psp);
811 DRM_ERROR("PSP tmr init failed!\n");
815 ret = psp_tmr_load(psp);
817 DRM_ERROR("PSP load tmr failed!\n");
821 ret = psp_asd_init(psp);
823 DRM_ERROR("PSP asd init failed!\n");
827 ret = psp_asd_load(psp);
829 DRM_ERROR("PSP load asd failed!\n");
833 if (adev->gmc.xgmi.num_physical_nodes > 1) {
834 ret = psp_xgmi_initialize(psp);
835 /* Warning the XGMI seesion initialize failure
836 * Instead of stop driver initialization
839 dev_err(psp->adev->dev,
840 "XGMI: Failed to initialize XGMI session\n");
843 if (psp->adev->psp.ta_fw) {
844 ret = psp_ras_initialize(psp);
846 dev_err(psp->adev->dev,
847 "RAS: Failed to initialize RAS\n");
853 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
854 enum psp_gfx_fw_type *type)
856 switch (ucode->ucode_id) {
857 case AMDGPU_UCODE_ID_SDMA0:
858 *type = GFX_FW_TYPE_SDMA0;
860 case AMDGPU_UCODE_ID_SDMA1:
861 *type = GFX_FW_TYPE_SDMA1;
863 case AMDGPU_UCODE_ID_SDMA2:
864 *type = GFX_FW_TYPE_SDMA2;
866 case AMDGPU_UCODE_ID_SDMA3:
867 *type = GFX_FW_TYPE_SDMA3;
869 case AMDGPU_UCODE_ID_SDMA4:
870 *type = GFX_FW_TYPE_SDMA4;
872 case AMDGPU_UCODE_ID_SDMA5:
873 *type = GFX_FW_TYPE_SDMA5;
875 case AMDGPU_UCODE_ID_SDMA6:
876 *type = GFX_FW_TYPE_SDMA6;
878 case AMDGPU_UCODE_ID_SDMA7:
879 *type = GFX_FW_TYPE_SDMA7;
881 case AMDGPU_UCODE_ID_CP_CE:
882 *type = GFX_FW_TYPE_CP_CE;
884 case AMDGPU_UCODE_ID_CP_PFP:
885 *type = GFX_FW_TYPE_CP_PFP;
887 case AMDGPU_UCODE_ID_CP_ME:
888 *type = GFX_FW_TYPE_CP_ME;
890 case AMDGPU_UCODE_ID_CP_MEC1:
891 *type = GFX_FW_TYPE_CP_MEC;
893 case AMDGPU_UCODE_ID_CP_MEC1_JT:
894 *type = GFX_FW_TYPE_CP_MEC_ME1;
896 case AMDGPU_UCODE_ID_CP_MEC2:
897 *type = GFX_FW_TYPE_CP_MEC;
899 case AMDGPU_UCODE_ID_CP_MEC2_JT:
900 *type = GFX_FW_TYPE_CP_MEC_ME2;
902 case AMDGPU_UCODE_ID_RLC_G:
903 *type = GFX_FW_TYPE_RLC_G;
905 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
906 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
908 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
909 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
911 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
912 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
914 case AMDGPU_UCODE_ID_SMC:
915 *type = GFX_FW_TYPE_SMU;
917 case AMDGPU_UCODE_ID_UVD:
918 *type = GFX_FW_TYPE_UVD;
920 case AMDGPU_UCODE_ID_UVD1:
921 *type = GFX_FW_TYPE_UVD1;
923 case AMDGPU_UCODE_ID_VCE:
924 *type = GFX_FW_TYPE_VCE;
926 case AMDGPU_UCODE_ID_VCN:
927 *type = GFX_FW_TYPE_VCN;
929 case AMDGPU_UCODE_ID_DMCU_ERAM:
930 *type = GFX_FW_TYPE_DMCU_ERAM;
932 case AMDGPU_UCODE_ID_DMCU_INTV:
933 *type = GFX_FW_TYPE_DMCU_ISR;
935 case AMDGPU_UCODE_ID_VCN0_RAM:
936 *type = GFX_FW_TYPE_VCN0_RAM;
938 case AMDGPU_UCODE_ID_VCN1_RAM:
939 *type = GFX_FW_TYPE_VCN1_RAM;
941 case AMDGPU_UCODE_ID_MAXIMUM:
949 static void psp_print_fw_hdr(struct psp_context *psp,
950 struct amdgpu_firmware_info *ucode)
952 struct amdgpu_device *adev = psp->adev;
953 const struct sdma_firmware_header_v1_0 *sdma_hdr =
954 (const struct sdma_firmware_header_v1_0 *)
955 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
956 const struct gfx_firmware_header_v1_0 *ce_hdr =
957 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
958 const struct gfx_firmware_header_v1_0 *pfp_hdr =
959 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
960 const struct gfx_firmware_header_v1_0 *me_hdr =
961 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
962 const struct gfx_firmware_header_v1_0 *mec_hdr =
963 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
964 const struct rlc_firmware_header_v2_0 *rlc_hdr =
965 (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
966 const struct smc_firmware_header_v1_0 *smc_hdr =
967 (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;
969 switch (ucode->ucode_id) {
970 case AMDGPU_UCODE_ID_SDMA0:
971 case AMDGPU_UCODE_ID_SDMA1:
972 case AMDGPU_UCODE_ID_SDMA2:
973 case AMDGPU_UCODE_ID_SDMA3:
974 case AMDGPU_UCODE_ID_SDMA4:
975 case AMDGPU_UCODE_ID_SDMA5:
976 case AMDGPU_UCODE_ID_SDMA6:
977 case AMDGPU_UCODE_ID_SDMA7:
978 amdgpu_ucode_print_sdma_hdr(&sdma_hdr->header);
980 case AMDGPU_UCODE_ID_CP_CE:
981 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
983 case AMDGPU_UCODE_ID_CP_PFP:
984 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
986 case AMDGPU_UCODE_ID_CP_ME:
987 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
989 case AMDGPU_UCODE_ID_CP_MEC1:
990 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
992 case AMDGPU_UCODE_ID_RLC_G:
993 amdgpu_ucode_print_rlc_hdr(&rlc_hdr->header);
995 case AMDGPU_UCODE_ID_SMC:
996 amdgpu_ucode_print_smc_hdr(&smc_hdr->header);
1003 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
1004 struct psp_gfx_cmd_resp *cmd)
1007 uint64_t fw_mem_mc_addr = ucode->mc_addr;
1009 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
1011 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
1012 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
1013 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
1014 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
1016 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
1018 DRM_ERROR("Unknown firmware type\n");
1023 static int psp_execute_np_fw_load(struct psp_context *psp,
1024 struct amdgpu_firmware_info *ucode)
1028 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd);
1032 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
1033 psp->fence_buf_mc_addr);
1038 static int psp_np_fw_load(struct psp_context *psp)
1041 struct amdgpu_firmware_info *ucode;
1042 struct amdgpu_device* adev = psp->adev;
1044 if (psp->autoload_supported) {
1045 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
1049 ret = psp_execute_np_fw_load(psp, ucode);
1055 for (i = 0; i < adev->firmware.max_ucodes; i++) {
1056 ucode = &adev->firmware.ucode[i];
1060 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
1061 (psp_smu_reload_quirk(psp) || psp->autoload_supported))
1064 if (amdgpu_sriov_vf(adev) &&
1065 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
1066 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
1067 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
1068 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
1069 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
1070 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
1071 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
1072 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
1073 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
1074 /*skip ucode loading in SRIOV VF */
1077 if (psp->autoload_supported &&
1078 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
1079 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
1080 /* skip mec JT when autoload is enabled */
1082 /* Renoir only needs to load mec jump table one time */
1083 if (adev->asic_type == CHIP_RENOIR &&
1084 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)
1087 psp_print_fw_hdr(psp, ucode);
1089 ret = psp_execute_np_fw_load(psp, ucode);
1093 /* Start rlc autoload after psp recieved all the gfx firmware */
1094 if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
1095 ret = psp_rlc_autoload(psp);
1097 DRM_ERROR("Failed to start rlc autoload\n");
1102 /* check if firmware loaded sucessfully */
1103 if (!amdgpu_psp_check_fw_loading_status(adev, i))
1111 static int psp_load_fw(struct amdgpu_device *adev)
1114 struct psp_context *psp = &adev->psp;
1116 if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) {
1117 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
1121 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1125 /* this fw pri bo is not used under SRIOV */
1126 if (!amdgpu_sriov_vf(psp->adev)) {
1127 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
1128 AMDGPU_GEM_DOMAIN_GTT,
1130 &psp->fw_pri_mc_addr,
1136 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
1137 AMDGPU_GEM_DOMAIN_VRAM,
1139 &psp->fence_buf_mc_addr,
1144 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
1145 AMDGPU_GEM_DOMAIN_VRAM,
1146 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
1147 (void **)&psp->cmd_buf_mem);
1151 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
1153 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
1155 DRM_ERROR("PSP ring init failed!\n");
1160 ret = psp_hw_start(psp);
1164 ret = psp_np_fw_load(psp);
1172 * all cleanup jobs (xgmi terminate, ras terminate,
1173 * ring destroy, cmd/fence/fw buffers destory,
1174 * psp->cmd destory) are delayed to psp_hw_fini
1179 static int psp_hw_init(void *handle)
1182 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1184 mutex_lock(&adev->firmware.mutex);
1186 * This sequence is just used on hw_init only once, no need on
1189 ret = amdgpu_ucode_init_bo(adev);
1193 ret = psp_load_fw(adev);
1195 DRM_ERROR("PSP firmware loading failed\n");
1199 mutex_unlock(&adev->firmware.mutex);
1203 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
1204 mutex_unlock(&adev->firmware.mutex);
1208 static int psp_hw_fini(void *handle)
1210 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1211 struct psp_context *psp = &adev->psp;
1215 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1216 psp->xgmi_context.initialized == 1)
1217 psp_xgmi_terminate(psp);
1219 if (psp->adev->psp.ta_fw)
1220 psp_ras_terminate(psp);
1222 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
1224 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
1225 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
1226 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
1227 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
1228 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
1229 &psp->fence_buf_mc_addr, &psp->fence_buf);
1230 amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr,
1231 &psp->asd_shared_buf);
1232 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
1233 (void **)&psp->cmd_buf_mem);
1241 static int psp_suspend(void *handle)
1244 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1245 struct psp_context *psp = &adev->psp;
1247 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1248 psp->xgmi_context.initialized == 1) {
1249 ret = psp_xgmi_terminate(psp);
1251 DRM_ERROR("Failed to terminate xgmi ta\n");
1256 if (psp->adev->psp.ta_fw) {
1257 ret = psp_ras_terminate(psp);
1259 DRM_ERROR("Failed to terminate ras ta\n");
1264 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
1266 DRM_ERROR("PSP ring stop failed\n");
1273 static int psp_resume(void *handle)
1276 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1277 struct psp_context *psp = &adev->psp;
1279 DRM_INFO("PSP is resuming...\n");
1281 mutex_lock(&adev->firmware.mutex);
1283 ret = psp_hw_start(psp);
1287 ret = psp_np_fw_load(psp);
1291 mutex_unlock(&adev->firmware.mutex);
1296 DRM_ERROR("PSP resume failed\n");
1297 mutex_unlock(&adev->firmware.mutex);
1301 int psp_gpu_reset(struct amdgpu_device *adev)
1305 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1308 mutex_lock(&adev->psp.mutex);
1309 ret = psp_mode1_reset(&adev->psp);
1310 mutex_unlock(&adev->psp.mutex);
1315 int psp_rlc_autoload_start(struct psp_context *psp)
1318 struct psp_gfx_cmd_resp *cmd;
1320 if (amdgpu_sriov_vf(psp->adev))
1323 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1327 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
1329 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1330 psp->fence_buf_mc_addr);
1335 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
1336 uint64_t cmd_gpu_addr, int cmd_size)
1338 struct amdgpu_firmware_info ucode = {0};
1340 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
1341 AMDGPU_UCODE_ID_VCN0_RAM;
1342 ucode.mc_addr = cmd_gpu_addr;
1343 ucode.ucode_size = cmd_size;
1345 return psp_execute_np_fw_load(&adev->psp, &ucode);
1348 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
1349 enum AMDGPU_UCODE_ID ucode_type)
1351 struct amdgpu_firmware_info *ucode = NULL;
1353 if (!adev->firmware.fw_size)
1356 ucode = &adev->firmware.ucode[ucode_type];
1357 if (!ucode->fw || !ucode->ucode_size)
1360 return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
1363 static int psp_set_clockgating_state(void *handle,
1364 enum amd_clockgating_state state)
1369 static int psp_set_powergating_state(void *handle,
1370 enum amd_powergating_state state)
1375 const struct amd_ip_funcs psp_ip_funcs = {
1377 .early_init = psp_early_init,
1379 .sw_init = psp_sw_init,
1380 .sw_fini = psp_sw_fini,
1381 .hw_init = psp_hw_init,
1382 .hw_fini = psp_hw_fini,
1383 .suspend = psp_suspend,
1384 .resume = psp_resume,
1386 .check_soft_reset = NULL,
1387 .wait_for_idle = NULL,
1389 .set_clockgating_state = psp_set_clockgating_state,
1390 .set_powergating_state = psp_set_powergating_state,
1393 static const struct amdgpu_psp_funcs psp_funcs = {
1394 .check_fw_loading_status = psp_check_fw_loading_status,
1397 static void psp_set_funcs(struct amdgpu_device *adev)
1399 if (NULL == adev->firmware.funcs)
1400 adev->firmware.funcs = &psp_funcs;
1403 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
1405 .type = AMD_IP_BLOCK_TYPE_PSP,
1409 .funcs = &psp_ip_funcs,
1412 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
1414 .type = AMD_IP_BLOCK_TYPE_PSP,
1418 .funcs = &psp_ip_funcs,
1421 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
1423 .type = AMD_IP_BLOCK_TYPE_PSP,
1427 .funcs = &psp_ip_funcs,
1430 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
1432 .type = AMD_IP_BLOCK_TYPE_PSP,
1436 .funcs = &psp_ip_funcs,