drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25 #ifndef __AMDGPU_PSP_H__
  26 #define __AMDGPU_PSP_H__
  27
  28 #include "amdgpu.h"
  29 #include "psp_gfx_if.h"
  30 #include "ta_xgmi_if.h"
  31 #include "ta_ras_if.h"
  32
  33 #define PSP_FENCE_BUFFER_SIZE   0x1000
  34 #define PSP_CMD_BUFFER_SIZE     0x1000
  35 #define PSP_ASD_SHARED_MEM_SIZE 0x4000
  36 #define PSP_XGMI_SHARED_MEM_SIZE 0x4000
  37 #define PSP_RAS_SHARED_MEM_SIZE 0x4000
  38 #define PSP_1_MEG               0x100000
  39 #define PSP_TMR_SIZE    0x400000
  40
  41 struct psp_context;
  42 struct psp_xgmi_node_info;
  43 struct psp_xgmi_topology_info;
  44
  45 enum psp_bootloader_cmd {
  46         PSP_BL__LOAD_SYSDRV             = 0x10000,
  47         PSP_BL__LOAD_SOSDRV             = 0x20000,
  48         PSP_BL__LOAD_KEY_DATABASE       = 0x80000,
  49 };
  50
  51 enum psp_ring_type
  52 {
  53         PSP_RING_TYPE__INVALID = 0,
  54         /*
  55          * These values map to the way the PSP kernel identifies the
  56          * rings.
  57          */
  58         PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
  59         PSP_RING_TYPE__KM = 2  /* Kernel mode ring (formerly called GPCOM) */
  60 };
  61
  62 struct psp_ring
  63 {
  64         enum psp_ring_type              ring_type;
  65         struct psp_gfx_rb_frame         *ring_mem;
  66         uint64_t                        ring_mem_mc_addr;
  67         void                            *ring_mem_handle;
  68         uint32_t                        ring_size;
  69 };
  70
  71 /* More registers may will be supported */
  72 enum psp_reg_prog_id {
  73         PSP_REG_IH_RB_CNTL        = 0,  /* register IH_RB_CNTL */
  74         PSP_REG_IH_RB_CNTL_RING1  = 1,  /* register IH_RB_CNTL_RING1 */
  75         PSP_REG_IH_RB_CNTL_RING2  = 2,  /* register IH_RB_CNTL_RING2 */
  76         PSP_REG_LAST
  77 };
  78
  79 struct psp_funcs
  80 {
  81         int (*init_microcode)(struct psp_context *psp);
  82         int (*bootloader_load_kdb)(struct psp_context *psp);
  83         int (*bootloader_load_sysdrv)(struct psp_context *psp);
  84         int (*bootloader_load_sos)(struct psp_context *psp);
  85         int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
  86         int (*ring_create)(struct psp_context *psp,
  87                            enum psp_ring_type ring_type);
  88         int (*ring_stop)(struct psp_context *psp,
  89                             enum psp_ring_type ring_type);
  90         int (*ring_destroy)(struct psp_context *psp,
  91                             enum psp_ring_type ring_type);
  92         int (*cmd_submit)(struct psp_context *psp,
  93                           struct amdgpu_firmware_info *ucode,
  94                           uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
  95                           int index);
  96         bool (*compare_sram_data)(struct psp_context *psp,
  97                                   struct amdgpu_firmware_info *ucode,
  98                                   enum AMDGPU_UCODE_ID ucode_type);
  99         bool (*smu_reload_quirk)(struct psp_context *psp);
 100         int (*mode1_reset)(struct psp_context *psp);
 101         int (*xgmi_get_node_id)(struct psp_context *psp, uint64_t *node_id);
 102         int (*xgmi_get_hive_id)(struct psp_context *psp, uint64_t *hive_id);
 103         int (*xgmi_get_topology_info)(struct psp_context *psp, int number_devices,
 104                                       struct psp_xgmi_topology_info *topology);
 105         int (*xgmi_set_topology_info)(struct psp_context *psp, int number_devices,
 106                                       struct psp_xgmi_topology_info *topology);
 107         bool (*support_vmr_ring)(struct psp_context *psp);
 108         int (*ras_trigger_error)(struct psp_context *psp,
 109                         struct ta_ras_trigger_error_input *info);
 110         int (*ras_cure_posion)(struct psp_context *psp, uint64_t *mode_ptr);
 111         int (*rlc_autoload_start)(struct psp_context *psp);
 112 };
 113
 114 #define AMDGPU_XGMI_MAX_CONNECTED_NODES         64
 115 struct psp_xgmi_node_info {
 116         uint64_t                                node_id;
 117         uint8_t                                 num_hops;
 118         uint8_t                                 is_sharing_enabled;
 119         enum ta_xgmi_assigned_sdma_engine       sdma_engine;
 120 };
 121
 122 struct psp_xgmi_topology_info {
 123         uint32_t                        num_nodes;
 124         struct psp_xgmi_node_info       nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
 125 };
 126
 127 struct psp_xgmi_context {
 128         uint8_t                         initialized;
 129         uint32_t                        session_id;
 130         struct amdgpu_bo                *xgmi_shared_bo;
 131         uint64_t                        xgmi_shared_mc_addr;
 132         void                            *xgmi_shared_buf;
 133         struct psp_xgmi_topology_info   top_info;
 134 };
 135
 136 struct psp_ras_context {
 137         /*ras fw*/
 138         bool                    ras_initialized;
 139         uint32_t                session_id;
 140         struct amdgpu_bo        *ras_shared_bo;
 141         uint64_t                ras_shared_mc_addr;
 142         void                    *ras_shared_buf;
 143         struct amdgpu_ras       *ras;
 144 };
 145
 146 struct psp_context
 147 {
 148         struct amdgpu_device            *adev;
 149         struct psp_ring                 km_ring;
 150         struct psp_gfx_cmd_resp         *cmd;
 151
 152         const struct psp_funcs          *funcs;
 153
 154         /* firmware buffer */
 155         struct amdgpu_bo                *fw_pri_bo;
 156         uint64_t                        fw_pri_mc_addr;
 157         void                            *fw_pri_buf;
 158
 159         /* sos firmware */
 160         const struct firmware           *sos_fw;
 161         uint32_t                        sos_fw_version;
 162         uint32_t                        sos_feature_version;
 163         uint32_t                        sys_bin_size;
 164         uint32_t                        sos_bin_size;
 165         uint32_t                        toc_bin_size;
 166         uint32_t                        kdb_bin_size;
 167         uint8_t                         *sys_start_addr;
 168         uint8_t                         *sos_start_addr;
 169         uint8_t                         *toc_start_addr;
 170         uint8_t                         *kdb_start_addr;
 171
 172         /* tmr buffer */
 173         struct amdgpu_bo                *tmr_bo;
 174         uint64_t                        tmr_mc_addr;
 175         void                            *tmr_buf;
 176
 177         /* asd firmware and buffer */
 178         const struct firmware           *asd_fw;
 179         uint32_t                        asd_fw_version;
 180         uint32_t                        asd_feature_version;
 181         uint32_t                        asd_ucode_size;
 182         uint8_t                         *asd_start_addr;
 183         struct amdgpu_bo                *asd_shared_bo;
 184         uint64_t                        asd_shared_mc_addr;
 185         void                            *asd_shared_buf;
 186
 187         /* fence buffer */
 188         struct amdgpu_bo                *fence_buf_bo;
 189         uint64_t                        fence_buf_mc_addr;
 190         void                            *fence_buf;
 191
 192         /* cmd buffer */
 193         struct amdgpu_bo                *cmd_buf_bo;
 194         uint64_t                        cmd_buf_mc_addr;
 195         struct psp_gfx_cmd_resp         *cmd_buf_mem;
 196
 197         /* fence value associated with cmd buffer */
 198         atomic_t                        fence_value;
 199         /* flag to mark whether gfx fw autoload is supported or not */
 200         bool                            autoload_supported;
 201
 202         /* xgmi ta firmware and buffer */
 203         const struct firmware           *ta_fw;
 204         uint32_t                        ta_fw_version;
 205         uint32_t                        ta_xgmi_ucode_version;
 206         uint32_t                        ta_xgmi_ucode_size;
 207         uint8_t                         *ta_xgmi_start_addr;
 208         uint32_t                        ta_ras_ucode_version;
 209         uint32_t                        ta_ras_ucode_size;
 210         uint8_t                         *ta_ras_start_addr;
 211         struct psp_xgmi_context         xgmi_context;
 212         struct psp_ras_context          ras;
 213         struct mutex                    mutex;
 214 };
 215
 216 struct amdgpu_psp_funcs {
 217         bool (*check_fw_loading_status)(struct amdgpu_device *adev,
 218                                         enum AMDGPU_UCODE_ID);
 219 };
 220
 221
 222 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type))
 223 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
 224 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
 225 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
 226 #define psp_cmd_submit(psp, ucode, cmd_mc, fence_mc, index) \
 227                 (psp)->funcs->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index))
 228 #define psp_compare_sram_data(psp, ucode, type) \
 229                 (psp)->funcs->compare_sram_data((psp), (ucode), (type))
 230 #define psp_init_microcode(psp) \
 231                 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
 232 #define psp_bootloader_load_kdb(psp) \
 233                 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
 234 #define psp_bootloader_load_sysdrv(psp) \
 235                 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
 236 #define psp_bootloader_load_sos(psp) \
 237                 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
 238 #define psp_smu_reload_quirk(psp) \
 239                 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
 240 #define psp_support_vmr_ring(psp) \
 241                 ((psp)->funcs->support_vmr_ring ? (psp)->funcs->support_vmr_ring((psp)) : false)
 242 #define psp_mode1_reset(psp) \
 243                 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
 244 #define psp_xgmi_get_node_id(psp, node_id) \
 245                 ((psp)->funcs->xgmi_get_node_id ? (psp)->funcs->xgmi_get_node_id((psp), (node_id)) : -EINVAL)
 246 #define psp_xgmi_get_hive_id(psp, hive_id) \
 247                 ((psp)->funcs->xgmi_get_hive_id ? (psp)->funcs->xgmi_get_hive_id((psp), (hive_id)) : -EINVAL)
 248 #define psp_xgmi_get_topology_info(psp, num_device, topology) \
 249                 ((psp)->funcs->xgmi_get_topology_info ? \
 250                 (psp)->funcs->xgmi_get_topology_info((psp), (num_device), (topology)) : -EINVAL)
 251 #define psp_xgmi_set_topology_info(psp, num_device, topology) \
 252                 ((psp)->funcs->xgmi_set_topology_info ?  \
 253                 (psp)->funcs->xgmi_set_topology_info((psp), (num_device), (topology)) : -EINVAL)
 254 #define psp_rlc_autoload(psp) \
 255                 ((psp)->funcs->rlc_autoload_start ? (psp)->funcs->rlc_autoload_start((psp)) : 0)
 256
 257 #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
 258
 259 #define psp_ras_trigger_error(psp, info) \
 260         ((psp)->funcs->ras_trigger_error ? \
 261         (psp)->funcs->ras_trigger_error((psp), (info)) : -EINVAL)
 262 #define psp_ras_cure_posion(psp, addr) \
 263         ((psp)->funcs->ras_cure_posion ? \
 264         (psp)->funcs->ras_cure_posion(psp, (addr)) : -EINVAL)
 265
 266 extern const struct amd_ip_funcs psp_ip_funcs;
 267
 268 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
 269 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 270                         uint32_t field_val, uint32_t mask, bool check_changed);
 271
 272 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
 273 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
 274
 275 int psp_gpu_reset(struct amdgpu_device *adev);
 276 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
 277                         uint64_t cmd_gpu_addr, int cmd_size);
 278
 279 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
 280
 281 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
 282 int psp_ras_enable_features(struct psp_context *psp,
 283                 union ta_ras_cmd_input *info, bool enable);
 284
 285 int psp_rlc_autoload_start(struct psp_context *psp);
 286
 287 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
 288 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
 289                 uint32_t value);
 290 #endif