2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/debugfs.h>
25 #include <linux/list.h>
26 #include <linux/module.h>
28 #include "amdgpu_ras.h"
29 #include "amdgpu_atomfirmware.h"
32 /* interrupt bottom half */
33 struct work_struct ih_work;
39 unsigned int ring_size;
40 unsigned int element_size;
41 unsigned int aligned_element_size;
48 char debugfs_name[32];
52 unsigned long ue_count;
53 unsigned long ce_count;
56 struct ras_err_handler_data {
57 /* point to bad pages array */
62 /* the count of entries */
64 /* the space can place new entries */
66 /* last reserved entry's index + 1 */
71 struct ras_common_if head;
75 struct list_head node;
77 struct amdgpu_device *adev;
81 struct device_attribute sysfs_attr;
85 struct ras_fs_data fs_data;
88 struct ras_ih_data ih_data;
90 struct ras_err_data err_data;
93 const char *ras_error_string[] = {
97 "multi_uncorrectable",
101 const char *ras_block_string[] = {
118 #define ras_err_str(i) (ras_error_string[ffs(i)])
119 #define ras_block_str(i) (ras_block_string[i])
121 enum amdgpu_ras_flags {
122 AMDGPU_RAS_FLAG_INIT_BY_VBIOS = 1,
124 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
126 static void amdgpu_ras_self_test(struct amdgpu_device *adev)
131 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
132 size_t size, loff_t *pos)
134 struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
135 struct ras_query_if info = {
141 if (amdgpu_ras_error_query(obj->adev, &info))
144 s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
146 "ce", info.ce_count);
151 s = min_t(u64, s, size);
154 if (copy_to_user(buf, &val[*pos], s))
162 static ssize_t amdgpu_ras_debugfs_write(struct file *f, const char __user *buf,
163 size_t size, loff_t *pos)
165 struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
166 struct ras_inject_if info = {
169 ssize_t s = min_t(u64, 64, size);
172 memset(val, 0, sizeof(val));
177 if (copy_from_user(str, buf, s))
180 /* only care ue/ce for now. */
181 if (memcmp(str, "ue", 2) == 0) {
182 info.head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
184 } else if (memcmp(str, "ce", 2) == 0) {
185 info.head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
189 if (sscanf(str, "0x%llx 0x%llx", &info.address, &info.value) != 2) {
190 if (sscanf(str, "%llu %llu", &info.address, &info.value) != 2)
196 if (amdgpu_ras_error_inject(obj->adev, &info))
202 static const struct file_operations amdgpu_ras_debugfs_ops = {
203 .owner = THIS_MODULE,
204 .read = amdgpu_ras_debugfs_read,
205 .write = amdgpu_ras_debugfs_write,
206 .llseek = default_llseek
209 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
213 for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
215 if (strcmp(name, ras_block_str(i)) == 0)
221 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
222 const char __user *buf, size_t size,
223 loff_t *pos, struct ras_debug_if *data)
225 ssize_t s = min_t(u64, 64, size);
237 memset(str, 0, sizeof(str));
238 memset(data, 0, sizeof(*data));
240 if (copy_from_user(str, buf, s))
243 if (sscanf(str, "disable %32s", block_name) == 1)
245 else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
247 else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
249 else if (str[0] && str[1] && str[2] && str[3])
250 /* ascii string, but commands are not matched. */
254 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
257 data->head.block = block_id;
258 data->head.type = memcmp("ue", err, 2) == 0 ?
259 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE :
260 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
264 if (sscanf(str, "%*s %*s %*s %llu %llu",
265 &address, &value) != 2)
266 if (sscanf(str, "%*s %*s %*s 0x%llx 0x%llx",
267 &address, &value) != 2)
269 data->inject.address = address;
270 data->inject.value = value;
273 if (size < sizeof(data))
276 if (copy_from_user(data, buf, sizeof(*data)))
283 * DOC: ras debugfs control interface
285 * It accepts struct ras_debug_if who has two members.
287 * First member: ras_debug_if::head or ras_debug_if::inject.
289 * head is used to indicate which IP block will be under control.
291 * head has four members, they are block, type, sub_block_index, name.
292 * block: which IP will be under control.
293 * type: what kind of error will be enabled/disabled/injected.
294 * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
295 * name: the name of IP.
297 * inject has two more members than head, they are address, value.
298 * As their names indicate, inject operation will write the
299 * value to the address.
301 * Second member: struct ras_debug_if::op.
302 * It has three kinds of operations.
303 * 0: disable RAS on the block. Take ::head as its data.
304 * 1: enable RAS on the block. Take ::head as its data.
305 * 2: inject errors on the block. Take ::inject as its data.
307 * How to use the interface?
309 * copy the struct ras_debug_if in your codes and initialize it.
310 * write the struct to the control node.
313 * echo op block [error [address value]] > .../ras/ras_ctrl
314 * op: disable, enable, inject
315 * disable: only block is needed
316 * enable: block and error are needed
317 * inject: error, address, value are needed
318 * block: umc, smda, gfx, .........
319 * see ras_block_string[] for details
321 * ue: multi_uncorrectable
322 * ce: single_correctable
324 * here are some examples for bash commands,
325 * echo inject umc ue 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
326 * echo inject umc ce 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
327 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
329 * How to check the result?
331 * For disable/enable, please check ras features at
332 * /sys/class/drm/card[0/1/2...]/device/ras/features
334 * For inject, please check corresponding err count at
335 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
337 * NOTE: operation is only allowed on blocks which are supported.
338 * Please check ras mask at /sys/module/amdgpu/parameters/ras_mask
340 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf,
341 size_t size, loff_t *pos)
343 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
344 struct ras_debug_if data;
347 ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
351 if (!amdgpu_ras_is_supported(adev, data.head.block))
356 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
359 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
362 ret = amdgpu_ras_error_inject(adev, &data.inject);
375 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
376 .owner = THIS_MODULE,
378 .write = amdgpu_ras_debugfs_ctrl_write,
379 .llseek = default_llseek
382 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
383 struct device_attribute *attr, char *buf)
385 struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
386 struct ras_query_if info = {
390 if (amdgpu_ras_error_query(obj->adev, &info))
393 return snprintf(buf, PAGE_SIZE, "%s: %lu\n%s: %lu\n",
395 "ce", info.ce_count);
400 #define get_obj(obj) do { (obj)->use++; } while (0)
401 #define alive_obj(obj) ((obj)->use)
403 static inline void put_obj(struct ras_manager *obj)
405 if (obj && --obj->use == 0)
406 list_del(&obj->node);
407 if (obj && obj->use < 0) {
408 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name);
412 /* make one obj and return it. */
413 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
414 struct ras_common_if *head)
416 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
417 struct ras_manager *obj;
422 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
425 obj = &con->objs[head->block];
426 /* already exist. return obj? */
432 list_add(&obj->node, &con->head);
438 /* return an obj equal to head, or the first when head is NULL */
439 static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
440 struct ras_common_if *head)
442 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
443 struct ras_manager *obj;
450 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
453 obj = &con->objs[head->block];
455 if (alive_obj(obj)) {
456 WARN_ON(head->block != obj->head.block);
460 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
462 if (alive_obj(obj)) {
463 WARN_ON(i != obj->head.block);
473 /* feature ctl begin */
474 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
475 struct ras_common_if *head)
477 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
479 return con->hw_supported & BIT(head->block);
482 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
483 struct ras_common_if *head)
485 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
487 return con->features & BIT(head->block);
491 * if obj is not created, then create one.
492 * set feature enable flag.
494 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
495 struct ras_common_if *head, int enable)
497 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
498 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
500 /* If hardware does not support ras, then do not create obj.
501 * But if hardware support ras, we can create the obj.
502 * Ras framework checks con->hw_supported to see if it need do
503 * corresponding initialization.
504 * IP checks con->support to see if it need disable ras.
506 if (!amdgpu_ras_is_feature_allowed(adev, head))
508 if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
513 obj = amdgpu_ras_create_obj(adev, head);
517 /* In case we create obj somewhere else */
520 con->features |= BIT(head->block);
522 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
523 con->features &= ~BIT(head->block);
531 /* wrapper of psp_ras_enable_features */
532 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
533 struct ras_common_if *head, bool enable)
535 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
536 union ta_ras_cmd_input info;
543 info.disable_features = (struct ta_ras_disable_features_input) {
544 .block_id = head->block,
545 .error_type = head->type,
548 info.enable_features = (struct ta_ras_enable_features_input) {
549 .block_id = head->block,
550 .error_type = head->type,
554 /* Do not enable if it is not allowed. */
555 WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
556 /* Are we alerady in that state we are going to set? */
557 if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
560 ret = psp_ras_enable_features(&adev->psp, &info, enable);
562 DRM_ERROR("RAS ERROR: %s %s feature failed ret %d\n",
563 enable ? "enable":"disable",
564 ras_block_str(head->block),
570 __amdgpu_ras_feature_enable(adev, head, enable);
575 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
578 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
579 struct ras_manager *obj, *tmp;
581 list_for_each_entry_safe(obj, tmp, &con->head, node) {
583 * aka just release the obj and corresponding flags
586 if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
589 if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
594 return con->features;
597 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
600 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
601 int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
604 for (i = 0; i < ras_block_count; i++) {
605 struct ras_common_if head = {
607 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
608 .sub_block_index = 0,
610 strcpy(head.name, ras_block_str(i));
613 * bypass psp. vbios enable ras for us.
614 * so just create the obj
616 if (__amdgpu_ras_feature_enable(adev, &head, 1))
619 if (amdgpu_ras_feature_enable(adev, &head, 1))
624 return con->features;
626 /* feature ctl end */
628 /* query/inject/cure begin */
629 int amdgpu_ras_error_query(struct amdgpu_device *adev,
630 struct ras_query_if *info)
632 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
636 /* TODO might read the register to read the count */
638 info->ue_count = obj->err_data.ue_count;
639 info->ce_count = obj->err_data.ce_count;
644 /* wrapper of psp_ras_trigger_error */
645 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
646 struct ras_inject_if *info)
648 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
649 struct ta_ras_trigger_error_input block_info = {
650 .block_id = info->head.block,
651 .inject_error_type = info->head.type,
652 .sub_block_index = info->head.sub_block_index,
653 .address = info->address,
654 .value = info->value,
661 ret = psp_ras_trigger_error(&adev->psp, &block_info);
663 DRM_ERROR("RAS ERROR: inject %s error failed ret %d\n",
664 ras_block_str(info->head.block),
670 int amdgpu_ras_error_cure(struct amdgpu_device *adev,
671 struct ras_cure_if *info)
673 /* psp fw has no cure interface for now. */
677 /* get the total error counts on all IPs */
678 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
681 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
682 struct ras_manager *obj;
683 struct ras_err_data data = {0, 0};
688 list_for_each_entry(obj, &con->head, node) {
689 struct ras_query_if info = {
693 if (amdgpu_ras_error_query(adev, &info))
696 data.ce_count += info.ce_count;
697 data.ue_count += info.ue_count;
700 return is_ce ? data.ce_count : data.ue_count;
702 /* query/inject/cure end */
707 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
708 struct device_attribute *attr, char *buf)
710 struct amdgpu_ras *con =
711 container_of(attr, struct amdgpu_ras, features_attr);
712 struct drm_device *ddev = dev_get_drvdata(dev);
713 struct amdgpu_device *adev = ddev->dev_private;
714 struct ras_common_if head;
715 int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
718 struct ras_manager *obj;
720 s = scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
722 for (i = 0; i < ras_block_count; i++) {
725 if (amdgpu_ras_is_feature_enabled(adev, &head)) {
726 obj = amdgpu_ras_find_obj(adev, &head);
727 s += scnprintf(&buf[s], PAGE_SIZE - s,
730 ras_err_str(obj->head.type));
732 s += scnprintf(&buf[s], PAGE_SIZE - s,
740 static int amdgpu_ras_sysfs_create_feature_node(struct amdgpu_device *adev)
742 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
743 struct attribute *attrs[] = {
744 &con->features_attr.attr,
747 struct attribute_group group = {
752 con->features_attr = (struct device_attribute) {
757 .show = amdgpu_ras_sysfs_features_read,
759 sysfs_attr_init(attrs[0]);
761 return sysfs_create_group(&adev->dev->kobj, &group);
764 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
766 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
767 struct attribute *attrs[] = {
768 &con->features_attr.attr,
771 struct attribute_group group = {
776 sysfs_remove_group(&adev->dev->kobj, &group);
781 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
782 struct ras_fs_if *head)
784 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
786 if (!obj || obj->attr_inuse)
791 memcpy(obj->fs_data.sysfs_name,
793 sizeof(obj->fs_data.sysfs_name));
795 obj->sysfs_attr = (struct device_attribute){
797 .name = obj->fs_data.sysfs_name,
800 .show = amdgpu_ras_sysfs_read,
802 sysfs_attr_init(&obj->sysfs_attr.attr);
804 if (sysfs_add_file_to_group(&adev->dev->kobj,
805 &obj->sysfs_attr.attr,
816 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
817 struct ras_common_if *head)
819 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
821 if (!obj || !obj->attr_inuse)
824 sysfs_remove_file_from_group(&adev->dev->kobj,
825 &obj->sysfs_attr.attr,
833 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
835 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
836 struct ras_manager *obj, *tmp;
838 list_for_each_entry_safe(obj, tmp, &con->head, node) {
839 amdgpu_ras_sysfs_remove(adev, &obj->head);
842 amdgpu_ras_sysfs_remove_feature_node(adev);
849 static int amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
851 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
852 struct drm_minor *minor = adev->ddev->primary;
853 struct dentry *root = minor->debugfs_root, *dir;
856 dir = debugfs_create_dir("ras", root);
862 ent = debugfs_create_file("ras_ctrl",
863 S_IWUGO | S_IRUGO, con->dir,
864 adev, &amdgpu_ras_debugfs_ctrl_ops);
866 debugfs_remove(con->dir);
874 int amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
875 struct ras_fs_if *head)
877 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
878 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
881 if (!obj || obj->ent)
886 memcpy(obj->fs_data.debugfs_name,
888 sizeof(obj->fs_data.debugfs_name));
890 ent = debugfs_create_file(obj->fs_data.debugfs_name,
891 S_IWUGO | S_IRUGO, con->dir,
892 obj, &amdgpu_ras_debugfs_ops);
902 int amdgpu_ras_debugfs_remove(struct amdgpu_device *adev,
903 struct ras_common_if *head)
905 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
907 if (!obj || !obj->ent)
910 debugfs_remove(obj->ent);
917 static int amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev)
919 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
920 struct ras_manager *obj, *tmp;
922 list_for_each_entry_safe(obj, tmp, &con->head, node) {
923 amdgpu_ras_debugfs_remove(adev, &obj->head);
926 debugfs_remove(con->ent);
927 debugfs_remove(con->dir);
937 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
939 amdgpu_ras_sysfs_create_feature_node(adev);
940 amdgpu_ras_debugfs_create_ctrl_node(adev);
945 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
947 amdgpu_ras_debugfs_remove_all(adev);
948 amdgpu_ras_sysfs_remove_all(adev);
954 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
956 struct ras_ih_data *data = &obj->ih_data;
957 struct amdgpu_iv_entry entry;
960 while (data->rptr != data->wptr) {
962 memcpy(&entry, &data->ring[data->rptr],
966 data->rptr = (data->aligned_element_size +
967 data->rptr) % data->ring_size;
969 /* Let IP handle its data, maybe we need get the output
970 * from the callback to udpate the error type/count, etc
973 ret = data->cb(obj->adev, &entry);
974 /* ue will trigger an interrupt, and in that case
975 * we need do a reset to recovery the whole system.
976 * But leave IP do that recovery, here we just dispatch
979 if (ret == AMDGPU_RAS_UE) {
980 obj->err_data.ue_count++;
982 /* Might need get ce count by register, but not all IP
983 * saves ce count, some IP just use one bit or two bits
984 * to indicate ce happened.
990 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
992 struct ras_ih_data *data =
993 container_of(work, struct ras_ih_data, ih_work);
994 struct ras_manager *obj =
995 container_of(data, struct ras_manager, ih_data);
997 amdgpu_ras_interrupt_handler(obj);
1000 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1001 struct ras_dispatch_if *info)
1003 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1004 struct ras_ih_data *data = &obj->ih_data;
1009 if (data->inuse == 0)
1012 /* Might be overflow... */
1013 memcpy(&data->ring[data->wptr], info->entry,
1014 data->element_size);
1017 data->wptr = (data->aligned_element_size +
1018 data->wptr) % data->ring_size;
1020 schedule_work(&data->ih_work);
1025 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1026 struct ras_ih_if *info)
1028 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1029 struct ras_ih_data *data;
1034 data = &obj->ih_data;
1035 if (data->inuse == 0)
1038 cancel_work_sync(&data->ih_work);
1041 memset(data, 0, sizeof(*data));
1047 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1048 struct ras_ih_if *info)
1050 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1051 struct ras_ih_data *data;
1054 /* in case we registe the IH before enable ras feature */
1055 obj = amdgpu_ras_create_obj(adev, &info->head);
1061 data = &obj->ih_data;
1062 /* add the callback.etc */
1063 *data = (struct ras_ih_data) {
1066 .element_size = sizeof(struct amdgpu_iv_entry),
1071 INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1073 data->aligned_element_size = ALIGN(data->element_size, 8);
1074 /* the ring can store 64 iv entries. */
1075 data->ring_size = 64 * data->aligned_element_size;
1076 data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1088 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1090 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1091 struct ras_manager *obj, *tmp;
1093 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1094 struct ras_ih_if info = {
1097 amdgpu_ras_interrupt_remove_handler(adev, &info);
1104 /* recovery begin */
1105 static void amdgpu_ras_do_recovery(struct work_struct *work)
1107 struct amdgpu_ras *ras =
1108 container_of(work, struct amdgpu_ras, recovery_work);
1110 amdgpu_device_gpu_recover(ras->adev, 0);
1111 atomic_set(&ras->in_recovery, 0);
1114 static int amdgpu_ras_release_vram(struct amdgpu_device *adev,
1115 struct amdgpu_bo **bo_ptr)
1117 /* no need to free it actually. */
1118 amdgpu_bo_free_kernel(bo_ptr, NULL, NULL);
1122 /* reserve vram with size@offset */
1123 static int amdgpu_ras_reserve_vram(struct amdgpu_device *adev,
1124 uint64_t offset, uint64_t size,
1125 struct amdgpu_bo **bo_ptr)
1127 struct ttm_operation_ctx ctx = { false, false };
1128 struct amdgpu_bo_param bp;
1131 struct amdgpu_bo *bo;
1135 memset(&bp, 0, sizeof(bp));
1137 bp.byte_align = PAGE_SIZE;
1138 bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
1139 bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
1140 AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
1141 bp.type = ttm_bo_type_kernel;
1144 r = amdgpu_bo_create(adev, &bp, &bo);
1148 r = amdgpu_bo_reserve(bo, false);
1152 offset = ALIGN(offset, PAGE_SIZE);
1153 for (i = 0; i < bo->placement.num_placement; ++i) {
1154 bo->placements[i].fpfn = offset >> PAGE_SHIFT;
1155 bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
1158 ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
1159 r = ttm_bo_mem_space(&bo->tbo, &bo->placement, &bo->tbo.mem, &ctx);
1163 r = amdgpu_bo_pin_restricted(bo,
1164 AMDGPU_GEM_DOMAIN_VRAM,
1173 amdgpu_bo_unreserve(bo);
1177 amdgpu_bo_unreserve(bo);
1179 amdgpu_bo_unref(&bo);
1183 /* alloc/realloc bps array */
1184 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
1185 struct ras_err_handler_data *data, int pages)
1187 unsigned int old_space = data->count + data->space_left;
1188 unsigned int new_space = old_space + pages;
1189 unsigned int align_space = ALIGN(new_space, 1024);
1190 void *tmp = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1196 memcpy(tmp, data->bps,
1197 data->count * sizeof(*data->bps));
1202 data->space_left += align_space - old_space;
1206 /* it deal with vram only. */
1207 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
1208 unsigned long *bps, int pages)
1210 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1211 struct ras_err_handler_data *data = con->eh_data;
1215 if (!con || !data || !bps || pages <= 0)
1218 mutex_lock(&con->recovery_lock);
1222 if (data->space_left <= pages)
1223 if (amdgpu_ras_realloc_eh_data_space(adev, data, pages)) {
1229 data->bps[data->count++].bp = bps[i];
1231 data->space_left -= pages;
1233 mutex_unlock(&con->recovery_lock);
1238 /* called in gpu recovery/init */
1239 int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev)
1241 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1242 struct ras_err_handler_data *data = con->eh_data;
1244 struct amdgpu_bo *bo;
1250 mutex_lock(&con->recovery_lock);
1251 /* reserve vram at driver post stage. */
1252 for (i = data->last_reserved; i < data->count; i++) {
1253 bp = data->bps[i].bp;
1255 if (amdgpu_ras_reserve_vram(adev, bp << PAGE_SHIFT,
1257 DRM_ERROR("RAS ERROR: reserve vram %llx fail\n", bp);
1259 data->bps[i].bo = bo;
1260 data->last_reserved = i + 1;
1262 mutex_unlock(&con->recovery_lock);
1266 /* called when driver unload */
1267 static int amdgpu_ras_release_bad_pages(struct amdgpu_device *adev)
1269 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1270 struct ras_err_handler_data *data = con->eh_data;
1271 struct amdgpu_bo *bo;
1277 mutex_lock(&con->recovery_lock);
1278 for (i = data->last_reserved - 1; i >= 0; i--) {
1279 bo = data->bps[i].bo;
1281 amdgpu_ras_release_vram(adev, &bo);
1283 data->bps[i].bo = bo;
1284 data->last_reserved = i;
1286 mutex_unlock(&con->recovery_lock);
1290 static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
1293 * write the array to eeprom when SMU disabled.
1298 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
1301 * read the array to eeprom when SMU disabled.
1306 static int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
1308 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1309 struct ras_err_handler_data **data = &con->eh_data;
1311 *data = kmalloc(sizeof(**data),
1312 GFP_KERNEL|__GFP_ZERO);
1316 mutex_init(&con->recovery_lock);
1317 INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
1318 atomic_set(&con->in_recovery, 0);
1321 amdgpu_ras_load_bad_pages(adev);
1322 amdgpu_ras_reserve_bad_pages(adev);
1327 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
1329 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1330 struct ras_err_handler_data *data = con->eh_data;
1332 cancel_work_sync(&con->recovery_work);
1333 amdgpu_ras_save_bad_pages(adev);
1334 amdgpu_ras_release_bad_pages(adev);
1336 mutex_lock(&con->recovery_lock);
1337 con->eh_data = NULL;
1340 mutex_unlock(&con->recovery_lock);
1347 * check hardware's ras ability which will be saved in hw_supported.
1348 * if hardware does not support ras, we can skip some ras initializtion and
1349 * forbid some ras operations from IP.
1350 * if software itself, say boot parameter, limit the ras ability. We still
1351 * need allow IP do some limited operations, like disable. In such case,
1352 * we have to initialize ras as normal. but need check if operation is
1353 * allowed or not in each function.
1355 static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
1356 uint32_t *hw_supported, uint32_t *supported)
1361 if (amdgpu_sriov_vf(adev) ||
1362 adev->asic_type != CHIP_VEGA20)
1365 if (adev->is_atom_fw &&
1366 (amdgpu_atomfirmware_mem_ecc_supported(adev) ||
1367 amdgpu_atomfirmware_sram_ecc_supported(adev)))
1368 *hw_supported = AMDGPU_RAS_BLOCK_MASK;
1370 *supported = amdgpu_ras_enable == 0 ?
1371 0 : *hw_supported & amdgpu_ras_mask;
1374 int amdgpu_ras_init(struct amdgpu_device *adev)
1376 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1381 con = kmalloc(sizeof(struct amdgpu_ras) +
1382 sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT,
1383 GFP_KERNEL|__GFP_ZERO);
1387 con->objs = (struct ras_manager *)(con + 1);
1389 amdgpu_ras_set_context(adev, con);
1391 amdgpu_ras_check_supported(adev, &con->hw_supported,
1394 INIT_LIST_HEAD(&con->head);
1395 /* Might need get this flag from vbios. */
1396 con->flags = RAS_DEFAULT_FLAGS;
1398 if (amdgpu_ras_recovery_init(adev))
1401 amdgpu_ras_mask &= AMDGPU_RAS_BLOCK_MASK;
1403 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
1404 amdgpu_ras_enable_all_features(adev, 1);
1406 if (amdgpu_ras_fs_init(adev))
1409 amdgpu_ras_self_test(adev);
1411 DRM_INFO("RAS INFO: ras initialized successfully, "
1412 "hardware ability[%x] ras_mask[%x]\n",
1413 con->hw_supported, con->supported);
1416 amdgpu_ras_recovery_fini(adev);
1418 amdgpu_ras_set_context(adev, NULL);
1424 /* do some init work after IP late init as dependence */
1425 void amdgpu_ras_post_init(struct amdgpu_device *adev)
1427 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1428 struct ras_manager *obj, *tmp;
1433 /* We enable ras on all hw_supported block, but as boot parameter might
1434 * disable some of them and one or more IP has not implemented yet.
1435 * So we disable them on behalf.
1437 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
1438 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1439 if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
1440 amdgpu_ras_feature_enable(adev, &obj->head, 0);
1441 /* there should be no any reference. */
1442 WARN_ON(alive_obj(obj));
1448 /* do some fini work before IP fini as dependence */
1449 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
1451 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1456 /* Need disable ras on all IPs here before ip [hw/sw]fini */
1457 amdgpu_ras_disable_all_features(adev, 0);
1458 amdgpu_ras_recovery_fini(adev);
1462 int amdgpu_ras_fini(struct amdgpu_device *adev)
1464 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1469 amdgpu_ras_fs_fini(adev);
1470 amdgpu_ras_interrupt_remove_all(adev);
1472 WARN(con->features, "Feature mask is not cleared");
1475 amdgpu_ras_disable_all_features(adev, 1);
1477 amdgpu_ras_set_context(adev, NULL);