2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Christian König
24 #ifndef __AMDGPU_RING_H__
25 #define __AMDGPU_RING_H__
27 #include <drm/amdgpu_drm.h>
28 #include <drm/gpu_scheduler.h>
30 /* max number of rings */
31 #define AMDGPU_MAX_RINGS 18
32 #define AMDGPU_MAX_GFX_RINGS 1
33 #define AMDGPU_MAX_COMPUTE_RINGS 8
34 #define AMDGPU_MAX_VCE_RINGS 3
35 #define AMDGPU_MAX_UVD_ENC_RINGS 2
37 /* some special values for the owner field */
38 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
39 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
41 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
42 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
44 enum amdgpu_ring_type {
46 AMDGPU_RING_TYPE_COMPUTE,
47 AMDGPU_RING_TYPE_SDMA,
51 AMDGPU_RING_TYPE_UVD_ENC,
52 AMDGPU_RING_TYPE_VCN_DEC,
53 AMDGPU_RING_TYPE_VCN_ENC
59 struct amdgpu_cs_parser;
65 struct amdgpu_fence_driver {
67 volatile uint32_t *cpu_addr;
68 /* sync_seq is protected by ring emission lock */
72 struct amdgpu_irq_src *irq_src;
74 struct timer_list fallback_timer;
75 unsigned num_fences_mask;
77 struct dma_fence **fences;
80 int amdgpu_fence_driver_init(struct amdgpu_device *adev);
81 void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
82 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
84 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
85 unsigned num_hw_submission);
86 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
87 struct amdgpu_irq_src *irq_src,
89 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
90 void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
91 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence);
92 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s);
93 void amdgpu_fence_process(struct amdgpu_ring *ring);
94 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
95 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
98 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
104 /* provided by hw blocks that expose a ring buffer for commands */
105 struct amdgpu_ring_funcs {
106 enum amdgpu_ring_type type;
109 bool support_64bit_ptrs;
112 /* ring read/write ptr handling */
113 u64 (*get_rptr)(struct amdgpu_ring *ring);
114 u64 (*get_wptr)(struct amdgpu_ring *ring);
115 void (*set_wptr)(struct amdgpu_ring *ring);
116 /* validating and patching of IBs */
117 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
118 /* constants to calculate how many DW are needed for an emit */
119 unsigned emit_frame_size;
120 unsigned emit_ib_size;
121 /* command emit functions */
122 void (*emit_ib)(struct amdgpu_ring *ring,
123 struct amdgpu_ib *ib,
124 unsigned vmid, bool ctx_switch);
125 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
126 uint64_t seq, unsigned flags);
127 void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
128 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
129 unsigned pasid, uint64_t pd_addr);
130 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
131 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
132 uint32_t gds_base, uint32_t gds_size,
133 uint32_t gws_base, uint32_t gws_size,
134 uint32_t oa_base, uint32_t oa_size);
135 /* testing functions */
136 int (*test_ring)(struct amdgpu_ring *ring);
137 int (*test_ib)(struct amdgpu_ring *ring, long timeout);
138 /* insert NOP packets */
139 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
140 void (*insert_start)(struct amdgpu_ring *ring);
141 void (*insert_end)(struct amdgpu_ring *ring);
142 /* pad the indirect buffer to the necessary number of dw */
143 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
144 unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
145 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
146 /* note usage for clock and power gating */
147 void (*begin_use)(struct amdgpu_ring *ring);
148 void (*end_use)(struct amdgpu_ring *ring);
149 void (*emit_switch_buffer) (struct amdgpu_ring *ring);
150 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
151 void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
152 void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
153 void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
154 uint32_t val, uint32_t mask);
155 void (*emit_tmz)(struct amdgpu_ring *ring, bool start);
156 /* priority functions */
157 void (*set_priority) (struct amdgpu_ring *ring,
158 enum drm_sched_priority priority);
162 struct amdgpu_device *adev;
163 const struct amdgpu_ring_funcs *funcs;
164 struct amdgpu_fence_driver fence_drv;
165 struct drm_gpu_scheduler sched;
166 struct list_head lru_list;
168 struct amdgpu_bo *ring_obj;
169 volatile uint32_t *ring;
184 struct amdgpu_bo *mqd_obj;
185 uint64_t mqd_gpu_addr;
187 uint64_t eop_gpu_addr;
193 uint64_t current_ctx;
195 unsigned cond_exe_offs;
196 u64 cond_exe_gpu_addr;
197 volatile u32 *cond_exe_cpu_addr;
199 bool has_compute_vm_bug;
201 atomic_t num_jobs[DRM_SCHED_PRIORITY_MAX];
202 struct mutex priority_mutex;
203 /* protected by priority_mutex */
206 #if defined(CONFIG_DEBUG_FS)
211 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
212 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
213 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
214 void amdgpu_ring_commit(struct amdgpu_ring *ring);
215 void amdgpu_ring_undo(struct amdgpu_ring *ring);
216 void amdgpu_ring_priority_get(struct amdgpu_ring *ring,
217 enum drm_sched_priority priority);
218 void amdgpu_ring_priority_put(struct amdgpu_ring *ring,
219 enum drm_sched_priority priority);
220 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
221 unsigned ring_size, struct amdgpu_irq_src *irq_src,
223 void amdgpu_ring_fini(struct amdgpu_ring *ring);
224 int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type,
225 int *blacklist, int num_blacklist,
226 bool lru_pipe_order, struct amdgpu_ring **ring);
227 void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct amdgpu_ring *ring);
228 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
231 while (i <= ring->buf_mask)
232 ring->ring[i++] = ring->funcs->nop;
236 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
238 if (ring->count_dw <= 0)
239 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
240 ring->ring[ring->wptr++ & ring->buf_mask] = v;
241 ring->wptr &= ring->ptr_mask;
245 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,
246 void *src, int count_dw)
248 unsigned occupied, chunk1, chunk2;
251 if (unlikely(ring->count_dw < count_dw))
252 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
254 occupied = ring->wptr & ring->buf_mask;
255 dst = (void *)&ring->ring[occupied];
256 chunk1 = ring->buf_mask + 1 - occupied;
257 chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
258 chunk2 = count_dw - chunk1;
263 memcpy(dst, src, chunk1);
267 dst = (void *)ring->ring;
268 memcpy(dst, src, chunk2);
271 ring->wptr += count_dw;
272 ring->wptr &= ring->ptr_mask;
273 ring->count_dw -= count_dw;