2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/dma-fence-array.h>
29 #include <linux/interval_tree_generic.h>
30 #include <linux/idr.h>
32 #include <drm/amdgpu_drm.h>
34 #include "amdgpu_trace.h"
35 #include "amdgpu_amdkfd.h"
36 #include "amdgpu_gmc.h"
37 #include "amdgpu_xgmi.h"
42 * GPUVM is similar to the legacy gart on older asics, however
43 * rather than there being a single global gart table
44 * for the entire GPU, there are multiple VM page tables active
45 * at any given time. The VM page tables can contain a mix
46 * vram pages and system memory pages and system memory pages
47 * can be mapped as snooped (cached system pages) or unsnooped
48 * (uncached system pages).
49 * Each VM has an ID associated with it and there is a page table
50 * associated with each VMID. When execting a command buffer,
51 * the kernel tells the the ring what VMID to use for that command
52 * buffer. VMIDs are allocated dynamically as commands are submitted.
53 * The userspace drivers maintain their own address space and the kernel
54 * sets up their pages tables accordingly when they submit their
55 * command buffers and a VMID is assigned.
56 * Cayman/Trinity support up to 8 active VMs at any given time;
60 #define START(node) ((node)->start)
61 #define LAST(node) ((node)->last)
63 INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
64 START, LAST, static, amdgpu_vm_it)
70 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
72 struct amdgpu_prt_cb {
75 * @adev: amdgpu device
77 struct amdgpu_device *adev;
82 struct dma_fence_cb cb;
86 * amdgpu_vm_level_shift - return the addr shift for each level
88 * @adev: amdgpu_device pointer
92 * The number of bits the pfn needs to be right shifted for a level.
94 static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
97 unsigned shift = 0xff;
103 shift = 9 * (AMDGPU_VM_PDB0 - level) +
104 adev->vm_manager.block_size;
110 dev_err(adev->dev, "the level%d isn't supported.\n", level);
117 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
119 * @adev: amdgpu_device pointer
123 * The number of entries in a page directory or page table.
125 static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
128 unsigned shift = amdgpu_vm_level_shift(adev,
129 adev->vm_manager.root_level);
131 if (level == adev->vm_manager.root_level)
132 /* For the root directory */
133 return round_up(adev->vm_manager.max_pfn, 1ULL << shift) >> shift;
134 else if (level != AMDGPU_VM_PTB)
135 /* Everything in between */
138 /* For the page tables on the leaves */
139 return AMDGPU_VM_PTE_COUNT(adev);
143 * amdgpu_vm_num_ats_entries - return the number of ATS entries in the root PD
145 * @adev: amdgpu_device pointer
148 * The number of entries in the root page directory which needs the ATS setting.
150 static unsigned amdgpu_vm_num_ats_entries(struct amdgpu_device *adev)
154 shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level);
155 return AMDGPU_GMC_HOLE_START >> (shift + AMDGPU_GPU_PAGE_SHIFT);
159 * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT
161 * @adev: amdgpu_device pointer
165 * The mask to extract the entry number of a PD/PT from an address.
167 static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
170 if (level <= adev->vm_manager.root_level)
172 else if (level != AMDGPU_VM_PTB)
175 return AMDGPU_VM_PTE_COUNT(adev) - 1;
179 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
181 * @adev: amdgpu_device pointer
185 * The size of the BO for a page directory or page table in bytes.
187 static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
189 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
193 * amdgpu_vm_bo_evicted - vm_bo is evicted
195 * @vm_bo: vm_bo which is evicted
197 * State for PDs/PTs and per VM BOs which are not at the location they should
200 static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
202 struct amdgpu_vm *vm = vm_bo->vm;
203 struct amdgpu_bo *bo = vm_bo->bo;
206 if (bo->tbo.type == ttm_bo_type_kernel)
207 list_move(&vm_bo->vm_status, &vm->evicted);
209 list_move_tail(&vm_bo->vm_status, &vm->evicted);
213 * amdgpu_vm_bo_relocated - vm_bo is reloacted
215 * @vm_bo: vm_bo which is relocated
217 * State for PDs/PTs which needs to update their parent PD.
219 static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
221 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
225 * amdgpu_vm_bo_moved - vm_bo is moved
227 * @vm_bo: vm_bo which is moved
229 * State for per VM BOs which are moved, but that change is not yet reflected
230 * in the page tables.
232 static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
234 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
238 * amdgpu_vm_bo_idle - vm_bo is idle
240 * @vm_bo: vm_bo which is now idle
242 * State for PDs/PTs and per VM BOs which have gone through the state machine
245 static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
247 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
248 vm_bo->moved = false;
252 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
254 * @vm_bo: vm_bo which is now invalidated
256 * State for normal BOs which are invalidated and that change not yet reflected
259 static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
261 spin_lock(&vm_bo->vm->invalidated_lock);
262 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
263 spin_unlock(&vm_bo->vm->invalidated_lock);
267 * amdgpu_vm_bo_done - vm_bo is done
269 * @vm_bo: vm_bo which is now done
271 * State for normal BOs which are invalidated and that change has been updated
274 static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
276 spin_lock(&vm_bo->vm->invalidated_lock);
277 list_del_init(&vm_bo->vm_status);
278 spin_unlock(&vm_bo->vm->invalidated_lock);
282 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
284 * @base: base structure for tracking BO usage in a VM
285 * @vm: vm to which bo is to be added
286 * @bo: amdgpu buffer object
288 * Initialize a bo_va_base structure and add it to the appropriate lists
291 static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
292 struct amdgpu_vm *vm,
293 struct amdgpu_bo *bo)
298 INIT_LIST_HEAD(&base->vm_status);
302 base->next = bo->vm_bo;
305 if (bo->tbo.resv != vm->root.base.bo->tbo.resv)
308 vm->bulk_moveable = false;
309 if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
310 amdgpu_vm_bo_relocated(base);
312 amdgpu_vm_bo_idle(base);
314 if (bo->preferred_domains &
315 amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type))
319 * we checked all the prerequisites, but it looks like this per vm bo
320 * is currently evicted. add the bo to the evicted list to make sure it
321 * is validated on next vm use to avoid fault.
323 amdgpu_vm_bo_evicted(base);
327 * amdgpu_vm_pt_parent - get the parent page directory
329 * @pt: child page table
331 * Helper to get the parent entry for the child page table. NULL if we are at
332 * the root page directory.
334 static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt)
336 struct amdgpu_bo *parent = pt->base.bo->parent;
341 return container_of(parent->vm_bo, struct amdgpu_vm_pt, base);
345 * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt
347 struct amdgpu_vm_pt_cursor {
349 struct amdgpu_vm_pt *parent;
350 struct amdgpu_vm_pt *entry;
355 * amdgpu_vm_pt_start - start PD/PT walk
357 * @adev: amdgpu_device pointer
358 * @vm: amdgpu_vm structure
359 * @start: start address of the walk
360 * @cursor: state to initialize
362 * Initialize a amdgpu_vm_pt_cursor to start a walk.
364 static void amdgpu_vm_pt_start(struct amdgpu_device *adev,
365 struct amdgpu_vm *vm, uint64_t start,
366 struct amdgpu_vm_pt_cursor *cursor)
369 cursor->parent = NULL;
370 cursor->entry = &vm->root;
371 cursor->level = adev->vm_manager.root_level;
375 * amdgpu_vm_pt_descendant - go to child node
377 * @adev: amdgpu_device pointer
378 * @cursor: current state
380 * Walk to the child node of the current node.
382 * True if the walk was possible, false otherwise.
384 static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,
385 struct amdgpu_vm_pt_cursor *cursor)
387 unsigned mask, shift, idx;
389 if (!cursor->entry->entries)
392 BUG_ON(!cursor->entry->base.bo);
393 mask = amdgpu_vm_entries_mask(adev, cursor->level);
394 shift = amdgpu_vm_level_shift(adev, cursor->level);
397 idx = (cursor->pfn >> shift) & mask;
398 cursor->parent = cursor->entry;
399 cursor->entry = &cursor->entry->entries[idx];
404 * amdgpu_vm_pt_sibling - go to sibling node
406 * @adev: amdgpu_device pointer
407 * @cursor: current state
409 * Walk to the sibling node of the current node.
411 * True if the walk was possible, false otherwise.
413 static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev,
414 struct amdgpu_vm_pt_cursor *cursor)
416 unsigned shift, num_entries;
418 /* Root doesn't have a sibling */
422 /* Go to our parents and see if we got a sibling */
423 shift = amdgpu_vm_level_shift(adev, cursor->level - 1);
424 num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1);
426 if (cursor->entry == &cursor->parent->entries[num_entries - 1])
429 cursor->pfn += 1ULL << shift;
430 cursor->pfn &= ~((1ULL << shift) - 1);
436 * amdgpu_vm_pt_ancestor - go to parent node
438 * @cursor: current state
440 * Walk to the parent node of the current node.
442 * True if the walk was possible, false otherwise.
444 static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor)
450 cursor->entry = cursor->parent;
451 cursor->parent = amdgpu_vm_pt_parent(cursor->parent);
456 * amdgpu_vm_pt_next - get next PD/PT in hieratchy
458 * @adev: amdgpu_device pointer
459 * @cursor: current state
461 * Walk the PD/PT tree to the next node.
463 static void amdgpu_vm_pt_next(struct amdgpu_device *adev,
464 struct amdgpu_vm_pt_cursor *cursor)
466 /* First try a newborn child */
467 if (amdgpu_vm_pt_descendant(adev, cursor))
470 /* If that didn't worked try to find a sibling */
471 while (!amdgpu_vm_pt_sibling(adev, cursor)) {
472 /* No sibling, go to our parents and grandparents */
473 if (!amdgpu_vm_pt_ancestor(cursor)) {
481 * amdgpu_vm_pt_first_dfs - start a deep first search
483 * @adev: amdgpu_device structure
484 * @vm: amdgpu_vm structure
485 * @cursor: state to initialize
487 * Starts a deep first traversal of the PD/PT tree.
489 static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev,
490 struct amdgpu_vm *vm,
491 struct amdgpu_vm_pt_cursor *start,
492 struct amdgpu_vm_pt_cursor *cursor)
497 amdgpu_vm_pt_start(adev, vm, 0, cursor);
498 while (amdgpu_vm_pt_descendant(adev, cursor));
502 * amdgpu_vm_pt_continue_dfs - check if the deep first search should continue
504 * @start: starting point for the search
505 * @entry: current entry
508 * True when the search should continue, false otherwise.
510 static bool amdgpu_vm_pt_continue_dfs(struct amdgpu_vm_pt_cursor *start,
511 struct amdgpu_vm_pt *entry)
513 return entry && (!start || entry != start->entry);
517 * amdgpu_vm_pt_next_dfs - get the next node for a deep first search
519 * @adev: amdgpu_device structure
520 * @cursor: current state
522 * Move the cursor to the next node in a deep first search.
524 static void amdgpu_vm_pt_next_dfs(struct amdgpu_device *adev,
525 struct amdgpu_vm_pt_cursor *cursor)
531 cursor->entry = NULL;
532 else if (amdgpu_vm_pt_sibling(adev, cursor))
533 while (amdgpu_vm_pt_descendant(adev, cursor));
535 amdgpu_vm_pt_ancestor(cursor);
539 * for_each_amdgpu_vm_pt_dfs_safe - safe deep first search of all PDs/PTs
541 #define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) \
542 for (amdgpu_vm_pt_first_dfs((adev), (vm), (start), &(cursor)), \
543 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor));\
544 amdgpu_vm_pt_continue_dfs((start), (entry)); \
545 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor)))
548 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
550 * @vm: vm providing the BOs
551 * @validated: head of validation list
552 * @entry: entry to add
554 * Add the page directory to the list of BOs to
555 * validate for command submission.
557 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
558 struct list_head *validated,
559 struct amdgpu_bo_list_entry *entry)
562 entry->tv.bo = &vm->root.base.bo->tbo;
563 /* One for the VM updates, one for TTM and one for the CS job */
564 entry->tv.num_shared = 3;
565 entry->user_pages = NULL;
566 list_add(&entry->tv.head, validated);
569 void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo)
571 struct amdgpu_bo *abo;
572 struct amdgpu_vm_bo_base *bo_base;
574 if (!amdgpu_bo_is_amdgpu_bo(bo))
577 if (bo->mem.placement & TTM_PL_FLAG_NO_EVICT)
580 abo = ttm_to_amdgpu_bo(bo);
583 for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) {
584 struct amdgpu_vm *vm = bo_base->vm;
586 if (abo->tbo.resv == vm->root.base.bo->tbo.resv)
587 vm->bulk_moveable = false;
592 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
594 * @adev: amdgpu device pointer
595 * @vm: vm providing the BOs
597 * Move all BOs to the end of LRU and remember their positions to put them
600 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
601 struct amdgpu_vm *vm)
603 struct ttm_bo_global *glob = adev->mman.bdev.glob;
604 struct amdgpu_vm_bo_base *bo_base;
606 if (vm->bulk_moveable) {
607 spin_lock(&glob->lru_lock);
608 ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
609 spin_unlock(&glob->lru_lock);
613 memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));
615 spin_lock(&glob->lru_lock);
616 list_for_each_entry(bo_base, &vm->idle, vm_status) {
617 struct amdgpu_bo *bo = bo_base->bo;
622 ttm_bo_move_to_lru_tail(&bo->tbo, &vm->lru_bulk_move);
624 ttm_bo_move_to_lru_tail(&bo->shadow->tbo,
627 spin_unlock(&glob->lru_lock);
629 vm->bulk_moveable = true;
633 * amdgpu_vm_validate_pt_bos - validate the page table BOs
635 * @adev: amdgpu device pointer
636 * @vm: vm providing the BOs
637 * @validate: callback to do the validation
638 * @param: parameter for the validation callback
640 * Validate the page table BOs on command submission if neccessary.
645 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
646 int (*validate)(void *p, struct amdgpu_bo *bo),
649 struct amdgpu_vm_bo_base *bo_base, *tmp;
652 list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
653 struct amdgpu_bo *bo = bo_base->bo;
655 r = validate(param, bo);
659 if (bo->tbo.type != ttm_bo_type_kernel) {
660 amdgpu_vm_bo_moved(bo_base);
662 vm->update_funcs->map_table(bo);
664 amdgpu_vm_bo_relocated(bo_base);
666 amdgpu_vm_bo_idle(bo_base);
674 * amdgpu_vm_ready - check VM is ready for updates
678 * Check if all VM PDs/PTs are ready for updates
681 * True if eviction list is empty.
683 bool amdgpu_vm_ready(struct amdgpu_vm *vm)
685 return list_empty(&vm->evicted);
689 * amdgpu_vm_clear_bo - initially clear the PDs/PTs
691 * @adev: amdgpu_device pointer
692 * @vm: VM to clear BO from
695 * Root PD needs to be reserved when calling this.
698 * 0 on success, errno otherwise.
700 static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
701 struct amdgpu_vm *vm,
702 struct amdgpu_bo *bo)
704 struct ttm_operation_ctx ctx = { true, false };
705 unsigned level = adev->vm_manager.root_level;
706 struct amdgpu_vm_update_params params;
707 struct amdgpu_bo *ancestor = bo;
708 unsigned entries, ats_entries;
712 /* Figure out our place in the hierarchy */
713 if (ancestor->parent) {
715 while (ancestor->parent->parent) {
717 ancestor = ancestor->parent;
721 entries = amdgpu_bo_size(bo) / 8;
722 if (!vm->pte_support_ats) {
725 } else if (!bo->parent) {
726 ats_entries = amdgpu_vm_num_ats_entries(adev);
727 ats_entries = min(ats_entries, entries);
728 entries -= ats_entries;
731 struct amdgpu_vm_pt *pt;
733 pt = container_of(ancestor->vm_bo, struct amdgpu_vm_pt, base);
734 ats_entries = amdgpu_vm_num_ats_entries(adev);
735 if ((pt - vm->root.entries) >= ats_entries) {
738 ats_entries = entries;
743 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
748 r = ttm_bo_validate(&bo->shadow->tbo, &bo->shadow->placement,
754 r = vm->update_funcs->map_table(bo);
758 memset(¶ms, 0, sizeof(params));
762 r = vm->update_funcs->prepare(¶ms, AMDGPU_FENCE_OWNER_KFD, NULL);
770 ats_value = AMDGPU_PTE_DEFAULT_ATC;
771 if (level != AMDGPU_VM_PTB)
772 ats_value |= AMDGPU_PDE_PTE;
774 r = vm->update_funcs->update(¶ms, bo, addr, 0, ats_entries,
779 addr += ats_entries * 8;
785 /* Workaround for fault priority problem on GMC9 */
786 if (level == AMDGPU_VM_PTB &&
787 adev->asic_type >= CHIP_VEGA10)
788 value = AMDGPU_PTE_EXECUTABLE;
790 r = vm->update_funcs->update(¶ms, bo, addr, 0, entries,
796 return vm->update_funcs->commit(¶ms, NULL);
800 * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation
802 * @adev: amdgpu_device pointer
804 * @bp: resulting BO allocation parameters
806 static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
807 int level, struct amdgpu_bo_param *bp)
809 memset(bp, 0, sizeof(*bp));
811 bp->size = amdgpu_vm_bo_size(adev, level);
812 bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
813 bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
814 bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
815 bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
816 AMDGPU_GEM_CREATE_CPU_GTT_USWC;
817 if (vm->use_cpu_for_update)
818 bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
819 else if (!vm->root.base.bo || vm->root.base.bo->shadow)
820 bp->flags |= AMDGPU_GEM_CREATE_SHADOW;
821 bp->type = ttm_bo_type_kernel;
822 if (vm->root.base.bo)
823 bp->resv = vm->root.base.bo->tbo.resv;
827 * amdgpu_vm_alloc_pts - Allocate a specific page table
829 * @adev: amdgpu_device pointer
830 * @vm: VM to allocate page tables for
831 * @cursor: Which page table to allocate
833 * Make sure a specific page table or directory is allocated.
836 * 1 if page table needed to be allocated, 0 if page table was already
837 * allocated, negative errno if an error occurred.
839 static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
840 struct amdgpu_vm *vm,
841 struct amdgpu_vm_pt_cursor *cursor)
843 struct amdgpu_vm_pt *entry = cursor->entry;
844 struct amdgpu_bo_param bp;
845 struct amdgpu_bo *pt;
848 if (cursor->level < AMDGPU_VM_PTB && !entry->entries) {
849 unsigned num_entries;
851 num_entries = amdgpu_vm_num_entries(adev, cursor->level);
852 entry->entries = kvmalloc_array(num_entries,
853 sizeof(*entry->entries),
854 GFP_KERNEL | __GFP_ZERO);
862 amdgpu_vm_bo_param(adev, vm, cursor->level, &bp);
864 r = amdgpu_bo_create(adev, &bp, &pt);
868 /* Keep a reference to the root directory to avoid
869 * freeing them up in the wrong order.
871 pt->parent = amdgpu_bo_ref(cursor->parent->base.bo);
872 amdgpu_vm_bo_base_init(&entry->base, vm, pt);
874 r = amdgpu_vm_clear_bo(adev, vm, pt);
881 amdgpu_bo_unref(&pt->shadow);
882 amdgpu_bo_unref(&pt);
887 * amdgpu_vm_free_table - fre one PD/PT
889 * @entry: PDE to free
891 static void amdgpu_vm_free_table(struct amdgpu_vm_pt *entry)
893 if (entry->base.bo) {
894 entry->base.bo->vm_bo = NULL;
895 list_del(&entry->base.vm_status);
896 amdgpu_bo_unref(&entry->base.bo->shadow);
897 amdgpu_bo_unref(&entry->base.bo);
899 kvfree(entry->entries);
900 entry->entries = NULL;
904 * amdgpu_vm_free_pts - free PD/PT levels
906 * @adev: amdgpu device structure
907 * @vm: amdgpu vm structure
908 * @start: optional cursor where to start freeing PDs/PTs
910 * Free the page directory or page table level and all sub levels.
912 static void amdgpu_vm_free_pts(struct amdgpu_device *adev,
913 struct amdgpu_vm *vm,
914 struct amdgpu_vm_pt_cursor *start)
916 struct amdgpu_vm_pt_cursor cursor;
917 struct amdgpu_vm_pt *entry;
919 vm->bulk_moveable = false;
921 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)
922 amdgpu_vm_free_table(entry);
925 amdgpu_vm_free_table(start->entry);
929 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
931 * @adev: amdgpu_device pointer
933 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
935 const struct amdgpu_ip_block *ip_block;
936 bool has_compute_vm_bug;
937 struct amdgpu_ring *ring;
940 has_compute_vm_bug = false;
942 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
944 /* Compute has a VM bug for GFX version < 7.
945 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
946 if (ip_block->version->major <= 7)
947 has_compute_vm_bug = true;
948 else if (ip_block->version->major == 8)
949 if (adev->gfx.mec_fw_version < 673)
950 has_compute_vm_bug = true;
953 for (i = 0; i < adev->num_rings; i++) {
954 ring = adev->rings[i];
955 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
956 /* only compute rings */
957 ring->has_compute_vm_bug = has_compute_vm_bug;
959 ring->has_compute_vm_bug = false;
964 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
966 * @ring: ring on which the job will be submitted
967 * @job: job to submit
970 * True if sync is needed.
972 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
973 struct amdgpu_job *job)
975 struct amdgpu_device *adev = ring->adev;
976 unsigned vmhub = ring->funcs->vmhub;
977 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
978 struct amdgpu_vmid *id;
979 bool gds_switch_needed;
980 bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
984 id = &id_mgr->ids[job->vmid];
985 gds_switch_needed = ring->funcs->emit_gds_switch && (
986 id->gds_base != job->gds_base ||
987 id->gds_size != job->gds_size ||
988 id->gws_base != job->gws_base ||
989 id->gws_size != job->gws_size ||
990 id->oa_base != job->oa_base ||
991 id->oa_size != job->oa_size);
993 if (amdgpu_vmid_had_gpu_reset(adev, id))
996 return vm_flush_needed || gds_switch_needed;
1000 * amdgpu_vm_flush - hardware flush the vm
1002 * @ring: ring to use for flush
1004 * @need_pipe_sync: is pipe sync needed
1006 * Emit a VM flush when it is necessary.
1009 * 0 on success, errno otherwise.
1011 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync)
1013 struct amdgpu_device *adev = ring->adev;
1014 unsigned vmhub = ring->funcs->vmhub;
1015 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1016 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
1017 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
1018 id->gds_base != job->gds_base ||
1019 id->gds_size != job->gds_size ||
1020 id->gws_base != job->gws_base ||
1021 id->gws_size != job->gws_size ||
1022 id->oa_base != job->oa_base ||
1023 id->oa_size != job->oa_size);
1024 bool vm_flush_needed = job->vm_needs_flush;
1025 bool pasid_mapping_needed = id->pasid != job->pasid ||
1026 !id->pasid_mapping ||
1027 !dma_fence_is_signaled(id->pasid_mapping);
1028 struct dma_fence *fence = NULL;
1029 unsigned patch_offset = 0;
1032 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
1033 gds_switch_needed = true;
1034 vm_flush_needed = true;
1035 pasid_mapping_needed = true;
1038 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
1039 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
1040 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
1041 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
1042 ring->funcs->emit_wreg;
1044 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
1047 if (ring->funcs->init_cond_exec)
1048 patch_offset = amdgpu_ring_init_cond_exec(ring);
1051 amdgpu_ring_emit_pipeline_sync(ring);
1053 if (vm_flush_needed) {
1054 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
1055 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
1058 if (pasid_mapping_needed)
1059 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
1061 if (vm_flush_needed || pasid_mapping_needed) {
1062 r = amdgpu_fence_emit(ring, &fence, 0);
1067 if (vm_flush_needed) {
1068 mutex_lock(&id_mgr->lock);
1069 dma_fence_put(id->last_flush);
1070 id->last_flush = dma_fence_get(fence);
1071 id->current_gpu_reset_count =
1072 atomic_read(&adev->gpu_reset_counter);
1073 mutex_unlock(&id_mgr->lock);
1076 if (pasid_mapping_needed) {
1077 id->pasid = job->pasid;
1078 dma_fence_put(id->pasid_mapping);
1079 id->pasid_mapping = dma_fence_get(fence);
1081 dma_fence_put(fence);
1083 if (ring->funcs->emit_gds_switch && gds_switch_needed) {
1084 id->gds_base = job->gds_base;
1085 id->gds_size = job->gds_size;
1086 id->gws_base = job->gws_base;
1087 id->gws_size = job->gws_size;
1088 id->oa_base = job->oa_base;
1089 id->oa_size = job->oa_size;
1090 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
1091 job->gds_size, job->gws_base,
1092 job->gws_size, job->oa_base,
1096 if (ring->funcs->patch_cond_exec)
1097 amdgpu_ring_patch_cond_exec(ring, patch_offset);
1099 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
1100 if (ring->funcs->emit_switch_buffer) {
1101 amdgpu_ring_emit_switch_buffer(ring);
1102 amdgpu_ring_emit_switch_buffer(ring);
1108 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
1111 * @bo: requested buffer object
1113 * Find @bo inside the requested vm.
1114 * Search inside the @bos vm list for the requested vm
1115 * Returns the found bo_va or NULL if none is found
1117 * Object has to be reserved!
1120 * Found bo_va or NULL.
1122 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
1123 struct amdgpu_bo *bo)
1125 struct amdgpu_vm_bo_base *base;
1127 for (base = bo->vm_bo; base; base = base->next) {
1131 return container_of(base, struct amdgpu_bo_va, base);
1137 * amdgpu_vm_map_gart - Resolve gart mapping of addr
1139 * @pages_addr: optional DMA address to use for lookup
1140 * @addr: the unmapped addr
1142 * Look up the physical address of the page that the pte resolves
1146 * The pointer for the page table entry.
1148 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
1152 /* page table offset */
1153 result = pages_addr[addr >> PAGE_SHIFT];
1155 /* in case cpu page size != gpu page size*/
1156 result |= addr & (~PAGE_MASK);
1158 result &= 0xFFFFFFFFFFFFF000ULL;
1164 * amdgpu_vm_update_pde - update a single level in the hierarchy
1166 * @param: parameters for the update
1168 * @entry: entry to update
1170 * Makes sure the requested entry in parent is up to date.
1172 static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params,
1173 struct amdgpu_vm *vm,
1174 struct amdgpu_vm_pt *entry)
1176 struct amdgpu_vm_pt *parent = amdgpu_vm_pt_parent(entry);
1177 struct amdgpu_bo *bo = parent->base.bo, *pbo;
1178 uint64_t pde, pt, flags;
1181 for (level = 0, pbo = bo->parent; pbo; ++level)
1184 level += params->adev->vm_manager.root_level;
1185 amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags);
1186 pde = (entry - parent->entries) * 8;
1187 return vm->update_funcs->update(params, bo, pde, pt, 1, 0, flags);
1191 * amdgpu_vm_invalidate_pds - mark all PDs as invalid
1193 * @adev: amdgpu_device pointer
1196 * Mark all PD level as invalid after an error.
1198 static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev,
1199 struct amdgpu_vm *vm)
1201 struct amdgpu_vm_pt_cursor cursor;
1202 struct amdgpu_vm_pt *entry;
1204 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, NULL, cursor, entry)
1205 if (entry->base.bo && !entry->base.moved)
1206 amdgpu_vm_bo_relocated(&entry->base);
1210 * amdgpu_vm_update_directories - make sure that all directories are valid
1212 * @adev: amdgpu_device pointer
1215 * Makes sure all directories are up to date.
1218 * 0 for success, error for failure.
1220 int amdgpu_vm_update_directories(struct amdgpu_device *adev,
1221 struct amdgpu_vm *vm)
1223 struct amdgpu_vm_update_params params;
1226 if (list_empty(&vm->relocated))
1229 memset(¶ms, 0, sizeof(params));
1233 r = vm->update_funcs->prepare(¶ms, AMDGPU_FENCE_OWNER_VM, NULL);
1237 while (!list_empty(&vm->relocated)) {
1238 struct amdgpu_vm_pt *entry;
1240 entry = list_first_entry(&vm->relocated, struct amdgpu_vm_pt,
1242 amdgpu_vm_bo_idle(&entry->base);
1244 r = amdgpu_vm_update_pde(¶ms, vm, entry);
1249 r = vm->update_funcs->commit(¶ms, &vm->last_update);
1255 amdgpu_vm_invalidate_pds(adev, vm);
1260 * amdgpu_vm_update_flags - figure out flags for PTE updates
1262 * Make sure to set the right flags for the PTEs at the desired level.
1264 static void amdgpu_vm_update_flags(struct amdgpu_vm_update_params *params,
1265 struct amdgpu_bo *bo, unsigned level,
1266 uint64_t pe, uint64_t addr,
1267 unsigned count, uint32_t incr,
1271 if (level != AMDGPU_VM_PTB) {
1272 flags |= AMDGPU_PDE_PTE;
1273 amdgpu_gmc_get_vm_pde(params->adev, level, &addr, &flags);
1275 } else if (params->adev->asic_type >= CHIP_VEGA10 &&
1276 !(flags & AMDGPU_PTE_VALID) &&
1277 !(flags & AMDGPU_PTE_PRT)) {
1279 /* Workaround for fault priority problem on GMC9 */
1280 flags |= AMDGPU_PTE_EXECUTABLE;
1283 params->vm->update_funcs->update(params, bo, pe, addr, count, incr,
1288 * amdgpu_vm_fragment - get fragment for PTEs
1290 * @params: see amdgpu_vm_update_params definition
1291 * @start: first PTE to handle
1292 * @end: last PTE to handle
1293 * @flags: hw mapping flags
1294 * @frag: resulting fragment size
1295 * @frag_end: end of this fragment
1297 * Returns the first possible fragment for the start and end address.
1299 static void amdgpu_vm_fragment(struct amdgpu_vm_update_params *params,
1300 uint64_t start, uint64_t end, uint64_t flags,
1301 unsigned int *frag, uint64_t *frag_end)
1304 * The MC L1 TLB supports variable sized pages, based on a fragment
1305 * field in the PTE. When this field is set to a non-zero value, page
1306 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1307 * flags are considered valid for all PTEs within the fragment range
1308 * and corresponding mappings are assumed to be physically contiguous.
1310 * The L1 TLB can store a single PTE for the whole fragment,
1311 * significantly increasing the space available for translation
1312 * caching. This leads to large improvements in throughput when the
1313 * TLB is under pressure.
1315 * The L2 TLB distributes small and large fragments into two
1316 * asymmetric partitions. The large fragment cache is significantly
1317 * larger. Thus, we try to use large fragments wherever possible.
1318 * Userspace can support this by aligning virtual base address and
1319 * allocation size to the fragment size.
1321 * Starting with Vega10 the fragment size only controls the L1. The L2
1322 * is now directly feed with small/huge/giant pages from the walker.
1326 if (params->adev->asic_type < CHIP_VEGA10)
1327 max_frag = params->adev->vm_manager.fragment_size;
1331 /* system pages are non continuously */
1332 if (params->pages_addr) {
1338 /* This intentionally wraps around if no bit is set */
1339 *frag = min((unsigned)ffs(start) - 1, (unsigned)fls64(end - start) - 1);
1340 if (*frag >= max_frag) {
1342 *frag_end = end & ~((1ULL << max_frag) - 1);
1344 *frag_end = start + (1 << *frag);
1349 * amdgpu_vm_update_ptes - make sure that page tables are valid
1351 * @params: see amdgpu_vm_update_params definition
1352 * @start: start of GPU address range
1353 * @end: end of GPU address range
1354 * @dst: destination address to map to, the next dst inside the function
1355 * @flags: mapping flags
1357 * Update the page tables in the range @start - @end.
1360 * 0 for success, -EINVAL for failure.
1362 static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
1363 uint64_t start, uint64_t end,
1364 uint64_t dst, uint64_t flags)
1366 struct amdgpu_device *adev = params->adev;
1367 struct amdgpu_vm_pt_cursor cursor;
1368 uint64_t frag_start = start, frag_end;
1372 /* figure out the initial fragment */
1373 amdgpu_vm_fragment(params, frag_start, end, flags, &frag, &frag_end);
1375 /* walk over the address space and update the PTs */
1376 amdgpu_vm_pt_start(adev, params->vm, start, &cursor);
1377 while (cursor.pfn < end) {
1378 unsigned shift, parent_shift, mask;
1379 uint64_t incr, entry_end, pe_start;
1380 struct amdgpu_bo *pt;
1382 r = amdgpu_vm_alloc_pts(params->adev, params->vm, &cursor);
1386 pt = cursor.entry->base.bo;
1388 /* The root level can't be a huge page */
1389 if (cursor.level == adev->vm_manager.root_level) {
1390 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1395 shift = amdgpu_vm_level_shift(adev, cursor.level);
1396 parent_shift = amdgpu_vm_level_shift(adev, cursor.level - 1);
1397 if (adev->asic_type < CHIP_VEGA10 &&
1398 (flags & AMDGPU_PTE_VALID)) {
1399 /* No huge page support before GMC v9 */
1400 if (cursor.level != AMDGPU_VM_PTB) {
1401 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1405 } else if (frag < shift) {
1406 /* We can't use this level when the fragment size is
1407 * smaller than the address shift. Go to the next
1408 * child entry and try again.
1410 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1413 } else if (frag >= parent_shift &&
1414 cursor.level - 1 != adev->vm_manager.root_level) {
1415 /* If the fragment size is even larger than the parent
1416 * shift we should go up one level and check it again
1417 * unless one level up is the root level.
1419 if (!amdgpu_vm_pt_ancestor(&cursor))
1424 /* Looks good so far, calculate parameters for the update */
1425 incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift;
1426 mask = amdgpu_vm_entries_mask(adev, cursor.level);
1427 pe_start = ((cursor.pfn >> shift) & mask) * 8;
1428 entry_end = (uint64_t)(mask + 1) << shift;
1429 entry_end += cursor.pfn & ~(entry_end - 1);
1430 entry_end = min(entry_end, end);
1433 uint64_t upd_end = min(entry_end, frag_end);
1434 unsigned nptes = (upd_end - frag_start) >> shift;
1436 amdgpu_vm_update_flags(params, pt, cursor.level,
1437 pe_start, dst, nptes, incr,
1438 flags | AMDGPU_PTE_FRAG(frag));
1440 pe_start += nptes * 8;
1441 dst += (uint64_t)nptes * AMDGPU_GPU_PAGE_SIZE << shift;
1443 frag_start = upd_end;
1444 if (frag_start >= frag_end) {
1445 /* figure out the next fragment */
1446 amdgpu_vm_fragment(params, frag_start, end,
1447 flags, &frag, &frag_end);
1451 } while (frag_start < entry_end);
1453 if (amdgpu_vm_pt_descendant(adev, &cursor)) {
1454 /* Free all child entries */
1455 while (cursor.pfn < frag_start) {
1456 amdgpu_vm_free_pts(adev, params->vm, &cursor);
1457 amdgpu_vm_pt_next(adev, &cursor);
1460 } else if (frag >= shift) {
1461 /* or just move on to the next on the same level. */
1462 amdgpu_vm_pt_next(adev, &cursor);
1470 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1472 * @adev: amdgpu_device pointer
1473 * @exclusive: fence we need to sync to
1474 * @pages_addr: DMA addresses to use for mapping
1476 * @start: start of mapped range
1477 * @last: last mapped entry
1478 * @flags: flags for the entries
1479 * @addr: addr to set the area to
1480 * @fence: optional resulting fence
1482 * Fill in the page table entries between @start and @last.
1485 * 0 for success, -EINVAL for failure.
1487 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1488 struct dma_fence *exclusive,
1489 dma_addr_t *pages_addr,
1490 struct amdgpu_vm *vm,
1491 uint64_t start, uint64_t last,
1492 uint64_t flags, uint64_t addr,
1493 struct dma_fence **fence)
1495 struct amdgpu_vm_update_params params;
1496 void *owner = AMDGPU_FENCE_OWNER_VM;
1499 memset(¶ms, 0, sizeof(params));
1502 params.pages_addr = pages_addr;
1504 /* sync to everything except eviction fences on unmapping */
1505 if (!(flags & AMDGPU_PTE_VALID))
1506 owner = AMDGPU_FENCE_OWNER_KFD;
1508 r = vm->update_funcs->prepare(¶ms, owner, exclusive);
1512 r = amdgpu_vm_update_ptes(¶ms, start, last + 1, addr, flags);
1516 return vm->update_funcs->commit(¶ms, fence);
1520 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
1522 * @adev: amdgpu_device pointer
1523 * @exclusive: fence we need to sync to
1524 * @pages_addr: DMA addresses to use for mapping
1526 * @mapping: mapped range and flags to use for the update
1527 * @flags: HW flags for the mapping
1528 * @bo_adev: amdgpu_device pointer that bo actually been allocated
1529 * @nodes: array of drm_mm_nodes with the MC addresses
1530 * @fence: optional resulting fence
1532 * Split the mapping into smaller chunks so that each update fits
1536 * 0 for success, -EINVAL for failure.
1538 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
1539 struct dma_fence *exclusive,
1540 dma_addr_t *pages_addr,
1541 struct amdgpu_vm *vm,
1542 struct amdgpu_bo_va_mapping *mapping,
1544 struct amdgpu_device *bo_adev,
1545 struct drm_mm_node *nodes,
1546 struct dma_fence **fence)
1548 unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size;
1549 uint64_t pfn, start = mapping->start;
1552 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1553 * but in case of something, we filter the flags in first place
1555 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1556 flags &= ~AMDGPU_PTE_READABLE;
1557 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1558 flags &= ~AMDGPU_PTE_WRITEABLE;
1560 flags &= ~AMDGPU_PTE_EXECUTABLE;
1561 flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1563 flags &= ~AMDGPU_PTE_MTYPE_MASK;
1564 flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK);
1566 if ((mapping->flags & AMDGPU_PTE_PRT) &&
1567 (adev->asic_type >= CHIP_VEGA10)) {
1568 flags |= AMDGPU_PTE_PRT;
1569 flags &= ~AMDGPU_PTE_VALID;
1572 trace_amdgpu_vm_bo_update(mapping);
1574 pfn = mapping->offset >> PAGE_SHIFT;
1576 while (pfn >= nodes->size) {
1583 dma_addr_t *dma_addr = NULL;
1584 uint64_t max_entries;
1585 uint64_t addr, last;
1588 addr = nodes->start << PAGE_SHIFT;
1589 max_entries = (nodes->size - pfn) *
1590 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1593 max_entries = S64_MAX;
1600 count < max_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1602 uint64_t idx = pfn + count;
1604 if (pages_addr[idx] !=
1605 (pages_addr[idx - 1] + PAGE_SIZE))
1609 if (count < min_linear_pages) {
1610 addr = pfn << PAGE_SHIFT;
1611 dma_addr = pages_addr;
1613 addr = pages_addr[pfn];
1614 max_entries = count * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1617 } else if (flags & AMDGPU_PTE_VALID) {
1618 addr += bo_adev->vm_manager.vram_base_offset;
1619 addr += pfn << PAGE_SHIFT;
1622 last = min((uint64_t)mapping->last, start + max_entries - 1);
1623 r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm,
1624 start, last, flags, addr,
1629 pfn += (last - start + 1) / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1630 if (nodes && nodes->size == pfn) {
1636 } while (unlikely(start != mapping->last + 1));
1642 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1644 * @adev: amdgpu_device pointer
1645 * @bo_va: requested BO and VM object
1646 * @clear: if true clear the entries
1648 * Fill in the page table entries for @bo_va.
1651 * 0 for success, -EINVAL for failure.
1653 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
1654 struct amdgpu_bo_va *bo_va,
1657 struct amdgpu_bo *bo = bo_va->base.bo;
1658 struct amdgpu_vm *vm = bo_va->base.vm;
1659 struct amdgpu_bo_va_mapping *mapping;
1660 dma_addr_t *pages_addr = NULL;
1661 struct ttm_mem_reg *mem;
1662 struct drm_mm_node *nodes;
1663 struct dma_fence *exclusive, **last_update;
1665 struct amdgpu_device *bo_adev = adev;
1673 struct ttm_dma_tt *ttm;
1676 nodes = mem->mm_node;
1677 if (mem->mem_type == TTM_PL_TT) {
1678 ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm);
1679 pages_addr = ttm->dma_address;
1681 exclusive = reservation_object_get_excl(bo->tbo.resv);
1685 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1686 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1691 if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
1692 last_update = &vm->last_update;
1694 last_update = &bo_va->last_pt_update;
1696 if (!clear && bo_va->base.moved) {
1697 bo_va->base.moved = false;
1698 list_splice_init(&bo_va->valids, &bo_va->invalids);
1700 } else if (bo_va->cleared != clear) {
1701 list_splice_init(&bo_va->valids, &bo_va->invalids);
1704 list_for_each_entry(mapping, &bo_va->invalids, list) {
1705 r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm,
1706 mapping, flags, bo_adev, nodes,
1712 if (vm->use_cpu_for_update) {
1715 amdgpu_asic_flush_hdp(adev, NULL);
1718 /* If the BO is not in its preferred location add it back to
1719 * the evicted list so that it gets validated again on the
1720 * next command submission.
1722 if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
1723 uint32_t mem_type = bo->tbo.mem.mem_type;
1725 if (!(bo->preferred_domains & amdgpu_mem_type_to_domain(mem_type)))
1726 amdgpu_vm_bo_evicted(&bo_va->base);
1728 amdgpu_vm_bo_idle(&bo_va->base);
1730 amdgpu_vm_bo_done(&bo_va->base);
1733 list_splice_init(&bo_va->invalids, &bo_va->valids);
1734 bo_va->cleared = clear;
1736 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1737 list_for_each_entry(mapping, &bo_va->valids, list)
1738 trace_amdgpu_vm_bo_mapping(mapping);
1745 * amdgpu_vm_update_prt_state - update the global PRT state
1747 * @adev: amdgpu_device pointer
1749 static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1751 unsigned long flags;
1754 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1755 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1756 adev->gmc.gmc_funcs->set_prt(adev, enable);
1757 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1761 * amdgpu_vm_prt_get - add a PRT user
1763 * @adev: amdgpu_device pointer
1765 static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1767 if (!adev->gmc.gmc_funcs->set_prt)
1770 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1771 amdgpu_vm_update_prt_state(adev);
1775 * amdgpu_vm_prt_put - drop a PRT user
1777 * @adev: amdgpu_device pointer
1779 static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1781 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1782 amdgpu_vm_update_prt_state(adev);
1786 * amdgpu_vm_prt_cb - callback for updating the PRT status
1788 * @fence: fence for the callback
1789 * @_cb: the callback function
1791 static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1793 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1795 amdgpu_vm_prt_put(cb->adev);
1800 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1802 * @adev: amdgpu_device pointer
1803 * @fence: fence for the callback
1805 static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1806 struct dma_fence *fence)
1808 struct amdgpu_prt_cb *cb;
1810 if (!adev->gmc.gmc_funcs->set_prt)
1813 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1815 /* Last resort when we are OOM */
1817 dma_fence_wait(fence, false);
1819 amdgpu_vm_prt_put(adev);
1822 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1824 amdgpu_vm_prt_cb(fence, &cb->cb);
1829 * amdgpu_vm_free_mapping - free a mapping
1831 * @adev: amdgpu_device pointer
1833 * @mapping: mapping to be freed
1834 * @fence: fence of the unmap operation
1836 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1838 static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1839 struct amdgpu_vm *vm,
1840 struct amdgpu_bo_va_mapping *mapping,
1841 struct dma_fence *fence)
1843 if (mapping->flags & AMDGPU_PTE_PRT)
1844 amdgpu_vm_add_prt_cb(adev, fence);
1849 * amdgpu_vm_prt_fini - finish all prt mappings
1851 * @adev: amdgpu_device pointer
1854 * Register a cleanup callback to disable PRT support after VM dies.
1856 static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1858 struct reservation_object *resv = vm->root.base.bo->tbo.resv;
1859 struct dma_fence *excl, **shared;
1860 unsigned i, shared_count;
1863 r = reservation_object_get_fences_rcu(resv, &excl,
1864 &shared_count, &shared);
1866 /* Not enough memory to grab the fence list, as last resort
1867 * block for all the fences to complete.
1869 reservation_object_wait_timeout_rcu(resv, true, false,
1870 MAX_SCHEDULE_TIMEOUT);
1874 /* Add a callback for each fence in the reservation object */
1875 amdgpu_vm_prt_get(adev);
1876 amdgpu_vm_add_prt_cb(adev, excl);
1878 for (i = 0; i < shared_count; ++i) {
1879 amdgpu_vm_prt_get(adev);
1880 amdgpu_vm_add_prt_cb(adev, shared[i]);
1887 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1889 * @adev: amdgpu_device pointer
1891 * @fence: optional resulting fence (unchanged if no work needed to be done
1892 * or if an error occurred)
1894 * Make sure all freed BOs are cleared in the PT.
1895 * PTs have to be reserved and mutex must be locked!
1901 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1902 struct amdgpu_vm *vm,
1903 struct dma_fence **fence)
1905 struct amdgpu_bo_va_mapping *mapping;
1906 uint64_t init_pte_value = 0;
1907 struct dma_fence *f = NULL;
1910 while (!list_empty(&vm->freed)) {
1911 mapping = list_first_entry(&vm->freed,
1912 struct amdgpu_bo_va_mapping, list);
1913 list_del(&mapping->list);
1915 if (vm->pte_support_ats &&
1916 mapping->start < AMDGPU_GMC_HOLE_START)
1917 init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
1919 r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm,
1920 mapping->start, mapping->last,
1921 init_pte_value, 0, &f);
1922 amdgpu_vm_free_mapping(adev, vm, mapping, f);
1930 dma_fence_put(*fence);
1941 * amdgpu_vm_handle_moved - handle moved BOs in the PT
1943 * @adev: amdgpu_device pointer
1946 * Make sure all BOs which are moved are updated in the PTs.
1951 * PTs have to be reserved!
1953 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
1954 struct amdgpu_vm *vm)
1956 struct amdgpu_bo_va *bo_va, *tmp;
1957 struct reservation_object *resv;
1961 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
1962 /* Per VM BOs never need to bo cleared in the page tables */
1963 r = amdgpu_vm_bo_update(adev, bo_va, false);
1968 spin_lock(&vm->invalidated_lock);
1969 while (!list_empty(&vm->invalidated)) {
1970 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
1972 resv = bo_va->base.bo->tbo.resv;
1973 spin_unlock(&vm->invalidated_lock);
1975 /* Try to reserve the BO to avoid clearing its ptes */
1976 if (!amdgpu_vm_debug && reservation_object_trylock(resv))
1978 /* Somebody else is using the BO right now */
1982 r = amdgpu_vm_bo_update(adev, bo_va, clear);
1987 reservation_object_unlock(resv);
1988 spin_lock(&vm->invalidated_lock);
1990 spin_unlock(&vm->invalidated_lock);
1996 * amdgpu_vm_bo_add - add a bo to a specific vm
1998 * @adev: amdgpu_device pointer
2000 * @bo: amdgpu buffer object
2002 * Add @bo into the requested vm.
2003 * Add @bo to the list of bos associated with the vm
2006 * Newly added bo_va or NULL for failure
2008 * Object has to be reserved!
2010 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2011 struct amdgpu_vm *vm,
2012 struct amdgpu_bo *bo)
2014 struct amdgpu_bo_va *bo_va;
2016 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
2017 if (bo_va == NULL) {
2020 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
2022 bo_va->ref_count = 1;
2023 INIT_LIST_HEAD(&bo_va->valids);
2024 INIT_LIST_HEAD(&bo_va->invalids);
2026 if (bo && amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev))) {
2027 bo_va->is_xgmi = true;
2028 mutex_lock(&adev->vm_manager.lock_pstate);
2029 /* Power up XGMI if it can be potentially used */
2030 if (++adev->vm_manager.xgmi_map_counter == 1)
2031 amdgpu_xgmi_set_pstate(adev, 1);
2032 mutex_unlock(&adev->vm_manager.lock_pstate);
2040 * amdgpu_vm_bo_insert_mapping - insert a new mapping
2042 * @adev: amdgpu_device pointer
2043 * @bo_va: bo_va to store the address
2044 * @mapping: the mapping to insert
2046 * Insert a new mapping into all structures.
2048 static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
2049 struct amdgpu_bo_va *bo_va,
2050 struct amdgpu_bo_va_mapping *mapping)
2052 struct amdgpu_vm *vm = bo_va->base.vm;
2053 struct amdgpu_bo *bo = bo_va->base.bo;
2055 mapping->bo_va = bo_va;
2056 list_add(&mapping->list, &bo_va->invalids);
2057 amdgpu_vm_it_insert(mapping, &vm->va);
2059 if (mapping->flags & AMDGPU_PTE_PRT)
2060 amdgpu_vm_prt_get(adev);
2062 if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv &&
2063 !bo_va->base.moved) {
2064 list_move(&bo_va->base.vm_status, &vm->moved);
2066 trace_amdgpu_vm_bo_map(bo_va, mapping);
2070 * amdgpu_vm_bo_map - map bo inside a vm
2072 * @adev: amdgpu_device pointer
2073 * @bo_va: bo_va to store the address
2074 * @saddr: where to map the BO
2075 * @offset: requested offset in the BO
2076 * @size: BO size in bytes
2077 * @flags: attributes of pages (read/write/valid/etc.)
2079 * Add a mapping of the BO at the specefied addr into the VM.
2082 * 0 for success, error for failure.
2084 * Object has to be reserved and unreserved outside!
2086 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2087 struct amdgpu_bo_va *bo_va,
2088 uint64_t saddr, uint64_t offset,
2089 uint64_t size, uint64_t flags)
2091 struct amdgpu_bo_va_mapping *mapping, *tmp;
2092 struct amdgpu_bo *bo = bo_va->base.bo;
2093 struct amdgpu_vm *vm = bo_va->base.vm;
2096 /* validate the parameters */
2097 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
2098 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
2101 /* make sure object fit at this offset */
2102 eaddr = saddr + size - 1;
2103 if (saddr >= eaddr ||
2104 (bo && offset + size > amdgpu_bo_size(bo)))
2107 saddr /= AMDGPU_GPU_PAGE_SIZE;
2108 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2110 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2112 /* bo and tmp overlap, invalid addr */
2113 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
2114 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
2115 tmp->start, tmp->last + 1);
2119 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2123 mapping->start = saddr;
2124 mapping->last = eaddr;
2125 mapping->offset = offset;
2126 mapping->flags = flags;
2128 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2134 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
2136 * @adev: amdgpu_device pointer
2137 * @bo_va: bo_va to store the address
2138 * @saddr: where to map the BO
2139 * @offset: requested offset in the BO
2140 * @size: BO size in bytes
2141 * @flags: attributes of pages (read/write/valid/etc.)
2143 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
2144 * mappings as we do so.
2147 * 0 for success, error for failure.
2149 * Object has to be reserved and unreserved outside!
2151 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
2152 struct amdgpu_bo_va *bo_va,
2153 uint64_t saddr, uint64_t offset,
2154 uint64_t size, uint64_t flags)
2156 struct amdgpu_bo_va_mapping *mapping;
2157 struct amdgpu_bo *bo = bo_va->base.bo;
2161 /* validate the parameters */
2162 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
2163 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
2166 /* make sure object fit at this offset */
2167 eaddr = saddr + size - 1;
2168 if (saddr >= eaddr ||
2169 (bo && offset + size > amdgpu_bo_size(bo)))
2172 /* Allocate all the needed memory */
2173 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2177 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
2183 saddr /= AMDGPU_GPU_PAGE_SIZE;
2184 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2186 mapping->start = saddr;
2187 mapping->last = eaddr;
2188 mapping->offset = offset;
2189 mapping->flags = flags;
2191 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2197 * amdgpu_vm_bo_unmap - remove bo mapping from vm
2199 * @adev: amdgpu_device pointer
2200 * @bo_va: bo_va to remove the address from
2201 * @saddr: where to the BO is mapped
2203 * Remove a mapping of the BO at the specefied addr from the VM.
2206 * 0 for success, error for failure.
2208 * Object has to be reserved and unreserved outside!
2210 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2211 struct amdgpu_bo_va *bo_va,
2214 struct amdgpu_bo_va_mapping *mapping;
2215 struct amdgpu_vm *vm = bo_va->base.vm;
2218 saddr /= AMDGPU_GPU_PAGE_SIZE;
2220 list_for_each_entry(mapping, &bo_va->valids, list) {
2221 if (mapping->start == saddr)
2225 if (&mapping->list == &bo_va->valids) {
2228 list_for_each_entry(mapping, &bo_va->invalids, list) {
2229 if (mapping->start == saddr)
2233 if (&mapping->list == &bo_va->invalids)
2237 list_del(&mapping->list);
2238 amdgpu_vm_it_remove(mapping, &vm->va);
2239 mapping->bo_va = NULL;
2240 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2243 list_add(&mapping->list, &vm->freed);
2245 amdgpu_vm_free_mapping(adev, vm, mapping,
2246 bo_va->last_pt_update);
2252 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
2254 * @adev: amdgpu_device pointer
2255 * @vm: VM structure to use
2256 * @saddr: start of the range
2257 * @size: size of the range
2259 * Remove all mappings in a range, split them as appropriate.
2262 * 0 for success, error for failure.
2264 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
2265 struct amdgpu_vm *vm,
2266 uint64_t saddr, uint64_t size)
2268 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
2272 eaddr = saddr + size - 1;
2273 saddr /= AMDGPU_GPU_PAGE_SIZE;
2274 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2276 /* Allocate all the needed memory */
2277 before = kzalloc(sizeof(*before), GFP_KERNEL);
2280 INIT_LIST_HEAD(&before->list);
2282 after = kzalloc(sizeof(*after), GFP_KERNEL);
2287 INIT_LIST_HEAD(&after->list);
2289 /* Now gather all removed mappings */
2290 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2292 /* Remember mapping split at the start */
2293 if (tmp->start < saddr) {
2294 before->start = tmp->start;
2295 before->last = saddr - 1;
2296 before->offset = tmp->offset;
2297 before->flags = tmp->flags;
2298 before->bo_va = tmp->bo_va;
2299 list_add(&before->list, &tmp->bo_va->invalids);
2302 /* Remember mapping split at the end */
2303 if (tmp->last > eaddr) {
2304 after->start = eaddr + 1;
2305 after->last = tmp->last;
2306 after->offset = tmp->offset;
2307 after->offset += after->start - tmp->start;
2308 after->flags = tmp->flags;
2309 after->bo_va = tmp->bo_va;
2310 list_add(&after->list, &tmp->bo_va->invalids);
2313 list_del(&tmp->list);
2314 list_add(&tmp->list, &removed);
2316 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
2319 /* And free them up */
2320 list_for_each_entry_safe(tmp, next, &removed, list) {
2321 amdgpu_vm_it_remove(tmp, &vm->va);
2322 list_del(&tmp->list);
2324 if (tmp->start < saddr)
2326 if (tmp->last > eaddr)
2330 list_add(&tmp->list, &vm->freed);
2331 trace_amdgpu_vm_bo_unmap(NULL, tmp);
2334 /* Insert partial mapping before the range */
2335 if (!list_empty(&before->list)) {
2336 amdgpu_vm_it_insert(before, &vm->va);
2337 if (before->flags & AMDGPU_PTE_PRT)
2338 amdgpu_vm_prt_get(adev);
2343 /* Insert partial mapping after the range */
2344 if (!list_empty(&after->list)) {
2345 amdgpu_vm_it_insert(after, &vm->va);
2346 if (after->flags & AMDGPU_PTE_PRT)
2347 amdgpu_vm_prt_get(adev);
2356 * amdgpu_vm_bo_lookup_mapping - find mapping by address
2358 * @vm: the requested VM
2359 * @addr: the address
2361 * Find a mapping by it's address.
2364 * The amdgpu_bo_va_mapping matching for addr or NULL
2367 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
2370 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
2374 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
2376 * @vm: the requested vm
2377 * @ticket: CS ticket
2379 * Trace all mappings of BOs reserved during a command submission.
2381 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
2383 struct amdgpu_bo_va_mapping *mapping;
2385 if (!trace_amdgpu_vm_bo_cs_enabled())
2388 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
2389 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
2390 if (mapping->bo_va && mapping->bo_va->base.bo) {
2391 struct amdgpu_bo *bo;
2393 bo = mapping->bo_va->base.bo;
2394 if (READ_ONCE(bo->tbo.resv->lock.ctx) != ticket)
2398 trace_amdgpu_vm_bo_cs(mapping);
2403 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2405 * @adev: amdgpu_device pointer
2406 * @bo_va: requested bo_va
2408 * Remove @bo_va->bo from the requested vm.
2410 * Object have to be reserved!
2412 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2413 struct amdgpu_bo_va *bo_va)
2415 struct amdgpu_bo_va_mapping *mapping, *next;
2416 struct amdgpu_bo *bo = bo_va->base.bo;
2417 struct amdgpu_vm *vm = bo_va->base.vm;
2418 struct amdgpu_vm_bo_base **base;
2421 if (bo->tbo.resv == vm->root.base.bo->tbo.resv)
2422 vm->bulk_moveable = false;
2424 for (base = &bo_va->base.bo->vm_bo; *base;
2425 base = &(*base)->next) {
2426 if (*base != &bo_va->base)
2429 *base = bo_va->base.next;
2434 spin_lock(&vm->invalidated_lock);
2435 list_del(&bo_va->base.vm_status);
2436 spin_unlock(&vm->invalidated_lock);
2438 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2439 list_del(&mapping->list);
2440 amdgpu_vm_it_remove(mapping, &vm->va);
2441 mapping->bo_va = NULL;
2442 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2443 list_add(&mapping->list, &vm->freed);
2445 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2446 list_del(&mapping->list);
2447 amdgpu_vm_it_remove(mapping, &vm->va);
2448 amdgpu_vm_free_mapping(adev, vm, mapping,
2449 bo_va->last_pt_update);
2452 dma_fence_put(bo_va->last_pt_update);
2454 if (bo && bo_va->is_xgmi) {
2455 mutex_lock(&adev->vm_manager.lock_pstate);
2456 if (--adev->vm_manager.xgmi_map_counter == 0)
2457 amdgpu_xgmi_set_pstate(adev, 0);
2458 mutex_unlock(&adev->vm_manager.lock_pstate);
2465 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2467 * @adev: amdgpu_device pointer
2468 * @bo: amdgpu buffer object
2469 * @evicted: is the BO evicted
2471 * Mark @bo as invalid.
2473 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2474 struct amdgpu_bo *bo, bool evicted)
2476 struct amdgpu_vm_bo_base *bo_base;
2478 /* shadow bo doesn't have bo base, its validation needs its parent */
2479 if (bo->parent && bo->parent->shadow == bo)
2482 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
2483 struct amdgpu_vm *vm = bo_base->vm;
2485 if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
2486 amdgpu_vm_bo_evicted(bo_base);
2492 bo_base->moved = true;
2494 if (bo->tbo.type == ttm_bo_type_kernel)
2495 amdgpu_vm_bo_relocated(bo_base);
2496 else if (bo->tbo.resv == vm->root.base.bo->tbo.resv)
2497 amdgpu_vm_bo_moved(bo_base);
2499 amdgpu_vm_bo_invalidated(bo_base);
2504 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2509 * VM page table as power of two
2511 static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2513 /* Total bits covered by PD + PTs */
2514 unsigned bits = ilog2(vm_size) + 18;
2516 /* Make sure the PD is 4K in size up to 8GB address space.
2517 Above that split equal between PD and PTs */
2521 return ((bits + 3) / 2);
2525 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2527 * @adev: amdgpu_device pointer
2528 * @min_vm_size: the minimum vm size in GB if it's set auto
2529 * @fragment_size_default: Default PTE fragment size
2530 * @max_level: max VMPT level
2531 * @max_bits: max address space size in bits
2534 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2535 uint32_t fragment_size_default, unsigned max_level,
2538 unsigned int max_size = 1 << (max_bits - 30);
2539 unsigned int vm_size;
2542 /* adjust vm size first */
2543 if (amdgpu_vm_size != -1) {
2544 vm_size = amdgpu_vm_size;
2545 if (vm_size > max_size) {
2546 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2547 amdgpu_vm_size, max_size);
2552 unsigned int phys_ram_gb;
2554 /* Optimal VM size depends on the amount of physical
2555 * RAM available. Underlying requirements and
2558 * - Need to map system memory and VRAM from all GPUs
2559 * - VRAM from other GPUs not known here
2560 * - Assume VRAM <= system memory
2561 * - On GFX8 and older, VM space can be segmented for
2563 * - Need to allow room for fragmentation, guard pages etc.
2565 * This adds up to a rough guess of system memory x3.
2566 * Round up to power of two to maximize the available
2567 * VM size with the given page table size.
2570 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2571 (1 << 30) - 1) >> 30;
2572 vm_size = roundup_pow_of_two(
2573 min(max(phys_ram_gb * 3, min_vm_size), max_size));
2576 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2578 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2579 if (amdgpu_vm_block_size != -1)
2580 tmp >>= amdgpu_vm_block_size - 9;
2581 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2582 adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
2583 switch (adev->vm_manager.num_level) {
2585 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2588 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2591 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2594 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2596 /* block size depends on vm size and hw setup*/
2597 if (amdgpu_vm_block_size != -1)
2598 adev->vm_manager.block_size =
2599 min((unsigned)amdgpu_vm_block_size, max_bits
2600 - AMDGPU_GPU_PAGE_SHIFT
2601 - 9 * adev->vm_manager.num_level);
2602 else if (adev->vm_manager.num_level > 1)
2603 adev->vm_manager.block_size = 9;
2605 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2607 if (amdgpu_vm_fragment_size == -1)
2608 adev->vm_manager.fragment_size = fragment_size_default;
2610 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2612 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2613 vm_size, adev->vm_manager.num_level + 1,
2614 adev->vm_manager.block_size,
2615 adev->vm_manager.fragment_size);
2619 * amdgpu_vm_wait_idle - wait for the VM to become idle
2621 * @vm: VM object to wait for
2622 * @timeout: timeout to wait for VM to become idle
2624 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2626 return reservation_object_wait_timeout_rcu(vm->root.base.bo->tbo.resv,
2627 true, true, timeout);
2631 * amdgpu_vm_init - initialize a vm instance
2633 * @adev: amdgpu_device pointer
2635 * @vm_context: Indicates if it GFX or Compute context
2636 * @pasid: Process address space identifier
2641 * 0 for success, error for failure.
2643 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2644 int vm_context, unsigned int pasid)
2646 struct amdgpu_bo_param bp;
2647 struct amdgpu_bo *root;
2650 vm->va = RB_ROOT_CACHED;
2651 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2652 vm->reserved_vmid[i] = NULL;
2653 INIT_LIST_HEAD(&vm->evicted);
2654 INIT_LIST_HEAD(&vm->relocated);
2655 INIT_LIST_HEAD(&vm->moved);
2656 INIT_LIST_HEAD(&vm->idle);
2657 INIT_LIST_HEAD(&vm->invalidated);
2658 spin_lock_init(&vm->invalidated_lock);
2659 INIT_LIST_HEAD(&vm->freed);
2661 /* create scheduler entity for page table updates */
2662 r = drm_sched_entity_init(&vm->entity, adev->vm_manager.vm_pte_rqs,
2663 adev->vm_manager.vm_pte_num_rqs, NULL);
2667 vm->pte_support_ats = false;
2669 if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) {
2670 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2671 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2673 if (adev->asic_type == CHIP_RAVEN)
2674 vm->pte_support_ats = true;
2676 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2677 AMDGPU_VM_USE_CPU_FOR_GFX);
2679 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2680 vm->use_cpu_for_update ? "CPU" : "SDMA");
2681 WARN_ONCE((vm->use_cpu_for_update && !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2682 "CPU update of VM recommended only for large BAR system\n");
2684 if (vm->use_cpu_for_update)
2685 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2687 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2688 vm->last_update = NULL;
2690 amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, &bp);
2691 if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE)
2692 bp.flags &= ~AMDGPU_GEM_CREATE_SHADOW;
2693 r = amdgpu_bo_create(adev, &bp, &root);
2695 goto error_free_sched_entity;
2697 r = amdgpu_bo_reserve(root, true);
2699 goto error_free_root;
2701 r = reservation_object_reserve_shared(root->tbo.resv, 1);
2703 goto error_unreserve;
2705 amdgpu_vm_bo_base_init(&vm->root.base, vm, root);
2707 r = amdgpu_vm_clear_bo(adev, vm, root);
2709 goto error_unreserve;
2711 amdgpu_bo_unreserve(vm->root.base.bo);
2714 unsigned long flags;
2716 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2717 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
2719 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2721 goto error_free_root;
2726 INIT_KFIFO(vm->faults);
2731 amdgpu_bo_unreserve(vm->root.base.bo);
2734 amdgpu_bo_unref(&vm->root.base.bo->shadow);
2735 amdgpu_bo_unref(&vm->root.base.bo);
2736 vm->root.base.bo = NULL;
2738 error_free_sched_entity:
2739 drm_sched_entity_destroy(&vm->entity);
2745 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
2747 * @adev: amdgpu_device pointer
2750 * This only works on GFX VMs that don't have any BOs added and no
2751 * page tables allocated yet.
2753 * Changes the following VM parameters:
2754 * - use_cpu_for_update
2755 * - pte_supports_ats
2756 * - pasid (old PASID is released, because compute manages its own PASIDs)
2758 * Reinitializes the page directory to reflect the changed ATS
2762 * 0 for success, -errno for errors.
2764 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid)
2766 bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
2769 r = amdgpu_bo_reserve(vm->root.base.bo, true);
2774 if (!RB_EMPTY_ROOT(&vm->va.rb_root) || vm->root.entries) {
2780 unsigned long flags;
2782 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2783 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
2785 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2792 /* Check if PD needs to be reinitialized and do it before
2793 * changing any other state, in case it fails.
2795 if (pte_support_ats != vm->pte_support_ats) {
2796 vm->pte_support_ats = pte_support_ats;
2797 r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo);
2802 /* Update VM state */
2803 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2804 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2805 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2806 vm->use_cpu_for_update ? "CPU" : "SDMA");
2807 WARN_ONCE((vm->use_cpu_for_update && !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2808 "CPU update of VM recommended only for large BAR system\n");
2811 unsigned long flags;
2813 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2814 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
2815 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2817 /* Free the original amdgpu allocated pasid
2818 * Will be replaced with kfd allocated pasid
2820 amdgpu_pasid_free(vm->pasid);
2824 /* Free the shadow bo for compute VM */
2825 amdgpu_bo_unref(&vm->root.base.bo->shadow);
2834 unsigned long flags;
2836 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2837 idr_remove(&adev->vm_manager.pasid_idr, pasid);
2838 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2841 amdgpu_bo_unreserve(vm->root.base.bo);
2846 * amdgpu_vm_release_compute - release a compute vm
2847 * @adev: amdgpu_device pointer
2848 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
2850 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
2851 * pasid from vm. Compute should stop use of vm after this call.
2853 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2856 unsigned long flags;
2858 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2859 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
2860 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2866 * amdgpu_vm_fini - tear down a vm instance
2868 * @adev: amdgpu_device pointer
2872 * Unbind the VM and remove all bos from the vm bo list
2874 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2876 struct amdgpu_bo_va_mapping *mapping, *tmp;
2877 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
2878 struct amdgpu_bo *root;
2881 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
2884 unsigned long flags;
2886 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2887 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
2888 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2891 drm_sched_entity_destroy(&vm->entity);
2893 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
2894 dev_err(adev->dev, "still active bo inside vm\n");
2896 rbtree_postorder_for_each_entry_safe(mapping, tmp,
2897 &vm->va.rb_root, rb) {
2898 /* Don't remove the mapping here, we don't want to trigger a
2899 * rebalance and the tree is about to be destroyed anyway.
2901 list_del(&mapping->list);
2904 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2905 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
2906 amdgpu_vm_prt_fini(adev, vm);
2907 prt_fini_needed = false;
2910 list_del(&mapping->list);
2911 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
2914 root = amdgpu_bo_ref(vm->root.base.bo);
2915 r = amdgpu_bo_reserve(root, true);
2917 dev_err(adev->dev, "Leaking page tables because BO reservation failed\n");
2919 amdgpu_vm_free_pts(adev, vm, NULL);
2920 amdgpu_bo_unreserve(root);
2922 amdgpu_bo_unref(&root);
2923 WARN_ON(vm->root.base.bo);
2924 dma_fence_put(vm->last_update);
2925 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2926 amdgpu_vmid_free_reserved(adev, vm, i);
2930 * amdgpu_vm_manager_init - init the VM manager
2932 * @adev: amdgpu_device pointer
2934 * Initialize the VM manager structures
2936 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
2940 amdgpu_vmid_mgr_init(adev);
2942 adev->vm_manager.fence_context =
2943 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2944 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2945 adev->vm_manager.seqno[i] = 0;
2947 spin_lock_init(&adev->vm_manager.prt_lock);
2948 atomic_set(&adev->vm_manager.num_prt_users, 0);
2950 /* If not overridden by the user, by default, only in large BAR systems
2951 * Compute VM tables will be updated by CPU
2953 #ifdef CONFIG_X86_64
2954 if (amdgpu_vm_update_mode == -1) {
2955 if (amdgpu_gmc_vram_full_visible(&adev->gmc))
2956 adev->vm_manager.vm_update_mode =
2957 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
2959 adev->vm_manager.vm_update_mode = 0;
2961 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
2963 adev->vm_manager.vm_update_mode = 0;
2966 idr_init(&adev->vm_manager.pasid_idr);
2967 spin_lock_init(&adev->vm_manager.pasid_lock);
2969 adev->vm_manager.xgmi_map_counter = 0;
2970 mutex_init(&adev->vm_manager.lock_pstate);
2974 * amdgpu_vm_manager_fini - cleanup VM manager
2976 * @adev: amdgpu_device pointer
2978 * Cleanup the VM manager and free resources.
2980 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
2982 WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr));
2983 idr_destroy(&adev->vm_manager.pasid_idr);
2985 amdgpu_vmid_mgr_fini(adev);
2989 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
2991 * @dev: drm device pointer
2992 * @data: drm_amdgpu_vm
2993 * @filp: drm file pointer
2996 * 0 for success, -errno for errors.
2998 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
3000 union drm_amdgpu_vm *args = data;
3001 struct amdgpu_device *adev = dev->dev_private;
3002 struct amdgpu_fpriv *fpriv = filp->driver_priv;
3005 switch (args->in.op) {
3006 case AMDGPU_VM_OP_RESERVE_VMID:
3007 /* current, we only have requirement to reserve vmid from gfxhub */
3008 r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
3012 case AMDGPU_VM_OP_UNRESERVE_VMID:
3013 amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
3023 * amdgpu_vm_get_task_info - Extracts task info for a PASID.
3025 * @adev: drm device pointer
3026 * @pasid: PASID identifier for VM
3027 * @task_info: task_info to fill.
3029 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid,
3030 struct amdgpu_task_info *task_info)
3032 struct amdgpu_vm *vm;
3033 unsigned long flags;
3035 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3037 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3039 *task_info = vm->task_info;
3041 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3045 * amdgpu_vm_set_task_info - Sets VMs task info.
3047 * @vm: vm for which to set the info
3049 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
3051 if (!vm->task_info.pid) {
3052 vm->task_info.pid = current->pid;
3053 get_task_comm(vm->task_info.task_name, current);
3055 if (current->group_leader->mm == current->mm) {
3056 vm->task_info.tgid = current->group_leader->pid;
3057 get_task_comm(vm->task_info.process_name, current->group_leader);