2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/dma-fence-array.h>
29 #include <linux/interval_tree_generic.h>
30 #include <linux/idr.h>
32 #include <drm/amdgpu_drm.h>
34 #include "amdgpu_trace.h"
35 #include "amdgpu_amdkfd.h"
36 #include "amdgpu_gmc.h"
37 #include "amdgpu_xgmi.h"
42 * GPUVM is similar to the legacy gart on older asics, however
43 * rather than there being a single global gart table
44 * for the entire GPU, there are multiple VM page tables active
45 * at any given time. The VM page tables can contain a mix
46 * vram pages and system memory pages and system memory pages
47 * can be mapped as snooped (cached system pages) or unsnooped
48 * (uncached system pages).
49 * Each VM has an ID associated with it and there is a page table
50 * associated with each VMID. When execting a command buffer,
51 * the kernel tells the the ring what VMID to use for that command
52 * buffer. VMIDs are allocated dynamically as commands are submitted.
53 * The userspace drivers maintain their own address space and the kernel
54 * sets up their pages tables accordingly when they submit their
55 * command buffers and a VMID is assigned.
56 * Cayman/Trinity support up to 8 active VMs at any given time;
60 #define START(node) ((node)->start)
61 #define LAST(node) ((node)->last)
63 INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
64 START, LAST, static, amdgpu_vm_it)
70 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
72 struct amdgpu_prt_cb {
75 * @adev: amdgpu device
77 struct amdgpu_device *adev;
82 struct dma_fence_cb cb;
86 * amdgpu_vm_level_shift - return the addr shift for each level
88 * @adev: amdgpu_device pointer
92 * The number of bits the pfn needs to be right shifted for a level.
94 static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
97 unsigned shift = 0xff;
103 shift = 9 * (AMDGPU_VM_PDB0 - level) +
104 adev->vm_manager.block_size;
110 dev_err(adev->dev, "the level%d isn't supported.\n", level);
117 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
119 * @adev: amdgpu_device pointer
123 * The number of entries in a page directory or page table.
125 static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
128 unsigned shift = amdgpu_vm_level_shift(adev,
129 adev->vm_manager.root_level);
131 if (level == adev->vm_manager.root_level)
132 /* For the root directory */
133 return round_up(adev->vm_manager.max_pfn, 1ULL << shift) >> shift;
134 else if (level != AMDGPU_VM_PTB)
135 /* Everything in between */
138 /* For the page tables on the leaves */
139 return AMDGPU_VM_PTE_COUNT(adev);
143 * amdgpu_vm_num_ats_entries - return the number of ATS entries in the root PD
145 * @adev: amdgpu_device pointer
148 * The number of entries in the root page directory which needs the ATS setting.
150 static unsigned amdgpu_vm_num_ats_entries(struct amdgpu_device *adev)
154 shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level);
155 return AMDGPU_GMC_HOLE_START >> (shift + AMDGPU_GPU_PAGE_SHIFT);
159 * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT
161 * @adev: amdgpu_device pointer
165 * The mask to extract the entry number of a PD/PT from an address.
167 static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
170 if (level <= adev->vm_manager.root_level)
172 else if (level != AMDGPU_VM_PTB)
175 return AMDGPU_VM_PTE_COUNT(adev) - 1;
179 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
181 * @adev: amdgpu_device pointer
185 * The size of the BO for a page directory or page table in bytes.
187 static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
189 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
193 * amdgpu_vm_bo_evicted - vm_bo is evicted
195 * @vm_bo: vm_bo which is evicted
197 * State for PDs/PTs and per VM BOs which are not at the location they should
200 static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
202 struct amdgpu_vm *vm = vm_bo->vm;
203 struct amdgpu_bo *bo = vm_bo->bo;
206 if (bo->tbo.type == ttm_bo_type_kernel)
207 list_move(&vm_bo->vm_status, &vm->evicted);
209 list_move_tail(&vm_bo->vm_status, &vm->evicted);
213 * amdgpu_vm_bo_relocated - vm_bo is reloacted
215 * @vm_bo: vm_bo which is relocated
217 * State for PDs/PTs which needs to update their parent PD.
219 static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
221 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
225 * amdgpu_vm_bo_moved - vm_bo is moved
227 * @vm_bo: vm_bo which is moved
229 * State for per VM BOs which are moved, but that change is not yet reflected
230 * in the page tables.
232 static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
234 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
238 * amdgpu_vm_bo_idle - vm_bo is idle
240 * @vm_bo: vm_bo which is now idle
242 * State for PDs/PTs and per VM BOs which have gone through the state machine
245 static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
247 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
248 vm_bo->moved = false;
252 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
254 * @vm_bo: vm_bo which is now invalidated
256 * State for normal BOs which are invalidated and that change not yet reflected
259 static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
261 spin_lock(&vm_bo->vm->invalidated_lock);
262 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
263 spin_unlock(&vm_bo->vm->invalidated_lock);
267 * amdgpu_vm_bo_done - vm_bo is done
269 * @vm_bo: vm_bo which is now done
271 * State for normal BOs which are invalidated and that change has been updated
274 static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
276 spin_lock(&vm_bo->vm->invalidated_lock);
277 list_del_init(&vm_bo->vm_status);
278 spin_unlock(&vm_bo->vm->invalidated_lock);
282 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
284 * @base: base structure for tracking BO usage in a VM
285 * @vm: vm to which bo is to be added
286 * @bo: amdgpu buffer object
288 * Initialize a bo_va_base structure and add it to the appropriate lists
291 static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
292 struct amdgpu_vm *vm,
293 struct amdgpu_bo *bo)
298 INIT_LIST_HEAD(&base->vm_status);
302 base->next = bo->vm_bo;
305 if (bo->tbo.resv != vm->root.base.bo->tbo.resv)
308 vm->bulk_moveable = false;
309 if (bo->tbo.type == ttm_bo_type_kernel)
310 amdgpu_vm_bo_relocated(base);
312 amdgpu_vm_bo_idle(base);
314 if (bo->preferred_domains &
315 amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type))
319 * we checked all the prerequisites, but it looks like this per vm bo
320 * is currently evicted. add the bo to the evicted list to make sure it
321 * is validated on next vm use to avoid fault.
323 amdgpu_vm_bo_evicted(base);
327 * amdgpu_vm_pt_parent - get the parent page directory
329 * @pt: child page table
331 * Helper to get the parent entry for the child page table. NULL if we are at
332 * the root page directory.
334 static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt)
336 struct amdgpu_bo *parent = pt->base.bo->parent;
341 return container_of(parent->vm_bo, struct amdgpu_vm_pt, base);
345 * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt
347 struct amdgpu_vm_pt_cursor {
349 struct amdgpu_vm_pt *parent;
350 struct amdgpu_vm_pt *entry;
355 * amdgpu_vm_pt_start - start PD/PT walk
357 * @adev: amdgpu_device pointer
358 * @vm: amdgpu_vm structure
359 * @start: start address of the walk
360 * @cursor: state to initialize
362 * Initialize a amdgpu_vm_pt_cursor to start a walk.
364 static void amdgpu_vm_pt_start(struct amdgpu_device *adev,
365 struct amdgpu_vm *vm, uint64_t start,
366 struct amdgpu_vm_pt_cursor *cursor)
369 cursor->parent = NULL;
370 cursor->entry = &vm->root;
371 cursor->level = adev->vm_manager.root_level;
375 * amdgpu_vm_pt_descendant - go to child node
377 * @adev: amdgpu_device pointer
378 * @cursor: current state
380 * Walk to the child node of the current node.
382 * True if the walk was possible, false otherwise.
384 static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,
385 struct amdgpu_vm_pt_cursor *cursor)
387 unsigned mask, shift, idx;
389 if (!cursor->entry->entries)
392 BUG_ON(!cursor->entry->base.bo);
393 mask = amdgpu_vm_entries_mask(adev, cursor->level);
394 shift = amdgpu_vm_level_shift(adev, cursor->level);
397 idx = (cursor->pfn >> shift) & mask;
398 cursor->parent = cursor->entry;
399 cursor->entry = &cursor->entry->entries[idx];
404 * amdgpu_vm_pt_sibling - go to sibling node
406 * @adev: amdgpu_device pointer
407 * @cursor: current state
409 * Walk to the sibling node of the current node.
411 * True if the walk was possible, false otherwise.
413 static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev,
414 struct amdgpu_vm_pt_cursor *cursor)
416 unsigned shift, num_entries;
418 /* Root doesn't have a sibling */
422 /* Go to our parents and see if we got a sibling */
423 shift = amdgpu_vm_level_shift(adev, cursor->level - 1);
424 num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1);
426 if (cursor->entry == &cursor->parent->entries[num_entries - 1])
429 cursor->pfn += 1ULL << shift;
430 cursor->pfn &= ~((1ULL << shift) - 1);
436 * amdgpu_vm_pt_ancestor - go to parent node
438 * @cursor: current state
440 * Walk to the parent node of the current node.
442 * True if the walk was possible, false otherwise.
444 static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor)
450 cursor->entry = cursor->parent;
451 cursor->parent = amdgpu_vm_pt_parent(cursor->parent);
456 * amdgpu_vm_pt_next - get next PD/PT in hieratchy
458 * @adev: amdgpu_device pointer
459 * @cursor: current state
461 * Walk the PD/PT tree to the next node.
463 static void amdgpu_vm_pt_next(struct amdgpu_device *adev,
464 struct amdgpu_vm_pt_cursor *cursor)
466 /* First try a newborn child */
467 if (amdgpu_vm_pt_descendant(adev, cursor))
470 /* If that didn't worked try to find a sibling */
471 while (!amdgpu_vm_pt_sibling(adev, cursor)) {
472 /* No sibling, go to our parents and grandparents */
473 if (!amdgpu_vm_pt_ancestor(cursor)) {
481 * amdgpu_vm_pt_first_dfs - start a deep first search
483 * @adev: amdgpu_device structure
484 * @vm: amdgpu_vm structure
485 * @cursor: state to initialize
487 * Starts a deep first traversal of the PD/PT tree.
489 static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev,
490 struct amdgpu_vm *vm,
491 struct amdgpu_vm_pt_cursor *start,
492 struct amdgpu_vm_pt_cursor *cursor)
497 amdgpu_vm_pt_start(adev, vm, 0, cursor);
498 while (amdgpu_vm_pt_descendant(adev, cursor));
502 * amdgpu_vm_pt_continue_dfs - check if the deep first search should continue
504 * @start: starting point for the search
505 * @entry: current entry
508 * True when the search should continue, false otherwise.
510 static bool amdgpu_vm_pt_continue_dfs(struct amdgpu_vm_pt_cursor *start,
511 struct amdgpu_vm_pt *entry)
513 return entry && (!start || entry != start->entry);
517 * amdgpu_vm_pt_next_dfs - get the next node for a deep first search
519 * @adev: amdgpu_device structure
520 * @cursor: current state
522 * Move the cursor to the next node in a deep first search.
524 static void amdgpu_vm_pt_next_dfs(struct amdgpu_device *adev,
525 struct amdgpu_vm_pt_cursor *cursor)
531 cursor->entry = NULL;
532 else if (amdgpu_vm_pt_sibling(adev, cursor))
533 while (amdgpu_vm_pt_descendant(adev, cursor));
535 amdgpu_vm_pt_ancestor(cursor);
539 * for_each_amdgpu_vm_pt_dfs_safe - safe deep first search of all PDs/PTs
541 #define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) \
542 for (amdgpu_vm_pt_first_dfs((adev), (vm), (start), &(cursor)), \
543 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor));\
544 amdgpu_vm_pt_continue_dfs((start), (entry)); \
545 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor)))
548 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
550 * @vm: vm providing the BOs
551 * @validated: head of validation list
552 * @entry: entry to add
554 * Add the page directory to the list of BOs to
555 * validate for command submission.
557 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
558 struct list_head *validated,
559 struct amdgpu_bo_list_entry *entry)
562 entry->tv.bo = &vm->root.base.bo->tbo;
563 /* One for the VM updates, one for TTM and one for the CS job */
564 entry->tv.num_shared = 3;
565 entry->user_pages = NULL;
566 list_add(&entry->tv.head, validated);
569 void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo)
571 struct amdgpu_bo *abo;
572 struct amdgpu_vm_bo_base *bo_base;
574 if (!amdgpu_bo_is_amdgpu_bo(bo))
577 if (bo->mem.placement & TTM_PL_FLAG_NO_EVICT)
580 abo = ttm_to_amdgpu_bo(bo);
583 for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) {
584 struct amdgpu_vm *vm = bo_base->vm;
586 if (abo->tbo.resv == vm->root.base.bo->tbo.resv)
587 vm->bulk_moveable = false;
592 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
594 * @adev: amdgpu device pointer
595 * @vm: vm providing the BOs
597 * Move all BOs to the end of LRU and remember their positions to put them
600 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
601 struct amdgpu_vm *vm)
603 struct ttm_bo_global *glob = adev->mman.bdev.glob;
604 struct amdgpu_vm_bo_base *bo_base;
606 if (vm->bulk_moveable) {
607 spin_lock(&glob->lru_lock);
608 ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
609 spin_unlock(&glob->lru_lock);
613 memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));
615 spin_lock(&glob->lru_lock);
616 list_for_each_entry(bo_base, &vm->idle, vm_status) {
617 struct amdgpu_bo *bo = bo_base->bo;
622 ttm_bo_move_to_lru_tail(&bo->tbo, &vm->lru_bulk_move);
624 ttm_bo_move_to_lru_tail(&bo->shadow->tbo,
627 spin_unlock(&glob->lru_lock);
629 vm->bulk_moveable = true;
633 * amdgpu_vm_validate_pt_bos - validate the page table BOs
635 * @adev: amdgpu device pointer
636 * @vm: vm providing the BOs
637 * @validate: callback to do the validation
638 * @param: parameter for the validation callback
640 * Validate the page table BOs on command submission if neccessary.
645 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
646 int (*validate)(void *p, struct amdgpu_bo *bo),
649 struct amdgpu_vm_bo_base *bo_base, *tmp;
652 list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
653 struct amdgpu_bo *bo = bo_base->bo;
655 r = validate(param, bo);
659 if (bo->tbo.type != ttm_bo_type_kernel) {
660 amdgpu_vm_bo_moved(bo_base);
662 if (vm->use_cpu_for_update)
663 r = amdgpu_bo_kmap(bo, NULL);
665 r = amdgpu_ttm_alloc_gart(&bo->tbo);
669 r = amdgpu_ttm_alloc_gart(&bo->shadow->tbo);
673 amdgpu_vm_bo_relocated(bo_base);
681 * amdgpu_vm_ready - check VM is ready for updates
685 * Check if all VM PDs/PTs are ready for updates
688 * True if eviction list is empty.
690 bool amdgpu_vm_ready(struct amdgpu_vm *vm)
692 return list_empty(&vm->evicted);
696 * amdgpu_vm_clear_bo - initially clear the PDs/PTs
698 * @adev: amdgpu_device pointer
699 * @vm: VM to clear BO from
702 * Root PD needs to be reserved when calling this.
705 * 0 on success, errno otherwise.
707 static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
708 struct amdgpu_vm *vm,
709 struct amdgpu_bo *bo)
711 struct ttm_operation_ctx ctx = { true, false };
712 unsigned level = adev->vm_manager.root_level;
713 struct amdgpu_vm_update_params params;
714 struct amdgpu_bo *ancestor = bo;
715 unsigned entries, ats_entries;
719 /* Figure out our place in the hierarchy */
720 if (ancestor->parent) {
722 while (ancestor->parent->parent) {
724 ancestor = ancestor->parent;
728 entries = amdgpu_bo_size(bo) / 8;
729 if (!vm->pte_support_ats) {
732 } else if (!bo->parent) {
733 ats_entries = amdgpu_vm_num_ats_entries(adev);
734 ats_entries = min(ats_entries, entries);
735 entries -= ats_entries;
738 struct amdgpu_vm_pt *pt;
740 pt = container_of(ancestor->vm_bo, struct amdgpu_vm_pt, base);
741 ats_entries = amdgpu_vm_num_ats_entries(adev);
742 if ((pt - vm->root.entries) >= ats_entries) {
745 ats_entries = entries;
750 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
754 r = amdgpu_ttm_alloc_gart(&bo->tbo);
759 r = ttm_bo_validate(&bo->shadow->tbo, &bo->shadow->placement,
764 r = amdgpu_ttm_alloc_gart(&bo->shadow->tbo);
770 memset(¶ms, 0, sizeof(params));
774 r = vm->update_funcs->prepare(¶ms, AMDGPU_FENCE_OWNER_KFD, NULL);
782 ats_value = AMDGPU_PTE_DEFAULT_ATC;
783 if (level != AMDGPU_VM_PTB)
784 ats_value |= AMDGPU_PDE_PTE;
786 r = vm->update_funcs->update(¶ms, bo, addr, 0, ats_entries,
791 addr += ats_entries * 8;
797 /* Workaround for fault priority problem on GMC9 */
798 if (level == AMDGPU_VM_PTB &&
799 adev->asic_type >= CHIP_VEGA10)
800 value = AMDGPU_PTE_EXECUTABLE;
802 r = vm->update_funcs->update(¶ms, bo, addr, 0, entries,
808 return vm->update_funcs->commit(¶ms, NULL);
812 * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation
814 * @adev: amdgpu_device pointer
816 * @bp: resulting BO allocation parameters
818 static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
819 int level, struct amdgpu_bo_param *bp)
821 memset(bp, 0, sizeof(*bp));
823 bp->size = amdgpu_vm_bo_size(adev, level);
824 bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
825 bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
826 bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
827 bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
828 AMDGPU_GEM_CREATE_CPU_GTT_USWC;
829 if (vm->use_cpu_for_update)
830 bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
831 else if (!vm->root.base.bo || vm->root.base.bo->shadow)
832 bp->flags |= AMDGPU_GEM_CREATE_SHADOW;
833 bp->type = ttm_bo_type_kernel;
834 if (vm->root.base.bo)
835 bp->resv = vm->root.base.bo->tbo.resv;
839 * amdgpu_vm_alloc_pts - Allocate a specific page table
841 * @adev: amdgpu_device pointer
842 * @vm: VM to allocate page tables for
843 * @cursor: Which page table to allocate
845 * Make sure a specific page table or directory is allocated.
848 * 1 if page table needed to be allocated, 0 if page table was already
849 * allocated, negative errno if an error occurred.
851 static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
852 struct amdgpu_vm *vm,
853 struct amdgpu_vm_pt_cursor *cursor)
855 struct amdgpu_vm_pt *entry = cursor->entry;
856 struct amdgpu_bo_param bp;
857 struct amdgpu_bo *pt;
860 if (cursor->level < AMDGPU_VM_PTB && !entry->entries) {
861 unsigned num_entries;
863 num_entries = amdgpu_vm_num_entries(adev, cursor->level);
864 entry->entries = kvmalloc_array(num_entries,
865 sizeof(*entry->entries),
866 GFP_KERNEL | __GFP_ZERO);
874 amdgpu_vm_bo_param(adev, vm, cursor->level, &bp);
876 r = amdgpu_bo_create(adev, &bp, &pt);
880 if (vm->use_cpu_for_update) {
881 r = amdgpu_bo_kmap(pt, NULL);
886 /* Keep a reference to the root directory to avoid
887 * freeing them up in the wrong order.
889 pt->parent = amdgpu_bo_ref(cursor->parent->base.bo);
890 amdgpu_vm_bo_base_init(&entry->base, vm, pt);
892 r = amdgpu_vm_clear_bo(adev, vm, pt);
899 amdgpu_bo_unref(&pt->shadow);
900 amdgpu_bo_unref(&pt);
905 * amdgpu_vm_free_table - fre one PD/PT
907 * @entry: PDE to free
909 static void amdgpu_vm_free_table(struct amdgpu_vm_pt *entry)
911 if (entry->base.bo) {
912 entry->base.bo->vm_bo = NULL;
913 list_del(&entry->base.vm_status);
914 amdgpu_bo_unref(&entry->base.bo->shadow);
915 amdgpu_bo_unref(&entry->base.bo);
917 kvfree(entry->entries);
918 entry->entries = NULL;
922 * amdgpu_vm_free_pts - free PD/PT levels
924 * @adev: amdgpu device structure
925 * @vm: amdgpu vm structure
926 * @start: optional cursor where to start freeing PDs/PTs
928 * Free the page directory or page table level and all sub levels.
930 static void amdgpu_vm_free_pts(struct amdgpu_device *adev,
931 struct amdgpu_vm *vm,
932 struct amdgpu_vm_pt_cursor *start)
934 struct amdgpu_vm_pt_cursor cursor;
935 struct amdgpu_vm_pt *entry;
937 vm->bulk_moveable = false;
939 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)
940 amdgpu_vm_free_table(entry);
943 amdgpu_vm_free_table(start->entry);
947 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
949 * @adev: amdgpu_device pointer
951 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
953 const struct amdgpu_ip_block *ip_block;
954 bool has_compute_vm_bug;
955 struct amdgpu_ring *ring;
958 has_compute_vm_bug = false;
960 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
962 /* Compute has a VM bug for GFX version < 7.
963 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
964 if (ip_block->version->major <= 7)
965 has_compute_vm_bug = true;
966 else if (ip_block->version->major == 8)
967 if (adev->gfx.mec_fw_version < 673)
968 has_compute_vm_bug = true;
971 for (i = 0; i < adev->num_rings; i++) {
972 ring = adev->rings[i];
973 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
974 /* only compute rings */
975 ring->has_compute_vm_bug = has_compute_vm_bug;
977 ring->has_compute_vm_bug = false;
982 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
984 * @ring: ring on which the job will be submitted
985 * @job: job to submit
988 * True if sync is needed.
990 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
991 struct amdgpu_job *job)
993 struct amdgpu_device *adev = ring->adev;
994 unsigned vmhub = ring->funcs->vmhub;
995 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
996 struct amdgpu_vmid *id;
997 bool gds_switch_needed;
998 bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
1002 id = &id_mgr->ids[job->vmid];
1003 gds_switch_needed = ring->funcs->emit_gds_switch && (
1004 id->gds_base != job->gds_base ||
1005 id->gds_size != job->gds_size ||
1006 id->gws_base != job->gws_base ||
1007 id->gws_size != job->gws_size ||
1008 id->oa_base != job->oa_base ||
1009 id->oa_size != job->oa_size);
1011 if (amdgpu_vmid_had_gpu_reset(adev, id))
1014 return vm_flush_needed || gds_switch_needed;
1018 * amdgpu_vm_flush - hardware flush the vm
1020 * @ring: ring to use for flush
1022 * @need_pipe_sync: is pipe sync needed
1024 * Emit a VM flush when it is necessary.
1027 * 0 on success, errno otherwise.
1029 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync)
1031 struct amdgpu_device *adev = ring->adev;
1032 unsigned vmhub = ring->funcs->vmhub;
1033 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1034 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
1035 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
1036 id->gds_base != job->gds_base ||
1037 id->gds_size != job->gds_size ||
1038 id->gws_base != job->gws_base ||
1039 id->gws_size != job->gws_size ||
1040 id->oa_base != job->oa_base ||
1041 id->oa_size != job->oa_size);
1042 bool vm_flush_needed = job->vm_needs_flush;
1043 bool pasid_mapping_needed = id->pasid != job->pasid ||
1044 !id->pasid_mapping ||
1045 !dma_fence_is_signaled(id->pasid_mapping);
1046 struct dma_fence *fence = NULL;
1047 unsigned patch_offset = 0;
1050 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
1051 gds_switch_needed = true;
1052 vm_flush_needed = true;
1053 pasid_mapping_needed = true;
1056 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
1057 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
1058 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
1059 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
1060 ring->funcs->emit_wreg;
1062 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
1065 if (ring->funcs->init_cond_exec)
1066 patch_offset = amdgpu_ring_init_cond_exec(ring);
1069 amdgpu_ring_emit_pipeline_sync(ring);
1071 if (vm_flush_needed) {
1072 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
1073 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
1076 if (pasid_mapping_needed)
1077 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
1079 if (vm_flush_needed || pasid_mapping_needed) {
1080 r = amdgpu_fence_emit(ring, &fence, 0);
1085 if (vm_flush_needed) {
1086 mutex_lock(&id_mgr->lock);
1087 dma_fence_put(id->last_flush);
1088 id->last_flush = dma_fence_get(fence);
1089 id->current_gpu_reset_count =
1090 atomic_read(&adev->gpu_reset_counter);
1091 mutex_unlock(&id_mgr->lock);
1094 if (pasid_mapping_needed) {
1095 id->pasid = job->pasid;
1096 dma_fence_put(id->pasid_mapping);
1097 id->pasid_mapping = dma_fence_get(fence);
1099 dma_fence_put(fence);
1101 if (ring->funcs->emit_gds_switch && gds_switch_needed) {
1102 id->gds_base = job->gds_base;
1103 id->gds_size = job->gds_size;
1104 id->gws_base = job->gws_base;
1105 id->gws_size = job->gws_size;
1106 id->oa_base = job->oa_base;
1107 id->oa_size = job->oa_size;
1108 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
1109 job->gds_size, job->gws_base,
1110 job->gws_size, job->oa_base,
1114 if (ring->funcs->patch_cond_exec)
1115 amdgpu_ring_patch_cond_exec(ring, patch_offset);
1117 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
1118 if (ring->funcs->emit_switch_buffer) {
1119 amdgpu_ring_emit_switch_buffer(ring);
1120 amdgpu_ring_emit_switch_buffer(ring);
1126 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
1129 * @bo: requested buffer object
1131 * Find @bo inside the requested vm.
1132 * Search inside the @bos vm list for the requested vm
1133 * Returns the found bo_va or NULL if none is found
1135 * Object has to be reserved!
1138 * Found bo_va or NULL.
1140 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
1141 struct amdgpu_bo *bo)
1143 struct amdgpu_vm_bo_base *base;
1145 for (base = bo->vm_bo; base; base = base->next) {
1149 return container_of(base, struct amdgpu_bo_va, base);
1155 * amdgpu_vm_map_gart - Resolve gart mapping of addr
1157 * @pages_addr: optional DMA address to use for lookup
1158 * @addr: the unmapped addr
1160 * Look up the physical address of the page that the pte resolves
1164 * The pointer for the page table entry.
1166 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
1170 /* page table offset */
1171 result = pages_addr[addr >> PAGE_SHIFT];
1173 /* in case cpu page size != gpu page size*/
1174 result |= addr & (~PAGE_MASK);
1176 result &= 0xFFFFFFFFFFFFF000ULL;
1182 * amdgpu_vm_update_pde - update a single level in the hierarchy
1184 * @param: parameters for the update
1186 * @parent: parent directory
1187 * @entry: entry to update
1189 * Makes sure the requested entry in parent is up to date.
1191 static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params,
1192 struct amdgpu_vm *vm,
1193 struct amdgpu_vm_pt *parent,
1194 struct amdgpu_vm_pt *entry)
1196 struct amdgpu_bo *bo = parent->base.bo, *pbo;
1197 uint64_t pde, pt, flags;
1200 for (level = 0, pbo = bo->parent; pbo; ++level)
1203 level += params->adev->vm_manager.root_level;
1204 amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags);
1205 pde = (entry - parent->entries) * 8;
1206 return vm->update_funcs->update(params, bo, pde, pt, 1, 0, flags);
1210 * amdgpu_vm_invalidate_pds - mark all PDs as invalid
1212 * @adev: amdgpu_device pointer
1215 * Mark all PD level as invalid after an error.
1217 static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev,
1218 struct amdgpu_vm *vm)
1220 struct amdgpu_vm_pt_cursor cursor;
1221 struct amdgpu_vm_pt *entry;
1223 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, NULL, cursor, entry)
1224 if (entry->base.bo && !entry->base.moved)
1225 amdgpu_vm_bo_relocated(&entry->base);
1229 * amdgpu_vm_update_directories - make sure that all directories are valid
1231 * @adev: amdgpu_device pointer
1234 * Makes sure all directories are up to date.
1237 * 0 for success, error for failure.
1239 int amdgpu_vm_update_directories(struct amdgpu_device *adev,
1240 struct amdgpu_vm *vm)
1242 struct amdgpu_vm_update_params params;
1245 if (list_empty(&vm->relocated))
1248 memset(¶ms, 0, sizeof(params));
1252 r = vm->update_funcs->prepare(¶ms, AMDGPU_FENCE_OWNER_VM, NULL);
1256 while (!list_empty(&vm->relocated)) {
1257 struct amdgpu_vm_pt *pt, *entry;
1259 entry = list_first_entry(&vm->relocated, struct amdgpu_vm_pt,
1261 amdgpu_vm_bo_idle(&entry->base);
1263 pt = amdgpu_vm_pt_parent(entry);
1267 r = amdgpu_vm_update_pde(¶ms, vm, pt, entry);
1272 r = vm->update_funcs->commit(¶ms, &vm->last_update);
1278 amdgpu_vm_invalidate_pds(adev, vm);
1283 * amdgpu_vm_update_flags - figure out flags for PTE updates
1285 * Make sure to set the right flags for the PTEs at the desired level.
1287 static void amdgpu_vm_update_flags(struct amdgpu_vm_update_params *params,
1288 struct amdgpu_bo *bo, unsigned level,
1289 uint64_t pe, uint64_t addr,
1290 unsigned count, uint32_t incr,
1294 if (level != AMDGPU_VM_PTB) {
1295 flags |= AMDGPU_PDE_PTE;
1296 amdgpu_gmc_get_vm_pde(params->adev, level, &addr, &flags);
1298 } else if (params->adev->asic_type >= CHIP_VEGA10 &&
1299 !(flags & AMDGPU_PTE_VALID) &&
1300 !(flags & AMDGPU_PTE_PRT)) {
1302 /* Workaround for fault priority problem on GMC9 */
1303 flags |= AMDGPU_PTE_EXECUTABLE;
1306 params->vm->update_funcs->update(params, bo, pe, addr, count, incr,
1311 * amdgpu_vm_fragment - get fragment for PTEs
1313 * @params: see amdgpu_vm_update_params definition
1314 * @start: first PTE to handle
1315 * @end: last PTE to handle
1316 * @flags: hw mapping flags
1317 * @frag: resulting fragment size
1318 * @frag_end: end of this fragment
1320 * Returns the first possible fragment for the start and end address.
1322 static void amdgpu_vm_fragment(struct amdgpu_vm_update_params *params,
1323 uint64_t start, uint64_t end, uint64_t flags,
1324 unsigned int *frag, uint64_t *frag_end)
1327 * The MC L1 TLB supports variable sized pages, based on a fragment
1328 * field in the PTE. When this field is set to a non-zero value, page
1329 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1330 * flags are considered valid for all PTEs within the fragment range
1331 * and corresponding mappings are assumed to be physically contiguous.
1333 * The L1 TLB can store a single PTE for the whole fragment,
1334 * significantly increasing the space available for translation
1335 * caching. This leads to large improvements in throughput when the
1336 * TLB is under pressure.
1338 * The L2 TLB distributes small and large fragments into two
1339 * asymmetric partitions. The large fragment cache is significantly
1340 * larger. Thus, we try to use large fragments wherever possible.
1341 * Userspace can support this by aligning virtual base address and
1342 * allocation size to the fragment size.
1344 * Starting with Vega10 the fragment size only controls the L1. The L2
1345 * is now directly feed with small/huge/giant pages from the walker.
1349 if (params->adev->asic_type < CHIP_VEGA10)
1350 max_frag = params->adev->vm_manager.fragment_size;
1354 /* system pages are non continuously */
1355 if (params->pages_addr) {
1361 /* This intentionally wraps around if no bit is set */
1362 *frag = min((unsigned)ffs(start) - 1, (unsigned)fls64(end - start) - 1);
1363 if (*frag >= max_frag) {
1365 *frag_end = end & ~((1ULL << max_frag) - 1);
1367 *frag_end = start + (1 << *frag);
1372 * amdgpu_vm_update_ptes - make sure that page tables are valid
1374 * @params: see amdgpu_vm_update_params definition
1375 * @start: start of GPU address range
1376 * @end: end of GPU address range
1377 * @dst: destination address to map to, the next dst inside the function
1378 * @flags: mapping flags
1380 * Update the page tables in the range @start - @end.
1383 * 0 for success, -EINVAL for failure.
1385 static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
1386 uint64_t start, uint64_t end,
1387 uint64_t dst, uint64_t flags)
1389 struct amdgpu_device *adev = params->adev;
1390 struct amdgpu_vm_pt_cursor cursor;
1391 uint64_t frag_start = start, frag_end;
1395 /* figure out the initial fragment */
1396 amdgpu_vm_fragment(params, frag_start, end, flags, &frag, &frag_end);
1398 /* walk over the address space and update the PTs */
1399 amdgpu_vm_pt_start(adev, params->vm, start, &cursor);
1400 while (cursor.pfn < end) {
1401 unsigned shift, parent_shift, mask;
1402 uint64_t incr, entry_end, pe_start;
1403 struct amdgpu_bo *pt;
1405 r = amdgpu_vm_alloc_pts(params->adev, params->vm, &cursor);
1409 pt = cursor.entry->base.bo;
1411 /* The root level can't be a huge page */
1412 if (cursor.level == adev->vm_manager.root_level) {
1413 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1418 shift = amdgpu_vm_level_shift(adev, cursor.level);
1419 parent_shift = amdgpu_vm_level_shift(adev, cursor.level - 1);
1420 if (adev->asic_type < CHIP_VEGA10 &&
1421 (flags & AMDGPU_PTE_VALID)) {
1422 /* No huge page support before GMC v9 */
1423 if (cursor.level != AMDGPU_VM_PTB) {
1424 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1428 } else if (frag < shift) {
1429 /* We can't use this level when the fragment size is
1430 * smaller than the address shift. Go to the next
1431 * child entry and try again.
1433 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1436 } else if (frag >= parent_shift &&
1437 cursor.level - 1 != adev->vm_manager.root_level) {
1438 /* If the fragment size is even larger than the parent
1439 * shift we should go up one level and check it again
1440 * unless one level up is the root level.
1442 if (!amdgpu_vm_pt_ancestor(&cursor))
1447 /* Looks good so far, calculate parameters for the update */
1448 incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift;
1449 mask = amdgpu_vm_entries_mask(adev, cursor.level);
1450 pe_start = ((cursor.pfn >> shift) & mask) * 8;
1451 entry_end = (uint64_t)(mask + 1) << shift;
1452 entry_end += cursor.pfn & ~(entry_end - 1);
1453 entry_end = min(entry_end, end);
1456 uint64_t upd_end = min(entry_end, frag_end);
1457 unsigned nptes = (upd_end - frag_start) >> shift;
1459 amdgpu_vm_update_flags(params, pt, cursor.level,
1460 pe_start, dst, nptes, incr,
1461 flags | AMDGPU_PTE_FRAG(frag));
1463 pe_start += nptes * 8;
1464 dst += (uint64_t)nptes * AMDGPU_GPU_PAGE_SIZE << shift;
1466 frag_start = upd_end;
1467 if (frag_start >= frag_end) {
1468 /* figure out the next fragment */
1469 amdgpu_vm_fragment(params, frag_start, end,
1470 flags, &frag, &frag_end);
1474 } while (frag_start < entry_end);
1476 if (amdgpu_vm_pt_descendant(adev, &cursor)) {
1477 /* Free all child entries */
1478 while (cursor.pfn < frag_start) {
1479 amdgpu_vm_free_pts(adev, params->vm, &cursor);
1480 amdgpu_vm_pt_next(adev, &cursor);
1483 } else if (frag >= shift) {
1484 /* or just move on to the next on the same level. */
1485 amdgpu_vm_pt_next(adev, &cursor);
1493 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1495 * @adev: amdgpu_device pointer
1496 * @exclusive: fence we need to sync to
1497 * @pages_addr: DMA addresses to use for mapping
1499 * @start: start of mapped range
1500 * @last: last mapped entry
1501 * @flags: flags for the entries
1502 * @addr: addr to set the area to
1503 * @fence: optional resulting fence
1505 * Fill in the page table entries between @start and @last.
1508 * 0 for success, -EINVAL for failure.
1510 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1511 struct dma_fence *exclusive,
1512 dma_addr_t *pages_addr,
1513 struct amdgpu_vm *vm,
1514 uint64_t start, uint64_t last,
1515 uint64_t flags, uint64_t addr,
1516 struct dma_fence **fence)
1518 struct amdgpu_vm_update_params params;
1519 void *owner = AMDGPU_FENCE_OWNER_VM;
1522 memset(¶ms, 0, sizeof(params));
1525 params.pages_addr = pages_addr;
1527 /* sync to everything except eviction fences on unmapping */
1528 if (!(flags & AMDGPU_PTE_VALID))
1529 owner = AMDGPU_FENCE_OWNER_KFD;
1531 r = vm->update_funcs->prepare(¶ms, owner, exclusive);
1535 r = amdgpu_vm_update_ptes(¶ms, start, last + 1, addr, flags);
1539 return vm->update_funcs->commit(¶ms, fence);
1543 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
1545 * @adev: amdgpu_device pointer
1546 * @exclusive: fence we need to sync to
1547 * @pages_addr: DMA addresses to use for mapping
1549 * @mapping: mapped range and flags to use for the update
1550 * @flags: HW flags for the mapping
1551 * @bo_adev: amdgpu_device pointer that bo actually been allocated
1552 * @nodes: array of drm_mm_nodes with the MC addresses
1553 * @fence: optional resulting fence
1555 * Split the mapping into smaller chunks so that each update fits
1559 * 0 for success, -EINVAL for failure.
1561 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
1562 struct dma_fence *exclusive,
1563 dma_addr_t *pages_addr,
1564 struct amdgpu_vm *vm,
1565 struct amdgpu_bo_va_mapping *mapping,
1567 struct amdgpu_device *bo_adev,
1568 struct drm_mm_node *nodes,
1569 struct dma_fence **fence)
1571 unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size;
1572 uint64_t pfn, start = mapping->start;
1575 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1576 * but in case of something, we filter the flags in first place
1578 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1579 flags &= ~AMDGPU_PTE_READABLE;
1580 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1581 flags &= ~AMDGPU_PTE_WRITEABLE;
1583 flags &= ~AMDGPU_PTE_EXECUTABLE;
1584 flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1586 flags &= ~AMDGPU_PTE_MTYPE_MASK;
1587 flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK);
1589 if ((mapping->flags & AMDGPU_PTE_PRT) &&
1590 (adev->asic_type >= CHIP_VEGA10)) {
1591 flags |= AMDGPU_PTE_PRT;
1592 flags &= ~AMDGPU_PTE_VALID;
1595 trace_amdgpu_vm_bo_update(mapping);
1597 pfn = mapping->offset >> PAGE_SHIFT;
1599 while (pfn >= nodes->size) {
1606 dma_addr_t *dma_addr = NULL;
1607 uint64_t max_entries;
1608 uint64_t addr, last;
1611 addr = nodes->start << PAGE_SHIFT;
1612 max_entries = (nodes->size - pfn) *
1613 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1616 max_entries = S64_MAX;
1623 count < max_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1625 uint64_t idx = pfn + count;
1627 if (pages_addr[idx] !=
1628 (pages_addr[idx - 1] + PAGE_SIZE))
1632 if (count < min_linear_pages) {
1633 addr = pfn << PAGE_SHIFT;
1634 dma_addr = pages_addr;
1636 addr = pages_addr[pfn];
1637 max_entries = count * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1640 } else if (flags & AMDGPU_PTE_VALID) {
1641 addr += bo_adev->vm_manager.vram_base_offset;
1642 addr += pfn << PAGE_SHIFT;
1645 last = min((uint64_t)mapping->last, start + max_entries - 1);
1646 r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm,
1647 start, last, flags, addr,
1652 pfn += (last - start + 1) / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1653 if (nodes && nodes->size == pfn) {
1659 } while (unlikely(start != mapping->last + 1));
1665 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1667 * @adev: amdgpu_device pointer
1668 * @bo_va: requested BO and VM object
1669 * @clear: if true clear the entries
1671 * Fill in the page table entries for @bo_va.
1674 * 0 for success, -EINVAL for failure.
1676 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
1677 struct amdgpu_bo_va *bo_va,
1680 struct amdgpu_bo *bo = bo_va->base.bo;
1681 struct amdgpu_vm *vm = bo_va->base.vm;
1682 struct amdgpu_bo_va_mapping *mapping;
1683 dma_addr_t *pages_addr = NULL;
1684 struct ttm_mem_reg *mem;
1685 struct drm_mm_node *nodes;
1686 struct dma_fence *exclusive, **last_update;
1688 struct amdgpu_device *bo_adev = adev;
1696 struct ttm_dma_tt *ttm;
1699 nodes = mem->mm_node;
1700 if (mem->mem_type == TTM_PL_TT) {
1701 ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm);
1702 pages_addr = ttm->dma_address;
1704 exclusive = reservation_object_get_excl(bo->tbo.resv);
1708 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1709 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1714 if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
1715 last_update = &vm->last_update;
1717 last_update = &bo_va->last_pt_update;
1719 if (!clear && bo_va->base.moved) {
1720 bo_va->base.moved = false;
1721 list_splice_init(&bo_va->valids, &bo_va->invalids);
1723 } else if (bo_va->cleared != clear) {
1724 list_splice_init(&bo_va->valids, &bo_va->invalids);
1727 list_for_each_entry(mapping, &bo_va->invalids, list) {
1728 r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm,
1729 mapping, flags, bo_adev, nodes,
1735 if (vm->use_cpu_for_update) {
1738 amdgpu_asic_flush_hdp(adev, NULL);
1741 /* If the BO is not in its preferred location add it back to
1742 * the evicted list so that it gets validated again on the
1743 * next command submission.
1745 if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
1746 uint32_t mem_type = bo->tbo.mem.mem_type;
1748 if (!(bo->preferred_domains & amdgpu_mem_type_to_domain(mem_type)))
1749 amdgpu_vm_bo_evicted(&bo_va->base);
1751 amdgpu_vm_bo_idle(&bo_va->base);
1753 amdgpu_vm_bo_done(&bo_va->base);
1756 list_splice_init(&bo_va->invalids, &bo_va->valids);
1757 bo_va->cleared = clear;
1759 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1760 list_for_each_entry(mapping, &bo_va->valids, list)
1761 trace_amdgpu_vm_bo_mapping(mapping);
1768 * amdgpu_vm_update_prt_state - update the global PRT state
1770 * @adev: amdgpu_device pointer
1772 static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1774 unsigned long flags;
1777 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1778 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1779 adev->gmc.gmc_funcs->set_prt(adev, enable);
1780 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1784 * amdgpu_vm_prt_get - add a PRT user
1786 * @adev: amdgpu_device pointer
1788 static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1790 if (!adev->gmc.gmc_funcs->set_prt)
1793 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1794 amdgpu_vm_update_prt_state(adev);
1798 * amdgpu_vm_prt_put - drop a PRT user
1800 * @adev: amdgpu_device pointer
1802 static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1804 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1805 amdgpu_vm_update_prt_state(adev);
1809 * amdgpu_vm_prt_cb - callback for updating the PRT status
1811 * @fence: fence for the callback
1812 * @_cb: the callback function
1814 static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1816 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1818 amdgpu_vm_prt_put(cb->adev);
1823 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1825 * @adev: amdgpu_device pointer
1826 * @fence: fence for the callback
1828 static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1829 struct dma_fence *fence)
1831 struct amdgpu_prt_cb *cb;
1833 if (!adev->gmc.gmc_funcs->set_prt)
1836 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1838 /* Last resort when we are OOM */
1840 dma_fence_wait(fence, false);
1842 amdgpu_vm_prt_put(adev);
1845 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1847 amdgpu_vm_prt_cb(fence, &cb->cb);
1852 * amdgpu_vm_free_mapping - free a mapping
1854 * @adev: amdgpu_device pointer
1856 * @mapping: mapping to be freed
1857 * @fence: fence of the unmap operation
1859 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1861 static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1862 struct amdgpu_vm *vm,
1863 struct amdgpu_bo_va_mapping *mapping,
1864 struct dma_fence *fence)
1866 if (mapping->flags & AMDGPU_PTE_PRT)
1867 amdgpu_vm_add_prt_cb(adev, fence);
1872 * amdgpu_vm_prt_fini - finish all prt mappings
1874 * @adev: amdgpu_device pointer
1877 * Register a cleanup callback to disable PRT support after VM dies.
1879 static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1881 struct reservation_object *resv = vm->root.base.bo->tbo.resv;
1882 struct dma_fence *excl, **shared;
1883 unsigned i, shared_count;
1886 r = reservation_object_get_fences_rcu(resv, &excl,
1887 &shared_count, &shared);
1889 /* Not enough memory to grab the fence list, as last resort
1890 * block for all the fences to complete.
1892 reservation_object_wait_timeout_rcu(resv, true, false,
1893 MAX_SCHEDULE_TIMEOUT);
1897 /* Add a callback for each fence in the reservation object */
1898 amdgpu_vm_prt_get(adev);
1899 amdgpu_vm_add_prt_cb(adev, excl);
1901 for (i = 0; i < shared_count; ++i) {
1902 amdgpu_vm_prt_get(adev);
1903 amdgpu_vm_add_prt_cb(adev, shared[i]);
1910 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1912 * @adev: amdgpu_device pointer
1914 * @fence: optional resulting fence (unchanged if no work needed to be done
1915 * or if an error occurred)
1917 * Make sure all freed BOs are cleared in the PT.
1918 * PTs have to be reserved and mutex must be locked!
1924 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1925 struct amdgpu_vm *vm,
1926 struct dma_fence **fence)
1928 struct amdgpu_bo_va_mapping *mapping;
1929 uint64_t init_pte_value = 0;
1930 struct dma_fence *f = NULL;
1933 while (!list_empty(&vm->freed)) {
1934 mapping = list_first_entry(&vm->freed,
1935 struct amdgpu_bo_va_mapping, list);
1936 list_del(&mapping->list);
1938 if (vm->pte_support_ats &&
1939 mapping->start < AMDGPU_GMC_HOLE_START)
1940 init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
1942 r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm,
1943 mapping->start, mapping->last,
1944 init_pte_value, 0, &f);
1945 amdgpu_vm_free_mapping(adev, vm, mapping, f);
1953 dma_fence_put(*fence);
1964 * amdgpu_vm_handle_moved - handle moved BOs in the PT
1966 * @adev: amdgpu_device pointer
1969 * Make sure all BOs which are moved are updated in the PTs.
1974 * PTs have to be reserved!
1976 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
1977 struct amdgpu_vm *vm)
1979 struct amdgpu_bo_va *bo_va, *tmp;
1980 struct reservation_object *resv;
1984 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
1985 /* Per VM BOs never need to bo cleared in the page tables */
1986 r = amdgpu_vm_bo_update(adev, bo_va, false);
1991 spin_lock(&vm->invalidated_lock);
1992 while (!list_empty(&vm->invalidated)) {
1993 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
1995 resv = bo_va->base.bo->tbo.resv;
1996 spin_unlock(&vm->invalidated_lock);
1998 /* Try to reserve the BO to avoid clearing its ptes */
1999 if (!amdgpu_vm_debug && reservation_object_trylock(resv))
2001 /* Somebody else is using the BO right now */
2005 r = amdgpu_vm_bo_update(adev, bo_va, clear);
2010 reservation_object_unlock(resv);
2011 spin_lock(&vm->invalidated_lock);
2013 spin_unlock(&vm->invalidated_lock);
2019 * amdgpu_vm_bo_add - add a bo to a specific vm
2021 * @adev: amdgpu_device pointer
2023 * @bo: amdgpu buffer object
2025 * Add @bo into the requested vm.
2026 * Add @bo to the list of bos associated with the vm
2029 * Newly added bo_va or NULL for failure
2031 * Object has to be reserved!
2033 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2034 struct amdgpu_vm *vm,
2035 struct amdgpu_bo *bo)
2037 struct amdgpu_bo_va *bo_va;
2039 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
2040 if (bo_va == NULL) {
2043 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
2045 bo_va->ref_count = 1;
2046 INIT_LIST_HEAD(&bo_va->valids);
2047 INIT_LIST_HEAD(&bo_va->invalids);
2049 if (bo && amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev))) {
2050 bo_va->is_xgmi = true;
2051 mutex_lock(&adev->vm_manager.lock_pstate);
2052 /* Power up XGMI if it can be potentially used */
2053 if (++adev->vm_manager.xgmi_map_counter == 1)
2054 amdgpu_xgmi_set_pstate(adev, 1);
2055 mutex_unlock(&adev->vm_manager.lock_pstate);
2063 * amdgpu_vm_bo_insert_mapping - insert a new mapping
2065 * @adev: amdgpu_device pointer
2066 * @bo_va: bo_va to store the address
2067 * @mapping: the mapping to insert
2069 * Insert a new mapping into all structures.
2071 static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
2072 struct amdgpu_bo_va *bo_va,
2073 struct amdgpu_bo_va_mapping *mapping)
2075 struct amdgpu_vm *vm = bo_va->base.vm;
2076 struct amdgpu_bo *bo = bo_va->base.bo;
2078 mapping->bo_va = bo_va;
2079 list_add(&mapping->list, &bo_va->invalids);
2080 amdgpu_vm_it_insert(mapping, &vm->va);
2082 if (mapping->flags & AMDGPU_PTE_PRT)
2083 amdgpu_vm_prt_get(adev);
2085 if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv &&
2086 !bo_va->base.moved) {
2087 list_move(&bo_va->base.vm_status, &vm->moved);
2089 trace_amdgpu_vm_bo_map(bo_va, mapping);
2093 * amdgpu_vm_bo_map - map bo inside a vm
2095 * @adev: amdgpu_device pointer
2096 * @bo_va: bo_va to store the address
2097 * @saddr: where to map the BO
2098 * @offset: requested offset in the BO
2099 * @size: BO size in bytes
2100 * @flags: attributes of pages (read/write/valid/etc.)
2102 * Add a mapping of the BO at the specefied addr into the VM.
2105 * 0 for success, error for failure.
2107 * Object has to be reserved and unreserved outside!
2109 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2110 struct amdgpu_bo_va *bo_va,
2111 uint64_t saddr, uint64_t offset,
2112 uint64_t size, uint64_t flags)
2114 struct amdgpu_bo_va_mapping *mapping, *tmp;
2115 struct amdgpu_bo *bo = bo_va->base.bo;
2116 struct amdgpu_vm *vm = bo_va->base.vm;
2119 /* validate the parameters */
2120 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
2121 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
2124 /* make sure object fit at this offset */
2125 eaddr = saddr + size - 1;
2126 if (saddr >= eaddr ||
2127 (bo && offset + size > amdgpu_bo_size(bo)))
2130 saddr /= AMDGPU_GPU_PAGE_SIZE;
2131 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2133 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2135 /* bo and tmp overlap, invalid addr */
2136 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
2137 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
2138 tmp->start, tmp->last + 1);
2142 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2146 mapping->start = saddr;
2147 mapping->last = eaddr;
2148 mapping->offset = offset;
2149 mapping->flags = flags;
2151 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2157 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
2159 * @adev: amdgpu_device pointer
2160 * @bo_va: bo_va to store the address
2161 * @saddr: where to map the BO
2162 * @offset: requested offset in the BO
2163 * @size: BO size in bytes
2164 * @flags: attributes of pages (read/write/valid/etc.)
2166 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
2167 * mappings as we do so.
2170 * 0 for success, error for failure.
2172 * Object has to be reserved and unreserved outside!
2174 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
2175 struct amdgpu_bo_va *bo_va,
2176 uint64_t saddr, uint64_t offset,
2177 uint64_t size, uint64_t flags)
2179 struct amdgpu_bo_va_mapping *mapping;
2180 struct amdgpu_bo *bo = bo_va->base.bo;
2184 /* validate the parameters */
2185 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
2186 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
2189 /* make sure object fit at this offset */
2190 eaddr = saddr + size - 1;
2191 if (saddr >= eaddr ||
2192 (bo && offset + size > amdgpu_bo_size(bo)))
2195 /* Allocate all the needed memory */
2196 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2200 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
2206 saddr /= AMDGPU_GPU_PAGE_SIZE;
2207 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2209 mapping->start = saddr;
2210 mapping->last = eaddr;
2211 mapping->offset = offset;
2212 mapping->flags = flags;
2214 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2220 * amdgpu_vm_bo_unmap - remove bo mapping from vm
2222 * @adev: amdgpu_device pointer
2223 * @bo_va: bo_va to remove the address from
2224 * @saddr: where to the BO is mapped
2226 * Remove a mapping of the BO at the specefied addr from the VM.
2229 * 0 for success, error for failure.
2231 * Object has to be reserved and unreserved outside!
2233 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2234 struct amdgpu_bo_va *bo_va,
2237 struct amdgpu_bo_va_mapping *mapping;
2238 struct amdgpu_vm *vm = bo_va->base.vm;
2241 saddr /= AMDGPU_GPU_PAGE_SIZE;
2243 list_for_each_entry(mapping, &bo_va->valids, list) {
2244 if (mapping->start == saddr)
2248 if (&mapping->list == &bo_va->valids) {
2251 list_for_each_entry(mapping, &bo_va->invalids, list) {
2252 if (mapping->start == saddr)
2256 if (&mapping->list == &bo_va->invalids)
2260 list_del(&mapping->list);
2261 amdgpu_vm_it_remove(mapping, &vm->va);
2262 mapping->bo_va = NULL;
2263 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2266 list_add(&mapping->list, &vm->freed);
2268 amdgpu_vm_free_mapping(adev, vm, mapping,
2269 bo_va->last_pt_update);
2275 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
2277 * @adev: amdgpu_device pointer
2278 * @vm: VM structure to use
2279 * @saddr: start of the range
2280 * @size: size of the range
2282 * Remove all mappings in a range, split them as appropriate.
2285 * 0 for success, error for failure.
2287 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
2288 struct amdgpu_vm *vm,
2289 uint64_t saddr, uint64_t size)
2291 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
2295 eaddr = saddr + size - 1;
2296 saddr /= AMDGPU_GPU_PAGE_SIZE;
2297 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2299 /* Allocate all the needed memory */
2300 before = kzalloc(sizeof(*before), GFP_KERNEL);
2303 INIT_LIST_HEAD(&before->list);
2305 after = kzalloc(sizeof(*after), GFP_KERNEL);
2310 INIT_LIST_HEAD(&after->list);
2312 /* Now gather all removed mappings */
2313 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2315 /* Remember mapping split at the start */
2316 if (tmp->start < saddr) {
2317 before->start = tmp->start;
2318 before->last = saddr - 1;
2319 before->offset = tmp->offset;
2320 before->flags = tmp->flags;
2321 before->bo_va = tmp->bo_va;
2322 list_add(&before->list, &tmp->bo_va->invalids);
2325 /* Remember mapping split at the end */
2326 if (tmp->last > eaddr) {
2327 after->start = eaddr + 1;
2328 after->last = tmp->last;
2329 after->offset = tmp->offset;
2330 after->offset += after->start - tmp->start;
2331 after->flags = tmp->flags;
2332 after->bo_va = tmp->bo_va;
2333 list_add(&after->list, &tmp->bo_va->invalids);
2336 list_del(&tmp->list);
2337 list_add(&tmp->list, &removed);
2339 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
2342 /* And free them up */
2343 list_for_each_entry_safe(tmp, next, &removed, list) {
2344 amdgpu_vm_it_remove(tmp, &vm->va);
2345 list_del(&tmp->list);
2347 if (tmp->start < saddr)
2349 if (tmp->last > eaddr)
2353 list_add(&tmp->list, &vm->freed);
2354 trace_amdgpu_vm_bo_unmap(NULL, tmp);
2357 /* Insert partial mapping before the range */
2358 if (!list_empty(&before->list)) {
2359 amdgpu_vm_it_insert(before, &vm->va);
2360 if (before->flags & AMDGPU_PTE_PRT)
2361 amdgpu_vm_prt_get(adev);
2366 /* Insert partial mapping after the range */
2367 if (!list_empty(&after->list)) {
2368 amdgpu_vm_it_insert(after, &vm->va);
2369 if (after->flags & AMDGPU_PTE_PRT)
2370 amdgpu_vm_prt_get(adev);
2379 * amdgpu_vm_bo_lookup_mapping - find mapping by address
2381 * @vm: the requested VM
2382 * @addr: the address
2384 * Find a mapping by it's address.
2387 * The amdgpu_bo_va_mapping matching for addr or NULL
2390 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
2393 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
2397 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
2399 * @vm: the requested vm
2400 * @ticket: CS ticket
2402 * Trace all mappings of BOs reserved during a command submission.
2404 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
2406 struct amdgpu_bo_va_mapping *mapping;
2408 if (!trace_amdgpu_vm_bo_cs_enabled())
2411 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
2412 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
2413 if (mapping->bo_va && mapping->bo_va->base.bo) {
2414 struct amdgpu_bo *bo;
2416 bo = mapping->bo_va->base.bo;
2417 if (READ_ONCE(bo->tbo.resv->lock.ctx) != ticket)
2421 trace_amdgpu_vm_bo_cs(mapping);
2426 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2428 * @adev: amdgpu_device pointer
2429 * @bo_va: requested bo_va
2431 * Remove @bo_va->bo from the requested vm.
2433 * Object have to be reserved!
2435 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2436 struct amdgpu_bo_va *bo_va)
2438 struct amdgpu_bo_va_mapping *mapping, *next;
2439 struct amdgpu_bo *bo = bo_va->base.bo;
2440 struct amdgpu_vm *vm = bo_va->base.vm;
2441 struct amdgpu_vm_bo_base **base;
2444 if (bo->tbo.resv == vm->root.base.bo->tbo.resv)
2445 vm->bulk_moveable = false;
2447 for (base = &bo_va->base.bo->vm_bo; *base;
2448 base = &(*base)->next) {
2449 if (*base != &bo_va->base)
2452 *base = bo_va->base.next;
2457 spin_lock(&vm->invalidated_lock);
2458 list_del(&bo_va->base.vm_status);
2459 spin_unlock(&vm->invalidated_lock);
2461 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2462 list_del(&mapping->list);
2463 amdgpu_vm_it_remove(mapping, &vm->va);
2464 mapping->bo_va = NULL;
2465 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2466 list_add(&mapping->list, &vm->freed);
2468 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2469 list_del(&mapping->list);
2470 amdgpu_vm_it_remove(mapping, &vm->va);
2471 amdgpu_vm_free_mapping(adev, vm, mapping,
2472 bo_va->last_pt_update);
2475 dma_fence_put(bo_va->last_pt_update);
2477 if (bo && bo_va->is_xgmi) {
2478 mutex_lock(&adev->vm_manager.lock_pstate);
2479 if (--adev->vm_manager.xgmi_map_counter == 0)
2480 amdgpu_xgmi_set_pstate(adev, 0);
2481 mutex_unlock(&adev->vm_manager.lock_pstate);
2488 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2490 * @adev: amdgpu_device pointer
2491 * @bo: amdgpu buffer object
2492 * @evicted: is the BO evicted
2494 * Mark @bo as invalid.
2496 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2497 struct amdgpu_bo *bo, bool evicted)
2499 struct amdgpu_vm_bo_base *bo_base;
2501 /* shadow bo doesn't have bo base, its validation needs its parent */
2502 if (bo->parent && bo->parent->shadow == bo)
2505 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
2506 struct amdgpu_vm *vm = bo_base->vm;
2508 if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
2509 amdgpu_vm_bo_evicted(bo_base);
2515 bo_base->moved = true;
2517 if (bo->tbo.type == ttm_bo_type_kernel)
2518 amdgpu_vm_bo_relocated(bo_base);
2519 else if (bo->tbo.resv == vm->root.base.bo->tbo.resv)
2520 amdgpu_vm_bo_moved(bo_base);
2522 amdgpu_vm_bo_invalidated(bo_base);
2527 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2532 * VM page table as power of two
2534 static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2536 /* Total bits covered by PD + PTs */
2537 unsigned bits = ilog2(vm_size) + 18;
2539 /* Make sure the PD is 4K in size up to 8GB address space.
2540 Above that split equal between PD and PTs */
2544 return ((bits + 3) / 2);
2548 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2550 * @adev: amdgpu_device pointer
2551 * @min_vm_size: the minimum vm size in GB if it's set auto
2552 * @fragment_size_default: Default PTE fragment size
2553 * @max_level: max VMPT level
2554 * @max_bits: max address space size in bits
2557 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2558 uint32_t fragment_size_default, unsigned max_level,
2561 unsigned int max_size = 1 << (max_bits - 30);
2562 unsigned int vm_size;
2565 /* adjust vm size first */
2566 if (amdgpu_vm_size != -1) {
2567 vm_size = amdgpu_vm_size;
2568 if (vm_size > max_size) {
2569 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2570 amdgpu_vm_size, max_size);
2575 unsigned int phys_ram_gb;
2577 /* Optimal VM size depends on the amount of physical
2578 * RAM available. Underlying requirements and
2581 * - Need to map system memory and VRAM from all GPUs
2582 * - VRAM from other GPUs not known here
2583 * - Assume VRAM <= system memory
2584 * - On GFX8 and older, VM space can be segmented for
2586 * - Need to allow room for fragmentation, guard pages etc.
2588 * This adds up to a rough guess of system memory x3.
2589 * Round up to power of two to maximize the available
2590 * VM size with the given page table size.
2593 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2594 (1 << 30) - 1) >> 30;
2595 vm_size = roundup_pow_of_two(
2596 min(max(phys_ram_gb * 3, min_vm_size), max_size));
2599 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2601 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2602 if (amdgpu_vm_block_size != -1)
2603 tmp >>= amdgpu_vm_block_size - 9;
2604 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2605 adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
2606 switch (adev->vm_manager.num_level) {
2608 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2611 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2614 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2617 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2619 /* block size depends on vm size and hw setup*/
2620 if (amdgpu_vm_block_size != -1)
2621 adev->vm_manager.block_size =
2622 min((unsigned)amdgpu_vm_block_size, max_bits
2623 - AMDGPU_GPU_PAGE_SHIFT
2624 - 9 * adev->vm_manager.num_level);
2625 else if (adev->vm_manager.num_level > 1)
2626 adev->vm_manager.block_size = 9;
2628 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2630 if (amdgpu_vm_fragment_size == -1)
2631 adev->vm_manager.fragment_size = fragment_size_default;
2633 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2635 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2636 vm_size, adev->vm_manager.num_level + 1,
2637 adev->vm_manager.block_size,
2638 adev->vm_manager.fragment_size);
2642 * amdgpu_vm_wait_idle - wait for the VM to become idle
2644 * @vm: VM object to wait for
2645 * @timeout: timeout to wait for VM to become idle
2647 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2649 return reservation_object_wait_timeout_rcu(vm->root.base.bo->tbo.resv,
2650 true, true, timeout);
2654 * amdgpu_vm_init - initialize a vm instance
2656 * @adev: amdgpu_device pointer
2658 * @vm_context: Indicates if it GFX or Compute context
2659 * @pasid: Process address space identifier
2664 * 0 for success, error for failure.
2666 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2667 int vm_context, unsigned int pasid)
2669 struct amdgpu_bo_param bp;
2670 struct amdgpu_bo *root;
2673 vm->va = RB_ROOT_CACHED;
2674 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2675 vm->reserved_vmid[i] = NULL;
2676 INIT_LIST_HEAD(&vm->evicted);
2677 INIT_LIST_HEAD(&vm->relocated);
2678 INIT_LIST_HEAD(&vm->moved);
2679 INIT_LIST_HEAD(&vm->idle);
2680 INIT_LIST_HEAD(&vm->invalidated);
2681 spin_lock_init(&vm->invalidated_lock);
2682 INIT_LIST_HEAD(&vm->freed);
2684 /* create scheduler entity for page table updates */
2685 r = drm_sched_entity_init(&vm->entity, adev->vm_manager.vm_pte_rqs,
2686 adev->vm_manager.vm_pte_num_rqs, NULL);
2690 vm->pte_support_ats = false;
2692 if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) {
2693 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2694 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2696 if (adev->asic_type == CHIP_RAVEN)
2697 vm->pte_support_ats = true;
2699 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2700 AMDGPU_VM_USE_CPU_FOR_GFX);
2702 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2703 vm->use_cpu_for_update ? "CPU" : "SDMA");
2704 WARN_ONCE((vm->use_cpu_for_update && !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2705 "CPU update of VM recommended only for large BAR system\n");
2707 if (vm->use_cpu_for_update)
2708 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2710 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2711 vm->last_update = NULL;
2713 amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, &bp);
2714 if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE)
2715 bp.flags &= ~AMDGPU_GEM_CREATE_SHADOW;
2716 r = amdgpu_bo_create(adev, &bp, &root);
2718 goto error_free_sched_entity;
2720 r = amdgpu_bo_reserve(root, true);
2722 goto error_free_root;
2724 r = reservation_object_reserve_shared(root->tbo.resv, 1);
2726 goto error_unreserve;
2728 amdgpu_vm_bo_base_init(&vm->root.base, vm, root);
2730 r = amdgpu_vm_clear_bo(adev, vm, root);
2732 goto error_unreserve;
2734 amdgpu_bo_unreserve(vm->root.base.bo);
2737 unsigned long flags;
2739 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2740 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
2742 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2744 goto error_free_root;
2749 INIT_KFIFO(vm->faults);
2754 amdgpu_bo_unreserve(vm->root.base.bo);
2757 amdgpu_bo_unref(&vm->root.base.bo->shadow);
2758 amdgpu_bo_unref(&vm->root.base.bo);
2759 vm->root.base.bo = NULL;
2761 error_free_sched_entity:
2762 drm_sched_entity_destroy(&vm->entity);
2768 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
2770 * @adev: amdgpu_device pointer
2773 * This only works on GFX VMs that don't have any BOs added and no
2774 * page tables allocated yet.
2776 * Changes the following VM parameters:
2777 * - use_cpu_for_update
2778 * - pte_supports_ats
2779 * - pasid (old PASID is released, because compute manages its own PASIDs)
2781 * Reinitializes the page directory to reflect the changed ATS
2785 * 0 for success, -errno for errors.
2787 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid)
2789 bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
2792 r = amdgpu_bo_reserve(vm->root.base.bo, true);
2797 if (!RB_EMPTY_ROOT(&vm->va.rb_root) || vm->root.entries) {
2803 unsigned long flags;
2805 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2806 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
2808 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2815 /* Check if PD needs to be reinitialized and do it before
2816 * changing any other state, in case it fails.
2818 if (pte_support_ats != vm->pte_support_ats) {
2819 vm->pte_support_ats = pte_support_ats;
2820 r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo);
2825 /* Update VM state */
2826 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2827 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2828 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2829 vm->use_cpu_for_update ? "CPU" : "SDMA");
2830 WARN_ONCE((vm->use_cpu_for_update && !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2831 "CPU update of VM recommended only for large BAR system\n");
2834 unsigned long flags;
2836 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2837 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
2838 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2840 /* Free the original amdgpu allocated pasid
2841 * Will be replaced with kfd allocated pasid
2843 amdgpu_pasid_free(vm->pasid);
2847 /* Free the shadow bo for compute VM */
2848 amdgpu_bo_unref(&vm->root.base.bo->shadow);
2857 unsigned long flags;
2859 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2860 idr_remove(&adev->vm_manager.pasid_idr, pasid);
2861 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2864 amdgpu_bo_unreserve(vm->root.base.bo);
2869 * amdgpu_vm_release_compute - release a compute vm
2870 * @adev: amdgpu_device pointer
2871 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
2873 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
2874 * pasid from vm. Compute should stop use of vm after this call.
2876 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2879 unsigned long flags;
2881 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2882 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
2883 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2889 * amdgpu_vm_fini - tear down a vm instance
2891 * @adev: amdgpu_device pointer
2895 * Unbind the VM and remove all bos from the vm bo list
2897 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2899 struct amdgpu_bo_va_mapping *mapping, *tmp;
2900 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
2901 struct amdgpu_bo *root;
2904 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
2907 unsigned long flags;
2909 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2910 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
2911 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2914 drm_sched_entity_destroy(&vm->entity);
2916 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
2917 dev_err(adev->dev, "still active bo inside vm\n");
2919 rbtree_postorder_for_each_entry_safe(mapping, tmp,
2920 &vm->va.rb_root, rb) {
2921 /* Don't remove the mapping here, we don't want to trigger a
2922 * rebalance and the tree is about to be destroyed anyway.
2924 list_del(&mapping->list);
2927 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2928 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
2929 amdgpu_vm_prt_fini(adev, vm);
2930 prt_fini_needed = false;
2933 list_del(&mapping->list);
2934 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
2937 root = amdgpu_bo_ref(vm->root.base.bo);
2938 r = amdgpu_bo_reserve(root, true);
2940 dev_err(adev->dev, "Leaking page tables because BO reservation failed\n");
2942 amdgpu_vm_free_pts(adev, vm, NULL);
2943 amdgpu_bo_unreserve(root);
2945 amdgpu_bo_unref(&root);
2946 WARN_ON(vm->root.base.bo);
2947 dma_fence_put(vm->last_update);
2948 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2949 amdgpu_vmid_free_reserved(adev, vm, i);
2953 * amdgpu_vm_manager_init - init the VM manager
2955 * @adev: amdgpu_device pointer
2957 * Initialize the VM manager structures
2959 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
2963 amdgpu_vmid_mgr_init(adev);
2965 adev->vm_manager.fence_context =
2966 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2967 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2968 adev->vm_manager.seqno[i] = 0;
2970 spin_lock_init(&adev->vm_manager.prt_lock);
2971 atomic_set(&adev->vm_manager.num_prt_users, 0);
2973 /* If not overridden by the user, by default, only in large BAR systems
2974 * Compute VM tables will be updated by CPU
2976 #ifdef CONFIG_X86_64
2977 if (amdgpu_vm_update_mode == -1) {
2978 if (amdgpu_gmc_vram_full_visible(&adev->gmc))
2979 adev->vm_manager.vm_update_mode =
2980 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
2982 adev->vm_manager.vm_update_mode = 0;
2984 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
2986 adev->vm_manager.vm_update_mode = 0;
2989 idr_init(&adev->vm_manager.pasid_idr);
2990 spin_lock_init(&adev->vm_manager.pasid_lock);
2992 adev->vm_manager.xgmi_map_counter = 0;
2993 mutex_init(&adev->vm_manager.lock_pstate);
2997 * amdgpu_vm_manager_fini - cleanup VM manager
2999 * @adev: amdgpu_device pointer
3001 * Cleanup the VM manager and free resources.
3003 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
3005 WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr));
3006 idr_destroy(&adev->vm_manager.pasid_idr);
3008 amdgpu_vmid_mgr_fini(adev);
3012 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
3014 * @dev: drm device pointer
3015 * @data: drm_amdgpu_vm
3016 * @filp: drm file pointer
3019 * 0 for success, -errno for errors.
3021 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
3023 union drm_amdgpu_vm *args = data;
3024 struct amdgpu_device *adev = dev->dev_private;
3025 struct amdgpu_fpriv *fpriv = filp->driver_priv;
3028 switch (args->in.op) {
3029 case AMDGPU_VM_OP_RESERVE_VMID:
3030 /* current, we only have requirement to reserve vmid from gfxhub */
3031 r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
3035 case AMDGPU_VM_OP_UNRESERVE_VMID:
3036 amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
3046 * amdgpu_vm_get_task_info - Extracts task info for a PASID.
3048 * @adev: drm device pointer
3049 * @pasid: PASID identifier for VM
3050 * @task_info: task_info to fill.
3052 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid,
3053 struct amdgpu_task_info *task_info)
3055 struct amdgpu_vm *vm;
3056 unsigned long flags;
3058 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3060 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3062 *task_info = vm->task_info;
3064 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3068 * amdgpu_vm_set_task_info - Sets VMs task info.
3070 * @vm: vm for which to set the info
3072 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
3074 if (!vm->task_info.pid) {
3075 vm->task_info.pid = current->pid;
3076 get_task_comm(vm->task_info.task_name, current);
3078 if (current->group_leader->mm == current->mm) {
3079 vm->task_info.tgid = current->group_leader->pid;
3080 get_task_comm(vm->task_info.process_name, current->group_leader);