2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/dma-fence-array.h>
29 #include <linux/interval_tree_generic.h>
30 #include <linux/idr.h>
32 #include <drm/amdgpu_drm.h>
34 #include "amdgpu_trace.h"
35 #include "amdgpu_amdkfd.h"
36 #include "amdgpu_gmc.h"
37 #include "amdgpu_xgmi.h"
42 * GPUVM is similar to the legacy gart on older asics, however
43 * rather than there being a single global gart table
44 * for the entire GPU, there are multiple VM page tables active
45 * at any given time. The VM page tables can contain a mix
46 * vram pages and system memory pages and system memory pages
47 * can be mapped as snooped (cached system pages) or unsnooped
48 * (uncached system pages).
49 * Each VM has an ID associated with it and there is a page table
50 * associated with each VMID. When execting a command buffer,
51 * the kernel tells the the ring what VMID to use for that command
52 * buffer. VMIDs are allocated dynamically as commands are submitted.
53 * The userspace drivers maintain their own address space and the kernel
54 * sets up their pages tables accordingly when they submit their
55 * command buffers and a VMID is assigned.
56 * Cayman/Trinity support up to 8 active VMs at any given time;
60 #define START(node) ((node)->start)
61 #define LAST(node) ((node)->last)
63 INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
64 START, LAST, static, amdgpu_vm_it)
70 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
72 struct amdgpu_prt_cb {
75 * @adev: amdgpu device
77 struct amdgpu_device *adev;
82 struct dma_fence_cb cb;
86 * amdgpu_vm_level_shift - return the addr shift for each level
88 * @adev: amdgpu_device pointer
92 * The number of bits the pfn needs to be right shifted for a level.
94 static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
97 unsigned shift = 0xff;
103 shift = 9 * (AMDGPU_VM_PDB0 - level) +
104 adev->vm_manager.block_size;
110 dev_err(adev->dev, "the level%d isn't supported.\n", level);
117 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
119 * @adev: amdgpu_device pointer
123 * The number of entries in a page directory or page table.
125 static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
128 unsigned shift = amdgpu_vm_level_shift(adev,
129 adev->vm_manager.root_level);
131 if (level == adev->vm_manager.root_level)
132 /* For the root directory */
133 return round_up(adev->vm_manager.max_pfn, 1ULL << shift) >> shift;
134 else if (level != AMDGPU_VM_PTB)
135 /* Everything in between */
138 /* For the page tables on the leaves */
139 return AMDGPU_VM_PTE_COUNT(adev);
143 * amdgpu_vm_num_ats_entries - return the number of ATS entries in the root PD
145 * @adev: amdgpu_device pointer
148 * The number of entries in the root page directory which needs the ATS setting.
150 static unsigned amdgpu_vm_num_ats_entries(struct amdgpu_device *adev)
154 shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level);
155 return AMDGPU_GMC_HOLE_START >> (shift + AMDGPU_GPU_PAGE_SHIFT);
159 * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT
161 * @adev: amdgpu_device pointer
165 * The mask to extract the entry number of a PD/PT from an address.
167 static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
170 if (level <= adev->vm_manager.root_level)
172 else if (level != AMDGPU_VM_PTB)
175 return AMDGPU_VM_PTE_COUNT(adev) - 1;
179 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
181 * @adev: amdgpu_device pointer
185 * The size of the BO for a page directory or page table in bytes.
187 static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
189 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
193 * amdgpu_vm_bo_evicted - vm_bo is evicted
195 * @vm_bo: vm_bo which is evicted
197 * State for PDs/PTs and per VM BOs which are not at the location they should
200 static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
202 struct amdgpu_vm *vm = vm_bo->vm;
203 struct amdgpu_bo *bo = vm_bo->bo;
206 if (bo->tbo.type == ttm_bo_type_kernel)
207 list_move(&vm_bo->vm_status, &vm->evicted);
209 list_move_tail(&vm_bo->vm_status, &vm->evicted);
213 * amdgpu_vm_bo_relocated - vm_bo is reloacted
215 * @vm_bo: vm_bo which is relocated
217 * State for PDs/PTs which needs to update their parent PD.
219 static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
221 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
225 * amdgpu_vm_bo_moved - vm_bo is moved
227 * @vm_bo: vm_bo which is moved
229 * State for per VM BOs which are moved, but that change is not yet reflected
230 * in the page tables.
232 static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
234 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
238 * amdgpu_vm_bo_idle - vm_bo is idle
240 * @vm_bo: vm_bo which is now idle
242 * State for PDs/PTs and per VM BOs which have gone through the state machine
245 static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
247 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
248 vm_bo->moved = false;
252 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
254 * @vm_bo: vm_bo which is now invalidated
256 * State for normal BOs which are invalidated and that change not yet reflected
259 static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
261 spin_lock(&vm_bo->vm->invalidated_lock);
262 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
263 spin_unlock(&vm_bo->vm->invalidated_lock);
267 * amdgpu_vm_bo_done - vm_bo is done
269 * @vm_bo: vm_bo which is now done
271 * State for normal BOs which are invalidated and that change has been updated
274 static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
276 spin_lock(&vm_bo->vm->invalidated_lock);
277 list_del_init(&vm_bo->vm_status);
278 spin_unlock(&vm_bo->vm->invalidated_lock);
282 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
284 * @base: base structure for tracking BO usage in a VM
285 * @vm: vm to which bo is to be added
286 * @bo: amdgpu buffer object
288 * Initialize a bo_va_base structure and add it to the appropriate lists
291 static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
292 struct amdgpu_vm *vm,
293 struct amdgpu_bo *bo)
298 INIT_LIST_HEAD(&base->vm_status);
302 base->next = bo->vm_bo;
305 if (bo->tbo.base.resv != vm->root.base.bo->tbo.base.resv)
308 vm->bulk_moveable = false;
309 if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
310 amdgpu_vm_bo_relocated(base);
312 amdgpu_vm_bo_idle(base);
314 if (bo->preferred_domains &
315 amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type))
319 * we checked all the prerequisites, but it looks like this per vm bo
320 * is currently evicted. add the bo to the evicted list to make sure it
321 * is validated on next vm use to avoid fault.
323 amdgpu_vm_bo_evicted(base);
327 * amdgpu_vm_pt_parent - get the parent page directory
329 * @pt: child page table
331 * Helper to get the parent entry for the child page table. NULL if we are at
332 * the root page directory.
334 static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt)
336 struct amdgpu_bo *parent = pt->base.bo->parent;
341 return container_of(parent->vm_bo, struct amdgpu_vm_pt, base);
345 * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt
347 struct amdgpu_vm_pt_cursor {
349 struct amdgpu_vm_pt *parent;
350 struct amdgpu_vm_pt *entry;
355 * amdgpu_vm_pt_start - start PD/PT walk
357 * @adev: amdgpu_device pointer
358 * @vm: amdgpu_vm structure
359 * @start: start address of the walk
360 * @cursor: state to initialize
362 * Initialize a amdgpu_vm_pt_cursor to start a walk.
364 static void amdgpu_vm_pt_start(struct amdgpu_device *adev,
365 struct amdgpu_vm *vm, uint64_t start,
366 struct amdgpu_vm_pt_cursor *cursor)
369 cursor->parent = NULL;
370 cursor->entry = &vm->root;
371 cursor->level = adev->vm_manager.root_level;
375 * amdgpu_vm_pt_descendant - go to child node
377 * @adev: amdgpu_device pointer
378 * @cursor: current state
380 * Walk to the child node of the current node.
382 * True if the walk was possible, false otherwise.
384 static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,
385 struct amdgpu_vm_pt_cursor *cursor)
387 unsigned mask, shift, idx;
389 if (!cursor->entry->entries)
392 BUG_ON(!cursor->entry->base.bo);
393 mask = amdgpu_vm_entries_mask(adev, cursor->level);
394 shift = amdgpu_vm_level_shift(adev, cursor->level);
397 idx = (cursor->pfn >> shift) & mask;
398 cursor->parent = cursor->entry;
399 cursor->entry = &cursor->entry->entries[idx];
404 * amdgpu_vm_pt_sibling - go to sibling node
406 * @adev: amdgpu_device pointer
407 * @cursor: current state
409 * Walk to the sibling node of the current node.
411 * True if the walk was possible, false otherwise.
413 static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev,
414 struct amdgpu_vm_pt_cursor *cursor)
416 unsigned shift, num_entries;
418 /* Root doesn't have a sibling */
422 /* Go to our parents and see if we got a sibling */
423 shift = amdgpu_vm_level_shift(adev, cursor->level - 1);
424 num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1);
426 if (cursor->entry == &cursor->parent->entries[num_entries - 1])
429 cursor->pfn += 1ULL << shift;
430 cursor->pfn &= ~((1ULL << shift) - 1);
436 * amdgpu_vm_pt_ancestor - go to parent node
438 * @cursor: current state
440 * Walk to the parent node of the current node.
442 * True if the walk was possible, false otherwise.
444 static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor)
450 cursor->entry = cursor->parent;
451 cursor->parent = amdgpu_vm_pt_parent(cursor->parent);
456 * amdgpu_vm_pt_next - get next PD/PT in hieratchy
458 * @adev: amdgpu_device pointer
459 * @cursor: current state
461 * Walk the PD/PT tree to the next node.
463 static void amdgpu_vm_pt_next(struct amdgpu_device *adev,
464 struct amdgpu_vm_pt_cursor *cursor)
466 /* First try a newborn child */
467 if (amdgpu_vm_pt_descendant(adev, cursor))
470 /* If that didn't worked try to find a sibling */
471 while (!amdgpu_vm_pt_sibling(adev, cursor)) {
472 /* No sibling, go to our parents and grandparents */
473 if (!amdgpu_vm_pt_ancestor(cursor)) {
481 * amdgpu_vm_pt_first_dfs - start a deep first search
483 * @adev: amdgpu_device structure
484 * @vm: amdgpu_vm structure
485 * @cursor: state to initialize
487 * Starts a deep first traversal of the PD/PT tree.
489 static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev,
490 struct amdgpu_vm *vm,
491 struct amdgpu_vm_pt_cursor *start,
492 struct amdgpu_vm_pt_cursor *cursor)
497 amdgpu_vm_pt_start(adev, vm, 0, cursor);
498 while (amdgpu_vm_pt_descendant(adev, cursor));
502 * amdgpu_vm_pt_continue_dfs - check if the deep first search should continue
504 * @start: starting point for the search
505 * @entry: current entry
508 * True when the search should continue, false otherwise.
510 static bool amdgpu_vm_pt_continue_dfs(struct amdgpu_vm_pt_cursor *start,
511 struct amdgpu_vm_pt *entry)
513 return entry && (!start || entry != start->entry);
517 * amdgpu_vm_pt_next_dfs - get the next node for a deep first search
519 * @adev: amdgpu_device structure
520 * @cursor: current state
522 * Move the cursor to the next node in a deep first search.
524 static void amdgpu_vm_pt_next_dfs(struct amdgpu_device *adev,
525 struct amdgpu_vm_pt_cursor *cursor)
531 cursor->entry = NULL;
532 else if (amdgpu_vm_pt_sibling(adev, cursor))
533 while (amdgpu_vm_pt_descendant(adev, cursor));
535 amdgpu_vm_pt_ancestor(cursor);
539 * for_each_amdgpu_vm_pt_dfs_safe - safe deep first search of all PDs/PTs
541 #define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) \
542 for (amdgpu_vm_pt_first_dfs((adev), (vm), (start), &(cursor)), \
543 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor));\
544 amdgpu_vm_pt_continue_dfs((start), (entry)); \
545 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor)))
548 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
550 * @vm: vm providing the BOs
551 * @validated: head of validation list
552 * @entry: entry to add
554 * Add the page directory to the list of BOs to
555 * validate for command submission.
557 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
558 struct list_head *validated,
559 struct amdgpu_bo_list_entry *entry)
562 entry->tv.bo = &vm->root.base.bo->tbo;
563 /* One for the VM updates, one for TTM and one for the CS job */
564 entry->tv.num_shared = 3;
565 entry->user_pages = NULL;
566 list_add(&entry->tv.head, validated);
569 void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo)
571 struct amdgpu_bo *abo;
572 struct amdgpu_vm_bo_base *bo_base;
574 if (!amdgpu_bo_is_amdgpu_bo(bo))
577 if (bo->mem.placement & TTM_PL_FLAG_NO_EVICT)
580 abo = ttm_to_amdgpu_bo(bo);
583 for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) {
584 struct amdgpu_vm *vm = bo_base->vm;
586 if (abo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
587 vm->bulk_moveable = false;
592 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
594 * @adev: amdgpu device pointer
595 * @vm: vm providing the BOs
597 * Move all BOs to the end of LRU and remember their positions to put them
600 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
601 struct amdgpu_vm *vm)
603 struct ttm_bo_global *glob = adev->mman.bdev.glob;
604 struct amdgpu_vm_bo_base *bo_base;
607 if (vm->bulk_moveable) {
608 spin_lock(&glob->lru_lock);
609 ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
610 spin_unlock(&glob->lru_lock);
615 memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));
617 spin_lock(&glob->lru_lock);
618 list_for_each_entry(bo_base, &vm->idle, vm_status) {
619 struct amdgpu_bo *bo = bo_base->bo;
624 ttm_bo_move_to_lru_tail(&bo->tbo, &vm->lru_bulk_move);
626 ttm_bo_move_to_lru_tail(&bo->shadow->tbo,
629 spin_unlock(&glob->lru_lock);
631 vm->bulk_moveable = true;
635 * amdgpu_vm_validate_pt_bos - validate the page table BOs
637 * @adev: amdgpu device pointer
638 * @vm: vm providing the BOs
639 * @validate: callback to do the validation
640 * @param: parameter for the validation callback
642 * Validate the page table BOs on command submission if neccessary.
647 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
648 int (*validate)(void *p, struct amdgpu_bo *bo),
651 struct amdgpu_vm_bo_base *bo_base, *tmp;
654 vm->bulk_moveable &= list_empty(&vm->evicted);
656 list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
657 struct amdgpu_bo *bo = bo_base->bo;
659 r = validate(param, bo);
663 if (bo->tbo.type != ttm_bo_type_kernel) {
664 amdgpu_vm_bo_moved(bo_base);
666 vm->update_funcs->map_table(bo);
668 amdgpu_vm_bo_relocated(bo_base);
670 amdgpu_vm_bo_idle(bo_base);
678 * amdgpu_vm_ready - check VM is ready for updates
682 * Check if all VM PDs/PTs are ready for updates
685 * True if eviction list is empty.
687 bool amdgpu_vm_ready(struct amdgpu_vm *vm)
689 return list_empty(&vm->evicted);
693 * amdgpu_vm_clear_bo - initially clear the PDs/PTs
695 * @adev: amdgpu_device pointer
696 * @vm: VM to clear BO from
699 * Root PD needs to be reserved when calling this.
702 * 0 on success, errno otherwise.
704 static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
705 struct amdgpu_vm *vm,
706 struct amdgpu_bo *bo)
708 struct ttm_operation_ctx ctx = { true, false };
709 unsigned level = adev->vm_manager.root_level;
710 struct amdgpu_vm_update_params params;
711 struct amdgpu_bo *ancestor = bo;
712 unsigned entries, ats_entries;
716 /* Figure out our place in the hierarchy */
717 if (ancestor->parent) {
719 while (ancestor->parent->parent) {
721 ancestor = ancestor->parent;
725 entries = amdgpu_bo_size(bo) / 8;
726 if (!vm->pte_support_ats) {
729 } else if (!bo->parent) {
730 ats_entries = amdgpu_vm_num_ats_entries(adev);
731 ats_entries = min(ats_entries, entries);
732 entries -= ats_entries;
735 struct amdgpu_vm_pt *pt;
737 pt = container_of(ancestor->vm_bo, struct amdgpu_vm_pt, base);
738 ats_entries = amdgpu_vm_num_ats_entries(adev);
739 if ((pt - vm->root.entries) >= ats_entries) {
742 ats_entries = entries;
747 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
752 r = ttm_bo_validate(&bo->shadow->tbo, &bo->shadow->placement,
758 r = vm->update_funcs->map_table(bo);
762 memset(¶ms, 0, sizeof(params));
766 r = vm->update_funcs->prepare(¶ms, AMDGPU_FENCE_OWNER_KFD, NULL);
772 uint64_t value = 0, flags;
774 flags = AMDGPU_PTE_DEFAULT_ATC;
775 if (level != AMDGPU_VM_PTB) {
776 /* Handle leaf PDEs as PTEs */
777 flags |= AMDGPU_PDE_PTE;
778 amdgpu_gmc_get_vm_pde(adev, level, &value, &flags);
781 r = vm->update_funcs->update(¶ms, bo, addr, 0, ats_entries,
786 addr += ats_entries * 8;
790 uint64_t value = 0, flags = 0;
792 if (adev->asic_type >= CHIP_VEGA10) {
793 if (level != AMDGPU_VM_PTB) {
794 /* Handle leaf PDEs as PTEs */
795 flags |= AMDGPU_PDE_PTE;
796 amdgpu_gmc_get_vm_pde(adev, level,
799 /* Workaround for fault priority problem on GMC9 */
800 flags = AMDGPU_PTE_EXECUTABLE;
804 r = vm->update_funcs->update(¶ms, bo, addr, 0, entries,
810 return vm->update_funcs->commit(¶ms, NULL);
814 * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation
816 * @adev: amdgpu_device pointer
818 * @bp: resulting BO allocation parameters
820 static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
821 int level, struct amdgpu_bo_param *bp)
823 memset(bp, 0, sizeof(*bp));
825 bp->size = amdgpu_vm_bo_size(adev, level);
826 bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
827 bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
828 bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
829 bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
830 AMDGPU_GEM_CREATE_CPU_GTT_USWC;
831 if (vm->use_cpu_for_update)
832 bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
833 else if (!vm->root.base.bo || vm->root.base.bo->shadow)
834 bp->flags |= AMDGPU_GEM_CREATE_SHADOW;
835 bp->type = ttm_bo_type_kernel;
836 if (vm->root.base.bo)
837 bp->resv = vm->root.base.bo->tbo.base.resv;
841 * amdgpu_vm_alloc_pts - Allocate a specific page table
843 * @adev: amdgpu_device pointer
844 * @vm: VM to allocate page tables for
845 * @cursor: Which page table to allocate
847 * Make sure a specific page table or directory is allocated.
850 * 1 if page table needed to be allocated, 0 if page table was already
851 * allocated, negative errno if an error occurred.
853 static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
854 struct amdgpu_vm *vm,
855 struct amdgpu_vm_pt_cursor *cursor)
857 struct amdgpu_vm_pt *entry = cursor->entry;
858 struct amdgpu_bo_param bp;
859 struct amdgpu_bo *pt;
862 if (cursor->level < AMDGPU_VM_PTB && !entry->entries) {
863 unsigned num_entries;
865 num_entries = amdgpu_vm_num_entries(adev, cursor->level);
866 entry->entries = kvmalloc_array(num_entries,
867 sizeof(*entry->entries),
868 GFP_KERNEL | __GFP_ZERO);
876 amdgpu_vm_bo_param(adev, vm, cursor->level, &bp);
878 r = amdgpu_bo_create(adev, &bp, &pt);
882 /* Keep a reference to the root directory to avoid
883 * freeing them up in the wrong order.
885 pt->parent = amdgpu_bo_ref(cursor->parent->base.bo);
886 amdgpu_vm_bo_base_init(&entry->base, vm, pt);
888 r = amdgpu_vm_clear_bo(adev, vm, pt);
895 amdgpu_bo_unref(&pt->shadow);
896 amdgpu_bo_unref(&pt);
901 * amdgpu_vm_free_table - fre one PD/PT
903 * @entry: PDE to free
905 static void amdgpu_vm_free_table(struct amdgpu_vm_pt *entry)
907 if (entry->base.bo) {
908 entry->base.bo->vm_bo = NULL;
909 list_del(&entry->base.vm_status);
910 amdgpu_bo_unref(&entry->base.bo->shadow);
911 amdgpu_bo_unref(&entry->base.bo);
913 kvfree(entry->entries);
914 entry->entries = NULL;
918 * amdgpu_vm_free_pts - free PD/PT levels
920 * @adev: amdgpu device structure
921 * @vm: amdgpu vm structure
922 * @start: optional cursor where to start freeing PDs/PTs
924 * Free the page directory or page table level and all sub levels.
926 static void amdgpu_vm_free_pts(struct amdgpu_device *adev,
927 struct amdgpu_vm *vm,
928 struct amdgpu_vm_pt_cursor *start)
930 struct amdgpu_vm_pt_cursor cursor;
931 struct amdgpu_vm_pt *entry;
933 vm->bulk_moveable = false;
935 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)
936 amdgpu_vm_free_table(entry);
939 amdgpu_vm_free_table(start->entry);
943 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
945 * @adev: amdgpu_device pointer
947 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
949 const struct amdgpu_ip_block *ip_block;
950 bool has_compute_vm_bug;
951 struct amdgpu_ring *ring;
954 has_compute_vm_bug = false;
956 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
958 /* Compute has a VM bug for GFX version < 7.
959 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
960 if (ip_block->version->major <= 7)
961 has_compute_vm_bug = true;
962 else if (ip_block->version->major == 8)
963 if (adev->gfx.mec_fw_version < 673)
964 has_compute_vm_bug = true;
967 for (i = 0; i < adev->num_rings; i++) {
968 ring = adev->rings[i];
969 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
970 /* only compute rings */
971 ring->has_compute_vm_bug = has_compute_vm_bug;
973 ring->has_compute_vm_bug = false;
978 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
980 * @ring: ring on which the job will be submitted
981 * @job: job to submit
984 * True if sync is needed.
986 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
987 struct amdgpu_job *job)
989 struct amdgpu_device *adev = ring->adev;
990 unsigned vmhub = ring->funcs->vmhub;
991 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
992 struct amdgpu_vmid *id;
993 bool gds_switch_needed;
994 bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
998 id = &id_mgr->ids[job->vmid];
999 gds_switch_needed = ring->funcs->emit_gds_switch && (
1000 id->gds_base != job->gds_base ||
1001 id->gds_size != job->gds_size ||
1002 id->gws_base != job->gws_base ||
1003 id->gws_size != job->gws_size ||
1004 id->oa_base != job->oa_base ||
1005 id->oa_size != job->oa_size);
1007 if (amdgpu_vmid_had_gpu_reset(adev, id))
1010 return vm_flush_needed || gds_switch_needed;
1014 * amdgpu_vm_flush - hardware flush the vm
1016 * @ring: ring to use for flush
1018 * @need_pipe_sync: is pipe sync needed
1020 * Emit a VM flush when it is necessary.
1023 * 0 on success, errno otherwise.
1025 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync)
1027 struct amdgpu_device *adev = ring->adev;
1028 unsigned vmhub = ring->funcs->vmhub;
1029 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1030 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
1031 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
1032 id->gds_base != job->gds_base ||
1033 id->gds_size != job->gds_size ||
1034 id->gws_base != job->gws_base ||
1035 id->gws_size != job->gws_size ||
1036 id->oa_base != job->oa_base ||
1037 id->oa_size != job->oa_size);
1038 bool vm_flush_needed = job->vm_needs_flush;
1039 struct dma_fence *fence = NULL;
1040 bool pasid_mapping_needed;
1041 unsigned patch_offset = 0;
1044 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
1045 gds_switch_needed = true;
1046 vm_flush_needed = true;
1047 pasid_mapping_needed = true;
1050 mutex_lock(&id_mgr->lock);
1051 if (id->pasid != job->pasid || !id->pasid_mapping ||
1052 !dma_fence_is_signaled(id->pasid_mapping))
1053 pasid_mapping_needed = true;
1054 mutex_unlock(&id_mgr->lock);
1056 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
1057 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
1058 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
1059 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
1060 ring->funcs->emit_wreg;
1062 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
1065 if (ring->funcs->init_cond_exec)
1066 patch_offset = amdgpu_ring_init_cond_exec(ring);
1069 amdgpu_ring_emit_pipeline_sync(ring);
1071 if (vm_flush_needed) {
1072 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
1073 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
1076 if (pasid_mapping_needed)
1077 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
1079 if (vm_flush_needed || pasid_mapping_needed) {
1080 r = amdgpu_fence_emit(ring, &fence, 0);
1085 if (vm_flush_needed) {
1086 mutex_lock(&id_mgr->lock);
1087 dma_fence_put(id->last_flush);
1088 id->last_flush = dma_fence_get(fence);
1089 id->current_gpu_reset_count =
1090 atomic_read(&adev->gpu_reset_counter);
1091 mutex_unlock(&id_mgr->lock);
1094 if (pasid_mapping_needed) {
1095 mutex_lock(&id_mgr->lock);
1096 id->pasid = job->pasid;
1097 dma_fence_put(id->pasid_mapping);
1098 id->pasid_mapping = dma_fence_get(fence);
1099 mutex_unlock(&id_mgr->lock);
1101 dma_fence_put(fence);
1103 if (ring->funcs->emit_gds_switch && gds_switch_needed) {
1104 id->gds_base = job->gds_base;
1105 id->gds_size = job->gds_size;
1106 id->gws_base = job->gws_base;
1107 id->gws_size = job->gws_size;
1108 id->oa_base = job->oa_base;
1109 id->oa_size = job->oa_size;
1110 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
1111 job->gds_size, job->gws_base,
1112 job->gws_size, job->oa_base,
1116 if (ring->funcs->patch_cond_exec)
1117 amdgpu_ring_patch_cond_exec(ring, patch_offset);
1119 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
1120 if (ring->funcs->emit_switch_buffer) {
1121 amdgpu_ring_emit_switch_buffer(ring);
1122 amdgpu_ring_emit_switch_buffer(ring);
1128 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
1131 * @bo: requested buffer object
1133 * Find @bo inside the requested vm.
1134 * Search inside the @bos vm list for the requested vm
1135 * Returns the found bo_va or NULL if none is found
1137 * Object has to be reserved!
1140 * Found bo_va or NULL.
1142 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
1143 struct amdgpu_bo *bo)
1145 struct amdgpu_vm_bo_base *base;
1147 for (base = bo->vm_bo; base; base = base->next) {
1151 return container_of(base, struct amdgpu_bo_va, base);
1157 * amdgpu_vm_map_gart - Resolve gart mapping of addr
1159 * @pages_addr: optional DMA address to use for lookup
1160 * @addr: the unmapped addr
1162 * Look up the physical address of the page that the pte resolves
1166 * The pointer for the page table entry.
1168 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
1172 /* page table offset */
1173 result = pages_addr[addr >> PAGE_SHIFT];
1175 /* in case cpu page size != gpu page size*/
1176 result |= addr & (~PAGE_MASK);
1178 result &= 0xFFFFFFFFFFFFF000ULL;
1184 * amdgpu_vm_update_pde - update a single level in the hierarchy
1186 * @param: parameters for the update
1188 * @entry: entry to update
1190 * Makes sure the requested entry in parent is up to date.
1192 static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params,
1193 struct amdgpu_vm *vm,
1194 struct amdgpu_vm_pt *entry)
1196 struct amdgpu_vm_pt *parent = amdgpu_vm_pt_parent(entry);
1197 struct amdgpu_bo *bo = parent->base.bo, *pbo;
1198 uint64_t pde, pt, flags;
1201 for (level = 0, pbo = bo->parent; pbo; ++level)
1204 level += params->adev->vm_manager.root_level;
1205 amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags);
1206 pde = (entry - parent->entries) * 8;
1207 return vm->update_funcs->update(params, bo, pde, pt, 1, 0, flags);
1211 * amdgpu_vm_invalidate_pds - mark all PDs as invalid
1213 * @adev: amdgpu_device pointer
1216 * Mark all PD level as invalid after an error.
1218 static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev,
1219 struct amdgpu_vm *vm)
1221 struct amdgpu_vm_pt_cursor cursor;
1222 struct amdgpu_vm_pt *entry;
1224 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, NULL, cursor, entry)
1225 if (entry->base.bo && !entry->base.moved)
1226 amdgpu_vm_bo_relocated(&entry->base);
1230 * amdgpu_vm_update_pdes - make sure that all directories are valid
1232 * @adev: amdgpu_device pointer
1234 * @direct: submit directly to the paging queue
1236 * Makes sure all directories are up to date.
1239 * 0 for success, error for failure.
1241 int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
1242 struct amdgpu_vm *vm, bool direct)
1244 struct amdgpu_vm_update_params params;
1247 if (list_empty(&vm->relocated))
1250 memset(¶ms, 0, sizeof(params));
1253 params.direct = direct;
1255 r = vm->update_funcs->prepare(¶ms, AMDGPU_FENCE_OWNER_VM, NULL);
1259 while (!list_empty(&vm->relocated)) {
1260 struct amdgpu_vm_pt *entry;
1262 entry = list_first_entry(&vm->relocated, struct amdgpu_vm_pt,
1264 amdgpu_vm_bo_idle(&entry->base);
1266 r = amdgpu_vm_update_pde(¶ms, vm, entry);
1271 r = vm->update_funcs->commit(¶ms, &vm->last_update);
1277 amdgpu_vm_invalidate_pds(adev, vm);
1282 * amdgpu_vm_update_flags - figure out flags for PTE updates
1284 * Make sure to set the right flags for the PTEs at the desired level.
1286 static void amdgpu_vm_update_flags(struct amdgpu_vm_update_params *params,
1287 struct amdgpu_bo *bo, unsigned level,
1288 uint64_t pe, uint64_t addr,
1289 unsigned count, uint32_t incr,
1293 if (level != AMDGPU_VM_PTB) {
1294 flags |= AMDGPU_PDE_PTE;
1295 amdgpu_gmc_get_vm_pde(params->adev, level, &addr, &flags);
1297 } else if (params->adev->asic_type >= CHIP_VEGA10 &&
1298 !(flags & AMDGPU_PTE_VALID) &&
1299 !(flags & AMDGPU_PTE_PRT)) {
1301 /* Workaround for fault priority problem on GMC9 */
1302 flags |= AMDGPU_PTE_EXECUTABLE;
1305 params->vm->update_funcs->update(params, bo, pe, addr, count, incr,
1310 * amdgpu_vm_fragment - get fragment for PTEs
1312 * @params: see amdgpu_vm_update_params definition
1313 * @start: first PTE to handle
1314 * @end: last PTE to handle
1315 * @flags: hw mapping flags
1316 * @frag: resulting fragment size
1317 * @frag_end: end of this fragment
1319 * Returns the first possible fragment for the start and end address.
1321 static void amdgpu_vm_fragment(struct amdgpu_vm_update_params *params,
1322 uint64_t start, uint64_t end, uint64_t flags,
1323 unsigned int *frag, uint64_t *frag_end)
1326 * The MC L1 TLB supports variable sized pages, based on a fragment
1327 * field in the PTE. When this field is set to a non-zero value, page
1328 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1329 * flags are considered valid for all PTEs within the fragment range
1330 * and corresponding mappings are assumed to be physically contiguous.
1332 * The L1 TLB can store a single PTE for the whole fragment,
1333 * significantly increasing the space available for translation
1334 * caching. This leads to large improvements in throughput when the
1335 * TLB is under pressure.
1337 * The L2 TLB distributes small and large fragments into two
1338 * asymmetric partitions. The large fragment cache is significantly
1339 * larger. Thus, we try to use large fragments wherever possible.
1340 * Userspace can support this by aligning virtual base address and
1341 * allocation size to the fragment size.
1343 * Starting with Vega10 the fragment size only controls the L1. The L2
1344 * is now directly feed with small/huge/giant pages from the walker.
1348 if (params->adev->asic_type < CHIP_VEGA10)
1349 max_frag = params->adev->vm_manager.fragment_size;
1353 /* system pages are non continuously */
1354 if (params->pages_addr) {
1360 /* This intentionally wraps around if no bit is set */
1361 *frag = min((unsigned)ffs(start) - 1, (unsigned)fls64(end - start) - 1);
1362 if (*frag >= max_frag) {
1364 *frag_end = end & ~((1ULL << max_frag) - 1);
1366 *frag_end = start + (1 << *frag);
1371 * amdgpu_vm_update_ptes - make sure that page tables are valid
1373 * @params: see amdgpu_vm_update_params definition
1374 * @start: start of GPU address range
1375 * @end: end of GPU address range
1376 * @dst: destination address to map to, the next dst inside the function
1377 * @flags: mapping flags
1379 * Update the page tables in the range @start - @end.
1382 * 0 for success, -EINVAL for failure.
1384 static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
1385 uint64_t start, uint64_t end,
1386 uint64_t dst, uint64_t flags)
1388 struct amdgpu_device *adev = params->adev;
1389 struct amdgpu_vm_pt_cursor cursor;
1390 uint64_t frag_start = start, frag_end;
1394 /* figure out the initial fragment */
1395 amdgpu_vm_fragment(params, frag_start, end, flags, &frag, &frag_end);
1397 /* walk over the address space and update the PTs */
1398 amdgpu_vm_pt_start(adev, params->vm, start, &cursor);
1399 while (cursor.pfn < end) {
1400 unsigned shift, parent_shift, mask;
1401 uint64_t incr, entry_end, pe_start;
1402 struct amdgpu_bo *pt;
1404 r = amdgpu_vm_alloc_pts(params->adev, params->vm, &cursor);
1408 pt = cursor.entry->base.bo;
1410 /* The root level can't be a huge page */
1411 if (cursor.level == adev->vm_manager.root_level) {
1412 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1417 shift = amdgpu_vm_level_shift(adev, cursor.level);
1418 parent_shift = amdgpu_vm_level_shift(adev, cursor.level - 1);
1419 if (adev->asic_type < CHIP_VEGA10 &&
1420 (flags & AMDGPU_PTE_VALID)) {
1421 /* No huge page support before GMC v9 */
1422 if (cursor.level != AMDGPU_VM_PTB) {
1423 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1427 } else if (frag < shift) {
1428 /* We can't use this level when the fragment size is
1429 * smaller than the address shift. Go to the next
1430 * child entry and try again.
1432 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1435 } else if (frag >= parent_shift &&
1436 cursor.level - 1 != adev->vm_manager.root_level) {
1437 /* If the fragment size is even larger than the parent
1438 * shift we should go up one level and check it again
1439 * unless one level up is the root level.
1441 if (!amdgpu_vm_pt_ancestor(&cursor))
1446 /* Looks good so far, calculate parameters for the update */
1447 incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift;
1448 mask = amdgpu_vm_entries_mask(adev, cursor.level);
1449 pe_start = ((cursor.pfn >> shift) & mask) * 8;
1450 entry_end = (uint64_t)(mask + 1) << shift;
1451 entry_end += cursor.pfn & ~(entry_end - 1);
1452 entry_end = min(entry_end, end);
1455 uint64_t upd_end = min(entry_end, frag_end);
1456 unsigned nptes = (upd_end - frag_start) >> shift;
1458 amdgpu_vm_update_flags(params, pt, cursor.level,
1459 pe_start, dst, nptes, incr,
1460 flags | AMDGPU_PTE_FRAG(frag));
1462 pe_start += nptes * 8;
1463 dst += (uint64_t)nptes * AMDGPU_GPU_PAGE_SIZE << shift;
1465 frag_start = upd_end;
1466 if (frag_start >= frag_end) {
1467 /* figure out the next fragment */
1468 amdgpu_vm_fragment(params, frag_start, end,
1469 flags, &frag, &frag_end);
1473 } while (frag_start < entry_end);
1475 if (amdgpu_vm_pt_descendant(adev, &cursor)) {
1476 /* Free all child entries */
1477 while (cursor.pfn < frag_start) {
1478 amdgpu_vm_free_pts(adev, params->vm, &cursor);
1479 amdgpu_vm_pt_next(adev, &cursor);
1482 } else if (frag >= shift) {
1483 /* or just move on to the next on the same level. */
1484 amdgpu_vm_pt_next(adev, &cursor);
1492 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1494 * @adev: amdgpu_device pointer
1496 * @direct: direct submission in a page fault
1497 * @exclusive: fence we need to sync to
1498 * @start: start of mapped range
1499 * @last: last mapped entry
1500 * @flags: flags for the entries
1501 * @addr: addr to set the area to
1502 * @pages_addr: DMA addresses to use for mapping
1503 * @fence: optional resulting fence
1505 * Fill in the page table entries between @start and @last.
1508 * 0 for success, -EINVAL for failure.
1510 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1511 struct amdgpu_vm *vm, bool direct,
1512 struct dma_fence *exclusive,
1513 uint64_t start, uint64_t last,
1514 uint64_t flags, uint64_t addr,
1515 dma_addr_t *pages_addr,
1516 struct dma_fence **fence)
1518 struct amdgpu_vm_update_params params;
1519 void *owner = AMDGPU_FENCE_OWNER_VM;
1522 memset(¶ms, 0, sizeof(params));
1525 params.direct = direct;
1526 params.pages_addr = pages_addr;
1528 /* sync to everything except eviction fences on unmapping */
1529 if (!(flags & AMDGPU_PTE_VALID))
1530 owner = AMDGPU_FENCE_OWNER_KFD;
1532 r = vm->update_funcs->prepare(¶ms, owner, exclusive);
1536 r = amdgpu_vm_update_ptes(¶ms, start, last + 1, addr, flags);
1540 return vm->update_funcs->commit(¶ms, fence);
1544 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
1546 * @adev: amdgpu_device pointer
1547 * @exclusive: fence we need to sync to
1548 * @pages_addr: DMA addresses to use for mapping
1550 * @mapping: mapped range and flags to use for the update
1551 * @flags: HW flags for the mapping
1552 * @bo_adev: amdgpu_device pointer that bo actually been allocated
1553 * @nodes: array of drm_mm_nodes with the MC addresses
1554 * @fence: optional resulting fence
1556 * Split the mapping into smaller chunks so that each update fits
1560 * 0 for success, -EINVAL for failure.
1562 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
1563 struct dma_fence *exclusive,
1564 dma_addr_t *pages_addr,
1565 struct amdgpu_vm *vm,
1566 struct amdgpu_bo_va_mapping *mapping,
1568 struct amdgpu_device *bo_adev,
1569 struct drm_mm_node *nodes,
1570 struct dma_fence **fence)
1572 unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size;
1573 uint64_t pfn, start = mapping->start;
1576 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1577 * but in case of something, we filter the flags in first place
1579 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1580 flags &= ~AMDGPU_PTE_READABLE;
1581 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1582 flags &= ~AMDGPU_PTE_WRITEABLE;
1584 /* Apply ASIC specific mapping flags */
1585 amdgpu_gmc_get_vm_pte(adev, mapping, &flags);
1587 trace_amdgpu_vm_bo_update(mapping);
1589 pfn = mapping->offset >> PAGE_SHIFT;
1591 while (pfn >= nodes->size) {
1598 dma_addr_t *dma_addr = NULL;
1599 uint64_t max_entries;
1600 uint64_t addr, last;
1603 addr = nodes->start << PAGE_SHIFT;
1604 max_entries = (nodes->size - pfn) *
1605 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1608 max_entries = S64_MAX;
1615 count < max_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1617 uint64_t idx = pfn + count;
1619 if (pages_addr[idx] !=
1620 (pages_addr[idx - 1] + PAGE_SIZE))
1624 if (count < min_linear_pages) {
1625 addr = pfn << PAGE_SHIFT;
1626 dma_addr = pages_addr;
1628 addr = pages_addr[pfn];
1629 max_entries = count * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1632 } else if (flags & AMDGPU_PTE_VALID) {
1633 addr += bo_adev->vm_manager.vram_base_offset;
1634 addr += pfn << PAGE_SHIFT;
1637 last = min((uint64_t)mapping->last, start + max_entries - 1);
1638 r = amdgpu_vm_bo_update_mapping(adev, vm, false, exclusive,
1639 start, last, flags, addr,
1644 pfn += (last - start + 1) / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1645 if (nodes && nodes->size == pfn) {
1651 } while (unlikely(start != mapping->last + 1));
1657 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1659 * @adev: amdgpu_device pointer
1660 * @bo_va: requested BO and VM object
1661 * @clear: if true clear the entries
1663 * Fill in the page table entries for @bo_va.
1666 * 0 for success, -EINVAL for failure.
1668 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
1669 struct amdgpu_bo_va *bo_va,
1672 struct amdgpu_bo *bo = bo_va->base.bo;
1673 struct amdgpu_vm *vm = bo_va->base.vm;
1674 struct amdgpu_bo_va_mapping *mapping;
1675 dma_addr_t *pages_addr = NULL;
1676 struct ttm_mem_reg *mem;
1677 struct drm_mm_node *nodes;
1678 struct dma_fence *exclusive, **last_update;
1680 struct amdgpu_device *bo_adev = adev;
1688 struct ttm_dma_tt *ttm;
1691 nodes = mem->mm_node;
1692 if (mem->mem_type == TTM_PL_TT) {
1693 ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm);
1694 pages_addr = ttm->dma_address;
1696 exclusive = bo->tbo.moving;
1700 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1701 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1706 if (clear || (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv))
1707 last_update = &vm->last_update;
1709 last_update = &bo_va->last_pt_update;
1711 if (!clear && bo_va->base.moved) {
1712 bo_va->base.moved = false;
1713 list_splice_init(&bo_va->valids, &bo_va->invalids);
1715 } else if (bo_va->cleared != clear) {
1716 list_splice_init(&bo_va->valids, &bo_va->invalids);
1719 list_for_each_entry(mapping, &bo_va->invalids, list) {
1720 r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm,
1721 mapping, flags, bo_adev, nodes,
1727 if (vm->use_cpu_for_update) {
1730 amdgpu_asic_flush_hdp(adev, NULL);
1733 /* If the BO is not in its preferred location add it back to
1734 * the evicted list so that it gets validated again on the
1735 * next command submission.
1737 if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) {
1738 uint32_t mem_type = bo->tbo.mem.mem_type;
1740 if (!(bo->preferred_domains & amdgpu_mem_type_to_domain(mem_type)))
1741 amdgpu_vm_bo_evicted(&bo_va->base);
1743 amdgpu_vm_bo_idle(&bo_va->base);
1745 amdgpu_vm_bo_done(&bo_va->base);
1748 list_splice_init(&bo_va->invalids, &bo_va->valids);
1749 bo_va->cleared = clear;
1751 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1752 list_for_each_entry(mapping, &bo_va->valids, list)
1753 trace_amdgpu_vm_bo_mapping(mapping);
1760 * amdgpu_vm_update_prt_state - update the global PRT state
1762 * @adev: amdgpu_device pointer
1764 static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1766 unsigned long flags;
1769 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1770 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1771 adev->gmc.gmc_funcs->set_prt(adev, enable);
1772 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1776 * amdgpu_vm_prt_get - add a PRT user
1778 * @adev: amdgpu_device pointer
1780 static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1782 if (!adev->gmc.gmc_funcs->set_prt)
1785 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1786 amdgpu_vm_update_prt_state(adev);
1790 * amdgpu_vm_prt_put - drop a PRT user
1792 * @adev: amdgpu_device pointer
1794 static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1796 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1797 amdgpu_vm_update_prt_state(adev);
1801 * amdgpu_vm_prt_cb - callback for updating the PRT status
1803 * @fence: fence for the callback
1804 * @_cb: the callback function
1806 static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1808 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1810 amdgpu_vm_prt_put(cb->adev);
1815 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1817 * @adev: amdgpu_device pointer
1818 * @fence: fence for the callback
1820 static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1821 struct dma_fence *fence)
1823 struct amdgpu_prt_cb *cb;
1825 if (!adev->gmc.gmc_funcs->set_prt)
1828 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1830 /* Last resort when we are OOM */
1832 dma_fence_wait(fence, false);
1834 amdgpu_vm_prt_put(adev);
1837 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1839 amdgpu_vm_prt_cb(fence, &cb->cb);
1844 * amdgpu_vm_free_mapping - free a mapping
1846 * @adev: amdgpu_device pointer
1848 * @mapping: mapping to be freed
1849 * @fence: fence of the unmap operation
1851 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1853 static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1854 struct amdgpu_vm *vm,
1855 struct amdgpu_bo_va_mapping *mapping,
1856 struct dma_fence *fence)
1858 if (mapping->flags & AMDGPU_PTE_PRT)
1859 amdgpu_vm_add_prt_cb(adev, fence);
1864 * amdgpu_vm_prt_fini - finish all prt mappings
1866 * @adev: amdgpu_device pointer
1869 * Register a cleanup callback to disable PRT support after VM dies.
1871 static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1873 struct dma_resv *resv = vm->root.base.bo->tbo.base.resv;
1874 struct dma_fence *excl, **shared;
1875 unsigned i, shared_count;
1878 r = dma_resv_get_fences_rcu(resv, &excl,
1879 &shared_count, &shared);
1881 /* Not enough memory to grab the fence list, as last resort
1882 * block for all the fences to complete.
1884 dma_resv_wait_timeout_rcu(resv, true, false,
1885 MAX_SCHEDULE_TIMEOUT);
1889 /* Add a callback for each fence in the reservation object */
1890 amdgpu_vm_prt_get(adev);
1891 amdgpu_vm_add_prt_cb(adev, excl);
1893 for (i = 0; i < shared_count; ++i) {
1894 amdgpu_vm_prt_get(adev);
1895 amdgpu_vm_add_prt_cb(adev, shared[i]);
1902 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1904 * @adev: amdgpu_device pointer
1906 * @fence: optional resulting fence (unchanged if no work needed to be done
1907 * or if an error occurred)
1909 * Make sure all freed BOs are cleared in the PT.
1910 * PTs have to be reserved and mutex must be locked!
1916 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1917 struct amdgpu_vm *vm,
1918 struct dma_fence **fence)
1920 struct amdgpu_bo_va_mapping *mapping;
1921 uint64_t init_pte_value = 0;
1922 struct dma_fence *f = NULL;
1925 while (!list_empty(&vm->freed)) {
1926 mapping = list_first_entry(&vm->freed,
1927 struct amdgpu_bo_va_mapping, list);
1928 list_del(&mapping->list);
1930 if (vm->pte_support_ats &&
1931 mapping->start < AMDGPU_GMC_HOLE_START)
1932 init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
1934 r = amdgpu_vm_bo_update_mapping(adev, vm, false, NULL,
1935 mapping->start, mapping->last,
1936 init_pte_value, 0, NULL, &f);
1937 amdgpu_vm_free_mapping(adev, vm, mapping, f);
1945 dma_fence_put(*fence);
1956 * amdgpu_vm_handle_moved - handle moved BOs in the PT
1958 * @adev: amdgpu_device pointer
1961 * Make sure all BOs which are moved are updated in the PTs.
1966 * PTs have to be reserved!
1968 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
1969 struct amdgpu_vm *vm)
1971 struct amdgpu_bo_va *bo_va, *tmp;
1972 struct dma_resv *resv;
1976 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
1977 /* Per VM BOs never need to bo cleared in the page tables */
1978 r = amdgpu_vm_bo_update(adev, bo_va, false);
1983 spin_lock(&vm->invalidated_lock);
1984 while (!list_empty(&vm->invalidated)) {
1985 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
1987 resv = bo_va->base.bo->tbo.base.resv;
1988 spin_unlock(&vm->invalidated_lock);
1990 /* Try to reserve the BO to avoid clearing its ptes */
1991 if (!amdgpu_vm_debug && dma_resv_trylock(resv))
1993 /* Somebody else is using the BO right now */
1997 r = amdgpu_vm_bo_update(adev, bo_va, clear);
2002 dma_resv_unlock(resv);
2003 spin_lock(&vm->invalidated_lock);
2005 spin_unlock(&vm->invalidated_lock);
2011 * amdgpu_vm_bo_add - add a bo to a specific vm
2013 * @adev: amdgpu_device pointer
2015 * @bo: amdgpu buffer object
2017 * Add @bo into the requested vm.
2018 * Add @bo to the list of bos associated with the vm
2021 * Newly added bo_va or NULL for failure
2023 * Object has to be reserved!
2025 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2026 struct amdgpu_vm *vm,
2027 struct amdgpu_bo *bo)
2029 struct amdgpu_bo_va *bo_va;
2031 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
2032 if (bo_va == NULL) {
2035 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
2037 bo_va->ref_count = 1;
2038 INIT_LIST_HEAD(&bo_va->valids);
2039 INIT_LIST_HEAD(&bo_va->invalids);
2041 if (bo && amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev)) &&
2042 (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM)) {
2043 bo_va->is_xgmi = true;
2044 mutex_lock(&adev->vm_manager.lock_pstate);
2045 /* Power up XGMI if it can be potentially used */
2046 if (++adev->vm_manager.xgmi_map_counter == 1)
2047 amdgpu_xgmi_set_pstate(adev, 1);
2048 mutex_unlock(&adev->vm_manager.lock_pstate);
2056 * amdgpu_vm_bo_insert_mapping - insert a new mapping
2058 * @adev: amdgpu_device pointer
2059 * @bo_va: bo_va to store the address
2060 * @mapping: the mapping to insert
2062 * Insert a new mapping into all structures.
2064 static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
2065 struct amdgpu_bo_va *bo_va,
2066 struct amdgpu_bo_va_mapping *mapping)
2068 struct amdgpu_vm *vm = bo_va->base.vm;
2069 struct amdgpu_bo *bo = bo_va->base.bo;
2071 mapping->bo_va = bo_va;
2072 list_add(&mapping->list, &bo_va->invalids);
2073 amdgpu_vm_it_insert(mapping, &vm->va);
2075 if (mapping->flags & AMDGPU_PTE_PRT)
2076 amdgpu_vm_prt_get(adev);
2078 if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv &&
2079 !bo_va->base.moved) {
2080 list_move(&bo_va->base.vm_status, &vm->moved);
2082 trace_amdgpu_vm_bo_map(bo_va, mapping);
2086 * amdgpu_vm_bo_map - map bo inside a vm
2088 * @adev: amdgpu_device pointer
2089 * @bo_va: bo_va to store the address
2090 * @saddr: where to map the BO
2091 * @offset: requested offset in the BO
2092 * @size: BO size in bytes
2093 * @flags: attributes of pages (read/write/valid/etc.)
2095 * Add a mapping of the BO at the specefied addr into the VM.
2098 * 0 for success, error for failure.
2100 * Object has to be reserved and unreserved outside!
2102 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2103 struct amdgpu_bo_va *bo_va,
2104 uint64_t saddr, uint64_t offset,
2105 uint64_t size, uint64_t flags)
2107 struct amdgpu_bo_va_mapping *mapping, *tmp;
2108 struct amdgpu_bo *bo = bo_va->base.bo;
2109 struct amdgpu_vm *vm = bo_va->base.vm;
2112 /* validate the parameters */
2113 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
2114 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
2117 /* make sure object fit at this offset */
2118 eaddr = saddr + size - 1;
2119 if (saddr >= eaddr ||
2120 (bo && offset + size > amdgpu_bo_size(bo)))
2123 saddr /= AMDGPU_GPU_PAGE_SIZE;
2124 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2126 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2128 /* bo and tmp overlap, invalid addr */
2129 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
2130 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
2131 tmp->start, tmp->last + 1);
2135 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2139 mapping->start = saddr;
2140 mapping->last = eaddr;
2141 mapping->offset = offset;
2142 mapping->flags = flags;
2144 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2150 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
2152 * @adev: amdgpu_device pointer
2153 * @bo_va: bo_va to store the address
2154 * @saddr: where to map the BO
2155 * @offset: requested offset in the BO
2156 * @size: BO size in bytes
2157 * @flags: attributes of pages (read/write/valid/etc.)
2159 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
2160 * mappings as we do so.
2163 * 0 for success, error for failure.
2165 * Object has to be reserved and unreserved outside!
2167 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
2168 struct amdgpu_bo_va *bo_va,
2169 uint64_t saddr, uint64_t offset,
2170 uint64_t size, uint64_t flags)
2172 struct amdgpu_bo_va_mapping *mapping;
2173 struct amdgpu_bo *bo = bo_va->base.bo;
2177 /* validate the parameters */
2178 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
2179 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
2182 /* make sure object fit at this offset */
2183 eaddr = saddr + size - 1;
2184 if (saddr >= eaddr ||
2185 (bo && offset + size > amdgpu_bo_size(bo)))
2188 /* Allocate all the needed memory */
2189 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2193 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
2199 saddr /= AMDGPU_GPU_PAGE_SIZE;
2200 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2202 mapping->start = saddr;
2203 mapping->last = eaddr;
2204 mapping->offset = offset;
2205 mapping->flags = flags;
2207 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2213 * amdgpu_vm_bo_unmap - remove bo mapping from vm
2215 * @adev: amdgpu_device pointer
2216 * @bo_va: bo_va to remove the address from
2217 * @saddr: where to the BO is mapped
2219 * Remove a mapping of the BO at the specefied addr from the VM.
2222 * 0 for success, error for failure.
2224 * Object has to be reserved and unreserved outside!
2226 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2227 struct amdgpu_bo_va *bo_va,
2230 struct amdgpu_bo_va_mapping *mapping;
2231 struct amdgpu_vm *vm = bo_va->base.vm;
2234 saddr /= AMDGPU_GPU_PAGE_SIZE;
2236 list_for_each_entry(mapping, &bo_va->valids, list) {
2237 if (mapping->start == saddr)
2241 if (&mapping->list == &bo_va->valids) {
2244 list_for_each_entry(mapping, &bo_va->invalids, list) {
2245 if (mapping->start == saddr)
2249 if (&mapping->list == &bo_va->invalids)
2253 list_del(&mapping->list);
2254 amdgpu_vm_it_remove(mapping, &vm->va);
2255 mapping->bo_va = NULL;
2256 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2259 list_add(&mapping->list, &vm->freed);
2261 amdgpu_vm_free_mapping(adev, vm, mapping,
2262 bo_va->last_pt_update);
2268 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
2270 * @adev: amdgpu_device pointer
2271 * @vm: VM structure to use
2272 * @saddr: start of the range
2273 * @size: size of the range
2275 * Remove all mappings in a range, split them as appropriate.
2278 * 0 for success, error for failure.
2280 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
2281 struct amdgpu_vm *vm,
2282 uint64_t saddr, uint64_t size)
2284 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
2288 eaddr = saddr + size - 1;
2289 saddr /= AMDGPU_GPU_PAGE_SIZE;
2290 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2292 /* Allocate all the needed memory */
2293 before = kzalloc(sizeof(*before), GFP_KERNEL);
2296 INIT_LIST_HEAD(&before->list);
2298 after = kzalloc(sizeof(*after), GFP_KERNEL);
2303 INIT_LIST_HEAD(&after->list);
2305 /* Now gather all removed mappings */
2306 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2308 /* Remember mapping split at the start */
2309 if (tmp->start < saddr) {
2310 before->start = tmp->start;
2311 before->last = saddr - 1;
2312 before->offset = tmp->offset;
2313 before->flags = tmp->flags;
2314 before->bo_va = tmp->bo_va;
2315 list_add(&before->list, &tmp->bo_va->invalids);
2318 /* Remember mapping split at the end */
2319 if (tmp->last > eaddr) {
2320 after->start = eaddr + 1;
2321 after->last = tmp->last;
2322 after->offset = tmp->offset;
2323 after->offset += after->start - tmp->start;
2324 after->flags = tmp->flags;
2325 after->bo_va = tmp->bo_va;
2326 list_add(&after->list, &tmp->bo_va->invalids);
2329 list_del(&tmp->list);
2330 list_add(&tmp->list, &removed);
2332 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
2335 /* And free them up */
2336 list_for_each_entry_safe(tmp, next, &removed, list) {
2337 amdgpu_vm_it_remove(tmp, &vm->va);
2338 list_del(&tmp->list);
2340 if (tmp->start < saddr)
2342 if (tmp->last > eaddr)
2346 list_add(&tmp->list, &vm->freed);
2347 trace_amdgpu_vm_bo_unmap(NULL, tmp);
2350 /* Insert partial mapping before the range */
2351 if (!list_empty(&before->list)) {
2352 amdgpu_vm_it_insert(before, &vm->va);
2353 if (before->flags & AMDGPU_PTE_PRT)
2354 amdgpu_vm_prt_get(adev);
2359 /* Insert partial mapping after the range */
2360 if (!list_empty(&after->list)) {
2361 amdgpu_vm_it_insert(after, &vm->va);
2362 if (after->flags & AMDGPU_PTE_PRT)
2363 amdgpu_vm_prt_get(adev);
2372 * amdgpu_vm_bo_lookup_mapping - find mapping by address
2374 * @vm: the requested VM
2375 * @addr: the address
2377 * Find a mapping by it's address.
2380 * The amdgpu_bo_va_mapping matching for addr or NULL
2383 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
2386 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
2390 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
2392 * @vm: the requested vm
2393 * @ticket: CS ticket
2395 * Trace all mappings of BOs reserved during a command submission.
2397 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
2399 struct amdgpu_bo_va_mapping *mapping;
2401 if (!trace_amdgpu_vm_bo_cs_enabled())
2404 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
2405 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
2406 if (mapping->bo_va && mapping->bo_va->base.bo) {
2407 struct amdgpu_bo *bo;
2409 bo = mapping->bo_va->base.bo;
2410 if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
2415 trace_amdgpu_vm_bo_cs(mapping);
2420 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2422 * @adev: amdgpu_device pointer
2423 * @bo_va: requested bo_va
2425 * Remove @bo_va->bo from the requested vm.
2427 * Object have to be reserved!
2429 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2430 struct amdgpu_bo_va *bo_va)
2432 struct amdgpu_bo_va_mapping *mapping, *next;
2433 struct amdgpu_bo *bo = bo_va->base.bo;
2434 struct amdgpu_vm *vm = bo_va->base.vm;
2435 struct amdgpu_vm_bo_base **base;
2438 if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
2439 vm->bulk_moveable = false;
2441 for (base = &bo_va->base.bo->vm_bo; *base;
2442 base = &(*base)->next) {
2443 if (*base != &bo_va->base)
2446 *base = bo_va->base.next;
2451 spin_lock(&vm->invalidated_lock);
2452 list_del(&bo_va->base.vm_status);
2453 spin_unlock(&vm->invalidated_lock);
2455 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2456 list_del(&mapping->list);
2457 amdgpu_vm_it_remove(mapping, &vm->va);
2458 mapping->bo_va = NULL;
2459 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2460 list_add(&mapping->list, &vm->freed);
2462 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2463 list_del(&mapping->list);
2464 amdgpu_vm_it_remove(mapping, &vm->va);
2465 amdgpu_vm_free_mapping(adev, vm, mapping,
2466 bo_va->last_pt_update);
2469 dma_fence_put(bo_va->last_pt_update);
2471 if (bo && bo_va->is_xgmi) {
2472 mutex_lock(&adev->vm_manager.lock_pstate);
2473 if (--adev->vm_manager.xgmi_map_counter == 0)
2474 amdgpu_xgmi_set_pstate(adev, 0);
2475 mutex_unlock(&adev->vm_manager.lock_pstate);
2482 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2484 * @adev: amdgpu_device pointer
2485 * @bo: amdgpu buffer object
2486 * @evicted: is the BO evicted
2488 * Mark @bo as invalid.
2490 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2491 struct amdgpu_bo *bo, bool evicted)
2493 struct amdgpu_vm_bo_base *bo_base;
2495 /* shadow bo doesn't have bo base, its validation needs its parent */
2496 if (bo->parent && bo->parent->shadow == bo)
2499 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
2500 struct amdgpu_vm *vm = bo_base->vm;
2502 if (evicted && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) {
2503 amdgpu_vm_bo_evicted(bo_base);
2509 bo_base->moved = true;
2511 if (bo->tbo.type == ttm_bo_type_kernel)
2512 amdgpu_vm_bo_relocated(bo_base);
2513 else if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
2514 amdgpu_vm_bo_moved(bo_base);
2516 amdgpu_vm_bo_invalidated(bo_base);
2521 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2526 * VM page table as power of two
2528 static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2530 /* Total bits covered by PD + PTs */
2531 unsigned bits = ilog2(vm_size) + 18;
2533 /* Make sure the PD is 4K in size up to 8GB address space.
2534 Above that split equal between PD and PTs */
2538 return ((bits + 3) / 2);
2542 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2544 * @adev: amdgpu_device pointer
2545 * @min_vm_size: the minimum vm size in GB if it's set auto
2546 * @fragment_size_default: Default PTE fragment size
2547 * @max_level: max VMPT level
2548 * @max_bits: max address space size in bits
2551 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2552 uint32_t fragment_size_default, unsigned max_level,
2555 unsigned int max_size = 1 << (max_bits - 30);
2556 unsigned int vm_size;
2559 /* adjust vm size first */
2560 if (amdgpu_vm_size != -1) {
2561 vm_size = amdgpu_vm_size;
2562 if (vm_size > max_size) {
2563 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2564 amdgpu_vm_size, max_size);
2569 unsigned int phys_ram_gb;
2571 /* Optimal VM size depends on the amount of physical
2572 * RAM available. Underlying requirements and
2575 * - Need to map system memory and VRAM from all GPUs
2576 * - VRAM from other GPUs not known here
2577 * - Assume VRAM <= system memory
2578 * - On GFX8 and older, VM space can be segmented for
2580 * - Need to allow room for fragmentation, guard pages etc.
2582 * This adds up to a rough guess of system memory x3.
2583 * Round up to power of two to maximize the available
2584 * VM size with the given page table size.
2587 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2588 (1 << 30) - 1) >> 30;
2589 vm_size = roundup_pow_of_two(
2590 min(max(phys_ram_gb * 3, min_vm_size), max_size));
2593 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2595 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2596 if (amdgpu_vm_block_size != -1)
2597 tmp >>= amdgpu_vm_block_size - 9;
2598 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2599 adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
2600 switch (adev->vm_manager.num_level) {
2602 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2605 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2608 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2611 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2613 /* block size depends on vm size and hw setup*/
2614 if (amdgpu_vm_block_size != -1)
2615 adev->vm_manager.block_size =
2616 min((unsigned)amdgpu_vm_block_size, max_bits
2617 - AMDGPU_GPU_PAGE_SHIFT
2618 - 9 * adev->vm_manager.num_level);
2619 else if (adev->vm_manager.num_level > 1)
2620 adev->vm_manager.block_size = 9;
2622 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2624 if (amdgpu_vm_fragment_size == -1)
2625 adev->vm_manager.fragment_size = fragment_size_default;
2627 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2629 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2630 vm_size, adev->vm_manager.num_level + 1,
2631 adev->vm_manager.block_size,
2632 adev->vm_manager.fragment_size);
2636 * amdgpu_vm_wait_idle - wait for the VM to become idle
2638 * @vm: VM object to wait for
2639 * @timeout: timeout to wait for VM to become idle
2641 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2643 return dma_resv_wait_timeout_rcu(vm->root.base.bo->tbo.base.resv,
2644 true, true, timeout);
2648 * amdgpu_vm_init - initialize a vm instance
2650 * @adev: amdgpu_device pointer
2652 * @vm_context: Indicates if it GFX or Compute context
2653 * @pasid: Process address space identifier
2658 * 0 for success, error for failure.
2660 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2661 int vm_context, unsigned int pasid)
2663 struct amdgpu_bo_param bp;
2664 struct amdgpu_bo *root;
2667 vm->va = RB_ROOT_CACHED;
2668 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2669 vm->reserved_vmid[i] = NULL;
2670 INIT_LIST_HEAD(&vm->evicted);
2671 INIT_LIST_HEAD(&vm->relocated);
2672 INIT_LIST_HEAD(&vm->moved);
2673 INIT_LIST_HEAD(&vm->idle);
2674 INIT_LIST_HEAD(&vm->invalidated);
2675 spin_lock_init(&vm->invalidated_lock);
2676 INIT_LIST_HEAD(&vm->freed);
2678 /* create scheduler entities for page table updates */
2679 r = drm_sched_entity_init(&vm->direct, adev->vm_manager.vm_pte_rqs,
2680 adev->vm_manager.vm_pte_num_rqs, NULL);
2684 r = drm_sched_entity_init(&vm->delayed, adev->vm_manager.vm_pte_rqs,
2685 adev->vm_manager.vm_pte_num_rqs, NULL);
2687 goto error_free_direct;
2689 vm->pte_support_ats = false;
2691 if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) {
2692 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2693 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2695 if (adev->asic_type == CHIP_RAVEN)
2696 vm->pte_support_ats = true;
2698 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2699 AMDGPU_VM_USE_CPU_FOR_GFX);
2701 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2702 vm->use_cpu_for_update ? "CPU" : "SDMA");
2703 WARN_ONCE((vm->use_cpu_for_update && !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2704 "CPU update of VM recommended only for large BAR system\n");
2706 if (vm->use_cpu_for_update)
2707 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2709 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2710 vm->last_update = NULL;
2712 amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, &bp);
2713 if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE)
2714 bp.flags &= ~AMDGPU_GEM_CREATE_SHADOW;
2715 r = amdgpu_bo_create(adev, &bp, &root);
2717 goto error_free_delayed;
2719 r = amdgpu_bo_reserve(root, true);
2721 goto error_free_root;
2723 r = dma_resv_reserve_shared(root->tbo.base.resv, 1);
2725 goto error_unreserve;
2727 amdgpu_vm_bo_base_init(&vm->root.base, vm, root);
2729 r = amdgpu_vm_clear_bo(adev, vm, root);
2731 goto error_unreserve;
2733 amdgpu_bo_unreserve(vm->root.base.bo);
2736 unsigned long flags;
2738 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2739 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
2741 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2743 goto error_free_root;
2748 INIT_KFIFO(vm->faults);
2753 amdgpu_bo_unreserve(vm->root.base.bo);
2756 amdgpu_bo_unref(&vm->root.base.bo->shadow);
2757 amdgpu_bo_unref(&vm->root.base.bo);
2758 vm->root.base.bo = NULL;
2761 drm_sched_entity_destroy(&vm->delayed);
2764 drm_sched_entity_destroy(&vm->direct);
2770 * amdgpu_vm_check_clean_reserved - check if a VM is clean
2772 * @adev: amdgpu_device pointer
2773 * @vm: the VM to check
2775 * check all entries of the root PD, if any subsequent PDs are allocated,
2776 * it means there are page table creating and filling, and is no a clean
2780 * 0 if this VM is clean
2782 static int amdgpu_vm_check_clean_reserved(struct amdgpu_device *adev,
2783 struct amdgpu_vm *vm)
2785 enum amdgpu_vm_level root = adev->vm_manager.root_level;
2786 unsigned int entries = amdgpu_vm_num_entries(adev, root);
2789 if (!(vm->root.entries))
2792 for (i = 0; i < entries; i++) {
2793 if (vm->root.entries[i].base.bo)
2801 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
2803 * @adev: amdgpu_device pointer
2806 * This only works on GFX VMs that don't have any BOs added and no
2807 * page tables allocated yet.
2809 * Changes the following VM parameters:
2810 * - use_cpu_for_update
2811 * - pte_supports_ats
2812 * - pasid (old PASID is released, because compute manages its own PASIDs)
2814 * Reinitializes the page directory to reflect the changed ATS
2818 * 0 for success, -errno for errors.
2820 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid)
2822 bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
2825 r = amdgpu_bo_reserve(vm->root.base.bo, true);
2830 r = amdgpu_vm_check_clean_reserved(adev, vm);
2835 unsigned long flags;
2837 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2838 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
2840 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2847 /* Check if PD needs to be reinitialized and do it before
2848 * changing any other state, in case it fails.
2850 if (pte_support_ats != vm->pte_support_ats) {
2851 vm->pte_support_ats = pte_support_ats;
2852 r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo);
2857 /* Update VM state */
2858 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2859 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2860 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2861 vm->use_cpu_for_update ? "CPU" : "SDMA");
2862 WARN_ONCE((vm->use_cpu_for_update && !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2863 "CPU update of VM recommended only for large BAR system\n");
2865 if (vm->use_cpu_for_update)
2866 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2868 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2869 dma_fence_put(vm->last_update);
2870 vm->last_update = NULL;
2873 unsigned long flags;
2875 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2876 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
2877 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2879 /* Free the original amdgpu allocated pasid
2880 * Will be replaced with kfd allocated pasid
2882 amdgpu_pasid_free(vm->pasid);
2886 /* Free the shadow bo for compute VM */
2887 amdgpu_bo_unref(&vm->root.base.bo->shadow);
2896 unsigned long flags;
2898 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2899 idr_remove(&adev->vm_manager.pasid_idr, pasid);
2900 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2903 amdgpu_bo_unreserve(vm->root.base.bo);
2908 * amdgpu_vm_release_compute - release a compute vm
2909 * @adev: amdgpu_device pointer
2910 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
2912 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
2913 * pasid from vm. Compute should stop use of vm after this call.
2915 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2918 unsigned long flags;
2920 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2921 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
2922 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2928 * amdgpu_vm_fini - tear down a vm instance
2930 * @adev: amdgpu_device pointer
2934 * Unbind the VM and remove all bos from the vm bo list
2936 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2938 struct amdgpu_bo_va_mapping *mapping, *tmp;
2939 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
2940 struct amdgpu_bo *root;
2943 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
2946 unsigned long flags;
2948 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2949 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
2950 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2953 drm_sched_entity_destroy(&vm->direct);
2954 drm_sched_entity_destroy(&vm->delayed);
2956 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
2957 dev_err(adev->dev, "still active bo inside vm\n");
2959 rbtree_postorder_for_each_entry_safe(mapping, tmp,
2960 &vm->va.rb_root, rb) {
2961 /* Don't remove the mapping here, we don't want to trigger a
2962 * rebalance and the tree is about to be destroyed anyway.
2964 list_del(&mapping->list);
2967 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2968 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
2969 amdgpu_vm_prt_fini(adev, vm);
2970 prt_fini_needed = false;
2973 list_del(&mapping->list);
2974 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
2977 root = amdgpu_bo_ref(vm->root.base.bo);
2978 r = amdgpu_bo_reserve(root, true);
2980 dev_err(adev->dev, "Leaking page tables because BO reservation failed\n");
2982 amdgpu_vm_free_pts(adev, vm, NULL);
2983 amdgpu_bo_unreserve(root);
2985 amdgpu_bo_unref(&root);
2986 WARN_ON(vm->root.base.bo);
2987 dma_fence_put(vm->last_update);
2988 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2989 amdgpu_vmid_free_reserved(adev, vm, i);
2993 * amdgpu_vm_manager_init - init the VM manager
2995 * @adev: amdgpu_device pointer
2997 * Initialize the VM manager structures
2999 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
3003 amdgpu_vmid_mgr_init(adev);
3005 adev->vm_manager.fence_context =
3006 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3007 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
3008 adev->vm_manager.seqno[i] = 0;
3010 spin_lock_init(&adev->vm_manager.prt_lock);
3011 atomic_set(&adev->vm_manager.num_prt_users, 0);
3013 /* If not overridden by the user, by default, only in large BAR systems
3014 * Compute VM tables will be updated by CPU
3016 #ifdef CONFIG_X86_64
3017 if (amdgpu_vm_update_mode == -1) {
3018 if (amdgpu_gmc_vram_full_visible(&adev->gmc))
3019 adev->vm_manager.vm_update_mode =
3020 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
3022 adev->vm_manager.vm_update_mode = 0;
3024 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
3026 adev->vm_manager.vm_update_mode = 0;
3029 idr_init(&adev->vm_manager.pasid_idr);
3030 spin_lock_init(&adev->vm_manager.pasid_lock);
3032 adev->vm_manager.xgmi_map_counter = 0;
3033 mutex_init(&adev->vm_manager.lock_pstate);
3037 * amdgpu_vm_manager_fini - cleanup VM manager
3039 * @adev: amdgpu_device pointer
3041 * Cleanup the VM manager and free resources.
3043 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
3045 WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr));
3046 idr_destroy(&adev->vm_manager.pasid_idr);
3048 amdgpu_vmid_mgr_fini(adev);
3052 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
3054 * @dev: drm device pointer
3055 * @data: drm_amdgpu_vm
3056 * @filp: drm file pointer
3059 * 0 for success, -errno for errors.
3061 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
3063 union drm_amdgpu_vm *args = data;
3064 struct amdgpu_device *adev = dev->dev_private;
3065 struct amdgpu_fpriv *fpriv = filp->driver_priv;
3068 switch (args->in.op) {
3069 case AMDGPU_VM_OP_RESERVE_VMID:
3070 /* current, we only have requirement to reserve vmid from gfxhub */
3071 r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
3075 case AMDGPU_VM_OP_UNRESERVE_VMID:
3076 amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
3086 * amdgpu_vm_get_task_info - Extracts task info for a PASID.
3088 * @adev: drm device pointer
3089 * @pasid: PASID identifier for VM
3090 * @task_info: task_info to fill.
3092 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid,
3093 struct amdgpu_task_info *task_info)
3095 struct amdgpu_vm *vm;
3096 unsigned long flags;
3098 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3100 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3102 *task_info = vm->task_info;
3104 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3108 * amdgpu_vm_set_task_info - Sets VMs task info.
3110 * @vm: vm for which to set the info
3112 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
3114 if (!vm->task_info.pid) {
3115 vm->task_info.pid = current->pid;
3116 get_task_comm(vm->task_info.task_name, current);
3118 if (current->group_leader->mm == current->mm) {
3119 vm->task_info.tgid = current->group_leader->pid;
3120 get_task_comm(vm->task_info.process_name, current->group_leader);