2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include "amdgpu_vm.h"
24 #include "amdgpu_object.h"
25 #include "amdgpu_trace.h"
28 * amdgpu_vm_cpu_prepare - prepare page table update with the CPU
30 * @p: see amdgpu_vm_update_params definition
31 * @owner: owner we need to sync to
32 * @exclusive: exclusive move fence we need to sync to
35 * Negativ errno, 0 for success.
37 static int amdgpu_vm_cpu_prepare(struct amdgpu_vm_update_params *p, void *owner,
38 struct dma_fence *exclusive)
42 /* Wait for PT BOs to be idle. PTs share the same resv. object
45 r = amdgpu_bo_sync_wait(p->vm->root.base.bo, owner, true);
49 /* Wait for any BO move to be completed */
51 r = dma_fence_wait(exclusive, true);
60 * amdgpu_vm_cpu_update - helper to update page tables via CPU
62 * @p: see amdgpu_vm_update_params definition
63 * @bo: PD/PT to update
64 * @pe: kmap addr of the page entry
65 * @addr: dst addr to write into pe
66 * @count: number of page entries to update
67 * @incr: increase next addr by incr bytes
68 * @flags: hw access flags
70 * Write count number of PT/PD entries directly.
72 static int amdgpu_vm_cpu_update(struct amdgpu_vm_update_params *p,
73 struct amdgpu_bo *bo, uint64_t pe,
74 uint64_t addr, unsigned count, uint32_t incr,
80 pe += (unsigned long)amdgpu_bo_kptr(bo);
82 trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
84 for (i = 0; i < count; i++) {
85 value = p->pages_addr ?
86 amdgpu_vm_map_gart(p->pages_addr, addr) :
88 amdgpu_gmc_set_pte_pde(p->adev, (void *)(uintptr_t)pe,
96 * amdgpu_vm_cpu_commit - commit page table update to the HW
98 * @p: see amdgpu_vm_update_params definition
101 * Make sure that the hardware sees the page table updates.
103 static int amdgpu_vm_cpu_commit(struct amdgpu_vm_update_params *p,
104 struct dma_fence **fence)
108 amdgpu_asic_flush_hdp(p->adev, NULL);
112 const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs = {
113 .prepare = amdgpu_vm_cpu_prepare,
114 .update = amdgpu_vm_cpu_update,
115 .commit = amdgpu_vm_cpu_commit