drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "drmP.h"
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "vid.h"
  28 #include "atom.h"
  29 #include "amdgpu_atombios.h"
  30 #include "atombios_crtc.h"
  31 #include "atombios_encoders.h"
  32 #include "amdgpu_pll.h"
  33 #include "amdgpu_connectors.h"
  34 #include "dce_v11_0.h"
  35
  36 #include "dce/dce_11_0_d.h"
  37 #include "dce/dce_11_0_sh_mask.h"
  38 #include "dce/dce_11_0_enum.h"
  39 #include "oss/oss_3_0_d.h"
  40 #include "oss/oss_3_0_sh_mask.h"
  41 #include "gmc/gmc_8_1_d.h"
  42 #include "gmc/gmc_8_1_sh_mask.h"
  43
  44 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
  45 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
  46
  47 static const u32 crtc_offsets[] =
  48 {
  49         CRTC0_REGISTER_OFFSET,
  50         CRTC1_REGISTER_OFFSET,
  51         CRTC2_REGISTER_OFFSET,
  52         CRTC3_REGISTER_OFFSET,
  53         CRTC4_REGISTER_OFFSET,
  54         CRTC5_REGISTER_OFFSET,
  55         CRTC6_REGISTER_OFFSET
  56 };
  57
  58 static const u32 hpd_offsets[] =
  59 {
  60         HPD0_REGISTER_OFFSET,
  61         HPD1_REGISTER_OFFSET,
  62         HPD2_REGISTER_OFFSET,
  63         HPD3_REGISTER_OFFSET,
  64         HPD4_REGISTER_OFFSET,
  65         HPD5_REGISTER_OFFSET
  66 };
  67
  68 static const uint32_t dig_offsets[] = {
  69         DIG0_REGISTER_OFFSET,
  70         DIG1_REGISTER_OFFSET,
  71         DIG2_REGISTER_OFFSET,
  72         DIG3_REGISTER_OFFSET,
  73         DIG4_REGISTER_OFFSET,
  74         DIG5_REGISTER_OFFSET,
  75         DIG6_REGISTER_OFFSET,
  76         DIG7_REGISTER_OFFSET,
  77         DIG8_REGISTER_OFFSET
  78 };
  79
  80 static const struct {
  81         uint32_t        reg;
  82         uint32_t        vblank;
  83         uint32_t        vline;
  84         uint32_t        hpd;
  85
  86 } interrupt_status_offsets[] = { {
  87         .reg = mmDISP_INTERRUPT_STATUS,
  88         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  89         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  90         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  91 }, {
  92         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  93         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  94         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  95         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  96 }, {
  97         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  98         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
  99         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
 100         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
 101 }, {
 102         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 103         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 104         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 105         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 106 }, {
 107         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 108         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 109         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 110         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 111 }, {
 112         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 113         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 114         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 115         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 116 } };
 117
 118 static const u32 cz_golden_settings_a11[] =
 119 {
 120         mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
 121         mmFBC_MISC, 0x1f311fff, 0x14300000,
 122 };
 123
 124 static const u32 cz_mgcg_cgcg_init[] =
 125 {
 126         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 127         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 128 };
 129
 130 static const u32 stoney_golden_settings_a11[] =
 131 {
 132         mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
 133         mmFBC_MISC, 0x1f311fff, 0x14302000,
 134 };
 135
 136 static const u32 polaris11_golden_settings_a11[] =
 137 {
 138         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 139         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 140         mmFBC_DEBUG1, 0xffffffff, 0x00000008,
 141         mmFBC_MISC, 0x9f313fff, 0x14302008,
 142         mmHDMI_CONTROL, 0x313f031f, 0x00000011,
 143 };
 144
 145 static const u32 polaris10_golden_settings_a11[] =
 146 {
 147         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 148         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 149         mmFBC_MISC, 0x9f313fff, 0x14302008,
 150         mmHDMI_CONTROL, 0x313f031f, 0x00000011,
 151 };
 152
 153 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
 154 {
 155         switch (adev->asic_type) {
 156         case CHIP_CARRIZO:
 157                 amdgpu_program_register_sequence(adev,
 158                                                  cz_mgcg_cgcg_init,
 159                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 160                 amdgpu_program_register_sequence(adev,
 161                                                  cz_golden_settings_a11,
 162                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
 163                 break;
 164         case CHIP_STONEY:
 165                 amdgpu_program_register_sequence(adev,
 166                                                  stoney_golden_settings_a11,
 167                                                  (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
 168                 break;
 169         case CHIP_POLARIS11:
 170         case CHIP_POLARIS12:
 171                 amdgpu_program_register_sequence(adev,
 172                                                  polaris11_golden_settings_a11,
 173                                                  (const u32)ARRAY_SIZE(polaris11_golden_settings_a11));
 174                 break;
 175         case CHIP_POLARIS10:
 176                 amdgpu_program_register_sequence(adev,
 177                                                  polaris10_golden_settings_a11,
 178                                                  (const u32)ARRAY_SIZE(polaris10_golden_settings_a11));
 179                 break;
 180         default:
 181                 break;
 182         }
 183 }
 184
 185 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
 186                                      u32 block_offset, u32 reg)
 187 {
 188         unsigned long flags;
 189         u32 r;
 190
 191         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 192         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 193         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 194         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 195
 196         return r;
 197 }
 198
 199 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
 200                                       u32 block_offset, u32 reg, u32 v)
 201 {
 202         unsigned long flags;
 203
 204         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 205         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 206         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 207         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 208 }
 209
 210 static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
 211 {
 212         if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
 213                         CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
 214                 return true;
 215         else
 216                 return false;
 217 }
 218
 219 static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
 220 {
 221         u32 pos1, pos2;
 222
 223         pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 224         pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 225
 226         if (pos1 != pos2)
 227                 return true;
 228         else
 229                 return false;
 230 }
 231
 232 /**
 233  * dce_v11_0_vblank_wait - vblank wait asic callback.
 234  *
 235  * @adev: amdgpu_device pointer
 236  * @crtc: crtc to wait for vblank on
 237  *
 238  * Wait for vblank on the requested crtc (evergreen+).
 239  */
 240 static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
 241 {
 242         unsigned i = 100;
 243
 244         if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
 245                 return;
 246
 247         if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
 248                 return;
 249
 250         /* depending on when we hit vblank, we may be close to active; if so,
 251          * wait for another frame.
 252          */
 253         while (dce_v11_0_is_in_vblank(adev, crtc)) {
 254                 if (i++ == 100) {
 255                         i = 0;
 256                         if (!dce_v11_0_is_counter_moving(adev, crtc))
 257                                 break;
 258                 }
 259         }
 260
 261         while (!dce_v11_0_is_in_vblank(adev, crtc)) {
 262                 if (i++ == 100) {
 263                         i = 0;
 264                         if (!dce_v11_0_is_counter_moving(adev, crtc))
 265                                 break;
 266                 }
 267         }
 268 }
 269
 270 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 271 {
 272         if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
 273                 return 0;
 274         else
 275                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 276 }
 277
 278 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
 279 {
 280         unsigned i;
 281
 282         /* Enable pflip interrupts */
 283         for (i = 0; i < adev->mode_info.num_crtc; i++)
 284                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
 285 }
 286
 287 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
 288 {
 289         unsigned i;
 290
 291         /* Disable pflip interrupts */
 292         for (i = 0; i < adev->mode_info.num_crtc; i++)
 293                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
 294 }
 295
 296 /**
 297  * dce_v11_0_page_flip - pageflip callback.
 298  *
 299  * @adev: amdgpu_device pointer
 300  * @crtc_id: crtc to cleanup pageflip on
 301  * @crtc_base: new address of the crtc (GPU MC address)
 302  *
 303  * Triggers the actual pageflip by updating the primary
 304  * surface base address.
 305  */
 306 static void dce_v11_0_page_flip(struct amdgpu_device *adev,
 307                                 int crtc_id, u64 crtc_base, bool async)
 308 {
 309         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 310         u32 tmp;
 311
 312         /* flip immediate for async, default is vsync */
 313         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
 314         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
 315                             GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
 316         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 317         /* update the scanout addresses */
 318         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 319                upper_32_bits(crtc_base));
 320         /* writing to the low address triggers the update */
 321         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 322                lower_32_bits(crtc_base));
 323         /* post the write */
 324         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 325 }
 326
 327 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 328                                         u32 *vbl, u32 *position)
 329 {
 330         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 331                 return -EINVAL;
 332
 333         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 334         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 335
 336         return 0;
 337 }
 338
 339 /**
 340  * dce_v11_0_hpd_sense - hpd sense callback.
 341  *
 342  * @adev: amdgpu_device pointer
 343  * @hpd: hpd (hotplug detect) pin
 344  *
 345  * Checks if a digital monitor is connected (evergreen+).
 346  * Returns true if connected, false if not connected.
 347  */
 348 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
 349                                enum amdgpu_hpd_id hpd)
 350 {
 351         bool connected = false;
 352
 353         if (hpd >= adev->mode_info.num_hpd)
 354                 return connected;
 355
 356         if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
 357             DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
 358                 connected = true;
 359
 360         return connected;
 361 }
 362
 363 /**
 364  * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
 365  *
 366  * @adev: amdgpu_device pointer
 367  * @hpd: hpd (hotplug detect) pin
 368  *
 369  * Set the polarity of the hpd pin (evergreen+).
 370  */
 371 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
 372                                       enum amdgpu_hpd_id hpd)
 373 {
 374         u32 tmp;
 375         bool connected = dce_v11_0_hpd_sense(adev, hpd);
 376
 377         if (hpd >= adev->mode_info.num_hpd)
 378                 return;
 379
 380         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
 381         if (connected)
 382                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
 383         else
 384                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
 385         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
 386 }
 387
 388 /**
 389  * dce_v11_0_hpd_init - hpd setup callback.
 390  *
 391  * @adev: amdgpu_device pointer
 392  *
 393  * Setup the hpd pins used by the card (evergreen+).
 394  * Enable the pin, set the polarity, and enable the hpd interrupts.
 395  */
 396 static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
 397 {
 398         struct drm_device *dev = adev->ddev;
 399         struct drm_connector *connector;
 400         u32 tmp;
 401
 402         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 403                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 404
 405                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 406                         continue;
 407
 408                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 409                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 410                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 411                          * aux dp channel on imac and help (but not completely fix)
 412                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 413                          * also avoid interrupt storms during dpms.
 414                          */
 415                         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 416                         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
 417                         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 418                         continue;
 419                 }
 420
 421                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 422                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
 423                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 424
 425                 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 426                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 427                                     DC_HPD_CONNECT_INT_DELAY,
 428                                     AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
 429                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 430                                     DC_HPD_DISCONNECT_INT_DELAY,
 431                                     AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
 432                 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 433
 434                 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 435                 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 436         }
 437 }
 438
 439 /**
 440  * dce_v11_0_hpd_fini - hpd tear down callback.
 441  *
 442  * @adev: amdgpu_device pointer
 443  *
 444  * Tear down the hpd pins used by the card (evergreen+).
 445  * Disable the hpd interrupts.
 446  */
 447 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
 448 {
 449         struct drm_device *dev = adev->ddev;
 450         struct drm_connector *connector;
 451         u32 tmp;
 452
 453         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 454                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 455
 456                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 457                         continue;
 458
 459                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 460                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
 461                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 462
 463                 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 464         }
 465 }
 466
 467 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 468 {
 469         return mmDC_GPIO_HPD_A;
 470 }
 471
 472 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
 473 {
 474         u32 crtc_hung = 0;
 475         u32 crtc_status[6];
 476         u32 i, j, tmp;
 477
 478         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 479                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 480                 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
 481                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 482                         crtc_hung |= (1 << i);
 483                 }
 484         }
 485
 486         for (j = 0; j < 10; j++) {
 487                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 488                         if (crtc_hung & (1 << i)) {
 489                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 490                                 if (tmp != crtc_status[i])
 491                                         crtc_hung &= ~(1 << i);
 492                         }
 493                 }
 494                 if (crtc_hung == 0)
 495                         return false;
 496                 udelay(100);
 497         }
 498
 499         return true;
 500 }
 501
 502 static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
 503                                      struct amdgpu_mode_mc_save *save)
 504 {
 505         u32 crtc_enabled, tmp;
 506         int i;
 507
 508         save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 509         save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
 510
 511         /* disable VGA render */
 512         tmp = RREG32(mmVGA_RENDER_CONTROL);
 513         tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 514         WREG32(mmVGA_RENDER_CONTROL, tmp);
 515
 516         /* blank the display controllers */
 517         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 518                 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 519                                              CRTC_CONTROL, CRTC_MASTER_EN);
 520                 if (crtc_enabled) {
 521 #if 1
 522                         save->crtc_enabled[i] = true;
 523                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 524                         if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
 525                                 /*it is correct only for RGB ; black is 0*/
 526                                 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
 527                                 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
 528                                 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 529                         }
 530 #else
 531                         /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
 532                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 533                         tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 534                         tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 535                         WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 536                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 537                         save->crtc_enabled[i] = false;
 538                         /* ***** */
 539 #endif
 540                 } else {
 541                         save->crtc_enabled[i] = false;
 542                 }
 543         }
 544 }
 545
 546 static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
 547                                        struct amdgpu_mode_mc_save *save)
 548 {
 549         u32 tmp;
 550         int i;
 551
 552         /* update crtc base addresses */
 553         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 554                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 555                        upper_32_bits(adev->mc.vram_start));
 556                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
 557                        (u32)adev->mc.vram_start);
 558
 559                 if (save->crtc_enabled[i]) {
 560                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 561                         tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
 562                         WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 563                 }
 564         }
 565
 566         WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
 567         WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
 568
 569         /* Unlock vga access */
 570         WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
 571         mdelay(1);
 572         WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
 573 }
 574
 575 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
 576                                            bool render)
 577 {
 578         u32 tmp;
 579
 580         /* Lockout access through VGA aperture*/
 581         tmp = RREG32(mmVGA_HDP_CONTROL);
 582         if (render)
 583                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 584         else
 585                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 586         WREG32(mmVGA_HDP_CONTROL, tmp);
 587
 588         /* disable VGA render */
 589         tmp = RREG32(mmVGA_RENDER_CONTROL);
 590         if (render)
 591                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 592         else
 593                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 594         WREG32(mmVGA_RENDER_CONTROL, tmp);
 595 }
 596
 597 static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
 598 {
 599         int num_crtc = 0;
 600
 601         switch (adev->asic_type) {
 602         case CHIP_CARRIZO:
 603                 num_crtc = 3;
 604                 break;
 605         case CHIP_STONEY:
 606                 num_crtc = 2;
 607                 break;
 608         case CHIP_POLARIS10:
 609                 num_crtc = 6;
 610                 break;
 611         case CHIP_POLARIS11:
 612         case CHIP_POLARIS12:
 613                 num_crtc = 5;
 614                 break;
 615         default:
 616                 num_crtc = 0;
 617         }
 618         return num_crtc;
 619 }
 620
 621 void dce_v11_0_disable_dce(struct amdgpu_device *adev)
 622 {
 623         /*Disable VGA render and enabled crtc, if has DCE engine*/
 624         if (amdgpu_atombios_has_dce_engine_info(adev)) {
 625                 u32 tmp;
 626                 int crtc_enabled, i;
 627
 628                 dce_v11_0_set_vga_render_state(adev, false);
 629
 630                 /*Disable crtc*/
 631                 for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) {
 632                         crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 633                                                                          CRTC_CONTROL, CRTC_MASTER_EN);
 634                         if (crtc_enabled) {
 635                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 636                                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 637                                 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 638                                 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 639                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 640                         }
 641                 }
 642         }
 643 }
 644
 645 static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
 646 {
 647         struct drm_device *dev = encoder->dev;
 648         struct amdgpu_device *adev = dev->dev_private;
 649         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 650         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 651         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 652         int bpc = 0;
 653         u32 tmp = 0;
 654         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 655
 656         if (connector) {
 657                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 658                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 659                 dither = amdgpu_connector->dither;
 660         }
 661
 662         /* LVDS/eDP FMT is set up by atom */
 663         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 664                 return;
 665
 666         /* not needed for analog */
 667         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 668             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 669                 return;
 670
 671         if (bpc == 0)
 672                 return;
 673
 674         switch (bpc) {
 675         case 6:
 676                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 677                         /* XXX sort out optimal dither settings */
 678                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 679                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 680                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 681                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
 682                 } else {
 683                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 684                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
 685                 }
 686                 break;
 687         case 8:
 688                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 689                         /* XXX sort out optimal dither settings */
 690                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 691                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 692                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 693                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 694                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
 695                 } else {
 696                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 697                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
 698                 }
 699                 break;
 700         case 10:
 701                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 702                         /* XXX sort out optimal dither settings */
 703                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 704                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 705                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 706                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 707                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
 708                 } else {
 709                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 710                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
 711                 }
 712                 break;
 713         default:
 714                 /* not needed */
 715                 break;
 716         }
 717
 718         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 719 }
 720
 721
 722 /* display watermark setup */
 723 /**
 724  * dce_v11_0_line_buffer_adjust - Set up the line buffer
 725  *
 726  * @adev: amdgpu_device pointer
 727  * @amdgpu_crtc: the selected display controller
 728  * @mode: the current display mode on the selected display
 729  * controller
 730  *
 731  * Setup up the line buffer allocation for
 732  * the selected display controller (CIK).
 733  * Returns the line buffer size in pixels.
 734  */
 735 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
 736                                        struct amdgpu_crtc *amdgpu_crtc,
 737                                        struct drm_display_mode *mode)
 738 {
 739         u32 tmp, buffer_alloc, i, mem_cfg;
 740         u32 pipe_offset = amdgpu_crtc->crtc_id;
 741         /*
 742          * Line Buffer Setup
 743          * There are 6 line buffers, one for each display controllers.
 744          * There are 3 partitions per LB. Select the number of partitions
 745          * to enable based on the display width.  For display widths larger
 746          * than 4096, you need use to use 2 display controllers and combine
 747          * them using the stereo blender.
 748          */
 749         if (amdgpu_crtc->base.enabled && mode) {
 750                 if (mode->crtc_hdisplay < 1920) {
 751                         mem_cfg = 1;
 752                         buffer_alloc = 2;
 753                 } else if (mode->crtc_hdisplay < 2560) {
 754                         mem_cfg = 2;
 755                         buffer_alloc = 2;
 756                 } else if (mode->crtc_hdisplay < 4096) {
 757                         mem_cfg = 0;
 758                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 759                 } else {
 760                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 761                         mem_cfg = 0;
 762                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 763                 }
 764         } else {
 765                 mem_cfg = 1;
 766                 buffer_alloc = 0;
 767         }
 768
 769         tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
 770         tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
 771         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
 772
 773         tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 774         tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
 775         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
 776
 777         for (i = 0; i < adev->usec_timeout; i++) {
 778                 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 779                 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
 780                         break;
 781                 udelay(1);
 782         }
 783
 784         if (amdgpu_crtc->base.enabled && mode) {
 785                 switch (mem_cfg) {
 786                 case 0:
 787                 default:
 788                         return 4096 * 2;
 789                 case 1:
 790                         return 1920 * 2;
 791                 case 2:
 792                         return 2560 * 2;
 793                 }
 794         }
 795
 796         /* controller not enabled, so no lb used */
 797         return 0;
 798 }
 799
 800 /**
 801  * cik_get_number_of_dram_channels - get the number of dram channels
 802  *
 803  * @adev: amdgpu_device pointer
 804  *
 805  * Look up the number of video ram channels (CIK).
 806  * Used for display watermark bandwidth calculations
 807  * Returns the number of dram channels
 808  */
 809 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 810 {
 811         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 812
 813         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 814         case 0:
 815         default:
 816                 return 1;
 817         case 1:
 818                 return 2;
 819         case 2:
 820                 return 4;
 821         case 3:
 822                 return 8;
 823         case 4:
 824                 return 3;
 825         case 5:
 826                 return 6;
 827         case 6:
 828                 return 10;
 829         case 7:
 830                 return 12;
 831         case 8:
 832                 return 16;
 833         }
 834 }
 835
 836 struct dce10_wm_params {
 837         u32 dram_channels; /* number of dram channels */
 838         u32 yclk;          /* bandwidth per dram data pin in kHz */
 839         u32 sclk;          /* engine clock in kHz */
 840         u32 disp_clk;      /* display clock in kHz */
 841         u32 src_width;     /* viewport width */
 842         u32 active_time;   /* active display time in ns */
 843         u32 blank_time;    /* blank time in ns */
 844         bool interlaced;    /* mode is interlaced */
 845         fixed20_12 vsc;    /* vertical scale ratio */
 846         u32 num_heads;     /* number of active crtcs */
 847         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 848         u32 lb_size;       /* line buffer allocated to pipe */
 849         u32 vtaps;         /* vertical scaler taps */
 850 };
 851
 852 /**
 853  * dce_v11_0_dram_bandwidth - get the dram bandwidth
 854  *
 855  * @wm: watermark calculation data
 856  *
 857  * Calculate the raw dram bandwidth (CIK).
 858  * Used for display watermark bandwidth calculations
 859  * Returns the dram bandwidth in MBytes/s
 860  */
 861 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
 862 {
 863         /* Calculate raw DRAM Bandwidth */
 864         fixed20_12 dram_efficiency; /* 0.7 */
 865         fixed20_12 yclk, dram_channels, bandwidth;
 866         fixed20_12 a;
 867
 868         a.full = dfixed_const(1000);
 869         yclk.full = dfixed_const(wm->yclk);
 870         yclk.full = dfixed_div(yclk, a);
 871         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 872         a.full = dfixed_const(10);
 873         dram_efficiency.full = dfixed_const(7);
 874         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 875         bandwidth.full = dfixed_mul(dram_channels, yclk);
 876         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 877
 878         return dfixed_trunc(bandwidth);
 879 }
 880
 881 /**
 882  * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
 883  *
 884  * @wm: watermark calculation data
 885  *
 886  * Calculate the dram bandwidth used for display (CIK).
 887  * Used for display watermark bandwidth calculations
 888  * Returns the dram bandwidth for display in MBytes/s
 889  */
 890 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
 891 {
 892         /* Calculate DRAM Bandwidth and the part allocated to display. */
 893         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 894         fixed20_12 yclk, dram_channels, bandwidth;
 895         fixed20_12 a;
 896
 897         a.full = dfixed_const(1000);
 898         yclk.full = dfixed_const(wm->yclk);
 899         yclk.full = dfixed_div(yclk, a);
 900         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 901         a.full = dfixed_const(10);
 902         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 903         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 904         bandwidth.full = dfixed_mul(dram_channels, yclk);
 905         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 906
 907         return dfixed_trunc(bandwidth);
 908 }
 909
 910 /**
 911  * dce_v11_0_data_return_bandwidth - get the data return bandwidth
 912  *
 913  * @wm: watermark calculation data
 914  *
 915  * Calculate the data return bandwidth used for display (CIK).
 916  * Used for display watermark bandwidth calculations
 917  * Returns the data return bandwidth in MBytes/s
 918  */
 919 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
 920 {
 921         /* Calculate the display Data return Bandwidth */
 922         fixed20_12 return_efficiency; /* 0.8 */
 923         fixed20_12 sclk, bandwidth;
 924         fixed20_12 a;
 925
 926         a.full = dfixed_const(1000);
 927         sclk.full = dfixed_const(wm->sclk);
 928         sclk.full = dfixed_div(sclk, a);
 929         a.full = dfixed_const(10);
 930         return_efficiency.full = dfixed_const(8);
 931         return_efficiency.full = dfixed_div(return_efficiency, a);
 932         a.full = dfixed_const(32);
 933         bandwidth.full = dfixed_mul(a, sclk);
 934         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 935
 936         return dfixed_trunc(bandwidth);
 937 }
 938
 939 /**
 940  * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
 941  *
 942  * @wm: watermark calculation data
 943  *
 944  * Calculate the dmif bandwidth used for display (CIK).
 945  * Used for display watermark bandwidth calculations
 946  * Returns the dmif bandwidth in MBytes/s
 947  */
 948 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
 949 {
 950         /* Calculate the DMIF Request Bandwidth */
 951         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 952         fixed20_12 disp_clk, bandwidth;
 953         fixed20_12 a, b;
 954
 955         a.full = dfixed_const(1000);
 956         disp_clk.full = dfixed_const(wm->disp_clk);
 957         disp_clk.full = dfixed_div(disp_clk, a);
 958         a.full = dfixed_const(32);
 959         b.full = dfixed_mul(a, disp_clk);
 960
 961         a.full = dfixed_const(10);
 962         disp_clk_request_efficiency.full = dfixed_const(8);
 963         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 964
 965         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
 966
 967         return dfixed_trunc(bandwidth);
 968 }
 969
 970 /**
 971  * dce_v11_0_available_bandwidth - get the min available bandwidth
 972  *
 973  * @wm: watermark calculation data
 974  *
 975  * Calculate the min available bandwidth used for display (CIK).
 976  * Used for display watermark bandwidth calculations
 977  * Returns the min available bandwidth in MBytes/s
 978  */
 979 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
 980 {
 981         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 982         u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
 983         u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
 984         u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
 985
 986         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 987 }
 988
 989 /**
 990  * dce_v11_0_average_bandwidth - get the average available bandwidth
 991  *
 992  * @wm: watermark calculation data
 993  *
 994  * Calculate the average available bandwidth used for display (CIK).
 995  * Used for display watermark bandwidth calculations
 996  * Returns the average available bandwidth in MBytes/s
 997  */
 998 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
 999 {
1000         /* Calculate the display mode Average Bandwidth
1001          * DisplayMode should contain the source and destination dimensions,
1002          * timing, etc.
1003          */
1004         fixed20_12 bpp;
1005         fixed20_12 line_time;
1006         fixed20_12 src_width;
1007         fixed20_12 bandwidth;
1008         fixed20_12 a;
1009
1010         a.full = dfixed_const(1000);
1011         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1012         line_time.full = dfixed_div(line_time, a);
1013         bpp.full = dfixed_const(wm->bytes_per_pixel);
1014         src_width.full = dfixed_const(wm->src_width);
1015         bandwidth.full = dfixed_mul(src_width, bpp);
1016         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1017         bandwidth.full = dfixed_div(bandwidth, line_time);
1018
1019         return dfixed_trunc(bandwidth);
1020 }
1021
1022 /**
1023  * dce_v11_0_latency_watermark - get the latency watermark
1024  *
1025  * @wm: watermark calculation data
1026  *
1027  * Calculate the latency watermark (CIK).
1028  * Used for display watermark bandwidth calculations
1029  * Returns the latency watermark in ns
1030  */
1031 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
1032 {
1033         /* First calculate the latency in ns */
1034         u32 mc_latency = 2000; /* 2000 ns. */
1035         u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
1036         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1037         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1038         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1039         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1040                 (wm->num_heads * cursor_line_pair_return_time);
1041         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1042         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1043         u32 tmp, dmif_size = 12288;
1044         fixed20_12 a, b, c;
1045
1046         if (wm->num_heads == 0)
1047                 return 0;
1048
1049         a.full = dfixed_const(2);
1050         b.full = dfixed_const(1);
1051         if ((wm->vsc.full > a.full) ||
1052             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1053             (wm->vtaps >= 5) ||
1054             ((wm->vsc.full >= a.full) && wm->interlaced))
1055                 max_src_lines_per_dst_line = 4;
1056         else
1057                 max_src_lines_per_dst_line = 2;
1058
1059         a.full = dfixed_const(available_bandwidth);
1060         b.full = dfixed_const(wm->num_heads);
1061         a.full = dfixed_div(a, b);
1062
1063         b.full = dfixed_const(mc_latency + 512);
1064         c.full = dfixed_const(wm->disp_clk);
1065         b.full = dfixed_div(b, c);
1066
1067         c.full = dfixed_const(dmif_size);
1068         b.full = dfixed_div(c, b);
1069
1070         tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1071
1072         b.full = dfixed_const(1000);
1073         c.full = dfixed_const(wm->disp_clk);
1074         b.full = dfixed_div(c, b);
1075         c.full = dfixed_const(wm->bytes_per_pixel);
1076         b.full = dfixed_mul(b, c);
1077
1078         lb_fill_bw = min(tmp, dfixed_trunc(b));
1079
1080         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1081         b.full = dfixed_const(1000);
1082         c.full = dfixed_const(lb_fill_bw);
1083         b.full = dfixed_div(c, b);
1084         a.full = dfixed_div(a, b);
1085         line_fill_time = dfixed_trunc(a);
1086
1087         if (line_fill_time < wm->active_time)
1088                 return latency;
1089         else
1090                 return latency + (line_fill_time - wm->active_time);
1091
1092 }
1093
1094 /**
1095  * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1096  * average and available dram bandwidth
1097  *
1098  * @wm: watermark calculation data
1099  *
1100  * Check if the display average bandwidth fits in the display
1101  * dram bandwidth (CIK).
1102  * Used for display watermark bandwidth calculations
1103  * Returns true if the display fits, false if not.
1104  */
1105 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1106 {
1107         if (dce_v11_0_average_bandwidth(wm) <=
1108             (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1109                 return true;
1110         else
1111                 return false;
1112 }
1113
1114 /**
1115  * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1116  * average and available bandwidth
1117  *
1118  * @wm: watermark calculation data
1119  *
1120  * Check if the display average bandwidth fits in the display
1121  * available bandwidth (CIK).
1122  * Used for display watermark bandwidth calculations
1123  * Returns true if the display fits, false if not.
1124  */
1125 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1126 {
1127         if (dce_v11_0_average_bandwidth(wm) <=
1128             (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1129                 return true;
1130         else
1131                 return false;
1132 }
1133
1134 /**
1135  * dce_v11_0_check_latency_hiding - check latency hiding
1136  *
1137  * @wm: watermark calculation data
1138  *
1139  * Check latency hiding (CIK).
1140  * Used for display watermark bandwidth calculations
1141  * Returns true if the display fits, false if not.
1142  */
1143 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1144 {
1145         u32 lb_partitions = wm->lb_size / wm->src_width;
1146         u32 line_time = wm->active_time + wm->blank_time;
1147         u32 latency_tolerant_lines;
1148         u32 latency_hiding;
1149         fixed20_12 a;
1150
1151         a.full = dfixed_const(1);
1152         if (wm->vsc.full > a.full)
1153                 latency_tolerant_lines = 1;
1154         else {
1155                 if (lb_partitions <= (wm->vtaps + 1))
1156                         latency_tolerant_lines = 1;
1157                 else
1158                         latency_tolerant_lines = 2;
1159         }
1160
1161         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1162
1163         if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1164                 return true;
1165         else
1166                 return false;
1167 }
1168
1169 /**
1170  * dce_v11_0_program_watermarks - program display watermarks
1171  *
1172  * @adev: amdgpu_device pointer
1173  * @amdgpu_crtc: the selected display controller
1174  * @lb_size: line buffer size
1175  * @num_heads: number of display controllers in use
1176  *
1177  * Calculate and program the display watermarks for the
1178  * selected display controller (CIK).
1179  */
1180 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1181                                         struct amdgpu_crtc *amdgpu_crtc,
1182                                         u32 lb_size, u32 num_heads)
1183 {
1184         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1185         struct dce10_wm_params wm_low, wm_high;
1186         u32 pixel_period;
1187         u32 line_time = 0;
1188         u32 latency_watermark_a = 0, latency_watermark_b = 0;
1189         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1190
1191         if (amdgpu_crtc->base.enabled && num_heads && mode) {
1192                 pixel_period = 1000000 / (u32)mode->clock;
1193                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1194
1195                 /* watermark for high clocks */
1196                 if (adev->pm.dpm_enabled) {
1197                         wm_high.yclk =
1198                                 amdgpu_dpm_get_mclk(adev, false) * 10;
1199                         wm_high.sclk =
1200                                 amdgpu_dpm_get_sclk(adev, false) * 10;
1201                 } else {
1202                         wm_high.yclk = adev->pm.current_mclk * 10;
1203                         wm_high.sclk = adev->pm.current_sclk * 10;
1204                 }
1205
1206                 wm_high.disp_clk = mode->clock;
1207                 wm_high.src_width = mode->crtc_hdisplay;
1208                 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1209                 wm_high.blank_time = line_time - wm_high.active_time;
1210                 wm_high.interlaced = false;
1211                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1212                         wm_high.interlaced = true;
1213                 wm_high.vsc = amdgpu_crtc->vsc;
1214                 wm_high.vtaps = 1;
1215                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1216                         wm_high.vtaps = 2;
1217                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1218                 wm_high.lb_size = lb_size;
1219                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1220                 wm_high.num_heads = num_heads;
1221
1222                 /* set for high clocks */
1223                 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1224
1225                 /* possibly force display priority to high */
1226                 /* should really do this at mode validation time... */
1227                 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1228                     !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1229                     !dce_v11_0_check_latency_hiding(&wm_high) ||
1230                     (adev->mode_info.disp_priority == 2)) {
1231                         DRM_DEBUG_KMS("force priority to high\n");
1232                 }
1233
1234                 /* watermark for low clocks */
1235                 if (adev->pm.dpm_enabled) {
1236                         wm_low.yclk =
1237                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1238                         wm_low.sclk =
1239                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1240                 } else {
1241                         wm_low.yclk = adev->pm.current_mclk * 10;
1242                         wm_low.sclk = adev->pm.current_sclk * 10;
1243                 }
1244
1245                 wm_low.disp_clk = mode->clock;
1246                 wm_low.src_width = mode->crtc_hdisplay;
1247                 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1248                 wm_low.blank_time = line_time - wm_low.active_time;
1249                 wm_low.interlaced = false;
1250                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1251                         wm_low.interlaced = true;
1252                 wm_low.vsc = amdgpu_crtc->vsc;
1253                 wm_low.vtaps = 1;
1254                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1255                         wm_low.vtaps = 2;
1256                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1257                 wm_low.lb_size = lb_size;
1258                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1259                 wm_low.num_heads = num_heads;
1260
1261                 /* set for low clocks */
1262                 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1263
1264                 /* possibly force display priority to high */
1265                 /* should really do this at mode validation time... */
1266                 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1267                     !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1268                     !dce_v11_0_check_latency_hiding(&wm_low) ||
1269                     (adev->mode_info.disp_priority == 2)) {
1270                         DRM_DEBUG_KMS("force priority to high\n");
1271                 }
1272                 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1273         }
1274
1275         /* select wm A */
1276         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1277         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1278         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1279         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1280         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1281         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1282         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1283         /* select wm B */
1284         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1285         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1286         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1287         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1288         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1289         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1290         /* restore original selection */
1291         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1292
1293         /* save values for DPM */
1294         amdgpu_crtc->line_time = line_time;
1295         amdgpu_crtc->wm_high = latency_watermark_a;
1296         amdgpu_crtc->wm_low = latency_watermark_b;
1297         /* Save number of lines the linebuffer leads before the scanout */
1298         amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1299 }
1300
1301 /**
1302  * dce_v11_0_bandwidth_update - program display watermarks
1303  *
1304  * @adev: amdgpu_device pointer
1305  *
1306  * Calculate and program the display watermarks and line
1307  * buffer allocation (CIK).
1308  */
1309 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1310 {
1311         struct drm_display_mode *mode = NULL;
1312         u32 num_heads = 0, lb_size;
1313         int i;
1314
1315         amdgpu_update_display_priority(adev);
1316
1317         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1318                 if (adev->mode_info.crtcs[i]->base.enabled)
1319                         num_heads++;
1320         }
1321         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1322                 mode = &adev->mode_info.crtcs[i]->base.mode;
1323                 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1324                 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1325                                             lb_size, num_heads);
1326         }
1327 }
1328
1329 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1330 {
1331         int i;
1332         u32 offset, tmp;
1333
1334         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1335                 offset = adev->mode_info.audio.pin[i].offset;
1336                 tmp = RREG32_AUDIO_ENDPT(offset,
1337                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1338                 if (((tmp &
1339                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1340                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1341                         adev->mode_info.audio.pin[i].connected = false;
1342                 else
1343                         adev->mode_info.audio.pin[i].connected = true;
1344         }
1345 }
1346
1347 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1348 {
1349         int i;
1350
1351         dce_v11_0_audio_get_connected_pins(adev);
1352
1353         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1354                 if (adev->mode_info.audio.pin[i].connected)
1355                         return &adev->mode_info.audio.pin[i];
1356         }
1357         DRM_ERROR("No connected audio pins found!\n");
1358         return NULL;
1359 }
1360
1361 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1362 {
1363         struct amdgpu_device *adev = encoder->dev->dev_private;
1364         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1365         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1366         u32 tmp;
1367
1368         if (!dig || !dig->afmt || !dig->afmt->pin)
1369                 return;
1370
1371         tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1372         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1373         WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1374 }
1375
1376 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1377                                                 struct drm_display_mode *mode)
1378 {
1379         struct amdgpu_device *adev = encoder->dev->dev_private;
1380         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1381         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1382         struct drm_connector *connector;
1383         struct amdgpu_connector *amdgpu_connector = NULL;
1384         u32 tmp;
1385         int interlace = 0;
1386
1387         if (!dig || !dig->afmt || !dig->afmt->pin)
1388                 return;
1389
1390         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1391                 if (connector->encoder == encoder) {
1392                         amdgpu_connector = to_amdgpu_connector(connector);
1393                         break;
1394                 }
1395         }
1396
1397         if (!amdgpu_connector) {
1398                 DRM_ERROR("Couldn't find encoder's connector\n");
1399                 return;
1400         }
1401
1402         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1403                 interlace = 1;
1404         if (connector->latency_present[interlace]) {
1405                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1406                                     VIDEO_LIPSYNC, connector->video_latency[interlace]);
1407                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1408                                     AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1409         } else {
1410                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1411                                     VIDEO_LIPSYNC, 0);
1412                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1413                                     AUDIO_LIPSYNC, 0);
1414         }
1415         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1416                            ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1417 }
1418
1419 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1420 {
1421         struct amdgpu_device *adev = encoder->dev->dev_private;
1422         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1423         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1424         struct drm_connector *connector;
1425         struct amdgpu_connector *amdgpu_connector = NULL;
1426         u32 tmp;
1427         u8 *sadb = NULL;
1428         int sad_count;
1429
1430         if (!dig || !dig->afmt || !dig->afmt->pin)
1431                 return;
1432
1433         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1434                 if (connector->encoder == encoder) {
1435                         amdgpu_connector = to_amdgpu_connector(connector);
1436                         break;
1437                 }
1438         }
1439
1440         if (!amdgpu_connector) {
1441                 DRM_ERROR("Couldn't find encoder's connector\n");
1442                 return;
1443         }
1444
1445         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1446         if (sad_count < 0) {
1447                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1448                 sad_count = 0;
1449         }
1450
1451         /* program the speaker allocation */
1452         tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1453                                  ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1454         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1455                             DP_CONNECTION, 0);
1456         /* set HDMI mode */
1457         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1458                             HDMI_CONNECTION, 1);
1459         if (sad_count)
1460                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1461                                     SPEAKER_ALLOCATION, sadb[0]);
1462         else
1463                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1464                                     SPEAKER_ALLOCATION, 5); /* stereo */
1465         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1466                            ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1467
1468         kfree(sadb);
1469 }
1470
1471 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1472 {
1473         struct amdgpu_device *adev = encoder->dev->dev_private;
1474         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1475         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1476         struct drm_connector *connector;
1477         struct amdgpu_connector *amdgpu_connector = NULL;
1478         struct cea_sad *sads;
1479         int i, sad_count;
1480
1481         static const u16 eld_reg_to_type[][2] = {
1482                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1483                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1484                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1485                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1486                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1487                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1488                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1489                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1490                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1491                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1492                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1493                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1494         };
1495
1496         if (!dig || !dig->afmt || !dig->afmt->pin)
1497                 return;
1498
1499         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1500                 if (connector->encoder == encoder) {
1501                         amdgpu_connector = to_amdgpu_connector(connector);
1502                         break;
1503                 }
1504         }
1505
1506         if (!amdgpu_connector) {
1507                 DRM_ERROR("Couldn't find encoder's connector\n");
1508                 return;
1509         }
1510
1511         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1512         if (sad_count <= 0) {
1513                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1514                 return;
1515         }
1516         BUG_ON(!sads);
1517
1518         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1519                 u32 tmp = 0;
1520                 u8 stereo_freqs = 0;
1521                 int max_channels = -1;
1522                 int j;
1523
1524                 for (j = 0; j < sad_count; j++) {
1525                         struct cea_sad *sad = &sads[j];
1526
1527                         if (sad->format == eld_reg_to_type[i][1]) {
1528                                 if (sad->channels > max_channels) {
1529                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1530                                                             MAX_CHANNELS, sad->channels);
1531                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1532                                                             DESCRIPTOR_BYTE_2, sad->byte2);
1533                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1534                                                             SUPPORTED_FREQUENCIES, sad->freq);
1535                                         max_channels = sad->channels;
1536                                 }
1537
1538                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1539                                         stereo_freqs |= sad->freq;
1540                                 else
1541                                         break;
1542                         }
1543                 }
1544
1545                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1546                                     SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1547                 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1548         }
1549
1550         kfree(sads);
1551 }
1552
1553 static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1554                                   struct amdgpu_audio_pin *pin,
1555                                   bool enable)
1556 {
1557         if (!pin)
1558                 return;
1559
1560         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1561                            enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1562 }
1563
1564 static const u32 pin_offsets[] =
1565 {
1566         AUD0_REGISTER_OFFSET,
1567         AUD1_REGISTER_OFFSET,
1568         AUD2_REGISTER_OFFSET,
1569         AUD3_REGISTER_OFFSET,
1570         AUD4_REGISTER_OFFSET,
1571         AUD5_REGISTER_OFFSET,
1572         AUD6_REGISTER_OFFSET,
1573         AUD7_REGISTER_OFFSET,
1574 };
1575
1576 static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1577 {
1578         int i;
1579
1580         if (!amdgpu_audio)
1581                 return 0;
1582
1583         adev->mode_info.audio.enabled = true;
1584
1585         switch (adev->asic_type) {
1586         case CHIP_CARRIZO:
1587         case CHIP_STONEY:
1588                 adev->mode_info.audio.num_pins = 7;
1589                 break;
1590         case CHIP_POLARIS10:
1591                 adev->mode_info.audio.num_pins = 8;
1592                 break;
1593         case CHIP_POLARIS11:
1594         case CHIP_POLARIS12:
1595                 adev->mode_info.audio.num_pins = 6;
1596                 break;
1597         default:
1598                 return -EINVAL;
1599         }
1600
1601         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1602                 adev->mode_info.audio.pin[i].channels = -1;
1603                 adev->mode_info.audio.pin[i].rate = -1;
1604                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1605                 adev->mode_info.audio.pin[i].status_bits = 0;
1606                 adev->mode_info.audio.pin[i].category_code = 0;
1607                 adev->mode_info.audio.pin[i].connected = false;
1608                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1609                 adev->mode_info.audio.pin[i].id = i;
1610                 /* disable audio.  it will be set up later */
1611                 /* XXX remove once we switch to ip funcs */
1612                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1613         }
1614
1615         return 0;
1616 }
1617
1618 static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1619 {
1620         int i;
1621
1622         if (!amdgpu_audio)
1623                 return;
1624
1625         if (!adev->mode_info.audio.enabled)
1626                 return;
1627
1628         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1629                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1630
1631         adev->mode_info.audio.enabled = false;
1632 }
1633
1634 /*
1635  * update the N and CTS parameters for a given pixel clock rate
1636  */
1637 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1638 {
1639         struct drm_device *dev = encoder->dev;
1640         struct amdgpu_device *adev = dev->dev_private;
1641         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1642         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1643         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1644         u32 tmp;
1645
1646         tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1647         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1648         WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1649         tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1650         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1651         WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1652
1653         tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1654         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1655         WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1656         tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1657         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1658         WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1659
1660         tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1661         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1662         WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1663         tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1664         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1665         WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1666
1667 }
1668
1669 /*
1670  * build a HDMI Video Info Frame
1671  */
1672 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1673                                                void *buffer, size_t size)
1674 {
1675         struct drm_device *dev = encoder->dev;
1676         struct amdgpu_device *adev = dev->dev_private;
1677         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1678         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1679         uint8_t *frame = buffer + 3;
1680         uint8_t *header = buffer;
1681
1682         WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1683                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1684         WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1685                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1686         WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1687                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1688         WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1689                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1690 }
1691
1692 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1693 {
1694         struct drm_device *dev = encoder->dev;
1695         struct amdgpu_device *adev = dev->dev_private;
1696         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1697         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1698         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1699         u32 dto_phase = 24 * 1000;
1700         u32 dto_modulo = clock;
1701         u32 tmp;
1702
1703         if (!dig || !dig->afmt)
1704                 return;
1705
1706         /* XXX two dtos; generally use dto0 for hdmi */
1707         /* Express [24MHz / target pixel clock] as an exact rational
1708          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1709          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1710          */
1711         tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1712         tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1713                             amdgpu_crtc->crtc_id);
1714         WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1715         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1716         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1717 }
1718
1719 /*
1720  * update the info frames with the data from the current display mode
1721  */
1722 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1723                                   struct drm_display_mode *mode)
1724 {
1725         struct drm_device *dev = encoder->dev;
1726         struct amdgpu_device *adev = dev->dev_private;
1727         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1728         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1729         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1730         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1731         struct hdmi_avi_infoframe frame;
1732         ssize_t err;
1733         u32 tmp;
1734         int bpc = 8;
1735
1736         if (!dig || !dig->afmt)
1737                 return;
1738
1739         /* Silent, r600_hdmi_enable will raise WARN for us */
1740         if (!dig->afmt->enabled)
1741                 return;
1742
1743         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1744         if (encoder->crtc) {
1745                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1746                 bpc = amdgpu_crtc->bpc;
1747         }
1748
1749         /* disable audio prior to setting up hw */
1750         dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1751         dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1752
1753         dce_v11_0_audio_set_dto(encoder, mode->clock);
1754
1755         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1756         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1757         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1758
1759         WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1760
1761         tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1762         switch (bpc) {
1763         case 0:
1764         case 6:
1765         case 8:
1766         case 16:
1767         default:
1768                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1769                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1770                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1771                           connector->name, bpc);
1772                 break;
1773         case 10:
1774                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1775                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1776                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1777                           connector->name);
1778                 break;
1779         case 12:
1780                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1781                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1782                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1783                           connector->name);
1784                 break;
1785         }
1786         WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1787
1788         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1789         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1790         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1791         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1792         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1793
1794         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1795         /* enable audio info frames (frames won't be set until audio is enabled) */
1796         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1797         /* required for audio info values to be updated */
1798         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1799         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1800
1801         tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1802         /* required for audio info values to be updated */
1803         tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1804         WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1805
1806         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1807         /* anything other than 0 */
1808         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1809         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1810
1811         WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1812
1813         tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1814         /* set the default audio delay */
1815         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1816         /* should be suffient for all audio modes and small enough for all hblanks */
1817         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1818         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1819
1820         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1821         /* allow 60958 channel status fields to be updated */
1822         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1823         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1824
1825         tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1826         if (bpc > 8)
1827                 /* clear SW CTS value */
1828                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1829         else
1830                 /* select SW CTS value */
1831                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1832         /* allow hw to sent ACR packets when required */
1833         tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1834         WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1835
1836         dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1837
1838         tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1839         tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1840         WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1841
1842         tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1843         tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1844         WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1845
1846         tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1847         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1848         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1849         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1850         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1851         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1852         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1853         WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1854
1855         dce_v11_0_audio_write_speaker_allocation(encoder);
1856
1857         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1858                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1859
1860         dce_v11_0_afmt_audio_select_pin(encoder);
1861         dce_v11_0_audio_write_sad_regs(encoder);
1862         dce_v11_0_audio_write_latency_fields(encoder, mode);
1863
1864         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1865         if (err < 0) {
1866                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1867                 return;
1868         }
1869
1870         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1871         if (err < 0) {
1872                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1873                 return;
1874         }
1875
1876         dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1877
1878         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1879         /* enable AVI info frames */
1880         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1881         /* required for audio info values to be updated */
1882         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1883         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1884
1885         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1886         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1887         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1888
1889         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1890         /* send audio packets */
1891         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1892         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1893
1894         WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1895         WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1896         WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1897         WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1898
1899         /* enable audio after to setting up hw */
1900         dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1901 }
1902
1903 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1904 {
1905         struct drm_device *dev = encoder->dev;
1906         struct amdgpu_device *adev = dev->dev_private;
1907         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1908         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1909
1910         if (!dig || !dig->afmt)
1911                 return;
1912
1913         /* Silent, r600_hdmi_enable will raise WARN for us */
1914         if (enable && dig->afmt->enabled)
1915                 return;
1916         if (!enable && !dig->afmt->enabled)
1917                 return;
1918
1919         if (!enable && dig->afmt->pin) {
1920                 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1921                 dig->afmt->pin = NULL;
1922         }
1923
1924         dig->afmt->enabled = enable;
1925
1926         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1927                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1928 }
1929
1930 static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
1931 {
1932         int i;
1933
1934         for (i = 0; i < adev->mode_info.num_dig; i++)
1935                 adev->mode_info.afmt[i] = NULL;
1936
1937         /* DCE11 has audio blocks tied to DIG encoders */
1938         for (i = 0; i < adev->mode_info.num_dig; i++) {
1939                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1940                 if (adev->mode_info.afmt[i]) {
1941                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1942                         adev->mode_info.afmt[i]->id = i;
1943                 } else {
1944                         int j;
1945                         for (j = 0; j < i; j++) {
1946                                 kfree(adev->mode_info.afmt[j]);
1947                                 adev->mode_info.afmt[j] = NULL;
1948                         }
1949                         return -ENOMEM;
1950                 }
1951         }
1952         return 0;
1953 }
1954
1955 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1956 {
1957         int i;
1958
1959         for (i = 0; i < adev->mode_info.num_dig; i++) {
1960                 kfree(adev->mode_info.afmt[i]);
1961                 adev->mode_info.afmt[i] = NULL;
1962         }
1963 }
1964
1965 static const u32 vga_control_regs[6] =
1966 {
1967         mmD1VGA_CONTROL,
1968         mmD2VGA_CONTROL,
1969         mmD3VGA_CONTROL,
1970         mmD4VGA_CONTROL,
1971         mmD5VGA_CONTROL,
1972         mmD6VGA_CONTROL,
1973 };
1974
1975 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
1976 {
1977         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1978         struct drm_device *dev = crtc->dev;
1979         struct amdgpu_device *adev = dev->dev_private;
1980         u32 vga_control;
1981
1982         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1983         if (enable)
1984                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1985         else
1986                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1987 }
1988
1989 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
1990 {
1991         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1992         struct drm_device *dev = crtc->dev;
1993         struct amdgpu_device *adev = dev->dev_private;
1994
1995         if (enable)
1996                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1997         else
1998                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1999 }
2000
2001 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
2002                                      struct drm_framebuffer *fb,
2003                                      int x, int y, int atomic)
2004 {
2005         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2006         struct drm_device *dev = crtc->dev;
2007         struct amdgpu_device *adev = dev->dev_private;
2008         struct amdgpu_framebuffer *amdgpu_fb;
2009         struct drm_framebuffer *target_fb;
2010         struct drm_gem_object *obj;
2011         struct amdgpu_bo *abo;
2012         uint64_t fb_location, tiling_flags;
2013         uint32_t fb_format, fb_pitch_pixels;
2014         u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2015         u32 pipe_config;
2016         u32 tmp, viewport_w, viewport_h;
2017         int r;
2018         bool bypass_lut = false;
2019         struct drm_format_name_buf format_name;
2020
2021         /* no fb bound */
2022         if (!atomic && !crtc->primary->fb) {
2023                 DRM_DEBUG_KMS("No FB bound\n");
2024                 return 0;
2025         }
2026
2027         if (atomic) {
2028                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2029                 target_fb = fb;
2030         } else {
2031                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2032                 target_fb = crtc->primary->fb;
2033         }
2034
2035         /* If atomic, assume fb object is pinned & idle & fenced and
2036          * just update base pointers
2037          */
2038         obj = amdgpu_fb->obj;
2039         abo = gem_to_amdgpu_bo(obj);
2040         r = amdgpu_bo_reserve(abo, false);
2041         if (unlikely(r != 0))
2042                 return r;
2043
2044         if (atomic) {
2045                 fb_location = amdgpu_bo_gpu_offset(abo);
2046         } else {
2047                 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2048                 if (unlikely(r != 0)) {
2049                         amdgpu_bo_unreserve(abo);
2050                         return -EINVAL;
2051                 }
2052         }
2053
2054         amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
2055         amdgpu_bo_unreserve(abo);
2056
2057         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2058
2059         switch (target_fb->pixel_format) {
2060         case DRM_FORMAT_C8:
2061                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2062                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2063                 break;
2064         case DRM_FORMAT_XRGB4444:
2065         case DRM_FORMAT_ARGB4444:
2066                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2067                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2068 #ifdef __BIG_ENDIAN
2069                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2070                                         ENDIAN_8IN16);
2071 #endif
2072                 break;
2073         case DRM_FORMAT_XRGB1555:
2074         case DRM_FORMAT_ARGB1555:
2075                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2076                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2077 #ifdef __BIG_ENDIAN
2078                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2079                                         ENDIAN_8IN16);
2080 #endif
2081                 break;
2082         case DRM_FORMAT_BGRX5551:
2083         case DRM_FORMAT_BGRA5551:
2084                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2085                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2086 #ifdef __BIG_ENDIAN
2087                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2088                                         ENDIAN_8IN16);
2089 #endif
2090                 break;
2091         case DRM_FORMAT_RGB565:
2092                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2093                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2094 #ifdef __BIG_ENDIAN
2095                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2096                                         ENDIAN_8IN16);
2097 #endif
2098                 break;
2099         case DRM_FORMAT_XRGB8888:
2100         case DRM_FORMAT_ARGB8888:
2101                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2102                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2103 #ifdef __BIG_ENDIAN
2104                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2105                                         ENDIAN_8IN32);
2106 #endif
2107                 break;
2108         case DRM_FORMAT_XRGB2101010:
2109         case DRM_FORMAT_ARGB2101010:
2110                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2111                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2112 #ifdef __BIG_ENDIAN
2113                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2114                                         ENDIAN_8IN32);
2115 #endif
2116                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2117                 bypass_lut = true;
2118                 break;
2119         case DRM_FORMAT_BGRX1010102:
2120         case DRM_FORMAT_BGRA1010102:
2121                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2122                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2123 #ifdef __BIG_ENDIAN
2124                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2125                                         ENDIAN_8IN32);
2126 #endif
2127                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2128                 bypass_lut = true;
2129                 break;
2130         default:
2131                 DRM_ERROR("Unsupported screen format %s\n",
2132                           drm_get_format_name(target_fb->pixel_format, &format_name));
2133                 return -EINVAL;
2134         }
2135
2136         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2137                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2138
2139                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2140                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2141                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2142                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2143                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2144
2145                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2146                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2147                                           ARRAY_2D_TILED_THIN1);
2148                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2149                                           tile_split);
2150                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2151                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2152                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2153                                           mtaspect);
2154                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2155                                           ADDR_SURF_MICRO_TILING_DISPLAY);
2156         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2157                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2158                                           ARRAY_1D_TILED_THIN1);
2159         }
2160
2161         fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2162                                   pipe_config);
2163
2164         dce_v11_0_vga_enable(crtc, false);
2165
2166         /* Make sure surface address is updated at vertical blank rather than
2167          * horizontal blank
2168          */
2169         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2170         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2171                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2172         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2173
2174         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2175                upper_32_bits(fb_location));
2176         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2177                upper_32_bits(fb_location));
2178         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2179                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2180         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2181                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2182         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2183         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2184
2185         /*
2186          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2187          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2188          * retain the full precision throughout the pipeline.
2189          */
2190         tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2191         if (bypass_lut)
2192                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2193         else
2194                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2195         WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2196
2197         if (bypass_lut)
2198                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2199
2200         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2201         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2202         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2203         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2204         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2205         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2206
2207         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2208         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2209
2210         dce_v11_0_grph_enable(crtc, true);
2211
2212         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2213                target_fb->height);
2214
2215         x &= ~3;
2216         y &= ~1;
2217         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2218                (x << 16) | y);
2219         viewport_w = crtc->mode.hdisplay;
2220         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2221         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2222                (viewport_w << 16) | viewport_h);
2223
2224         /* set pageflip to happen anywhere in vblank interval */
2225         WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2226
2227         if (!atomic && fb && fb != crtc->primary->fb) {
2228                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2229                 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2230                 r = amdgpu_bo_reserve(abo, false);
2231                 if (unlikely(r != 0))
2232                         return r;
2233                 amdgpu_bo_unpin(abo);
2234                 amdgpu_bo_unreserve(abo);
2235         }
2236
2237         /* Bytes per pixel may have changed */
2238         dce_v11_0_bandwidth_update(adev);
2239
2240         return 0;
2241 }
2242
2243 static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2244                                      struct drm_display_mode *mode)
2245 {
2246         struct drm_device *dev = crtc->dev;
2247         struct amdgpu_device *adev = dev->dev_private;
2248         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2249         u32 tmp;
2250
2251         tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2252         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2253                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2254         else
2255                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2256         WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2257 }
2258
2259 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2260 {
2261         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2262         struct drm_device *dev = crtc->dev;
2263         struct amdgpu_device *adev = dev->dev_private;
2264         int i;
2265         u32 tmp;
2266
2267         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2268
2269         tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2270         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2271         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2272
2273         tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2274         tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2275         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2276
2277         tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2278         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2279         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2280
2281         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2282
2283         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2284         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2285         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2286
2287         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2288         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2289         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2290
2291         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2292         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2293
2294         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2295         for (i = 0; i < 256; i++) {
2296                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2297                        (amdgpu_crtc->lut_r[i] << 20) |
2298                        (amdgpu_crtc->lut_g[i] << 10) |
2299                        (amdgpu_crtc->lut_b[i] << 0));
2300         }
2301
2302         tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2303         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2304         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2305         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2306         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2307
2308         tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2309         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2310         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2311
2312         tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2313         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2314         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2315
2316         tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2317         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2318         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2319
2320         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2321         WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2322         /* XXX this only needs to be programmed once per crtc at startup,
2323          * not sure where the best place for it is
2324          */
2325         tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2326         tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2327         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2328 }
2329
2330 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2331 {
2332         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2333         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2334
2335         switch (amdgpu_encoder->encoder_id) {
2336         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2337                 if (dig->linkb)
2338                         return 1;
2339                 else
2340                         return 0;
2341                 break;
2342         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2343                 if (dig->linkb)
2344                         return 3;
2345                 else
2346                         return 2;
2347                 break;
2348         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2349                 if (dig->linkb)
2350                         return 5;
2351                 else
2352                         return 4;
2353                 break;
2354         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2355                 return 6;
2356                 break;
2357         default:
2358                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2359                 return 0;
2360         }
2361 }
2362
2363 /**
2364  * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2365  *
2366  * @crtc: drm crtc
2367  *
2368  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2369  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2370  * monitors a dedicated PPLL must be used.  If a particular board has
2371  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2372  * as there is no need to program the PLL itself.  If we are not able to
2373  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2374  * avoid messing up an existing monitor.
2375  *
2376  * Asic specific PLL information
2377  *
2378  * DCE 10.x
2379  * Tonga
2380  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2381  * CI
2382  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2383  *
2384  */
2385 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2386 {
2387         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2388         struct drm_device *dev = crtc->dev;
2389         struct amdgpu_device *adev = dev->dev_private;
2390         u32 pll_in_use;
2391         int pll;
2392
2393         if ((adev->asic_type == CHIP_POLARIS10) ||
2394             (adev->asic_type == CHIP_POLARIS11) ||
2395             (adev->asic_type == CHIP_POLARIS12)) {
2396                 struct amdgpu_encoder *amdgpu_encoder =
2397                         to_amdgpu_encoder(amdgpu_crtc->encoder);
2398                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2399
2400                 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2401                         return ATOM_DP_DTO;
2402
2403                 switch (amdgpu_encoder->encoder_id) {
2404                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2405                         if (dig->linkb)
2406                                 return ATOM_COMBOPHY_PLL1;
2407                         else
2408                                 return ATOM_COMBOPHY_PLL0;
2409                         break;
2410                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2411                         if (dig->linkb)
2412                                 return ATOM_COMBOPHY_PLL3;
2413                         else
2414                                 return ATOM_COMBOPHY_PLL2;
2415                         break;
2416                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2417                         if (dig->linkb)
2418                                 return ATOM_COMBOPHY_PLL5;
2419                         else
2420                                 return ATOM_COMBOPHY_PLL4;
2421                         break;
2422                 default:
2423                         DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2424                         return ATOM_PPLL_INVALID;
2425                 }
2426         }
2427
2428         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2429                 if (adev->clock.dp_extclk)
2430                         /* skip PPLL programming if using ext clock */
2431                         return ATOM_PPLL_INVALID;
2432                 else {
2433                         /* use the same PPLL for all DP monitors */
2434                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2435                         if (pll != ATOM_PPLL_INVALID)
2436                                 return pll;
2437                 }
2438         } else {
2439                 /* use the same PPLL for all monitors with the same clock */
2440                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2441                 if (pll != ATOM_PPLL_INVALID)
2442                         return pll;
2443         }
2444
2445         /* XXX need to determine what plls are available on each DCE11 part */
2446         pll_in_use = amdgpu_pll_get_use_mask(crtc);
2447         if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
2448                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2449                         return ATOM_PPLL1;
2450                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2451                         return ATOM_PPLL0;
2452                 DRM_ERROR("unable to allocate a PPLL\n");
2453                 return ATOM_PPLL_INVALID;
2454         } else {
2455                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2456                         return ATOM_PPLL2;
2457                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2458                         return ATOM_PPLL1;
2459                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2460                         return ATOM_PPLL0;
2461                 DRM_ERROR("unable to allocate a PPLL\n");
2462                 return ATOM_PPLL_INVALID;
2463         }
2464         return ATOM_PPLL_INVALID;
2465 }
2466
2467 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2468 {
2469         struct amdgpu_device *adev = crtc->dev->dev_private;
2470         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2471         uint32_t cur_lock;
2472
2473         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2474         if (lock)
2475                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2476         else
2477                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2478         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2479 }
2480
2481 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2482 {
2483         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2484         struct amdgpu_device *adev = crtc->dev->dev_private;
2485         u32 tmp;
2486
2487         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2488         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2489         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2490 }
2491
2492 static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2493 {
2494         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2495         struct amdgpu_device *adev = crtc->dev->dev_private;
2496         u32 tmp;
2497
2498         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2499                upper_32_bits(amdgpu_crtc->cursor_addr));
2500         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2501                lower_32_bits(amdgpu_crtc->cursor_addr));
2502
2503         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2504         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2505         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2506         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2507 }
2508
2509 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2510                                         int x, int y)
2511 {
2512         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2513         struct amdgpu_device *adev = crtc->dev->dev_private;
2514         int xorigin = 0, yorigin = 0;
2515
2516         amdgpu_crtc->cursor_x = x;
2517         amdgpu_crtc->cursor_y = y;
2518
2519         /* avivo cursor are offset into the total surface */
2520         x += crtc->x;
2521         y += crtc->y;
2522         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2523
2524         if (x < 0) {
2525                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2526                 x = 0;
2527         }
2528         if (y < 0) {
2529                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2530                 y = 0;
2531         }
2532
2533         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2534         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2535
2536         return 0;
2537 }
2538
2539 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2540                                       int x, int y)
2541 {
2542         int ret;
2543
2544         dce_v11_0_lock_cursor(crtc, true);
2545         ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2546         dce_v11_0_lock_cursor(crtc, false);
2547
2548         return ret;
2549 }
2550
2551 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2552                                       struct drm_file *file_priv,
2553                                       uint32_t handle,
2554                                       uint32_t width,
2555                                       uint32_t height,
2556                                       int32_t hot_x,
2557                                       int32_t hot_y)
2558 {
2559         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2560         struct amdgpu_device *adev = crtc->dev->dev_private;
2561         struct drm_gem_object *obj;
2562         struct amdgpu_bo *aobj;
2563         int ret;
2564
2565         if (!handle) {
2566                 /* turn off cursor */
2567                 dce_v11_0_hide_cursor(crtc);
2568                 obj = NULL;
2569                 goto unpin;
2570         }
2571
2572         if ((width > amdgpu_crtc->max_cursor_width) ||
2573             (height > amdgpu_crtc->max_cursor_height)) {
2574                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2575                 return -EINVAL;
2576         }
2577
2578         obj = drm_gem_object_lookup(file_priv, handle);
2579         if (!obj) {
2580                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2581                 return -ENOENT;
2582         }
2583
2584         aobj = gem_to_amdgpu_bo(obj);
2585         ret = amdgpu_bo_reserve(aobj, false);
2586         if (ret != 0) {
2587                 drm_gem_object_unreference_unlocked(obj);
2588                 return ret;
2589         }
2590
2591         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2592         amdgpu_bo_unreserve(aobj);
2593         if (ret) {
2594                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2595                 drm_gem_object_unreference_unlocked(obj);
2596                 return ret;
2597         }
2598
2599         dce_v11_0_lock_cursor(crtc, true);
2600
2601         if (hot_x != amdgpu_crtc->cursor_hot_x ||
2602             hot_y != amdgpu_crtc->cursor_hot_y) {
2603                 int x, y;
2604
2605                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2606                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2607
2608                 dce_v11_0_cursor_move_locked(crtc, x, y);
2609
2610                 amdgpu_crtc->cursor_hot_x = hot_x;
2611                 amdgpu_crtc->cursor_hot_y = hot_y;
2612         }
2613
2614         if (width != amdgpu_crtc->cursor_width ||
2615             height != amdgpu_crtc->cursor_height) {
2616                 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2617                        (width - 1) << 16 | (height - 1));
2618                 amdgpu_crtc->cursor_width = width;
2619                 amdgpu_crtc->cursor_height = height;
2620         }
2621
2622         dce_v11_0_show_cursor(crtc);
2623         dce_v11_0_lock_cursor(crtc, false);
2624
2625 unpin:
2626         if (amdgpu_crtc->cursor_bo) {
2627                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2628                 ret = amdgpu_bo_reserve(aobj, false);
2629                 if (likely(ret == 0)) {
2630                         amdgpu_bo_unpin(aobj);
2631                         amdgpu_bo_unreserve(aobj);
2632                 }
2633                 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2634         }
2635
2636         amdgpu_crtc->cursor_bo = obj;
2637         return 0;
2638 }
2639
2640 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2641 {
2642         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2643         struct amdgpu_device *adev = crtc->dev->dev_private;
2644
2645         if (amdgpu_crtc->cursor_bo) {
2646                 dce_v11_0_lock_cursor(crtc, true);
2647
2648                 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2649                                              amdgpu_crtc->cursor_y);
2650
2651                 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2652                        (amdgpu_crtc->cursor_width - 1) << 16 |
2653                        (amdgpu_crtc->cursor_height - 1));
2654
2655                 dce_v11_0_show_cursor(crtc);
2656
2657                 dce_v11_0_lock_cursor(crtc, false);
2658         }
2659 }
2660
2661 static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2662                                     u16 *blue, uint32_t size)
2663 {
2664         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2665         int i;
2666
2667         /* userspace palettes are always correct as is */
2668         for (i = 0; i < size; i++) {
2669                 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2670                 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2671                 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2672         }
2673         dce_v11_0_crtc_load_lut(crtc);
2674
2675         return 0;
2676 }
2677
2678 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2679 {
2680         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2681
2682         drm_crtc_cleanup(crtc);
2683         kfree(amdgpu_crtc);
2684 }
2685
2686 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2687         .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2688         .cursor_move = dce_v11_0_crtc_cursor_move,
2689         .gamma_set = dce_v11_0_crtc_gamma_set,
2690         .set_config = amdgpu_crtc_set_config,
2691         .destroy = dce_v11_0_crtc_destroy,
2692         .page_flip_target = amdgpu_crtc_page_flip_target,
2693 };
2694
2695 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2696 {
2697         struct drm_device *dev = crtc->dev;
2698         struct amdgpu_device *adev = dev->dev_private;
2699         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2700         unsigned type;
2701
2702         switch (mode) {
2703         case DRM_MODE_DPMS_ON:
2704                 amdgpu_crtc->enabled = true;
2705                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2706                 dce_v11_0_vga_enable(crtc, true);
2707                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2708                 dce_v11_0_vga_enable(crtc, false);
2709                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2710                 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2711                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2712                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2713                 drm_crtc_vblank_on(crtc);
2714                 dce_v11_0_crtc_load_lut(crtc);
2715                 break;
2716         case DRM_MODE_DPMS_STANDBY:
2717         case DRM_MODE_DPMS_SUSPEND:
2718         case DRM_MODE_DPMS_OFF:
2719                 drm_crtc_vblank_off(crtc);
2720                 if (amdgpu_crtc->enabled) {
2721                         dce_v11_0_vga_enable(crtc, true);
2722                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2723                         dce_v11_0_vga_enable(crtc, false);
2724                 }
2725                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2726                 amdgpu_crtc->enabled = false;
2727                 break;
2728         }
2729         /* adjust pm to dpms */
2730         amdgpu_pm_compute_clocks(adev);
2731 }
2732
2733 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2734 {
2735         /* disable crtc pair power gating before programming */
2736         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2737         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2738         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2739 }
2740
2741 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2742 {
2743         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2744         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2745 }
2746
2747 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2748 {
2749         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2750         struct drm_device *dev = crtc->dev;
2751         struct amdgpu_device *adev = dev->dev_private;
2752         struct amdgpu_atom_ss ss;
2753         int i;
2754
2755         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2756         if (crtc->primary->fb) {
2757                 int r;
2758                 struct amdgpu_framebuffer *amdgpu_fb;
2759                 struct amdgpu_bo *abo;
2760
2761                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2762                 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2763                 r = amdgpu_bo_reserve(abo, false);
2764                 if (unlikely(r))
2765                         DRM_ERROR("failed to reserve abo before unpin\n");
2766                 else {
2767                         amdgpu_bo_unpin(abo);
2768                         amdgpu_bo_unreserve(abo);
2769                 }
2770         }
2771         /* disable the GRPH */
2772         dce_v11_0_grph_enable(crtc, false);
2773
2774         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2775
2776         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2777                 if (adev->mode_info.crtcs[i] &&
2778                     adev->mode_info.crtcs[i]->enabled &&
2779                     i != amdgpu_crtc->crtc_id &&
2780                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2781                         /* one other crtc is using this pll don't turn
2782                          * off the pll
2783                          */
2784                         goto done;
2785                 }
2786         }
2787
2788         switch (amdgpu_crtc->pll_id) {
2789         case ATOM_PPLL0:
2790         case ATOM_PPLL1:
2791         case ATOM_PPLL2:
2792                 /* disable the ppll */
2793                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2794                                                  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2795                 break;
2796         case ATOM_COMBOPHY_PLL0:
2797         case ATOM_COMBOPHY_PLL1:
2798         case ATOM_COMBOPHY_PLL2:
2799         case ATOM_COMBOPHY_PLL3:
2800         case ATOM_COMBOPHY_PLL4:
2801         case ATOM_COMBOPHY_PLL5:
2802                 /* disable the ppll */
2803                 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
2804                                                  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2805                 break;
2806         default:
2807                 break;
2808         }
2809 done:
2810         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2811         amdgpu_crtc->adjusted_clock = 0;
2812         amdgpu_crtc->encoder = NULL;
2813         amdgpu_crtc->connector = NULL;
2814 }
2815
2816 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2817                                   struct drm_display_mode *mode,
2818                                   struct drm_display_mode *adjusted_mode,
2819                                   int x, int y, struct drm_framebuffer *old_fb)
2820 {
2821         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2822         struct drm_device *dev = crtc->dev;
2823         struct amdgpu_device *adev = dev->dev_private;
2824
2825         if (!amdgpu_crtc->adjusted_clock)
2826                 return -EINVAL;
2827
2828         if ((adev->asic_type == CHIP_POLARIS10) ||
2829             (adev->asic_type == CHIP_POLARIS11) ||
2830             (adev->asic_type == CHIP_POLARIS12)) {
2831                 struct amdgpu_encoder *amdgpu_encoder =
2832                         to_amdgpu_encoder(amdgpu_crtc->encoder);
2833                 int encoder_mode =
2834                         amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2835
2836                 /* SetPixelClock calculates the plls and ss values now */
2837                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2838                                                  amdgpu_crtc->pll_id,
2839                                                  encoder_mode, amdgpu_encoder->encoder_id,
2840                                                  adjusted_mode->clock, 0, 0, 0, 0,
2841                                                  amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2842         } else {
2843                 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2844         }
2845         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2846         dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2847         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2848         amdgpu_atombios_crtc_scaler_setup(crtc);
2849         dce_v11_0_cursor_reset(crtc);
2850         /* update the hw version fpr dpm */
2851         amdgpu_crtc->hw_mode = *adjusted_mode;
2852
2853         return 0;
2854 }
2855
2856 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2857                                      const struct drm_display_mode *mode,
2858                                      struct drm_display_mode *adjusted_mode)
2859 {
2860         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2861         struct drm_device *dev = crtc->dev;
2862         struct drm_encoder *encoder;
2863
2864         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2865         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2866                 if (encoder->crtc == crtc) {
2867                         amdgpu_crtc->encoder = encoder;
2868                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2869                         break;
2870                 }
2871         }
2872         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2873                 amdgpu_crtc->encoder = NULL;
2874                 amdgpu_crtc->connector = NULL;
2875                 return false;
2876         }
2877         if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2878                 return false;
2879         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2880                 return false;
2881         /* pick pll */
2882         amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2883         /* if we can't get a PPLL for a non-DP encoder, fail */
2884         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2885             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2886                 return false;
2887
2888         return true;
2889 }
2890
2891 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2892                                   struct drm_framebuffer *old_fb)
2893 {
2894         return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2895 }
2896
2897 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2898                                          struct drm_framebuffer *fb,
2899                                          int x, int y, enum mode_set_atomic state)
2900 {
2901        return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2902 }
2903
2904 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2905         .dpms = dce_v11_0_crtc_dpms,
2906         .mode_fixup = dce_v11_0_crtc_mode_fixup,
2907         .mode_set = dce_v11_0_crtc_mode_set,
2908         .mode_set_base = dce_v11_0_crtc_set_base,
2909         .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2910         .prepare = dce_v11_0_crtc_prepare,
2911         .commit = dce_v11_0_crtc_commit,
2912         .load_lut = dce_v11_0_crtc_load_lut,
2913         .disable = dce_v11_0_crtc_disable,
2914 };
2915
2916 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2917 {
2918         struct amdgpu_crtc *amdgpu_crtc;
2919         int i;
2920
2921         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2922                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2923         if (amdgpu_crtc == NULL)
2924                 return -ENOMEM;
2925
2926         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2927
2928         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2929         amdgpu_crtc->crtc_id = index;
2930         adev->mode_info.crtcs[index] = amdgpu_crtc;
2931
2932         amdgpu_crtc->max_cursor_width = 128;
2933         amdgpu_crtc->max_cursor_height = 128;
2934         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2935         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2936
2937         for (i = 0; i < 256; i++) {
2938                 amdgpu_crtc->lut_r[i] = i << 2;
2939                 amdgpu_crtc->lut_g[i] = i << 2;
2940                 amdgpu_crtc->lut_b[i] = i << 2;
2941         }
2942
2943         switch (amdgpu_crtc->crtc_id) {
2944         case 0:
2945         default:
2946                 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2947                 break;
2948         case 1:
2949                 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2950                 break;
2951         case 2:
2952                 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2953                 break;
2954         case 3:
2955                 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2956                 break;
2957         case 4:
2958                 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2959                 break;
2960         case 5:
2961                 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2962                 break;
2963         }
2964
2965         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2966         amdgpu_crtc->adjusted_clock = 0;
2967         amdgpu_crtc->encoder = NULL;
2968         amdgpu_crtc->connector = NULL;
2969         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2970
2971         return 0;
2972 }
2973
2974 static int dce_v11_0_early_init(void *handle)
2975 {
2976         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2977
2978         adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2979         adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2980
2981         dce_v11_0_set_display_funcs(adev);
2982         dce_v11_0_set_irq_funcs(adev);
2983
2984         adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
2985
2986         switch (adev->asic_type) {
2987         case CHIP_CARRIZO:
2988                 adev->mode_info.num_hpd = 6;
2989                 adev->mode_info.num_dig = 9;
2990                 break;
2991         case CHIP_STONEY:
2992                 adev->mode_info.num_hpd = 6;
2993                 adev->mode_info.num_dig = 9;
2994                 break;
2995         case CHIP_POLARIS10:
2996                 adev->mode_info.num_hpd = 6;
2997                 adev->mode_info.num_dig = 6;
2998                 break;
2999         case CHIP_POLARIS11:
3000         case CHIP_POLARIS12:
3001                 adev->mode_info.num_hpd = 5;
3002                 adev->mode_info.num_dig = 5;
3003                 break;
3004         default:
3005                 /* FIXME: not supported yet */
3006                 return -EINVAL;
3007         }
3008
3009         return 0;
3010 }
3011
3012 static int dce_v11_0_sw_init(void *handle)
3013 {
3014         int r, i;
3015         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3016
3017         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3018                 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
3019                 if (r)
3020                         return r;
3021         }
3022
3023         for (i = 8; i < 20; i += 2) {
3024                 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
3025                 if (r)
3026                         return r;
3027         }
3028
3029         /* HPD hotplug */
3030         r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
3031         if (r)
3032                 return r;
3033
3034         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
3035
3036         adev->ddev->mode_config.async_page_flip = true;
3037
3038         adev->ddev->mode_config.max_width = 16384;
3039         adev->ddev->mode_config.max_height = 16384;
3040
3041         adev->ddev->mode_config.preferred_depth = 24;
3042         adev->ddev->mode_config.prefer_shadow = 1;
3043
3044         adev->ddev->mode_config.fb_base = adev->mc.aper_base;
3045
3046         r = amdgpu_modeset_create_props(adev);
3047         if (r)
3048                 return r;
3049
3050         adev->ddev->mode_config.max_width = 16384;
3051         adev->ddev->mode_config.max_height = 16384;
3052
3053
3054         /* allocate crtcs */
3055         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3056                 r = dce_v11_0_crtc_init(adev, i);
3057                 if (r)
3058                         return r;
3059         }
3060
3061         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
3062                 amdgpu_print_display_setup(adev->ddev);
3063         else
3064                 return -EINVAL;
3065
3066         /* setup afmt */
3067         r = dce_v11_0_afmt_init(adev);
3068         if (r)
3069                 return r;
3070
3071         r = dce_v11_0_audio_init(adev);
3072         if (r)
3073                 return r;
3074
3075         drm_kms_helper_poll_init(adev->ddev);
3076
3077         adev->mode_info.mode_config_initialized = true;
3078         return 0;
3079 }
3080
3081 static int dce_v11_0_sw_fini(void *handle)
3082 {
3083         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3084
3085         kfree(adev->mode_info.bios_hardcoded_edid);
3086
3087         drm_kms_helper_poll_fini(adev->ddev);
3088
3089         dce_v11_0_audio_fini(adev);
3090
3091         dce_v11_0_afmt_fini(adev);
3092
3093         drm_mode_config_cleanup(adev->ddev);
3094         adev->mode_info.mode_config_initialized = false;
3095
3096         return 0;
3097 }
3098
3099 static int dce_v11_0_hw_init(void *handle)
3100 {
3101         int i;
3102         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3103
3104         dce_v11_0_init_golden_registers(adev);
3105
3106         /* init dig PHYs, disp eng pll */
3107         amdgpu_atombios_crtc_powergate_init(adev);
3108         amdgpu_atombios_encoder_init_dig(adev);
3109         if ((adev->asic_type == CHIP_POLARIS10) ||
3110             (adev->asic_type == CHIP_POLARIS11) ||
3111             (adev->asic_type == CHIP_POLARIS12)) {
3112                 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
3113                                                    DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
3114                 amdgpu_atombios_crtc_set_dce_clock(adev, 0,
3115                                                    DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
3116         } else {
3117                 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3118         }
3119
3120         /* initialize hpd */
3121         dce_v11_0_hpd_init(adev);
3122
3123         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3124                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3125         }
3126
3127         dce_v11_0_pageflip_interrupt_init(adev);
3128
3129         return 0;
3130 }
3131
3132 static int dce_v11_0_hw_fini(void *handle)
3133 {
3134         int i;
3135         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3136
3137         dce_v11_0_hpd_fini(adev);
3138
3139         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3140                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3141         }
3142
3143         dce_v11_0_pageflip_interrupt_fini(adev);
3144
3145         return 0;
3146 }
3147
3148 static int dce_v11_0_suspend(void *handle)
3149 {
3150         return dce_v11_0_hw_fini(handle);
3151 }
3152
3153 static int dce_v11_0_resume(void *handle)
3154 {
3155         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3156         int ret;
3157
3158         ret = dce_v11_0_hw_init(handle);
3159
3160         /* turn on the BL */
3161         if (adev->mode_info.bl_encoder) {
3162                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3163                                                                   adev->mode_info.bl_encoder);
3164                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3165                                                     bl_level);
3166         }
3167
3168         return ret;
3169 }
3170
3171 static bool dce_v11_0_is_idle(void *handle)
3172 {
3173         return true;
3174 }
3175
3176 static int dce_v11_0_wait_for_idle(void *handle)
3177 {
3178         return 0;
3179 }
3180
3181 static int dce_v11_0_soft_reset(void *handle)
3182 {
3183         u32 srbm_soft_reset = 0, tmp;
3184         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3185
3186         if (dce_v11_0_is_display_hung(adev))
3187                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3188
3189         if (srbm_soft_reset) {
3190                 tmp = RREG32(mmSRBM_SOFT_RESET);
3191                 tmp |= srbm_soft_reset;
3192                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3193                 WREG32(mmSRBM_SOFT_RESET, tmp);
3194                 tmp = RREG32(mmSRBM_SOFT_RESET);
3195
3196                 udelay(50);
3197
3198                 tmp &= ~srbm_soft_reset;
3199                 WREG32(mmSRBM_SOFT_RESET, tmp);
3200                 tmp = RREG32(mmSRBM_SOFT_RESET);
3201
3202                 /* Wait a little for things to settle down */
3203                 udelay(50);
3204         }
3205         return 0;
3206 }
3207
3208 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3209                                                      int crtc,
3210                                                      enum amdgpu_interrupt_state state)
3211 {
3212         u32 lb_interrupt_mask;
3213
3214         if (crtc >= adev->mode_info.num_crtc) {
3215                 DRM_DEBUG("invalid crtc %d\n", crtc);
3216                 return;
3217         }
3218
3219         switch (state) {
3220         case AMDGPU_IRQ_STATE_DISABLE:
3221                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3222                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3223                                                   VBLANK_INTERRUPT_MASK, 0);
3224                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3225                 break;
3226         case AMDGPU_IRQ_STATE_ENABLE:
3227                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3228                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3229                                                   VBLANK_INTERRUPT_MASK, 1);
3230                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3231                 break;
3232         default:
3233                 break;
3234         }
3235 }
3236
3237 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3238                                                     int crtc,
3239                                                     enum amdgpu_interrupt_state state)
3240 {
3241         u32 lb_interrupt_mask;
3242
3243         if (crtc >= adev->mode_info.num_crtc) {
3244                 DRM_DEBUG("invalid crtc %d\n", crtc);
3245                 return;
3246         }
3247
3248         switch (state) {
3249         case AMDGPU_IRQ_STATE_DISABLE:
3250                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3251                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3252                                                   VLINE_INTERRUPT_MASK, 0);
3253                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3254                 break;
3255         case AMDGPU_IRQ_STATE_ENABLE:
3256                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3257                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3258                                                   VLINE_INTERRUPT_MASK, 1);
3259                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3260                 break;
3261         default:
3262                 break;
3263         }
3264 }
3265
3266 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3267                                         struct amdgpu_irq_src *source,
3268                                         unsigned hpd,
3269                                         enum amdgpu_interrupt_state state)
3270 {
3271         u32 tmp;
3272
3273         if (hpd >= adev->mode_info.num_hpd) {
3274                 DRM_DEBUG("invalid hdp %d\n", hpd);
3275                 return 0;
3276         }
3277
3278         switch (state) {
3279         case AMDGPU_IRQ_STATE_DISABLE:
3280                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3281                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3282                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3283                 break;
3284         case AMDGPU_IRQ_STATE_ENABLE:
3285                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3286                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3287                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3288                 break;
3289         default:
3290                 break;
3291         }
3292
3293         return 0;
3294 }
3295
3296 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3297                                         struct amdgpu_irq_src *source,
3298                                         unsigned type,
3299                                         enum amdgpu_interrupt_state state)
3300 {
3301         switch (type) {
3302         case AMDGPU_CRTC_IRQ_VBLANK1:
3303                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3304                 break;
3305         case AMDGPU_CRTC_IRQ_VBLANK2:
3306                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3307                 break;
3308         case AMDGPU_CRTC_IRQ_VBLANK3:
3309                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3310                 break;
3311         case AMDGPU_CRTC_IRQ_VBLANK4:
3312                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3313                 break;
3314         case AMDGPU_CRTC_IRQ_VBLANK5:
3315                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3316                 break;
3317         case AMDGPU_CRTC_IRQ_VBLANK6:
3318                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3319                 break;
3320         case AMDGPU_CRTC_IRQ_VLINE1:
3321                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3322                 break;
3323         case AMDGPU_CRTC_IRQ_VLINE2:
3324                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3325                 break;
3326         case AMDGPU_CRTC_IRQ_VLINE3:
3327                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3328                 break;
3329         case AMDGPU_CRTC_IRQ_VLINE4:
3330                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3331                 break;
3332         case AMDGPU_CRTC_IRQ_VLINE5:
3333                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3334                 break;
3335          case AMDGPU_CRTC_IRQ_VLINE6:
3336                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3337                 break;
3338         default:
3339                 break;
3340         }
3341         return 0;
3342 }
3343
3344 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3345                                             struct amdgpu_irq_src *src,
3346                                             unsigned type,
3347                                             enum amdgpu_interrupt_state state)
3348 {
3349         u32 reg;
3350
3351         if (type >= adev->mode_info.num_crtc) {
3352                 DRM_ERROR("invalid pageflip crtc %d\n", type);
3353                 return -EINVAL;
3354         }
3355
3356         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3357         if (state == AMDGPU_IRQ_STATE_DISABLE)
3358                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3359                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3360         else
3361                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3362                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3363
3364         return 0;
3365 }
3366
3367 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3368                                   struct amdgpu_irq_src *source,
3369                                   struct amdgpu_iv_entry *entry)
3370 {
3371         unsigned long flags;
3372         unsigned crtc_id;
3373         struct amdgpu_crtc *amdgpu_crtc;
3374         struct amdgpu_flip_work *works;
3375
3376         crtc_id = (entry->src_id - 8) >> 1;
3377         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3378
3379         if (crtc_id >= adev->mode_info.num_crtc) {
3380                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3381                 return -EINVAL;
3382         }
3383
3384         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3385             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3386                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3387                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3388
3389         /* IRQ could occur when in initial stage */
3390         if(amdgpu_crtc == NULL)
3391                 return 0;
3392
3393         spin_lock_irqsave(&adev->ddev->event_lock, flags);
3394         works = amdgpu_crtc->pflip_works;
3395         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3396                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3397                                                  "AMDGPU_FLIP_SUBMITTED(%d)\n",
3398                                                  amdgpu_crtc->pflip_status,
3399                                                  AMDGPU_FLIP_SUBMITTED);
3400                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3401                 return 0;
3402         }
3403
3404         /* page flip completed. clean up */
3405         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3406         amdgpu_crtc->pflip_works = NULL;
3407
3408         /* wakeup usersapce */
3409         if(works->event)
3410                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3411
3412         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3413
3414         drm_crtc_vblank_put(&amdgpu_crtc->base);
3415         schedule_work(&works->unpin_work);
3416
3417         return 0;
3418 }
3419
3420 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3421                                   int hpd)
3422 {
3423         u32 tmp;
3424
3425         if (hpd >= adev->mode_info.num_hpd) {
3426                 DRM_DEBUG("invalid hdp %d\n", hpd);
3427                 return;
3428         }
3429
3430         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3431         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3432         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3433 }
3434
3435 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3436                                           int crtc)
3437 {
3438         u32 tmp;
3439
3440         if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3441                 DRM_DEBUG("invalid crtc %d\n", crtc);
3442                 return;
3443         }
3444
3445         tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3446         tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3447         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3448 }
3449
3450 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3451                                          int crtc)
3452 {
3453         u32 tmp;
3454
3455         if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3456                 DRM_DEBUG("invalid crtc %d\n", crtc);
3457                 return;
3458         }
3459
3460         tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3461         tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3462         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3463 }
3464
3465 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3466                                 struct amdgpu_irq_src *source,
3467                                 struct amdgpu_iv_entry *entry)
3468 {
3469         unsigned crtc = entry->src_id - 1;
3470         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3471         unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3472
3473         switch (entry->src_data) {
3474         case 0: /* vblank */
3475                 if (disp_int & interrupt_status_offsets[crtc].vblank)
3476                         dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3477                 else
3478                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3479
3480                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3481                         drm_handle_vblank(adev->ddev, crtc);
3482                 }
3483                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3484
3485                 break;
3486         case 1: /* vline */
3487                 if (disp_int & interrupt_status_offsets[crtc].vline)
3488                         dce_v11_0_crtc_vline_int_ack(adev, crtc);
3489                 else
3490                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3491
3492                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3493
3494                 break;
3495         default:
3496                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3497                 break;
3498         }
3499
3500         return 0;
3501 }
3502
3503 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3504                              struct amdgpu_irq_src *source,
3505                              struct amdgpu_iv_entry *entry)
3506 {
3507         uint32_t disp_int, mask;
3508         unsigned hpd;
3509
3510         if (entry->src_data >= adev->mode_info.num_hpd) {
3511                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3512                 return 0;
3513         }
3514
3515         hpd = entry->src_data;
3516         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3517         mask = interrupt_status_offsets[hpd].hpd;
3518
3519         if (disp_int & mask) {
3520                 dce_v11_0_hpd_int_ack(adev, hpd);
3521                 schedule_work(&adev->hotplug_work);
3522                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3523         }
3524
3525         return 0;
3526 }
3527
3528 static int dce_v11_0_set_clockgating_state(void *handle,
3529                                           enum amd_clockgating_state state)
3530 {
3531         return 0;
3532 }
3533
3534 static int dce_v11_0_set_powergating_state(void *handle,
3535                                           enum amd_powergating_state state)
3536 {
3537         return 0;
3538 }
3539
3540 static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3541         .name = "dce_v11_0",
3542         .early_init = dce_v11_0_early_init,
3543         .late_init = NULL,
3544         .sw_init = dce_v11_0_sw_init,
3545         .sw_fini = dce_v11_0_sw_fini,
3546         .hw_init = dce_v11_0_hw_init,
3547         .hw_fini = dce_v11_0_hw_fini,
3548         .suspend = dce_v11_0_suspend,
3549         .resume = dce_v11_0_resume,
3550         .is_idle = dce_v11_0_is_idle,
3551         .wait_for_idle = dce_v11_0_wait_for_idle,
3552         .soft_reset = dce_v11_0_soft_reset,
3553         .set_clockgating_state = dce_v11_0_set_clockgating_state,
3554         .set_powergating_state = dce_v11_0_set_powergating_state,
3555 };
3556
3557 static void
3558 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3559                           struct drm_display_mode *mode,
3560                           struct drm_display_mode *adjusted_mode)
3561 {
3562         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3563
3564         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3565
3566         /* need to call this here rather than in prepare() since we need some crtc info */
3567         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3568
3569         /* set scaler clears this on some chips */
3570         dce_v11_0_set_interleave(encoder->crtc, mode);
3571
3572         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3573                 dce_v11_0_afmt_enable(encoder, true);
3574                 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3575         }
3576 }
3577
3578 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3579 {
3580         struct amdgpu_device *adev = encoder->dev->dev_private;
3581         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3582         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3583
3584         if ((amdgpu_encoder->active_device &
3585              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3586             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3587              ENCODER_OBJECT_ID_NONE)) {
3588                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3589                 if (dig) {
3590                         dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3591                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3592                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3593                 }
3594         }
3595
3596         amdgpu_atombios_scratch_regs_lock(adev, true);
3597
3598         if (connector) {
3599                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3600
3601                 /* select the clock/data port if it uses a router */
3602                 if (amdgpu_connector->router.cd_valid)
3603                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3604
3605                 /* turn eDP panel on for mode set */
3606                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3607                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3608                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3609         }
3610
3611         /* this is needed for the pll/ss setup to work correctly in some cases */
3612         amdgpu_atombios_encoder_set_crtc_source(encoder);
3613         /* set up the FMT blocks */
3614         dce_v11_0_program_fmt(encoder);
3615 }
3616
3617 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3618 {
3619         struct drm_device *dev = encoder->dev;
3620         struct amdgpu_device *adev = dev->dev_private;
3621
3622         /* need to call this here as we need the crtc set up */
3623         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3624         amdgpu_atombios_scratch_regs_lock(adev, false);
3625 }
3626
3627 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3628 {
3629         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3630         struct amdgpu_encoder_atom_dig *dig;
3631
3632         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3633
3634         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3635                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3636                         dce_v11_0_afmt_enable(encoder, false);
3637                 dig = amdgpu_encoder->enc_priv;
3638                 dig->dig_encoder = -1;
3639         }
3640         amdgpu_encoder->active_device = 0;
3641 }
3642
3643 /* these are handled by the primary encoders */
3644 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3645 {
3646
3647 }
3648
3649 static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3650 {
3651
3652 }
3653
3654 static void
3655 dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3656                       struct drm_display_mode *mode,
3657                       struct drm_display_mode *adjusted_mode)
3658 {
3659
3660 }
3661
3662 static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3663 {
3664
3665 }
3666
3667 static void
3668 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3669 {
3670
3671 }
3672
3673 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3674         .dpms = dce_v11_0_ext_dpms,
3675         .prepare = dce_v11_0_ext_prepare,
3676         .mode_set = dce_v11_0_ext_mode_set,
3677         .commit = dce_v11_0_ext_commit,
3678         .disable = dce_v11_0_ext_disable,
3679         /* no detect for TMDS/LVDS yet */
3680 };
3681
3682 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3683         .dpms = amdgpu_atombios_encoder_dpms,
3684         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3685         .prepare = dce_v11_0_encoder_prepare,
3686         .mode_set = dce_v11_0_encoder_mode_set,
3687         .commit = dce_v11_0_encoder_commit,
3688         .disable = dce_v11_0_encoder_disable,
3689         .detect = amdgpu_atombios_encoder_dig_detect,
3690 };
3691
3692 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3693         .dpms = amdgpu_atombios_encoder_dpms,
3694         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3695         .prepare = dce_v11_0_encoder_prepare,
3696         .mode_set = dce_v11_0_encoder_mode_set,
3697         .commit = dce_v11_0_encoder_commit,
3698         .detect = amdgpu_atombios_encoder_dac_detect,
3699 };
3700
3701 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3702 {
3703         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3704         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3705                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3706         kfree(amdgpu_encoder->enc_priv);
3707         drm_encoder_cleanup(encoder);
3708         kfree(amdgpu_encoder);
3709 }
3710
3711 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3712         .destroy = dce_v11_0_encoder_destroy,
3713 };
3714
3715 static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3716                                  uint32_t encoder_enum,
3717                                  uint32_t supported_device,
3718                                  u16 caps)
3719 {
3720         struct drm_device *dev = adev->ddev;
3721         struct drm_encoder *encoder;
3722         struct amdgpu_encoder *amdgpu_encoder;
3723
3724         /* see if we already added it */
3725         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3726                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3727                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3728                         amdgpu_encoder->devices |= supported_device;
3729                         return;
3730                 }
3731
3732         }
3733
3734         /* add a new one */
3735         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3736         if (!amdgpu_encoder)
3737                 return;
3738
3739         encoder = &amdgpu_encoder->base;
3740         switch (adev->mode_info.num_crtc) {
3741         case 1:
3742                 encoder->possible_crtcs = 0x1;
3743                 break;
3744         case 2:
3745         default:
3746                 encoder->possible_crtcs = 0x3;
3747                 break;
3748         case 4:
3749                 encoder->possible_crtcs = 0xf;
3750                 break;
3751         case 6:
3752                 encoder->possible_crtcs = 0x3f;
3753                 break;
3754         }
3755
3756         amdgpu_encoder->enc_priv = NULL;
3757
3758         amdgpu_encoder->encoder_enum = encoder_enum;
3759         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3760         amdgpu_encoder->devices = supported_device;
3761         amdgpu_encoder->rmx_type = RMX_OFF;
3762         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3763         amdgpu_encoder->is_ext_encoder = false;
3764         amdgpu_encoder->caps = caps;
3765
3766         switch (amdgpu_encoder->encoder_id) {
3767         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3768         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3769                 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3770                                  DRM_MODE_ENCODER_DAC, NULL);
3771                 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3772                 break;
3773         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3774         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3775         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3776         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3777         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3778                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3779                         amdgpu_encoder->rmx_type = RMX_FULL;
3780                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3781                                          DRM_MODE_ENCODER_LVDS, NULL);
3782                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3783                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3784                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3785                                          DRM_MODE_ENCODER_DAC, NULL);
3786                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3787                 } else {
3788                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3789                                          DRM_MODE_ENCODER_TMDS, NULL);
3790                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3791                 }
3792                 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3793                 break;
3794         case ENCODER_OBJECT_ID_SI170B:
3795         case ENCODER_OBJECT_ID_CH7303:
3796         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3797         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3798         case ENCODER_OBJECT_ID_TITFP513:
3799         case ENCODER_OBJECT_ID_VT1623:
3800         case ENCODER_OBJECT_ID_HDMI_SI1930:
3801         case ENCODER_OBJECT_ID_TRAVIS:
3802         case ENCODER_OBJECT_ID_NUTMEG:
3803                 /* these are handled by the primary encoders */
3804                 amdgpu_encoder->is_ext_encoder = true;
3805                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3806                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3807                                          DRM_MODE_ENCODER_LVDS, NULL);
3808                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3809                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3810                                          DRM_MODE_ENCODER_DAC, NULL);
3811                 else
3812                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3813                                          DRM_MODE_ENCODER_TMDS, NULL);
3814                 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3815                 break;
3816         }
3817 }
3818
3819 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3820         .set_vga_render_state = &dce_v11_0_set_vga_render_state,
3821         .bandwidth_update = &dce_v11_0_bandwidth_update,
3822         .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3823         .vblank_wait = &dce_v11_0_vblank_wait,
3824         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3825         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3826         .hpd_sense = &dce_v11_0_hpd_sense,
3827         .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3828         .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3829         .page_flip = &dce_v11_0_page_flip,
3830         .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3831         .add_encoder = &dce_v11_0_encoder_add,
3832         .add_connector = &amdgpu_connector_add,
3833         .stop_mc_access = &dce_v11_0_stop_mc_access,
3834         .resume_mc_access = &dce_v11_0_resume_mc_access,
3835 };
3836
3837 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3838 {
3839         if (adev->mode_info.funcs == NULL)
3840                 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3841 }
3842
3843 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3844         .set = dce_v11_0_set_crtc_irq_state,
3845         .process = dce_v11_0_crtc_irq,
3846 };
3847
3848 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3849         .set = dce_v11_0_set_pageflip_irq_state,
3850         .process = dce_v11_0_pageflip_irq,
3851 };
3852
3853 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3854         .set = dce_v11_0_set_hpd_irq_state,
3855         .process = dce_v11_0_hpd_irq,
3856 };
3857
3858 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3859 {
3860         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3861         adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3862
3863         adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3864         adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3865
3866         adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3867         adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3868 }
3869
3870 const struct amdgpu_ip_block_version dce_v11_0_ip_block =
3871 {
3872         .type = AMD_IP_BLOCK_TYPE_DCE,
3873         .major = 11,
3874         .minor = 0,
3875         .rev = 0,
3876         .funcs = &dce_v11_0_ip_funcs,
3877 };
3878
3879 const struct amdgpu_ip_block_version dce_v11_2_ip_block =
3880 {
3881         .type = AMD_IP_BLOCK_TYPE_DCE,
3882         .major = 11,
3883         .minor = 2,
3884         .rev = 0,
3885         .funcs = &dce_v11_0_ip_funcs,
3886 };