2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
29 #include "amdgpu_atombios.h"
30 #include "atombios_crtc.h"
31 #include "atombios_encoders.h"
32 #include "amdgpu_pll.h"
33 #include "amdgpu_connectors.h"
36 #include "dce/dce_8_0_d.h"
37 #include "dce/dce_8_0_sh_mask.h"
39 #include "gca/gfx_7_2_enum.h"
41 #include "gmc/gmc_7_1_d.h"
42 #include "gmc/gmc_7_1_sh_mask.h"
44 #include "oss/oss_2_0_d.h"
45 #include "oss/oss_2_0_sh_mask.h"
47 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev);
48 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev);
50 static const u32 crtc_offsets[6] =
52 CRTC0_REGISTER_OFFSET,
53 CRTC1_REGISTER_OFFSET,
54 CRTC2_REGISTER_OFFSET,
55 CRTC3_REGISTER_OFFSET,
56 CRTC4_REGISTER_OFFSET,
60 static const u32 hpd_offsets[] =
70 static const uint32_t dig_offsets[] = {
71 CRTC0_REGISTER_OFFSET,
72 CRTC1_REGISTER_OFFSET,
73 CRTC2_REGISTER_OFFSET,
74 CRTC3_REGISTER_OFFSET,
75 CRTC4_REGISTER_OFFSET,
76 CRTC5_REGISTER_OFFSET,
77 (0x13830 - 0x7030) >> 2,
86 } interrupt_status_offsets[6] = { {
87 .reg = mmDISP_INTERRUPT_STATUS,
88 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
89 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
90 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
92 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
93 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
94 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
95 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
97 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
98 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
99 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
100 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
104 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
109 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
114 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
118 static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev,
119 u32 block_offset, u32 reg)
124 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
125 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
126 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
127 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
132 static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev,
133 u32 block_offset, u32 reg, u32 v)
137 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
138 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
139 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
140 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
143 static bool dce_v8_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
145 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
146 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
152 static bool dce_v8_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
156 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
157 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
166 * dce_v8_0_vblank_wait - vblank wait asic callback.
168 * @adev: amdgpu_device pointer
169 * @crtc: crtc to wait for vblank on
171 * Wait for vblank on the requested crtc (evergreen+).
173 static void dce_v8_0_vblank_wait(struct amdgpu_device *adev, int crtc)
177 if (crtc >= adev->mode_info.num_crtc)
180 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
183 /* depending on when we hit vblank, we may be close to active; if so,
184 * wait for another frame.
186 while (dce_v8_0_is_in_vblank(adev, crtc)) {
189 if (!dce_v8_0_is_counter_moving(adev, crtc))
194 while (!dce_v8_0_is_in_vblank(adev, crtc)) {
197 if (!dce_v8_0_is_counter_moving(adev, crtc))
203 static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
205 if (crtc >= adev->mode_info.num_crtc)
208 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
211 static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev)
215 /* Enable pflip interrupts */
216 for (i = 0; i < adev->mode_info.num_crtc; i++)
217 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
220 static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
224 /* Disable pflip interrupts */
225 for (i = 0; i < adev->mode_info.num_crtc; i++)
226 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
230 * dce_v8_0_page_flip - pageflip callback.
232 * @adev: amdgpu_device pointer
233 * @crtc_id: crtc to cleanup pageflip on
234 * @crtc_base: new address of the crtc (GPU MC address)
236 * Triggers the actual pageflip by updating the primary
237 * surface base address.
239 static void dce_v8_0_page_flip(struct amdgpu_device *adev,
240 int crtc_id, u64 crtc_base, bool async)
242 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
244 /* flip at hsync for async, default is vsync */
245 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
246 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
247 /* update the primary scanout addresses */
248 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
249 upper_32_bits(crtc_base));
250 /* writing to the low address triggers the update */
251 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
252 lower_32_bits(crtc_base));
254 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
257 static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
258 u32 *vbl, u32 *position)
260 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
263 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
264 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
270 * dce_v8_0_hpd_sense - hpd sense callback.
272 * @adev: amdgpu_device pointer
273 * @hpd: hpd (hotplug detect) pin
275 * Checks if a digital monitor is connected (evergreen+).
276 * Returns true if connected, false if not connected.
278 static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev,
279 enum amdgpu_hpd_id hpd)
281 bool connected = false;
283 if (hpd >= adev->mode_info.num_hpd)
286 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &
287 DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
294 * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
296 * @adev: amdgpu_device pointer
297 * @hpd: hpd (hotplug detect) pin
299 * Set the polarity of the hpd pin (evergreen+).
301 static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev,
302 enum amdgpu_hpd_id hpd)
305 bool connected = dce_v8_0_hpd_sense(adev, hpd);
307 if (hpd >= adev->mode_info.num_hpd)
310 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
312 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
314 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
315 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
319 * dce_v8_0_hpd_init - hpd setup callback.
321 * @adev: amdgpu_device pointer
323 * Setup the hpd pins used by the card (evergreen+).
324 * Enable the pin, set the polarity, and enable the hpd interrupts.
326 static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
328 struct drm_device *dev = adev->ddev;
329 struct drm_connector *connector;
332 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
333 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
335 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
338 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
339 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
340 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
342 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
343 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
344 /* don't try to enable hpd on eDP or LVDS avoid breaking the
345 * aux dp channel on imac and help (but not completely fix)
346 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
347 * also avoid interrupt storms during dpms.
349 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
350 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
351 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
355 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
356 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
361 * dce_v8_0_hpd_fini - hpd tear down callback.
363 * @adev: amdgpu_device pointer
365 * Tear down the hpd pins used by the card (evergreen+).
366 * Disable the hpd interrupts.
368 static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
370 struct drm_device *dev = adev->ddev;
371 struct drm_connector *connector;
374 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
375 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
377 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
380 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
381 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
382 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
384 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
388 static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
390 return mmDC_GPIO_HPD_A;
393 static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev)
399 for (i = 0; i < adev->mode_info.num_crtc; i++) {
400 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
401 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
402 crtc_hung |= (1 << i);
406 for (j = 0; j < 10; j++) {
407 for (i = 0; i < adev->mode_info.num_crtc; i++) {
408 if (crtc_hung & (1 << i)) {
409 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
410 if (tmp != crtc_status[i])
411 crtc_hung &= ~(1 << i);
422 static void dce_v8_0_stop_mc_access(struct amdgpu_device *adev,
423 struct amdgpu_mode_mc_save *save)
425 u32 crtc_enabled, tmp;
428 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
429 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
431 /* disable VGA render */
432 tmp = RREG32(mmVGA_RENDER_CONTROL);
433 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
434 WREG32(mmVGA_RENDER_CONTROL, tmp);
436 /* blank the display controllers */
437 for (i = 0; i < adev->mode_info.num_crtc; i++) {
438 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
439 CRTC_CONTROL, CRTC_MASTER_EN);
442 save->crtc_enabled[i] = true;
443 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
444 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
445 /*it is correct only for RGB ; black is 0*/
446 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
447 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
448 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
452 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
453 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
454 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
455 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
456 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
457 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
458 save->crtc_enabled[i] = false;
462 save->crtc_enabled[i] = false;
467 static void dce_v8_0_resume_mc_access(struct amdgpu_device *adev,
468 struct amdgpu_mode_mc_save *save)
473 /* update crtc base addresses */
474 for (i = 0; i < adev->mode_info.num_crtc; i++) {
475 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
476 upper_32_bits(adev->mc.vram_start));
477 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
478 (u32)adev->mc.vram_start);
480 if (save->crtc_enabled[i]) {
481 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
482 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
483 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
488 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
489 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
491 /* Unlock vga access */
492 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
494 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
497 static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
502 /* Lockout access through VGA aperture*/
503 tmp = RREG32(mmVGA_HDP_CONTROL);
505 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
507 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
508 WREG32(mmVGA_HDP_CONTROL, tmp);
510 /* disable VGA render */
511 tmp = RREG32(mmVGA_RENDER_CONTROL);
513 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
515 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
516 WREG32(mmVGA_RENDER_CONTROL, tmp);
519 static int dce_v8_0_get_num_crtc(struct amdgpu_device *adev)
523 switch (adev->asic_type) {
541 void dce_v8_0_disable_dce(struct amdgpu_device *adev)
543 /*Disable VGA render and enabled crtc, if has DCE engine*/
544 if (amdgpu_atombios_has_dce_engine_info(adev)) {
548 dce_v8_0_set_vga_render_state(adev, false);
551 for (i = 0; i < dce_v8_0_get_num_crtc(adev); i++) {
552 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
553 CRTC_CONTROL, CRTC_MASTER_EN);
555 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
556 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
557 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
558 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
559 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
565 static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
567 struct drm_device *dev = encoder->dev;
568 struct amdgpu_device *adev = dev->dev_private;
569 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
570 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
571 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
574 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
577 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
578 bpc = amdgpu_connector_get_monitor_bpc(connector);
579 dither = amdgpu_connector->dither;
582 /* LVDS/eDP FMT is set up by atom */
583 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
586 /* not needed for analog */
587 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
588 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
596 if (dither == AMDGPU_FMT_DITHER_ENABLE)
597 /* XXX sort out optimal dither settings */
598 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
599 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
600 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
601 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
603 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
604 (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
607 if (dither == AMDGPU_FMT_DITHER_ENABLE)
608 /* XXX sort out optimal dither settings */
609 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
610 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
611 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
612 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
613 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
615 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
616 (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
619 if (dither == AMDGPU_FMT_DITHER_ENABLE)
620 /* XXX sort out optimal dither settings */
621 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
622 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
623 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
624 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
625 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
627 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
628 (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
635 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
639 /* display watermark setup */
641 * dce_v8_0_line_buffer_adjust - Set up the line buffer
643 * @adev: amdgpu_device pointer
644 * @amdgpu_crtc: the selected display controller
645 * @mode: the current display mode on the selected display
648 * Setup up the line buffer allocation for
649 * the selected display controller (CIK).
650 * Returns the line buffer size in pixels.
652 static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
653 struct amdgpu_crtc *amdgpu_crtc,
654 struct drm_display_mode *mode)
656 u32 tmp, buffer_alloc, i;
657 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
660 * There are 6 line buffers, one for each display controllers.
661 * There are 3 partitions per LB. Select the number of partitions
662 * to enable based on the display width. For display widths larger
663 * than 4096, you need use to use 2 display controllers and combine
664 * them using the stereo blender.
666 if (amdgpu_crtc->base.enabled && mode) {
667 if (mode->crtc_hdisplay < 1920) {
670 } else if (mode->crtc_hdisplay < 2560) {
673 } else if (mode->crtc_hdisplay < 4096) {
675 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
677 DRM_DEBUG_KMS("Mode too big for LB!\n");
679 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
686 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
687 (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) |
688 (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT));
690 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
691 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
692 for (i = 0; i < adev->usec_timeout; i++) {
693 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
694 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
699 if (amdgpu_crtc->base.enabled && mode) {
711 /* controller not enabled, so no lb used */
716 * cik_get_number_of_dram_channels - get the number of dram channels
718 * @adev: amdgpu_device pointer
720 * Look up the number of video ram channels (CIK).
721 * Used for display watermark bandwidth calculations
722 * Returns the number of dram channels
724 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
726 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
728 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
751 struct dce8_wm_params {
752 u32 dram_channels; /* number of dram channels */
753 u32 yclk; /* bandwidth per dram data pin in kHz */
754 u32 sclk; /* engine clock in kHz */
755 u32 disp_clk; /* display clock in kHz */
756 u32 src_width; /* viewport width */
757 u32 active_time; /* active display time in ns */
758 u32 blank_time; /* blank time in ns */
759 bool interlaced; /* mode is interlaced */
760 fixed20_12 vsc; /* vertical scale ratio */
761 u32 num_heads; /* number of active crtcs */
762 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
763 u32 lb_size; /* line buffer allocated to pipe */
764 u32 vtaps; /* vertical scaler taps */
768 * dce_v8_0_dram_bandwidth - get the dram bandwidth
770 * @wm: watermark calculation data
772 * Calculate the raw dram bandwidth (CIK).
773 * Used for display watermark bandwidth calculations
774 * Returns the dram bandwidth in MBytes/s
776 static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)
778 /* Calculate raw DRAM Bandwidth */
779 fixed20_12 dram_efficiency; /* 0.7 */
780 fixed20_12 yclk, dram_channels, bandwidth;
783 a.full = dfixed_const(1000);
784 yclk.full = dfixed_const(wm->yclk);
785 yclk.full = dfixed_div(yclk, a);
786 dram_channels.full = dfixed_const(wm->dram_channels * 4);
787 a.full = dfixed_const(10);
788 dram_efficiency.full = dfixed_const(7);
789 dram_efficiency.full = dfixed_div(dram_efficiency, a);
790 bandwidth.full = dfixed_mul(dram_channels, yclk);
791 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
793 return dfixed_trunc(bandwidth);
797 * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display
799 * @wm: watermark calculation data
801 * Calculate the dram bandwidth used for display (CIK).
802 * Used for display watermark bandwidth calculations
803 * Returns the dram bandwidth for display in MBytes/s
805 static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)
807 /* Calculate DRAM Bandwidth and the part allocated to display. */
808 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
809 fixed20_12 yclk, dram_channels, bandwidth;
812 a.full = dfixed_const(1000);
813 yclk.full = dfixed_const(wm->yclk);
814 yclk.full = dfixed_div(yclk, a);
815 dram_channels.full = dfixed_const(wm->dram_channels * 4);
816 a.full = dfixed_const(10);
817 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
818 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
819 bandwidth.full = dfixed_mul(dram_channels, yclk);
820 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
822 return dfixed_trunc(bandwidth);
826 * dce_v8_0_data_return_bandwidth - get the data return bandwidth
828 * @wm: watermark calculation data
830 * Calculate the data return bandwidth used for display (CIK).
831 * Used for display watermark bandwidth calculations
832 * Returns the data return bandwidth in MBytes/s
834 static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)
836 /* Calculate the display Data return Bandwidth */
837 fixed20_12 return_efficiency; /* 0.8 */
838 fixed20_12 sclk, bandwidth;
841 a.full = dfixed_const(1000);
842 sclk.full = dfixed_const(wm->sclk);
843 sclk.full = dfixed_div(sclk, a);
844 a.full = dfixed_const(10);
845 return_efficiency.full = dfixed_const(8);
846 return_efficiency.full = dfixed_div(return_efficiency, a);
847 a.full = dfixed_const(32);
848 bandwidth.full = dfixed_mul(a, sclk);
849 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
851 return dfixed_trunc(bandwidth);
855 * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth
857 * @wm: watermark calculation data
859 * Calculate the dmif bandwidth used for display (CIK).
860 * Used for display watermark bandwidth calculations
861 * Returns the dmif bandwidth in MBytes/s
863 static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)
865 /* Calculate the DMIF Request Bandwidth */
866 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
867 fixed20_12 disp_clk, bandwidth;
870 a.full = dfixed_const(1000);
871 disp_clk.full = dfixed_const(wm->disp_clk);
872 disp_clk.full = dfixed_div(disp_clk, a);
873 a.full = dfixed_const(32);
874 b.full = dfixed_mul(a, disp_clk);
876 a.full = dfixed_const(10);
877 disp_clk_request_efficiency.full = dfixed_const(8);
878 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
880 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
882 return dfixed_trunc(bandwidth);
886 * dce_v8_0_available_bandwidth - get the min available bandwidth
888 * @wm: watermark calculation data
890 * Calculate the min available bandwidth used for display (CIK).
891 * Used for display watermark bandwidth calculations
892 * Returns the min available bandwidth in MBytes/s
894 static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)
896 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
897 u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm);
898 u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm);
899 u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm);
901 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
905 * dce_v8_0_average_bandwidth - get the average available bandwidth
907 * @wm: watermark calculation data
909 * Calculate the average available bandwidth used for display (CIK).
910 * Used for display watermark bandwidth calculations
911 * Returns the average available bandwidth in MBytes/s
913 static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)
915 /* Calculate the display mode Average Bandwidth
916 * DisplayMode should contain the source and destination dimensions,
920 fixed20_12 line_time;
921 fixed20_12 src_width;
922 fixed20_12 bandwidth;
925 a.full = dfixed_const(1000);
926 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
927 line_time.full = dfixed_div(line_time, a);
928 bpp.full = dfixed_const(wm->bytes_per_pixel);
929 src_width.full = dfixed_const(wm->src_width);
930 bandwidth.full = dfixed_mul(src_width, bpp);
931 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
932 bandwidth.full = dfixed_div(bandwidth, line_time);
934 return dfixed_trunc(bandwidth);
938 * dce_v8_0_latency_watermark - get the latency watermark
940 * @wm: watermark calculation data
942 * Calculate the latency watermark (CIK).
943 * Used for display watermark bandwidth calculations
944 * Returns the latency watermark in ns
946 static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
948 /* First calculate the latency in ns */
949 u32 mc_latency = 2000; /* 2000 ns. */
950 u32 available_bandwidth = dce_v8_0_available_bandwidth(wm);
951 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
952 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
953 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
954 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
955 (wm->num_heads * cursor_line_pair_return_time);
956 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
957 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
958 u32 tmp, dmif_size = 12288;
961 if (wm->num_heads == 0)
964 a.full = dfixed_const(2);
965 b.full = dfixed_const(1);
966 if ((wm->vsc.full > a.full) ||
967 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
969 ((wm->vsc.full >= a.full) && wm->interlaced))
970 max_src_lines_per_dst_line = 4;
972 max_src_lines_per_dst_line = 2;
974 a.full = dfixed_const(available_bandwidth);
975 b.full = dfixed_const(wm->num_heads);
976 a.full = dfixed_div(a, b);
978 b.full = dfixed_const(mc_latency + 512);
979 c.full = dfixed_const(wm->disp_clk);
980 b.full = dfixed_div(b, c);
982 c.full = dfixed_const(dmif_size);
983 b.full = dfixed_div(c, b);
985 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
987 b.full = dfixed_const(1000);
988 c.full = dfixed_const(wm->disp_clk);
989 b.full = dfixed_div(c, b);
990 c.full = dfixed_const(wm->bytes_per_pixel);
991 b.full = dfixed_mul(b, c);
993 lb_fill_bw = min(tmp, dfixed_trunc(b));
995 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
996 b.full = dfixed_const(1000);
997 c.full = dfixed_const(lb_fill_bw);
998 b.full = dfixed_div(c, b);
999 a.full = dfixed_div(a, b);
1000 line_fill_time = dfixed_trunc(a);
1002 if (line_fill_time < wm->active_time)
1005 return latency + (line_fill_time - wm->active_time);
1010 * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1011 * average and available dram bandwidth
1013 * @wm: watermark calculation data
1015 * Check if the display average bandwidth fits in the display
1016 * dram bandwidth (CIK).
1017 * Used for display watermark bandwidth calculations
1018 * Returns true if the display fits, false if not.
1020 static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
1022 if (dce_v8_0_average_bandwidth(wm) <=
1023 (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1030 * dce_v8_0_average_bandwidth_vs_available_bandwidth - check
1031 * average and available bandwidth
1033 * @wm: watermark calculation data
1035 * Check if the display average bandwidth fits in the display
1036 * available bandwidth (CIK).
1037 * Used for display watermark bandwidth calculations
1038 * Returns true if the display fits, false if not.
1040 static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
1042 if (dce_v8_0_average_bandwidth(wm) <=
1043 (dce_v8_0_available_bandwidth(wm) / wm->num_heads))
1050 * dce_v8_0_check_latency_hiding - check latency hiding
1052 * @wm: watermark calculation data
1054 * Check latency hiding (CIK).
1055 * Used for display watermark bandwidth calculations
1056 * Returns true if the display fits, false if not.
1058 static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm)
1060 u32 lb_partitions = wm->lb_size / wm->src_width;
1061 u32 line_time = wm->active_time + wm->blank_time;
1062 u32 latency_tolerant_lines;
1066 a.full = dfixed_const(1);
1067 if (wm->vsc.full > a.full)
1068 latency_tolerant_lines = 1;
1070 if (lb_partitions <= (wm->vtaps + 1))
1071 latency_tolerant_lines = 1;
1073 latency_tolerant_lines = 2;
1076 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1078 if (dce_v8_0_latency_watermark(wm) <= latency_hiding)
1085 * dce_v8_0_program_watermarks - program display watermarks
1087 * @adev: amdgpu_device pointer
1088 * @amdgpu_crtc: the selected display controller
1089 * @lb_size: line buffer size
1090 * @num_heads: number of display controllers in use
1092 * Calculate and program the display watermarks for the
1093 * selected display controller (CIK).
1095 static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
1096 struct amdgpu_crtc *amdgpu_crtc,
1097 u32 lb_size, u32 num_heads)
1099 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1100 struct dce8_wm_params wm_low, wm_high;
1103 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1104 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1106 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1107 pixel_period = 1000000 / (u32)mode->clock;
1108 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1110 /* watermark for high clocks */
1111 if (adev->pm.dpm_enabled) {
1113 amdgpu_dpm_get_mclk(adev, false) * 10;
1115 amdgpu_dpm_get_sclk(adev, false) * 10;
1117 wm_high.yclk = adev->pm.current_mclk * 10;
1118 wm_high.sclk = adev->pm.current_sclk * 10;
1121 wm_high.disp_clk = mode->clock;
1122 wm_high.src_width = mode->crtc_hdisplay;
1123 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1124 wm_high.blank_time = line_time - wm_high.active_time;
1125 wm_high.interlaced = false;
1126 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1127 wm_high.interlaced = true;
1128 wm_high.vsc = amdgpu_crtc->vsc;
1130 if (amdgpu_crtc->rmx_type != RMX_OFF)
1132 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1133 wm_high.lb_size = lb_size;
1134 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1135 wm_high.num_heads = num_heads;
1137 /* set for high clocks */
1138 latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535);
1140 /* possibly force display priority to high */
1141 /* should really do this at mode validation time... */
1142 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1143 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1144 !dce_v8_0_check_latency_hiding(&wm_high) ||
1145 (adev->mode_info.disp_priority == 2)) {
1146 DRM_DEBUG_KMS("force priority to high\n");
1149 /* watermark for low clocks */
1150 if (adev->pm.dpm_enabled) {
1152 amdgpu_dpm_get_mclk(adev, true) * 10;
1154 amdgpu_dpm_get_sclk(adev, true) * 10;
1156 wm_low.yclk = adev->pm.current_mclk * 10;
1157 wm_low.sclk = adev->pm.current_sclk * 10;
1160 wm_low.disp_clk = mode->clock;
1161 wm_low.src_width = mode->crtc_hdisplay;
1162 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1163 wm_low.blank_time = line_time - wm_low.active_time;
1164 wm_low.interlaced = false;
1165 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1166 wm_low.interlaced = true;
1167 wm_low.vsc = amdgpu_crtc->vsc;
1169 if (amdgpu_crtc->rmx_type != RMX_OFF)
1171 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1172 wm_low.lb_size = lb_size;
1173 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1174 wm_low.num_heads = num_heads;
1176 /* set for low clocks */
1177 latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535);
1179 /* possibly force display priority to high */
1180 /* should really do this at mode validation time... */
1181 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1182 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1183 !dce_v8_0_check_latency_hiding(&wm_low) ||
1184 (adev->mode_info.disp_priority == 2)) {
1185 DRM_DEBUG_KMS("force priority to high\n");
1187 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1191 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1193 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1194 tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1195 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1196 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1197 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1198 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1200 tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1201 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1202 tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1203 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1204 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1205 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1206 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1207 /* restore original selection */
1208 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1210 /* save values for DPM */
1211 amdgpu_crtc->line_time = line_time;
1212 amdgpu_crtc->wm_high = latency_watermark_a;
1213 amdgpu_crtc->wm_low = latency_watermark_b;
1214 /* Save number of lines the linebuffer leads before the scanout */
1215 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1219 * dce_v8_0_bandwidth_update - program display watermarks
1221 * @adev: amdgpu_device pointer
1223 * Calculate and program the display watermarks and line
1224 * buffer allocation (CIK).
1226 static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev)
1228 struct drm_display_mode *mode = NULL;
1229 u32 num_heads = 0, lb_size;
1232 amdgpu_update_display_priority(adev);
1234 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1235 if (adev->mode_info.crtcs[i]->base.enabled)
1238 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1239 mode = &adev->mode_info.crtcs[i]->base.mode;
1240 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1241 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1242 lb_size, num_heads);
1246 static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev)
1251 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1252 offset = adev->mode_info.audio.pin[i].offset;
1253 tmp = RREG32_AUDIO_ENDPT(offset,
1254 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1256 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1257 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1258 adev->mode_info.audio.pin[i].connected = false;
1260 adev->mode_info.audio.pin[i].connected = true;
1264 static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev)
1268 dce_v8_0_audio_get_connected_pins(adev);
1270 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1271 if (adev->mode_info.audio.pin[i].connected)
1272 return &adev->mode_info.audio.pin[i];
1274 DRM_ERROR("No connected audio pins found!\n");
1278 static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1280 struct amdgpu_device *adev = encoder->dev->dev_private;
1281 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1282 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1285 if (!dig || !dig->afmt || !dig->afmt->pin)
1288 offset = dig->afmt->offset;
1290 WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset,
1291 (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT));
1294 static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
1295 struct drm_display_mode *mode)
1297 struct amdgpu_device *adev = encoder->dev->dev_private;
1298 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1299 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1300 struct drm_connector *connector;
1301 struct amdgpu_connector *amdgpu_connector = NULL;
1302 u32 tmp = 0, offset;
1304 if (!dig || !dig->afmt || !dig->afmt->pin)
1307 offset = dig->afmt->pin->offset;
1309 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1310 if (connector->encoder == encoder) {
1311 amdgpu_connector = to_amdgpu_connector(connector);
1316 if (!amdgpu_connector) {
1317 DRM_ERROR("Couldn't find encoder's connector\n");
1321 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1322 if (connector->latency_present[1])
1324 (connector->video_latency[1] <<
1325 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1326 (connector->audio_latency[1] <<
1327 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1331 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1333 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1335 if (connector->latency_present[0])
1337 (connector->video_latency[0] <<
1338 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1339 (connector->audio_latency[0] <<
1340 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1344 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1346 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1349 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1352 static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1354 struct amdgpu_device *adev = encoder->dev->dev_private;
1355 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1356 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1357 struct drm_connector *connector;
1358 struct amdgpu_connector *amdgpu_connector = NULL;
1363 if (!dig || !dig->afmt || !dig->afmt->pin)
1366 offset = dig->afmt->pin->offset;
1368 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1369 if (connector->encoder == encoder) {
1370 amdgpu_connector = to_amdgpu_connector(connector);
1375 if (!amdgpu_connector) {
1376 DRM_ERROR("Couldn't find encoder's connector\n");
1380 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1381 if (sad_count < 0) {
1382 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1386 /* program the speaker allocation */
1387 tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1388 tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK |
1389 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK);
1391 tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK;
1393 tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT);
1395 tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */
1396 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1401 static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
1403 struct amdgpu_device *adev = encoder->dev->dev_private;
1404 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1405 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1407 struct drm_connector *connector;
1408 struct amdgpu_connector *amdgpu_connector = NULL;
1409 struct cea_sad *sads;
1412 static const u16 eld_reg_to_type[][2] = {
1413 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1414 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1415 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1416 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1417 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1418 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1419 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1420 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1421 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1422 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1423 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1424 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1427 if (!dig || !dig->afmt || !dig->afmt->pin)
1430 offset = dig->afmt->pin->offset;
1432 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1433 if (connector->encoder == encoder) {
1434 amdgpu_connector = to_amdgpu_connector(connector);
1439 if (!amdgpu_connector) {
1440 DRM_ERROR("Couldn't find encoder's connector\n");
1444 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1445 if (sad_count <= 0) {
1446 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1451 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1453 u8 stereo_freqs = 0;
1454 int max_channels = -1;
1457 for (j = 0; j < sad_count; j++) {
1458 struct cea_sad *sad = &sads[j];
1460 if (sad->format == eld_reg_to_type[i][1]) {
1461 if (sad->channels > max_channels) {
1462 value = (sad->channels <<
1463 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) |
1465 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) |
1467 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT);
1468 max_channels = sad->channels;
1471 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1472 stereo_freqs |= sad->freq;
1478 value |= (stereo_freqs <<
1479 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT);
1481 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value);
1487 static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
1488 struct amdgpu_audio_pin *pin,
1494 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1495 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1498 static const u32 pin_offsets[7] =
1509 static int dce_v8_0_audio_init(struct amdgpu_device *adev)
1516 adev->mode_info.audio.enabled = true;
1518 if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */
1519 adev->mode_info.audio.num_pins = 7;
1520 else if ((adev->asic_type == CHIP_KABINI) ||
1521 (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */
1522 adev->mode_info.audio.num_pins = 3;
1523 else if ((adev->asic_type == CHIP_BONAIRE) ||
1524 (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */
1525 adev->mode_info.audio.num_pins = 7;
1527 adev->mode_info.audio.num_pins = 3;
1529 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1530 adev->mode_info.audio.pin[i].channels = -1;
1531 adev->mode_info.audio.pin[i].rate = -1;
1532 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1533 adev->mode_info.audio.pin[i].status_bits = 0;
1534 adev->mode_info.audio.pin[i].category_code = 0;
1535 adev->mode_info.audio.pin[i].connected = false;
1536 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1537 adev->mode_info.audio.pin[i].id = i;
1538 /* disable audio. it will be set up later */
1539 /* XXX remove once we switch to ip funcs */
1540 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1546 static void dce_v8_0_audio_fini(struct amdgpu_device *adev)
1553 if (!adev->mode_info.audio.enabled)
1556 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1557 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1559 adev->mode_info.audio.enabled = false;
1563 * update the N and CTS parameters for a given pixel clock rate
1565 static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1567 struct drm_device *dev = encoder->dev;
1568 struct amdgpu_device *adev = dev->dev_private;
1569 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1570 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1571 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1572 uint32_t offset = dig->afmt->offset;
1574 WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT));
1575 WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
1577 WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1578 WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);
1580 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
1581 WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);
1585 * build a HDMI Video Info Frame
1587 static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1588 void *buffer, size_t size)
1590 struct drm_device *dev = encoder->dev;
1591 struct amdgpu_device *adev = dev->dev_private;
1592 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1593 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1594 uint32_t offset = dig->afmt->offset;
1595 uint8_t *frame = buffer + 3;
1596 uint8_t *header = buffer;
1598 WREG32(mmAFMT_AVI_INFO0 + offset,
1599 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1600 WREG32(mmAFMT_AVI_INFO1 + offset,
1601 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1602 WREG32(mmAFMT_AVI_INFO2 + offset,
1603 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1604 WREG32(mmAFMT_AVI_INFO3 + offset,
1605 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1608 static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1610 struct drm_device *dev = encoder->dev;
1611 struct amdgpu_device *adev = dev->dev_private;
1612 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1613 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1614 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1615 u32 dto_phase = 24 * 1000;
1616 u32 dto_modulo = clock;
1618 if (!dig || !dig->afmt)
1621 /* XXX two dtos; generally use dto0 for hdmi */
1622 /* Express [24MHz / target pixel clock] as an exact rational
1623 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1624 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1626 WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
1627 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1628 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1632 * update the info frames with the data from the current display mode
1634 static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
1635 struct drm_display_mode *mode)
1637 struct drm_device *dev = encoder->dev;
1638 struct amdgpu_device *adev = dev->dev_private;
1639 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1640 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1641 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1642 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1643 struct hdmi_avi_infoframe frame;
1644 uint32_t offset, val;
1648 if (!dig || !dig->afmt)
1651 /* Silent, r600_hdmi_enable will raise WARN for us */
1652 if (!dig->afmt->enabled)
1655 offset = dig->afmt->offset;
1657 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1658 if (encoder->crtc) {
1659 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1660 bpc = amdgpu_crtc->bpc;
1663 /* disable audio prior to setting up hw */
1664 dig->afmt->pin = dce_v8_0_audio_get_pin(adev);
1665 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1667 dce_v8_0_audio_set_dto(encoder, mode->clock);
1669 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1670 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */
1672 WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
1674 val = RREG32(mmHDMI_CONTROL + offset);
1675 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1676 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK;
1684 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1685 connector->name, bpc);
1688 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1689 val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1690 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1694 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1695 val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1696 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1701 WREG32(mmHDMI_CONTROL + offset, val);
1703 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1704 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */
1705 HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */
1706 HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */
1708 WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset,
1709 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */
1710 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */
1712 WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset,
1713 AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */
1715 WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset,
1716 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */
1718 WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
1720 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset,
1721 (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */
1722 (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */
1724 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1725 AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */
1727 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
1730 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1731 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1733 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1734 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */
1735 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1737 dce_v8_0_afmt_update_ACR(encoder, mode->clock);
1739 WREG32(mmAFMT_60958_0 + offset,
1740 (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT));
1742 WREG32(mmAFMT_60958_1 + offset,
1743 (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT));
1745 WREG32(mmAFMT_60958_2 + offset,
1746 (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) |
1747 (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) |
1748 (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) |
1749 (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) |
1750 (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) |
1751 (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT));
1753 dce_v8_0_audio_write_speaker_allocation(encoder);
1756 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset,
1757 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1759 dce_v8_0_afmt_audio_select_pin(encoder);
1760 dce_v8_0_audio_write_sad_regs(encoder);
1761 dce_v8_0_audio_write_latency_fields(encoder, mode);
1763 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1765 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1769 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1771 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1775 dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1777 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,
1778 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */
1779 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK); /* required for audio info values to be updated */
1781 WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,
1782 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */
1783 ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK);
1785 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1786 AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */
1788 WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
1789 WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
1790 WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001);
1791 WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001);
1793 /* enable audio after setting up hw */
1794 dce_v8_0_audio_enable(adev, dig->afmt->pin, true);
1797 static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1799 struct drm_device *dev = encoder->dev;
1800 struct amdgpu_device *adev = dev->dev_private;
1801 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1802 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1804 if (!dig || !dig->afmt)
1807 /* Silent, r600_hdmi_enable will raise WARN for us */
1808 if (enable && dig->afmt->enabled)
1810 if (!enable && !dig->afmt->enabled)
1813 if (!enable && dig->afmt->pin) {
1814 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1815 dig->afmt->pin = NULL;
1818 dig->afmt->enabled = enable;
1820 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1821 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1824 static int dce_v8_0_afmt_init(struct amdgpu_device *adev)
1828 for (i = 0; i < adev->mode_info.num_dig; i++)
1829 adev->mode_info.afmt[i] = NULL;
1831 /* DCE8 has audio blocks tied to DIG encoders */
1832 for (i = 0; i < adev->mode_info.num_dig; i++) {
1833 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1834 if (adev->mode_info.afmt[i]) {
1835 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1836 adev->mode_info.afmt[i]->id = i;
1839 for (j = 0; j < i; j++) {
1840 kfree(adev->mode_info.afmt[j]);
1841 adev->mode_info.afmt[j] = NULL;
1849 static void dce_v8_0_afmt_fini(struct amdgpu_device *adev)
1853 for (i = 0; i < adev->mode_info.num_dig; i++) {
1854 kfree(adev->mode_info.afmt[i]);
1855 adev->mode_info.afmt[i] = NULL;
1859 static const u32 vga_control_regs[6] =
1869 static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
1871 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1872 struct drm_device *dev = crtc->dev;
1873 struct amdgpu_device *adev = dev->dev_private;
1876 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1878 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1880 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1883 static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
1885 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1886 struct drm_device *dev = crtc->dev;
1887 struct amdgpu_device *adev = dev->dev_private;
1890 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1892 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1895 static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
1896 struct drm_framebuffer *fb,
1897 int x, int y, int atomic)
1899 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1900 struct drm_device *dev = crtc->dev;
1901 struct amdgpu_device *adev = dev->dev_private;
1902 struct amdgpu_framebuffer *amdgpu_fb;
1903 struct drm_framebuffer *target_fb;
1904 struct drm_gem_object *obj;
1905 struct amdgpu_bo *abo;
1906 uint64_t fb_location, tiling_flags;
1907 uint32_t fb_format, fb_pitch_pixels;
1908 u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1910 u32 viewport_w, viewport_h;
1912 bool bypass_lut = false;
1913 struct drm_format_name_buf format_name;
1916 if (!atomic && !crtc->primary->fb) {
1917 DRM_DEBUG_KMS("No FB bound\n");
1922 amdgpu_fb = to_amdgpu_framebuffer(fb);
1925 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
1926 target_fb = crtc->primary->fb;
1929 /* If atomic, assume fb object is pinned & idle & fenced and
1930 * just update base pointers
1932 obj = amdgpu_fb->obj;
1933 abo = gem_to_amdgpu_bo(obj);
1934 r = amdgpu_bo_reserve(abo, false);
1935 if (unlikely(r != 0))
1939 fb_location = amdgpu_bo_gpu_offset(abo);
1941 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
1942 if (unlikely(r != 0)) {
1943 amdgpu_bo_unreserve(abo);
1948 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1949 amdgpu_bo_unreserve(abo);
1951 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1953 switch (target_fb->pixel_format) {
1955 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1956 (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1958 case DRM_FORMAT_XRGB4444:
1959 case DRM_FORMAT_ARGB4444:
1960 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1961 (GRPH_FORMAT_ARGB4444 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1963 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1966 case DRM_FORMAT_XRGB1555:
1967 case DRM_FORMAT_ARGB1555:
1968 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1969 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1971 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1974 case DRM_FORMAT_BGRX5551:
1975 case DRM_FORMAT_BGRA5551:
1976 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1977 (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1979 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1982 case DRM_FORMAT_RGB565:
1983 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1984 (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1986 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1989 case DRM_FORMAT_XRGB8888:
1990 case DRM_FORMAT_ARGB8888:
1991 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1992 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1994 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1997 case DRM_FORMAT_XRGB2101010:
1998 case DRM_FORMAT_ARGB2101010:
1999 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2000 (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2002 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2004 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2007 case DRM_FORMAT_BGRX1010102:
2008 case DRM_FORMAT_BGRA1010102:
2009 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2010 (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2012 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2014 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2018 DRM_ERROR("Unsupported screen format %s\n",
2019 drm_get_format_name(target_fb->pixel_format, &format_name));
2023 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2024 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2026 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2027 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2028 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2029 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2030 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2032 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);
2033 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
2034 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);
2035 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);
2036 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);
2037 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);
2038 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT);
2039 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2040 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
2043 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);
2045 dce_v8_0_vga_enable(crtc, false);
2047 /* Make sure surface address is updated at vertical blank rather than
2050 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
2052 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2053 upper_32_bits(fb_location));
2054 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2055 upper_32_bits(fb_location));
2056 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2057 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2058 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2059 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2060 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2061 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2064 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2065 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2066 * retain the full precision throughout the pipeline.
2068 WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
2069 (bypass_lut ? LUT_10BIT_BYPASS_EN : 0),
2070 ~LUT_10BIT_BYPASS_EN);
2073 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2075 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2076 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2077 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2078 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2079 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2080 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2082 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2083 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2085 dce_v8_0_grph_enable(crtc, true);
2087 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2092 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2094 viewport_w = crtc->mode.hdisplay;
2095 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2096 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2097 (viewport_w << 16) | viewport_h);
2099 /* set pageflip to happen anywhere in vblank interval */
2100 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2102 if (!atomic && fb && fb != crtc->primary->fb) {
2103 amdgpu_fb = to_amdgpu_framebuffer(fb);
2104 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2105 r = amdgpu_bo_reserve(abo, false);
2106 if (unlikely(r != 0))
2108 amdgpu_bo_unpin(abo);
2109 amdgpu_bo_unreserve(abo);
2112 /* Bytes per pixel may have changed */
2113 dce_v8_0_bandwidth_update(adev);
2118 static void dce_v8_0_set_interleave(struct drm_crtc *crtc,
2119 struct drm_display_mode *mode)
2121 struct drm_device *dev = crtc->dev;
2122 struct amdgpu_device *adev = dev->dev_private;
2123 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2125 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2126 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,
2127 LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT);
2129 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
2132 static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)
2134 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2135 struct drm_device *dev = crtc->dev;
2136 struct amdgpu_device *adev = dev->dev_private;
2139 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2141 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2142 ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2143 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2144 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2145 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2146 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2147 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2148 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2149 ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2150 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2152 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2154 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2155 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2156 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2158 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2159 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2160 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2162 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2163 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2165 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2166 for (i = 0; i < 256; i++) {
2167 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2168 (amdgpu_crtc->lut_r[i] << 20) |
2169 (amdgpu_crtc->lut_g[i] << 10) |
2170 (amdgpu_crtc->lut_b[i] << 0));
2173 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2174 ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2175 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2176 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2177 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2178 ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2179 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2180 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2181 ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2182 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2183 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2184 ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2185 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2186 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2187 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2188 /* XXX this only needs to be programmed once per crtc at startup,
2189 * not sure where the best place for it is
2191 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,
2192 ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK);
2195 static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder)
2197 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2198 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2200 switch (amdgpu_encoder->encoder_id) {
2201 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2207 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2213 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2219 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2223 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2229 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2233 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2234 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2235 * monitors a dedicated PPLL must be used. If a particular board has
2236 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2237 * as there is no need to program the PLL itself. If we are not able to
2238 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2239 * avoid messing up an existing monitor.
2241 * Asic specific PLL information
2245 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2247 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2250 static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)
2252 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2253 struct drm_device *dev = crtc->dev;
2254 struct amdgpu_device *adev = dev->dev_private;
2258 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2259 if (adev->clock.dp_extclk)
2260 /* skip PPLL programming if using ext clock */
2261 return ATOM_PPLL_INVALID;
2263 /* use the same PPLL for all DP monitors */
2264 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2265 if (pll != ATOM_PPLL_INVALID)
2269 /* use the same PPLL for all monitors with the same clock */
2270 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2271 if (pll != ATOM_PPLL_INVALID)
2274 /* otherwise, pick one of the plls */
2275 if ((adev->asic_type == CHIP_KABINI) ||
2276 (adev->asic_type == CHIP_MULLINS)) {
2277 /* KB/ML has PPLL1 and PPLL2 */
2278 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2279 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2281 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2283 DRM_ERROR("unable to allocate a PPLL\n");
2284 return ATOM_PPLL_INVALID;
2286 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
2287 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2288 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2290 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2292 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2294 DRM_ERROR("unable to allocate a PPLL\n");
2295 return ATOM_PPLL_INVALID;
2297 return ATOM_PPLL_INVALID;
2300 static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2302 struct amdgpu_device *adev = crtc->dev->dev_private;
2303 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2306 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2308 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2310 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2311 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2314 static void dce_v8_0_hide_cursor(struct drm_crtc *crtc)
2316 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2317 struct amdgpu_device *adev = crtc->dev->dev_private;
2319 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2320 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2321 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2324 static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
2326 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2327 struct amdgpu_device *adev = crtc->dev->dev_private;
2329 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2330 upper_32_bits(amdgpu_crtc->cursor_addr));
2331 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2332 lower_32_bits(amdgpu_crtc->cursor_addr));
2334 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2335 CUR_CONTROL__CURSOR_EN_MASK |
2336 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2337 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2340 static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
2343 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2344 struct amdgpu_device *adev = crtc->dev->dev_private;
2345 int xorigin = 0, yorigin = 0;
2347 amdgpu_crtc->cursor_x = x;
2348 amdgpu_crtc->cursor_y = y;
2350 /* avivo cursor are offset into the total surface */
2353 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2356 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2360 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2364 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2365 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2366 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2367 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2372 static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
2377 dce_v8_0_lock_cursor(crtc, true);
2378 ret = dce_v8_0_cursor_move_locked(crtc, x, y);
2379 dce_v8_0_lock_cursor(crtc, false);
2384 static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2385 struct drm_file *file_priv,
2392 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2393 struct drm_gem_object *obj;
2394 struct amdgpu_bo *aobj;
2398 /* turn off cursor */
2399 dce_v8_0_hide_cursor(crtc);
2404 if ((width > amdgpu_crtc->max_cursor_width) ||
2405 (height > amdgpu_crtc->max_cursor_height)) {
2406 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2410 obj = drm_gem_object_lookup(file_priv, handle);
2412 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2416 aobj = gem_to_amdgpu_bo(obj);
2417 ret = amdgpu_bo_reserve(aobj, false);
2419 drm_gem_object_unreference_unlocked(obj);
2423 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2424 amdgpu_bo_unreserve(aobj);
2426 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2427 drm_gem_object_unreference_unlocked(obj);
2431 dce_v8_0_lock_cursor(crtc, true);
2433 if (width != amdgpu_crtc->cursor_width ||
2434 height != amdgpu_crtc->cursor_height ||
2435 hot_x != amdgpu_crtc->cursor_hot_x ||
2436 hot_y != amdgpu_crtc->cursor_hot_y) {
2439 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2440 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2442 dce_v8_0_cursor_move_locked(crtc, x, y);
2444 amdgpu_crtc->cursor_width = width;
2445 amdgpu_crtc->cursor_height = height;
2446 amdgpu_crtc->cursor_hot_x = hot_x;
2447 amdgpu_crtc->cursor_hot_y = hot_y;
2450 dce_v8_0_show_cursor(crtc);
2451 dce_v8_0_lock_cursor(crtc, false);
2454 if (amdgpu_crtc->cursor_bo) {
2455 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2456 ret = amdgpu_bo_reserve(aobj, false);
2457 if (likely(ret == 0)) {
2458 amdgpu_bo_unpin(aobj);
2459 amdgpu_bo_unreserve(aobj);
2461 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2464 amdgpu_crtc->cursor_bo = obj;
2468 static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
2470 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2472 if (amdgpu_crtc->cursor_bo) {
2473 dce_v8_0_lock_cursor(crtc, true);
2475 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2476 amdgpu_crtc->cursor_y);
2478 dce_v8_0_show_cursor(crtc);
2480 dce_v8_0_lock_cursor(crtc, false);
2484 static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2485 u16 *blue, uint32_t size)
2487 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2490 /* userspace palettes are always correct as is */
2491 for (i = 0; i < size; i++) {
2492 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2493 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2494 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2496 dce_v8_0_crtc_load_lut(crtc);
2501 static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
2503 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2505 drm_crtc_cleanup(crtc);
2509 static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = {
2510 .cursor_set2 = dce_v8_0_crtc_cursor_set2,
2511 .cursor_move = dce_v8_0_crtc_cursor_move,
2512 .gamma_set = dce_v8_0_crtc_gamma_set,
2513 .set_config = amdgpu_crtc_set_config,
2514 .destroy = dce_v8_0_crtc_destroy,
2515 .page_flip_target = amdgpu_crtc_page_flip_target,
2518 static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2520 struct drm_device *dev = crtc->dev;
2521 struct amdgpu_device *adev = dev->dev_private;
2522 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2526 case DRM_MODE_DPMS_ON:
2527 amdgpu_crtc->enabled = true;
2528 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2529 dce_v8_0_vga_enable(crtc, true);
2530 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2531 dce_v8_0_vga_enable(crtc, false);
2532 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2533 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2534 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2535 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2536 drm_crtc_vblank_on(crtc);
2537 dce_v8_0_crtc_load_lut(crtc);
2539 case DRM_MODE_DPMS_STANDBY:
2540 case DRM_MODE_DPMS_SUSPEND:
2541 case DRM_MODE_DPMS_OFF:
2542 drm_crtc_vblank_off(crtc);
2543 if (amdgpu_crtc->enabled) {
2544 dce_v8_0_vga_enable(crtc, true);
2545 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2546 dce_v8_0_vga_enable(crtc, false);
2548 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2549 amdgpu_crtc->enabled = false;
2552 /* adjust pm to dpms */
2553 amdgpu_pm_compute_clocks(adev);
2556 static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc)
2558 /* disable crtc pair power gating before programming */
2559 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2560 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2561 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2564 static void dce_v8_0_crtc_commit(struct drm_crtc *crtc)
2566 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2567 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2570 static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
2572 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2573 struct drm_device *dev = crtc->dev;
2574 struct amdgpu_device *adev = dev->dev_private;
2575 struct amdgpu_atom_ss ss;
2578 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2579 if (crtc->primary->fb) {
2581 struct amdgpu_framebuffer *amdgpu_fb;
2582 struct amdgpu_bo *abo;
2584 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2585 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2586 r = amdgpu_bo_reserve(abo, false);
2588 DRM_ERROR("failed to reserve abo before unpin\n");
2590 amdgpu_bo_unpin(abo);
2591 amdgpu_bo_unreserve(abo);
2594 /* disable the GRPH */
2595 dce_v8_0_grph_enable(crtc, false);
2597 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2599 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2600 if (adev->mode_info.crtcs[i] &&
2601 adev->mode_info.crtcs[i]->enabled &&
2602 i != amdgpu_crtc->crtc_id &&
2603 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2604 /* one other crtc is using this pll don't turn
2611 switch (amdgpu_crtc->pll_id) {
2614 /* disable the ppll */
2615 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2616 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2619 /* disable the ppll */
2620 if ((adev->asic_type == CHIP_KAVERI) ||
2621 (adev->asic_type == CHIP_BONAIRE) ||
2622 (adev->asic_type == CHIP_HAWAII))
2623 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2624 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2630 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2631 amdgpu_crtc->adjusted_clock = 0;
2632 amdgpu_crtc->encoder = NULL;
2633 amdgpu_crtc->connector = NULL;
2636 static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,
2637 struct drm_display_mode *mode,
2638 struct drm_display_mode *adjusted_mode,
2639 int x, int y, struct drm_framebuffer *old_fb)
2641 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2643 if (!amdgpu_crtc->adjusted_clock)
2646 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2647 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2648 dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2649 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2650 amdgpu_atombios_crtc_scaler_setup(crtc);
2651 dce_v8_0_cursor_reset(crtc);
2652 /* update the hw version fpr dpm */
2653 amdgpu_crtc->hw_mode = *adjusted_mode;
2658 static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc,
2659 const struct drm_display_mode *mode,
2660 struct drm_display_mode *adjusted_mode)
2662 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2663 struct drm_device *dev = crtc->dev;
2664 struct drm_encoder *encoder;
2666 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2667 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2668 if (encoder->crtc == crtc) {
2669 amdgpu_crtc->encoder = encoder;
2670 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2674 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2675 amdgpu_crtc->encoder = NULL;
2676 amdgpu_crtc->connector = NULL;
2679 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2681 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2684 amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);
2685 /* if we can't get a PPLL for a non-DP encoder, fail */
2686 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2687 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2693 static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2694 struct drm_framebuffer *old_fb)
2696 return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2699 static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2700 struct drm_framebuffer *fb,
2701 int x, int y, enum mode_set_atomic state)
2703 return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
2706 static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
2707 .dpms = dce_v8_0_crtc_dpms,
2708 .mode_fixup = dce_v8_0_crtc_mode_fixup,
2709 .mode_set = dce_v8_0_crtc_mode_set,
2710 .mode_set_base = dce_v8_0_crtc_set_base,
2711 .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic,
2712 .prepare = dce_v8_0_crtc_prepare,
2713 .commit = dce_v8_0_crtc_commit,
2714 .load_lut = dce_v8_0_crtc_load_lut,
2715 .disable = dce_v8_0_crtc_disable,
2718 static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
2720 struct amdgpu_crtc *amdgpu_crtc;
2723 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2724 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2725 if (amdgpu_crtc == NULL)
2728 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
2730 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2731 amdgpu_crtc->crtc_id = index;
2732 adev->mode_info.crtcs[index] = amdgpu_crtc;
2734 amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
2735 amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
2736 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2737 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2739 for (i = 0; i < 256; i++) {
2740 amdgpu_crtc->lut_r[i] = i << 2;
2741 amdgpu_crtc->lut_g[i] = i << 2;
2742 amdgpu_crtc->lut_b[i] = i << 2;
2745 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2747 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2748 amdgpu_crtc->adjusted_clock = 0;
2749 amdgpu_crtc->encoder = NULL;
2750 amdgpu_crtc->connector = NULL;
2751 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);
2756 static int dce_v8_0_early_init(void *handle)
2758 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2760 adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg;
2761 adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
2763 dce_v8_0_set_display_funcs(adev);
2764 dce_v8_0_set_irq_funcs(adev);
2766 adev->mode_info.num_crtc = dce_v8_0_get_num_crtc(adev);
2768 switch (adev->asic_type) {
2771 adev->mode_info.num_hpd = 6;
2772 adev->mode_info.num_dig = 6;
2775 adev->mode_info.num_hpd = 6;
2776 adev->mode_info.num_dig = 7;
2780 adev->mode_info.num_hpd = 6;
2781 adev->mode_info.num_dig = 6; /* ? */
2784 /* FIXME: not supported yet */
2791 static int dce_v8_0_sw_init(void *handle)
2794 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2796 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2797 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2802 for (i = 8; i < 20; i += 2) {
2803 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2809 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2813 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2815 adev->ddev->mode_config.async_page_flip = true;
2817 adev->ddev->mode_config.max_width = 16384;
2818 adev->ddev->mode_config.max_height = 16384;
2820 adev->ddev->mode_config.preferred_depth = 24;
2821 adev->ddev->mode_config.prefer_shadow = 1;
2823 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2825 r = amdgpu_modeset_create_props(adev);
2829 adev->ddev->mode_config.max_width = 16384;
2830 adev->ddev->mode_config.max_height = 16384;
2832 /* allocate crtcs */
2833 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2834 r = dce_v8_0_crtc_init(adev, i);
2839 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2840 amdgpu_print_display_setup(adev->ddev);
2845 r = dce_v8_0_afmt_init(adev);
2849 r = dce_v8_0_audio_init(adev);
2853 drm_kms_helper_poll_init(adev->ddev);
2855 adev->mode_info.mode_config_initialized = true;
2859 static int dce_v8_0_sw_fini(void *handle)
2861 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2863 kfree(adev->mode_info.bios_hardcoded_edid);
2865 drm_kms_helper_poll_fini(adev->ddev);
2867 dce_v8_0_audio_fini(adev);
2869 dce_v8_0_afmt_fini(adev);
2871 drm_mode_config_cleanup(adev->ddev);
2872 adev->mode_info.mode_config_initialized = false;
2877 static int dce_v8_0_hw_init(void *handle)
2880 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2882 /* init dig PHYs, disp eng pll */
2883 amdgpu_atombios_encoder_init_dig(adev);
2884 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2886 /* initialize hpd */
2887 dce_v8_0_hpd_init(adev);
2889 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2890 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2893 dce_v8_0_pageflip_interrupt_init(adev);
2898 static int dce_v8_0_hw_fini(void *handle)
2901 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2903 dce_v8_0_hpd_fini(adev);
2905 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2906 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2909 dce_v8_0_pageflip_interrupt_fini(adev);
2914 static int dce_v8_0_suspend(void *handle)
2916 return dce_v8_0_hw_fini(handle);
2919 static int dce_v8_0_resume(void *handle)
2921 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2924 ret = dce_v8_0_hw_init(handle);
2926 /* turn on the BL */
2927 if (adev->mode_info.bl_encoder) {
2928 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2929 adev->mode_info.bl_encoder);
2930 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2937 static bool dce_v8_0_is_idle(void *handle)
2942 static int dce_v8_0_wait_for_idle(void *handle)
2947 static int dce_v8_0_soft_reset(void *handle)
2949 u32 srbm_soft_reset = 0, tmp;
2950 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2952 if (dce_v8_0_is_display_hung(adev))
2953 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
2955 if (srbm_soft_reset) {
2956 tmp = RREG32(mmSRBM_SOFT_RESET);
2957 tmp |= srbm_soft_reset;
2958 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2959 WREG32(mmSRBM_SOFT_RESET, tmp);
2960 tmp = RREG32(mmSRBM_SOFT_RESET);
2964 tmp &= ~srbm_soft_reset;
2965 WREG32(mmSRBM_SOFT_RESET, tmp);
2966 tmp = RREG32(mmSRBM_SOFT_RESET);
2968 /* Wait a little for things to settle down */
2974 static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2976 enum amdgpu_interrupt_state state)
2978 u32 reg_block, lb_interrupt_mask;
2980 if (crtc >= adev->mode_info.num_crtc) {
2981 DRM_DEBUG("invalid crtc %d\n", crtc);
2987 reg_block = CRTC0_REGISTER_OFFSET;
2990 reg_block = CRTC1_REGISTER_OFFSET;
2993 reg_block = CRTC2_REGISTER_OFFSET;
2996 reg_block = CRTC3_REGISTER_OFFSET;
2999 reg_block = CRTC4_REGISTER_OFFSET;
3002 reg_block = CRTC5_REGISTER_OFFSET;
3005 DRM_DEBUG("invalid crtc %d\n", crtc);
3010 case AMDGPU_IRQ_STATE_DISABLE:
3011 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3012 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
3013 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3015 case AMDGPU_IRQ_STATE_ENABLE:
3016 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3017 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
3018 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3025 static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3027 enum amdgpu_interrupt_state state)
3029 u32 reg_block, lb_interrupt_mask;
3031 if (crtc >= adev->mode_info.num_crtc) {
3032 DRM_DEBUG("invalid crtc %d\n", crtc);
3038 reg_block = CRTC0_REGISTER_OFFSET;
3041 reg_block = CRTC1_REGISTER_OFFSET;
3044 reg_block = CRTC2_REGISTER_OFFSET;
3047 reg_block = CRTC3_REGISTER_OFFSET;
3050 reg_block = CRTC4_REGISTER_OFFSET;
3053 reg_block = CRTC5_REGISTER_OFFSET;
3056 DRM_DEBUG("invalid crtc %d\n", crtc);
3061 case AMDGPU_IRQ_STATE_DISABLE:
3062 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3063 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
3064 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3066 case AMDGPU_IRQ_STATE_ENABLE:
3067 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3068 lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
3069 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3076 static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
3077 struct amdgpu_irq_src *src,
3079 enum amdgpu_interrupt_state state)
3081 u32 dc_hpd_int_cntl;
3083 if (type >= adev->mode_info.num_hpd) {
3084 DRM_DEBUG("invalid hdp %d\n", type);
3089 case AMDGPU_IRQ_STATE_DISABLE:
3090 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
3091 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3092 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
3094 case AMDGPU_IRQ_STATE_ENABLE:
3095 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
3096 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3097 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
3106 static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
3107 struct amdgpu_irq_src *src,
3109 enum amdgpu_interrupt_state state)
3112 case AMDGPU_CRTC_IRQ_VBLANK1:
3113 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3115 case AMDGPU_CRTC_IRQ_VBLANK2:
3116 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3118 case AMDGPU_CRTC_IRQ_VBLANK3:
3119 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3121 case AMDGPU_CRTC_IRQ_VBLANK4:
3122 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3124 case AMDGPU_CRTC_IRQ_VBLANK5:
3125 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3127 case AMDGPU_CRTC_IRQ_VBLANK6:
3128 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3130 case AMDGPU_CRTC_IRQ_VLINE1:
3131 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state);
3133 case AMDGPU_CRTC_IRQ_VLINE2:
3134 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state);
3136 case AMDGPU_CRTC_IRQ_VLINE3:
3137 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state);
3139 case AMDGPU_CRTC_IRQ_VLINE4:
3140 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state);
3142 case AMDGPU_CRTC_IRQ_VLINE5:
3143 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state);
3145 case AMDGPU_CRTC_IRQ_VLINE6:
3146 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state);
3154 static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
3155 struct amdgpu_irq_src *source,
3156 struct amdgpu_iv_entry *entry)
3158 unsigned crtc = entry->src_id - 1;
3159 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3160 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3162 switch (entry->src_data) {
3163 case 0: /* vblank */
3164 if (disp_int & interrupt_status_offsets[crtc].vblank)
3165 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
3167 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3169 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3170 drm_handle_vblank(adev->ddev, crtc);
3172 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3175 if (disp_int & interrupt_status_offsets[crtc].vline)
3176 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
3178 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3180 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3183 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3190 static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
3191 struct amdgpu_irq_src *src,
3193 enum amdgpu_interrupt_state state)
3197 if (type >= adev->mode_info.num_crtc) {
3198 DRM_ERROR("invalid pageflip crtc %d\n", type);
3202 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3203 if (state == AMDGPU_IRQ_STATE_DISABLE)
3204 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3205 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3207 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3208 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3213 static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
3214 struct amdgpu_irq_src *source,
3215 struct amdgpu_iv_entry *entry)
3217 unsigned long flags;
3219 struct amdgpu_crtc *amdgpu_crtc;
3220 struct amdgpu_flip_work *works;
3222 crtc_id = (entry->src_id - 8) >> 1;
3223 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3225 if (crtc_id >= adev->mode_info.num_crtc) {
3226 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3230 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3231 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3232 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3233 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3235 /* IRQ could occur when in initial stage */
3236 if (amdgpu_crtc == NULL)
3239 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3240 works = amdgpu_crtc->pflip_works;
3241 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3242 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3243 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3244 amdgpu_crtc->pflip_status,
3245 AMDGPU_FLIP_SUBMITTED);
3246 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3250 /* page flip completed. clean up */
3251 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3252 amdgpu_crtc->pflip_works = NULL;
3254 /* wakeup usersapce */
3256 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3258 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3260 drm_crtc_vblank_put(&amdgpu_crtc->base);
3261 schedule_work(&works->unpin_work);
3266 static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
3267 struct amdgpu_irq_src *source,
3268 struct amdgpu_iv_entry *entry)
3270 uint32_t disp_int, mask, tmp;
3273 if (entry->src_data >= adev->mode_info.num_hpd) {
3274 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3278 hpd = entry->src_data;
3279 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3280 mask = interrupt_status_offsets[hpd].hpd;
3282 if (disp_int & mask) {
3283 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
3284 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3285 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
3286 schedule_work(&adev->hotplug_work);
3287 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3294 static int dce_v8_0_set_clockgating_state(void *handle,
3295 enum amd_clockgating_state state)
3300 static int dce_v8_0_set_powergating_state(void *handle,
3301 enum amd_powergating_state state)
3306 static const struct amd_ip_funcs dce_v8_0_ip_funcs = {
3308 .early_init = dce_v8_0_early_init,
3310 .sw_init = dce_v8_0_sw_init,
3311 .sw_fini = dce_v8_0_sw_fini,
3312 .hw_init = dce_v8_0_hw_init,
3313 .hw_fini = dce_v8_0_hw_fini,
3314 .suspend = dce_v8_0_suspend,
3315 .resume = dce_v8_0_resume,
3316 .is_idle = dce_v8_0_is_idle,
3317 .wait_for_idle = dce_v8_0_wait_for_idle,
3318 .soft_reset = dce_v8_0_soft_reset,
3319 .set_clockgating_state = dce_v8_0_set_clockgating_state,
3320 .set_powergating_state = dce_v8_0_set_powergating_state,
3324 dce_v8_0_encoder_mode_set(struct drm_encoder *encoder,
3325 struct drm_display_mode *mode,
3326 struct drm_display_mode *adjusted_mode)
3328 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3330 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3332 /* need to call this here rather than in prepare() since we need some crtc info */
3333 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3335 /* set scaler clears this on some chips */
3336 dce_v8_0_set_interleave(encoder->crtc, mode);
3338 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3339 dce_v8_0_afmt_enable(encoder, true);
3340 dce_v8_0_afmt_setmode(encoder, adjusted_mode);
3344 static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
3346 struct amdgpu_device *adev = encoder->dev->dev_private;
3347 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3348 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3350 if ((amdgpu_encoder->active_device &
3351 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3352 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3353 ENCODER_OBJECT_ID_NONE)) {
3354 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3356 dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder);
3357 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3358 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3362 amdgpu_atombios_scratch_regs_lock(adev, true);
3365 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3367 /* select the clock/data port if it uses a router */
3368 if (amdgpu_connector->router.cd_valid)
3369 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3371 /* turn eDP panel on for mode set */
3372 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3373 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3374 ATOM_TRANSMITTER_ACTION_POWER_ON);
3377 /* this is needed for the pll/ss setup to work correctly in some cases */
3378 amdgpu_atombios_encoder_set_crtc_source(encoder);
3379 /* set up the FMT blocks */
3380 dce_v8_0_program_fmt(encoder);
3383 static void dce_v8_0_encoder_commit(struct drm_encoder *encoder)
3385 struct drm_device *dev = encoder->dev;
3386 struct amdgpu_device *adev = dev->dev_private;
3388 /* need to call this here as we need the crtc set up */
3389 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3390 amdgpu_atombios_scratch_regs_lock(adev, false);
3393 static void dce_v8_0_encoder_disable(struct drm_encoder *encoder)
3395 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3396 struct amdgpu_encoder_atom_dig *dig;
3398 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3400 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3401 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3402 dce_v8_0_afmt_enable(encoder, false);
3403 dig = amdgpu_encoder->enc_priv;
3404 dig->dig_encoder = -1;
3406 amdgpu_encoder->active_device = 0;
3409 /* these are handled by the primary encoders */
3410 static void dce_v8_0_ext_prepare(struct drm_encoder *encoder)
3415 static void dce_v8_0_ext_commit(struct drm_encoder *encoder)
3421 dce_v8_0_ext_mode_set(struct drm_encoder *encoder,
3422 struct drm_display_mode *mode,
3423 struct drm_display_mode *adjusted_mode)
3428 static void dce_v8_0_ext_disable(struct drm_encoder *encoder)
3434 dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode)
3439 static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = {
3440 .dpms = dce_v8_0_ext_dpms,
3441 .prepare = dce_v8_0_ext_prepare,
3442 .mode_set = dce_v8_0_ext_mode_set,
3443 .commit = dce_v8_0_ext_commit,
3444 .disable = dce_v8_0_ext_disable,
3445 /* no detect for TMDS/LVDS yet */
3448 static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = {
3449 .dpms = amdgpu_atombios_encoder_dpms,
3450 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3451 .prepare = dce_v8_0_encoder_prepare,
3452 .mode_set = dce_v8_0_encoder_mode_set,
3453 .commit = dce_v8_0_encoder_commit,
3454 .disable = dce_v8_0_encoder_disable,
3455 .detect = amdgpu_atombios_encoder_dig_detect,
3458 static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = {
3459 .dpms = amdgpu_atombios_encoder_dpms,
3460 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3461 .prepare = dce_v8_0_encoder_prepare,
3462 .mode_set = dce_v8_0_encoder_mode_set,
3463 .commit = dce_v8_0_encoder_commit,
3464 .detect = amdgpu_atombios_encoder_dac_detect,
3467 static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder)
3469 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3470 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3471 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3472 kfree(amdgpu_encoder->enc_priv);
3473 drm_encoder_cleanup(encoder);
3474 kfree(amdgpu_encoder);
3477 static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = {
3478 .destroy = dce_v8_0_encoder_destroy,
3481 static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
3482 uint32_t encoder_enum,
3483 uint32_t supported_device,
3486 struct drm_device *dev = adev->ddev;
3487 struct drm_encoder *encoder;
3488 struct amdgpu_encoder *amdgpu_encoder;
3490 /* see if we already added it */
3491 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3492 amdgpu_encoder = to_amdgpu_encoder(encoder);
3493 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3494 amdgpu_encoder->devices |= supported_device;
3501 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3502 if (!amdgpu_encoder)
3505 encoder = &amdgpu_encoder->base;
3506 switch (adev->mode_info.num_crtc) {
3508 encoder->possible_crtcs = 0x1;
3512 encoder->possible_crtcs = 0x3;
3515 encoder->possible_crtcs = 0xf;
3518 encoder->possible_crtcs = 0x3f;
3522 amdgpu_encoder->enc_priv = NULL;
3524 amdgpu_encoder->encoder_enum = encoder_enum;
3525 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3526 amdgpu_encoder->devices = supported_device;
3527 amdgpu_encoder->rmx_type = RMX_OFF;
3528 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3529 amdgpu_encoder->is_ext_encoder = false;
3530 amdgpu_encoder->caps = caps;
3532 switch (amdgpu_encoder->encoder_id) {
3533 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3534 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3535 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3536 DRM_MODE_ENCODER_DAC, NULL);
3537 drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs);
3539 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3540 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3541 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3542 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3543 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3544 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3545 amdgpu_encoder->rmx_type = RMX_FULL;
3546 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3547 DRM_MODE_ENCODER_LVDS, NULL);
3548 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3549 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3550 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3551 DRM_MODE_ENCODER_DAC, NULL);
3552 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3554 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3555 DRM_MODE_ENCODER_TMDS, NULL);
3556 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3558 drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs);
3560 case ENCODER_OBJECT_ID_SI170B:
3561 case ENCODER_OBJECT_ID_CH7303:
3562 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3563 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3564 case ENCODER_OBJECT_ID_TITFP513:
3565 case ENCODER_OBJECT_ID_VT1623:
3566 case ENCODER_OBJECT_ID_HDMI_SI1930:
3567 case ENCODER_OBJECT_ID_TRAVIS:
3568 case ENCODER_OBJECT_ID_NUTMEG:
3569 /* these are handled by the primary encoders */
3570 amdgpu_encoder->is_ext_encoder = true;
3571 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3572 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3573 DRM_MODE_ENCODER_LVDS, NULL);
3574 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3575 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3576 DRM_MODE_ENCODER_DAC, NULL);
3578 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3579 DRM_MODE_ENCODER_TMDS, NULL);
3580 drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs);
3585 static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
3586 .set_vga_render_state = &dce_v8_0_set_vga_render_state,
3587 .bandwidth_update = &dce_v8_0_bandwidth_update,
3588 .vblank_get_counter = &dce_v8_0_vblank_get_counter,
3589 .vblank_wait = &dce_v8_0_vblank_wait,
3590 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3591 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3592 .hpd_sense = &dce_v8_0_hpd_sense,
3593 .hpd_set_polarity = &dce_v8_0_hpd_set_polarity,
3594 .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg,
3595 .page_flip = &dce_v8_0_page_flip,
3596 .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos,
3597 .add_encoder = &dce_v8_0_encoder_add,
3598 .add_connector = &amdgpu_connector_add,
3599 .stop_mc_access = &dce_v8_0_stop_mc_access,
3600 .resume_mc_access = &dce_v8_0_resume_mc_access,
3603 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
3605 if (adev->mode_info.funcs == NULL)
3606 adev->mode_info.funcs = &dce_v8_0_display_funcs;
3609 static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {
3610 .set = dce_v8_0_set_crtc_interrupt_state,
3611 .process = dce_v8_0_crtc_irq,
3614 static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = {
3615 .set = dce_v8_0_set_pageflip_interrupt_state,
3616 .process = dce_v8_0_pageflip_irq,
3619 static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = {
3620 .set = dce_v8_0_set_hpd_interrupt_state,
3621 .process = dce_v8_0_hpd_irq,
3624 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
3626 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3627 adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;
3629 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3630 adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;
3632 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3633 adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
3636 const struct amdgpu_ip_block_version dce_v8_0_ip_block =
3638 .type = AMD_IP_BLOCK_TYPE_DCE,
3642 .funcs = &dce_v8_0_ip_funcs,
3645 const struct amdgpu_ip_block_version dce_v8_1_ip_block =
3647 .type = AMD_IP_BLOCK_TYPE_DCE,
3651 .funcs = &dce_v8_0_ip_funcs,
3654 const struct amdgpu_ip_block_version dce_v8_2_ip_block =
3656 .type = AMD_IP_BLOCK_TYPE_DCE,
3660 .funcs = &dce_v8_0_ip_funcs,
3663 const struct amdgpu_ip_block_version dce_v8_3_ip_block =
3665 .type = AMD_IP_BLOCK_TYPE_DCE,
3669 .funcs = &dce_v8_0_ip_funcs,
3672 const struct amdgpu_ip_block_version dce_v8_5_ip_block =
3674 .type = AMD_IP_BLOCK_TYPE_DCE,
3678 .funcs = &dce_v8_0_ip_funcs,