drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29
  30 #include "amdgpu.h"
  31 #include "amdgpu_gfx.h"
  32 #include "soc15.h"
  33 #include "soc15d.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_pm.h"
  36
  37 #include "gc/gc_9_0_offset.h"
  38 #include "gc/gc_9_0_sh_mask.h"
  39
  40 #include "vega10_enum.h"
  41 #include "hdp/hdp_4_0_offset.h"
  42
  43 #include "soc15_common.h"
  44 #include "clearstate_gfx9.h"
  45 #include "v9_structs.h"
  46
  47 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
  48
  49 #include "amdgpu_ras.h"
  50
  51 #include "gfx_v9_4.h"
  52
  53 #define GFX9_NUM_GFX_RINGS     1
  54 #define GFX9_MEC_HPD_SIZE 4096
  55 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
  56 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
  57
  58 #define mmPWR_MISC_CNTL_STATUS                                  0x0183
  59 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX                         0
  60 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT        0x0
  61 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT          0x1
  62 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK          0x00000001L
  63 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK            0x00000006L
  64
  65 #define mmGCEA_PROBE_MAP                        0x070c
  66 #define mmGCEA_PROBE_MAP_BASE_IDX               0
  67
  68 MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
  69 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
  70 MODULE_FIRMWARE("amdgpu/vega10_me.bin");
  71 MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
  72 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
  73 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
  74
  75 MODULE_FIRMWARE("amdgpu/vega12_ce.bin");
  76 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin");
  77 MODULE_FIRMWARE("amdgpu/vega12_me.bin");
  78 MODULE_FIRMWARE("amdgpu/vega12_mec.bin");
  79 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin");
  80 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin");
  81
  82 MODULE_FIRMWARE("amdgpu/vega20_ce.bin");
  83 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin");
  84 MODULE_FIRMWARE("amdgpu/vega20_me.bin");
  85 MODULE_FIRMWARE("amdgpu/vega20_mec.bin");
  86 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin");
  87 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin");
  88
  89 MODULE_FIRMWARE("amdgpu/raven_ce.bin");
  90 MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
  91 MODULE_FIRMWARE("amdgpu/raven_me.bin");
  92 MODULE_FIRMWARE("amdgpu/raven_mec.bin");
  93 MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
  94 MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
  95
  96 MODULE_FIRMWARE("amdgpu/picasso_ce.bin");
  97 MODULE_FIRMWARE("amdgpu/picasso_pfp.bin");
  98 MODULE_FIRMWARE("amdgpu/picasso_me.bin");
  99 MODULE_FIRMWARE("amdgpu/picasso_mec.bin");
 100 MODULE_FIRMWARE("amdgpu/picasso_mec2.bin");
 101 MODULE_FIRMWARE("amdgpu/picasso_rlc.bin");
 102 MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin");
 103
 104 MODULE_FIRMWARE("amdgpu/raven2_ce.bin");
 105 MODULE_FIRMWARE("amdgpu/raven2_pfp.bin");
 106 MODULE_FIRMWARE("amdgpu/raven2_me.bin");
 107 MODULE_FIRMWARE("amdgpu/raven2_mec.bin");
 108 MODULE_FIRMWARE("amdgpu/raven2_mec2.bin");
 109 MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
 110 MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin");
 111
 112 MODULE_FIRMWARE("amdgpu/arcturus_mec.bin");
 113 MODULE_FIRMWARE("amdgpu/arcturus_mec2.bin");
 114 MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin");
 115
 116 MODULE_FIRMWARE("amdgpu/renoir_ce.bin");
 117 MODULE_FIRMWARE("amdgpu/renoir_pfp.bin");
 118 MODULE_FIRMWARE("amdgpu/renoir_me.bin");
 119 MODULE_FIRMWARE("amdgpu/renoir_mec.bin");
 120 MODULE_FIRMWARE("amdgpu/renoir_mec2.bin");
 121 MODULE_FIRMWARE("amdgpu/renoir_rlc.bin");
 122
 123 #define mmTCP_CHAN_STEER_0_ARCT                                                         0x0b03
 124 #define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX                                                        0
 125 #define mmTCP_CHAN_STEER_1_ARCT                                                         0x0b04
 126 #define mmTCP_CHAN_STEER_1_ARCT_BASE_IDX                                                        0
 127 #define mmTCP_CHAN_STEER_2_ARCT                                                         0x0b09
 128 #define mmTCP_CHAN_STEER_2_ARCT_BASE_IDX                                                        0
 129 #define mmTCP_CHAN_STEER_3_ARCT                                                         0x0b0a
 130 #define mmTCP_CHAN_STEER_3_ARCT_BASE_IDX                                                        0
 131 #define mmTCP_CHAN_STEER_4_ARCT                                                         0x0b0b
 132 #define mmTCP_CHAN_STEER_4_ARCT_BASE_IDX                                                        0
 133 #define mmTCP_CHAN_STEER_5_ARCT                                                         0x0b0c
 134 #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX                                                        0
 135
 136 enum ta_ras_gfx_subblock {
 137         /*CPC*/
 138         TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
 139         TA_RAS_BLOCK__GFX_CPC_SCRATCH = TA_RAS_BLOCK__GFX_CPC_INDEX_START,
 140         TA_RAS_BLOCK__GFX_CPC_UCODE,
 141         TA_RAS_BLOCK__GFX_DC_STATE_ME1,
 142         TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
 143         TA_RAS_BLOCK__GFX_DC_RESTORE_ME1,
 144         TA_RAS_BLOCK__GFX_DC_STATE_ME2,
 145         TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
 146         TA_RAS_BLOCK__GFX_DC_RESTORE_ME2,
 147         TA_RAS_BLOCK__GFX_CPC_INDEX_END = TA_RAS_BLOCK__GFX_DC_RESTORE_ME2,
 148         /* CPF*/
 149         TA_RAS_BLOCK__GFX_CPF_INDEX_START,
 150         TA_RAS_BLOCK__GFX_CPF_ROQ_ME2 = TA_RAS_BLOCK__GFX_CPF_INDEX_START,
 151         TA_RAS_BLOCK__GFX_CPF_ROQ_ME1,
 152         TA_RAS_BLOCK__GFX_CPF_TAG,
 153         TA_RAS_BLOCK__GFX_CPF_INDEX_END = TA_RAS_BLOCK__GFX_CPF_TAG,
 154         /* CPG*/
 155         TA_RAS_BLOCK__GFX_CPG_INDEX_START,
 156         TA_RAS_BLOCK__GFX_CPG_DMA_ROQ = TA_RAS_BLOCK__GFX_CPG_INDEX_START,
 157         TA_RAS_BLOCK__GFX_CPG_DMA_TAG,
 158         TA_RAS_BLOCK__GFX_CPG_TAG,
 159         TA_RAS_BLOCK__GFX_CPG_INDEX_END = TA_RAS_BLOCK__GFX_CPG_TAG,
 160         /* GDS*/
 161         TA_RAS_BLOCK__GFX_GDS_INDEX_START,
 162         TA_RAS_BLOCK__GFX_GDS_MEM = TA_RAS_BLOCK__GFX_GDS_INDEX_START,
 163         TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
 164         TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
 165         TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
 166         TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
 167         TA_RAS_BLOCK__GFX_GDS_INDEX_END = TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
 168         /* SPI*/
 169         TA_RAS_BLOCK__GFX_SPI_SR_MEM,
 170         /* SQ*/
 171         TA_RAS_BLOCK__GFX_SQ_INDEX_START,
 172         TA_RAS_BLOCK__GFX_SQ_SGPR = TA_RAS_BLOCK__GFX_SQ_INDEX_START,
 173         TA_RAS_BLOCK__GFX_SQ_LDS_D,
 174         TA_RAS_BLOCK__GFX_SQ_LDS_I,
 175         TA_RAS_BLOCK__GFX_SQ_VGPR, /* VGPR = SP*/
 176         TA_RAS_BLOCK__GFX_SQ_INDEX_END = TA_RAS_BLOCK__GFX_SQ_VGPR,
 177         /* SQC (3 ranges)*/
 178         TA_RAS_BLOCK__GFX_SQC_INDEX_START,
 179         /* SQC range 0*/
 180         TA_RAS_BLOCK__GFX_SQC_INDEX0_START = TA_RAS_BLOCK__GFX_SQC_INDEX_START,
 181         TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
 182                 TA_RAS_BLOCK__GFX_SQC_INDEX0_START,
 183         TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
 184         TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
 185         TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
 186         TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
 187         TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
 188         TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
 189         TA_RAS_BLOCK__GFX_SQC_INDEX0_END =
 190                 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
 191         /* SQC range 1*/
 192         TA_RAS_BLOCK__GFX_SQC_INDEX1_START,
 193         TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
 194                 TA_RAS_BLOCK__GFX_SQC_INDEX1_START,
 195         TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
 196         TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
 197         TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
 198         TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
 199         TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
 200         TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
 201         TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
 202         TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
 203         TA_RAS_BLOCK__GFX_SQC_INDEX1_END =
 204                 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
 205         /* SQC range 2*/
 206         TA_RAS_BLOCK__GFX_SQC_INDEX2_START,
 207         TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
 208                 TA_RAS_BLOCK__GFX_SQC_INDEX2_START,
 209         TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
 210         TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
 211         TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
 212         TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
 213         TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
 214         TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
 215         TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
 216         TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
 217         TA_RAS_BLOCK__GFX_SQC_INDEX2_END =
 218                 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
 219         TA_RAS_BLOCK__GFX_SQC_INDEX_END = TA_RAS_BLOCK__GFX_SQC_INDEX2_END,
 220         /* TA*/
 221         TA_RAS_BLOCK__GFX_TA_INDEX_START,
 222         TA_RAS_BLOCK__GFX_TA_FS_DFIFO = TA_RAS_BLOCK__GFX_TA_INDEX_START,
 223         TA_RAS_BLOCK__GFX_TA_FS_AFIFO,
 224         TA_RAS_BLOCK__GFX_TA_FL_LFIFO,
 225         TA_RAS_BLOCK__GFX_TA_FX_LFIFO,
 226         TA_RAS_BLOCK__GFX_TA_FS_CFIFO,
 227         TA_RAS_BLOCK__GFX_TA_INDEX_END = TA_RAS_BLOCK__GFX_TA_FS_CFIFO,
 228         /* TCA*/
 229         TA_RAS_BLOCK__GFX_TCA_INDEX_START,
 230         TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO = TA_RAS_BLOCK__GFX_TCA_INDEX_START,
 231         TA_RAS_BLOCK__GFX_TCA_REQ_FIFO,
 232         TA_RAS_BLOCK__GFX_TCA_INDEX_END = TA_RAS_BLOCK__GFX_TCA_REQ_FIFO,
 233         /* TCC (5 sub-ranges)*/
 234         TA_RAS_BLOCK__GFX_TCC_INDEX_START,
 235         /* TCC range 0*/
 236         TA_RAS_BLOCK__GFX_TCC_INDEX0_START = TA_RAS_BLOCK__GFX_TCC_INDEX_START,
 237         TA_RAS_BLOCK__GFX_TCC_CACHE_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX0_START,
 238         TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
 239         TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
 240         TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
 241         TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
 242         TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
 243         TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
 244         TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
 245         TA_RAS_BLOCK__GFX_TCC_INDEX0_END = TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
 246         /* TCC range 1*/
 247         TA_RAS_BLOCK__GFX_TCC_INDEX1_START,
 248         TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC = TA_RAS_BLOCK__GFX_TCC_INDEX1_START,
 249         TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
 250         TA_RAS_BLOCK__GFX_TCC_INDEX1_END =
 251                 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
 252         /* TCC range 2*/
 253         TA_RAS_BLOCK__GFX_TCC_INDEX2_START,
 254         TA_RAS_BLOCK__GFX_TCC_RETURN_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX2_START,
 255         TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
 256         TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
 257         TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
 258         TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
 259         TA_RAS_BLOCK__GFX_TCC_SRC_FIFO,
 260         TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
 261         TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
 262         TA_RAS_BLOCK__GFX_TCC_INDEX2_END =
 263                 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
 264         /* TCC range 3*/
 265         TA_RAS_BLOCK__GFX_TCC_INDEX3_START,
 266         TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = TA_RAS_BLOCK__GFX_TCC_INDEX3_START,
 267         TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
 268         TA_RAS_BLOCK__GFX_TCC_INDEX3_END =
 269                 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
 270         /* TCC range 4*/
 271         TA_RAS_BLOCK__GFX_TCC_INDEX4_START,
 272         TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
 273                 TA_RAS_BLOCK__GFX_TCC_INDEX4_START,
 274         TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
 275         TA_RAS_BLOCK__GFX_TCC_INDEX4_END =
 276                 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
 277         TA_RAS_BLOCK__GFX_TCC_INDEX_END = TA_RAS_BLOCK__GFX_TCC_INDEX4_END,
 278         /* TCI*/
 279         TA_RAS_BLOCK__GFX_TCI_WRITE_RAM,
 280         /* TCP*/
 281         TA_RAS_BLOCK__GFX_TCP_INDEX_START,
 282         TA_RAS_BLOCK__GFX_TCP_CACHE_RAM = TA_RAS_BLOCK__GFX_TCP_INDEX_START,
 283         TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
 284         TA_RAS_BLOCK__GFX_TCP_CMD_FIFO,
 285         TA_RAS_BLOCK__GFX_TCP_VM_FIFO,
 286         TA_RAS_BLOCK__GFX_TCP_DB_RAM,
 287         TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
 288         TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
 289         TA_RAS_BLOCK__GFX_TCP_INDEX_END = TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
 290         /* TD*/
 291         TA_RAS_BLOCK__GFX_TD_INDEX_START,
 292         TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO = TA_RAS_BLOCK__GFX_TD_INDEX_START,
 293         TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
 294         TA_RAS_BLOCK__GFX_TD_CS_FIFO,
 295         TA_RAS_BLOCK__GFX_TD_INDEX_END = TA_RAS_BLOCK__GFX_TD_CS_FIFO,
 296         /* EA (3 sub-ranges)*/
 297         TA_RAS_BLOCK__GFX_EA_INDEX_START,
 298         /* EA range 0*/
 299         TA_RAS_BLOCK__GFX_EA_INDEX0_START = TA_RAS_BLOCK__GFX_EA_INDEX_START,
 300         TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = TA_RAS_BLOCK__GFX_EA_INDEX0_START,
 301         TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
 302         TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
 303         TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
 304         TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
 305         TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
 306         TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
 307         TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
 308         TA_RAS_BLOCK__GFX_EA_INDEX0_END = TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
 309         /* EA range 1*/
 310         TA_RAS_BLOCK__GFX_EA_INDEX1_START,
 311         TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = TA_RAS_BLOCK__GFX_EA_INDEX1_START,
 312         TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
 313         TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
 314         TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
 315         TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
 316         TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
 317         TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
 318         TA_RAS_BLOCK__GFX_EA_INDEX1_END = TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
 319         /* EA range 2*/
 320         TA_RAS_BLOCK__GFX_EA_INDEX2_START,
 321         TA_RAS_BLOCK__GFX_EA_MAM_D0MEM = TA_RAS_BLOCK__GFX_EA_INDEX2_START,
 322         TA_RAS_BLOCK__GFX_EA_MAM_D1MEM,
 323         TA_RAS_BLOCK__GFX_EA_MAM_D2MEM,
 324         TA_RAS_BLOCK__GFX_EA_MAM_D3MEM,
 325         TA_RAS_BLOCK__GFX_EA_INDEX2_END = TA_RAS_BLOCK__GFX_EA_MAM_D3MEM,
 326         TA_RAS_BLOCK__GFX_EA_INDEX_END = TA_RAS_BLOCK__GFX_EA_INDEX2_END,
 327         /* UTC VM L2 bank*/
 328         TA_RAS_BLOCK__UTC_VML2_BANK_CACHE,
 329         /* UTC VM walker*/
 330         TA_RAS_BLOCK__UTC_VML2_WALKER,
 331         /* UTC ATC L2 2MB cache*/
 332         TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
 333         /* UTC ATC L2 4KB cache*/
 334         TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
 335         TA_RAS_BLOCK__GFX_MAX
 336 };
 337
 338 struct ras_gfx_subblock {
 339         unsigned char *name;
 340         int ta_subblock;
 341         int hw_supported_error_type;
 342         int sw_supported_error_type;
 343 };
 344
 345 #define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h)                             \
 346         [AMDGPU_RAS_BLOCK__##subblock] = {                                     \
 347                 #subblock,                                                     \
 348                 TA_RAS_BLOCK__##subblock,                                      \
 349                 ((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)),                  \
 350                 (((e) << 1) | ((f) << 3) | (g) | ((h) << 2)),                  \
 351         }
 352
 353 static const struct ras_gfx_subblock ras_gfx_subblocks[] = {
 354         AMDGPU_RAS_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1, 1, 0, 0, 1),
 355         AMDGPU_RAS_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1, 1, 0, 0, 1),
 356         AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1, 0, 0, 1, 0),
 357         AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1, 0, 0, 0, 0),
 358         AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1, 0, 0, 0, 0),
 359         AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
 360         AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
 361         AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
 362         AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
 363         AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1, 0, 0, 1, 0),
 364         AMDGPU_RAS_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1, 1, 0, 0, 1),
 365         AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1, 0, 0, 1, 0),
 366         AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1, 0, 1, 0, 1),
 367         AMDGPU_RAS_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1, 1, 1, 0, 1),
 368         AMDGPU_RAS_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1, 0, 0, 0, 0),
 369         AMDGPU_RAS_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1, 0, 0, 0, 0),
 370         AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1, 0, 0, 0,
 371                              0),
 372         AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1, 0, 0, 0,
 373                              0),
 374         AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1, 0, 0, 0, 0),
 375         AMDGPU_RAS_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1, 0, 0, 0, 0),
 376         AMDGPU_RAS_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1, 0, 0, 0, 0),
 377         AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1, 1, 0, 0, 1),
 378         AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1, 0, 0, 0, 0),
 379         AMDGPU_RAS_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1, 0, 0, 0, 0),
 380         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 1),
 381         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,
 382                              0, 0),
 383         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0,
 384                              0),
 385         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,
 386                              0, 0),
 387         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1, 1, 0, 0,
 388                              0),
 389         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,
 390                              0, 0),
 391         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0,
 392                              0),
 393         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1, 1, 0, 0,
 394                              1),
 395         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0,
 396                              0, 0, 0),
 397         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
 398                              0),
 399         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
 400                              0),
 401         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1, 0, 0, 0,
 402                              0),
 403         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0,
 404                              0),
 405         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
 406                              0),
 407         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0,
 408                              0, 0),
 409         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
 410                              0),
 411         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1, 1, 0, 0,
 412                              0),
 413         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0,
 414                              0, 0, 0),
 415         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
 416                              0),
 417         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
 418                              0),
 419         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM, 0, 1, 1, 1, 0, 0, 0,
 420                              0),
 421         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0,
 422                              0),
 423         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
 424                              0),
 425         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0,
 426                              0, 0),
 427         AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
 428                              0),
 429         AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_DFIFO, 0, 1, 1, 1, 1, 0, 0, 1),
 430         AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_AFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
 431         AMDGPU_RAS_SUB_BLOCK(GFX_TA_FL_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
 432         AMDGPU_RAS_SUB_BLOCK(GFX_TA_FX_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
 433         AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_CFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
 434         AMDGPU_RAS_SUB_BLOCK(GFX_TCA_HOLE_FIFO, 1, 0, 0, 1, 0, 1, 1, 0),
 435         AMDGPU_RAS_SUB_BLOCK(GFX_TCA_REQ_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
 436         AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA, 0, 1, 1, 1, 1, 0, 0, 1),
 437         AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1, 0, 1, 1, 1, 1, 0, 0,
 438                              1),
 439         AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0, 0, 1, 1, 1, 1, 0, 0,
 440                              1),
 441         AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1, 0, 1, 1, 1, 1, 0, 0,
 442                              1),
 443         AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0, 0, 1, 1, 1, 0, 0, 0,
 444                              0),
 445         AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1, 0, 1, 1, 1, 0, 0, 0,
 446                              0),
 447         AMDGPU_RAS_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0),
 448         AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0),
 449         AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_DEC, 1, 0, 0, 1, 0, 0, 0, 0),
 450         AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER, 1, 0, 0, 1, 0, 0, 0, 0),
 451         AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_DATA, 1, 0, 0, 1, 0, 0, 0, 0),
 452         AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_CONTROL, 1, 0, 0, 1, 0, 0, 0, 0),
 453         AMDGPU_RAS_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
 454         AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_RETURN, 1, 0, 0, 1, 0, 1, 1, 0),
 455         AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ, 1, 0, 0, 1, 0, 0, 0, 0),
 456         AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO, 0, 1, 1, 1, 0, 0, 0, 0),
 457         AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 1, 0),
 458         AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO, 1, 0, 0, 1, 0, 0, 0,
 459                              0),
 460         AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
 461         AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 0,
 462                              0),
 463         AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN, 1, 0, 0, 1, 0, 0,
 464                              0, 0),
 465         AMDGPU_RAS_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER, 1, 0, 0, 1, 0, 0, 0,
 466                              0),
 467         AMDGPU_RAS_SUB_BLOCK(GFX_TCI_WRITE_RAM, 1, 0, 0, 1, 0, 0, 0, 0),
 468         AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CACHE_RAM, 0, 1, 1, 1, 1, 0, 0, 1),
 469         AMDGPU_RAS_SUB_BLOCK(GFX_TCP_LFIFO_RAM, 0, 1, 1, 1, 0, 0, 0, 0),
 470         AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CMD_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
 471         AMDGPU_RAS_SUB_BLOCK(GFX_TCP_VM_FIFO, 0, 1, 1, 1, 0, 0, 0, 0),
 472         AMDGPU_RAS_SUB_BLOCK(GFX_TCP_DB_RAM, 1, 0, 0, 1, 0, 0, 0, 0),
 473         AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0, 0, 1, 1, 1, 0, 0, 0, 0),
 474         AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1, 0, 1, 1, 1, 0, 0, 0, 0),
 475         AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_LO, 0, 1, 1, 1, 1, 0, 0, 1),
 476         AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_HI, 0, 1, 1, 1, 0, 0, 0, 0),
 477         AMDGPU_RAS_SUB_BLOCK(GFX_TD_CS_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
 478         AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM, 0, 1, 1, 1, 1, 0, 0, 1),
 479         AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0),
 480         AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0),
 481         AMDGPU_RAS_SUB_BLOCK(GFX_EA_RRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0),
 482         AMDGPU_RAS_SUB_BLOCK(GFX_EA_WRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0),
 483         AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0),
 484         AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0),
 485         AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0),
 486         AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
 487         AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
 488         AMDGPU_RAS_SUB_BLOCK(GFX_EA_IORD_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0),
 489         AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0),
 490         AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_DATAMEM, 1, 0, 0, 1, 0, 0, 0, 0),
 491         AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
 492         AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
 493         AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D0MEM, 1, 0, 0, 1, 0, 0, 0, 0),
 494         AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D1MEM, 1, 0, 0, 1, 0, 0, 0, 0),
 495         AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D2MEM, 1, 0, 0, 1, 0, 0, 0, 0),
 496         AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D3MEM, 1, 0, 0, 1, 0, 0, 0, 0),
 497         AMDGPU_RAS_SUB_BLOCK(UTC_VML2_BANK_CACHE, 0, 1, 1, 1, 0, 0, 0, 0),
 498         AMDGPU_RAS_SUB_BLOCK(UTC_VML2_WALKER, 0, 1, 1, 1, 0, 0, 0, 0),
 499         AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK, 1, 0, 0, 1, 0, 0, 0, 0),
 500         AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK, 0, 1, 1, 1, 0, 0, 0, 0),
 501 };
 502
 503 static const struct soc15_reg_golden golden_settings_gc_9_0[] =
 504 {
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000)
 525 };
 526
 527 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
 528 {
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
 547 };
 548
 549 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] =
 550 {
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000)
 562 };
 563
 564 static const struct soc15_reg_golden golden_settings_gc_9_1[] =
 565 {
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000)
 590 };
 591
 592 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] =
 593 {
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800)
 601 };
 602
 603 static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] =
 604 {
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
 624 };
 625
 626 static const struct soc15_reg_golden golden_settings_gc_9_1_rn[] =
 627 {
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x24000042),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x24000042),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_PROBE_MAP, 0xffffffff, 0x0000cccc),
 640 };
 641
 642 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] =
 643 {
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0xffffffff, 0x000001ff),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382)
 647 };
 648
 649 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] =
 650 {
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
 667 };
 668
 669 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] =
 670 {
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000)
 684 };
 685
 686 static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] =
 687 {
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x10b0000),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_0_ARCT, 0x3fffffff, 0x346f0a4e),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_1_ARCT, 0x3fffffff, 0x1c642ca),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_2_ARCT, 0x3fffffff, 0x26f45098),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00),
 698 };
 699
 700 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
 701 {
 702         mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 703         mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 704         mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 705         mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 706         mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 707         mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 708         mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 709         mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 710 };
 711
 712 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
 713 {
 714         mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 715         mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 716         mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 717         mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 718         mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 719         mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 720         mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 721         mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 722 };
 723
 724 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
 725 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041
 726 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
 727 #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041
 728
 729 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
 730 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
 731 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
 732 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
 733 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
 734                                  struct amdgpu_cu_info *cu_info);
 735 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 736 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
 737 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
 738 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring);
 739 static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
 740                                           void *ras_error_status);
 741 static void gfx_v9_0_clear_ras_edc_counter(struct amdgpu_device *adev);
 742 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
 743                                      void *inject_if);
 744
 745 static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring,
 746                                 uint64_t queue_mask)
 747 {
 748         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
 749         amdgpu_ring_write(kiq_ring,
 750                 PACKET3_SET_RESOURCES_VMID_MASK(0) |
 751                 /* vmid_mask:0* queue_type:0 (KIQ) */
 752                 PACKET3_SET_RESOURCES_QUEUE_TYPE(0));
 753         amdgpu_ring_write(kiq_ring,
 754                         lower_32_bits(queue_mask));     /* queue mask lo */
 755         amdgpu_ring_write(kiq_ring,
 756                         upper_32_bits(queue_mask));     /* queue mask hi */
 757         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
 758         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
 759         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
 760         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
 761 }
 762
 763 static void gfx_v9_0_kiq_map_queues(struct amdgpu_ring *kiq_ring,
 764                                  struct amdgpu_ring *ring)
 765 {
 766         struct amdgpu_device *adev = kiq_ring->adev;
 767         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
 768         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 769         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 770
 771         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
 772         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
 773         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 774                          PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
 775                          PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
 776                          PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
 777                          PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
 778                          PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
 779                          /*queue_type: normal compute queue */
 780                          PACKET3_MAP_QUEUES_QUEUE_TYPE(0) |
 781                          /* alloc format: all_on_one_pipe */
 782                          PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) |
 783                          PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
 784                          /* num_queues: must be 1 */
 785                          PACKET3_MAP_QUEUES_NUM_QUEUES(1));
 786         amdgpu_ring_write(kiq_ring,
 787                         PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
 788         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
 789         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
 790         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
 791         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
 792 }
 793
 794 static void gfx_v9_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
 795                                    struct amdgpu_ring *ring,
 796                                    enum amdgpu_unmap_queues_action action,
 797                                    u64 gpu_addr, u64 seq)
 798 {
 799         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 800
 801         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
 802         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 803                           PACKET3_UNMAP_QUEUES_ACTION(action) |
 804                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
 805                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
 806                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
 807         amdgpu_ring_write(kiq_ring,
 808                         PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
 809
 810         if (action == PREEMPT_QUEUES_NO_UNMAP) {
 811                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
 812                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
 813                 amdgpu_ring_write(kiq_ring, seq);
 814         } else {
 815                 amdgpu_ring_write(kiq_ring, 0);
 816                 amdgpu_ring_write(kiq_ring, 0);
 817                 amdgpu_ring_write(kiq_ring, 0);
 818         }
 819 }
 820
 821 static void gfx_v9_0_kiq_query_status(struct amdgpu_ring *kiq_ring,
 822                                    struct amdgpu_ring *ring,
 823                                    u64 addr,
 824                                    u64 seq)
 825 {
 826         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 827
 828         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
 829         amdgpu_ring_write(kiq_ring,
 830                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
 831                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
 832                           PACKET3_QUERY_STATUS_COMMAND(2));
 833         /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 834         amdgpu_ring_write(kiq_ring,
 835                         PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
 836                         PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
 837         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
 838         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
 839         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
 840         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
 841 }
 842
 843 static void gfx_v9_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
 844                                 uint16_t pasid, uint32_t flush_type,
 845                                 bool all_hub)
 846 {
 847         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
 848         amdgpu_ring_write(kiq_ring,
 849                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
 850                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
 851                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
 852                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
 853 }
 854
 855 static const struct kiq_pm4_funcs gfx_v9_0_kiq_pm4_funcs = {
 856         .kiq_set_resources = gfx_v9_0_kiq_set_resources,
 857         .kiq_map_queues = gfx_v9_0_kiq_map_queues,
 858         .kiq_unmap_queues = gfx_v9_0_kiq_unmap_queues,
 859         .kiq_query_status = gfx_v9_0_kiq_query_status,
 860         .kiq_invalidate_tlbs = gfx_v9_0_kiq_invalidate_tlbs,
 861         .set_resources_size = 8,
 862         .map_queues_size = 7,
 863         .unmap_queues_size = 6,
 864         .query_status_size = 7,
 865         .invalidate_tlbs_size = 2,
 866 };
 867
 868 static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
 869 {
 870         adev->gfx.kiq.pmf = &gfx_v9_0_kiq_pm4_funcs;
 871 }
 872
 873 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
 874 {
 875         switch (adev->asic_type) {
 876         case CHIP_VEGA10:
 877                 soc15_program_register_sequence(adev,
 878                                                 golden_settings_gc_9_0,
 879                                                 ARRAY_SIZE(golden_settings_gc_9_0));
 880                 soc15_program_register_sequence(adev,
 881                                                 golden_settings_gc_9_0_vg10,
 882                                                 ARRAY_SIZE(golden_settings_gc_9_0_vg10));
 883                 break;
 884         case CHIP_VEGA12:
 885                 soc15_program_register_sequence(adev,
 886                                                 golden_settings_gc_9_2_1,
 887                                                 ARRAY_SIZE(golden_settings_gc_9_2_1));
 888                 soc15_program_register_sequence(adev,
 889                                                 golden_settings_gc_9_2_1_vg12,
 890                                                 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12));
 891                 break;
 892         case CHIP_VEGA20:
 893                 soc15_program_register_sequence(adev,
 894                                                 golden_settings_gc_9_0,
 895                                                 ARRAY_SIZE(golden_settings_gc_9_0));
 896                 soc15_program_register_sequence(adev,
 897                                                 golden_settings_gc_9_0_vg20,
 898                                                 ARRAY_SIZE(golden_settings_gc_9_0_vg20));
 899                 break;
 900         case CHIP_ARCTURUS:
 901                 soc15_program_register_sequence(adev,
 902                                                 golden_settings_gc_9_4_1_arct,
 903                                                 ARRAY_SIZE(golden_settings_gc_9_4_1_arct));
 904                 break;
 905         case CHIP_RAVEN:
 906                 soc15_program_register_sequence(adev, golden_settings_gc_9_1,
 907                                                 ARRAY_SIZE(golden_settings_gc_9_1));
 908                 if (adev->rev_id >= 8)
 909                         soc15_program_register_sequence(adev,
 910                                                         golden_settings_gc_9_1_rv2,
 911                                                         ARRAY_SIZE(golden_settings_gc_9_1_rv2));
 912                 else
 913                         soc15_program_register_sequence(adev,
 914                                                         golden_settings_gc_9_1_rv1,
 915                                                         ARRAY_SIZE(golden_settings_gc_9_1_rv1));
 916                 break;
 917          case CHIP_RENOIR:
 918                 soc15_program_register_sequence(adev,
 919                                                 golden_settings_gc_9_1_rn,
 920                                                 ARRAY_SIZE(golden_settings_gc_9_1_rn));
 921                 return; /* for renoir, don't need common goldensetting */
 922         default:
 923                 break;
 924         }
 925
 926         if (adev->asic_type != CHIP_ARCTURUS)
 927                 soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
 928                                                 (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
 929 }
 930
 931 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
 932 {
 933         adev->gfx.scratch.num_reg = 8;
 934         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
 935         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
 936 }
 937
 938 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 939                                        bool wc, uint32_t reg, uint32_t val)
 940 {
 941         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 942         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 943                                 WRITE_DATA_DST_SEL(0) |
 944                                 (wc ? WR_CONFIRM : 0));
 945         amdgpu_ring_write(ring, reg);
 946         amdgpu_ring_write(ring, 0);
 947         amdgpu_ring_write(ring, val);
 948 }
 949
 950 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 951                                   int mem_space, int opt, uint32_t addr0,
 952                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 953                                   uint32_t inv)
 954 {
 955         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 956         amdgpu_ring_write(ring,
 957                                  /* memory (1) or register (0) */
 958                                  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 959                                  WAIT_REG_MEM_OPERATION(opt) | /* wait */
 960                                  WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 961                                  WAIT_REG_MEM_ENGINE(eng_sel)));
 962
 963         if (mem_space)
 964                 BUG_ON(addr0 & 0x3); /* Dword align */
 965         amdgpu_ring_write(ring, addr0);
 966         amdgpu_ring_write(ring, addr1);
 967         amdgpu_ring_write(ring, ref);
 968         amdgpu_ring_write(ring, mask);
 969         amdgpu_ring_write(ring, inv); /* poll interval */
 970 }
 971
 972 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
 973 {
 974         struct amdgpu_device *adev = ring->adev;
 975         uint32_t scratch;
 976         uint32_t tmp = 0;
 977         unsigned i;
 978         int r;
 979
 980         r = amdgpu_gfx_scratch_get(adev, &scratch);
 981         if (r)
 982                 return r;
 983
 984         WREG32(scratch, 0xCAFEDEAD);
 985         r = amdgpu_ring_alloc(ring, 3);
 986         if (r)
 987                 goto error_free_scratch;
 988
 989         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 990         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 991         amdgpu_ring_write(ring, 0xDEADBEEF);
 992         amdgpu_ring_commit(ring);
 993
 994         for (i = 0; i < adev->usec_timeout; i++) {
 995                 tmp = RREG32(scratch);
 996                 if (tmp == 0xDEADBEEF)
 997                         break;
 998                 udelay(1);
 999         }
1000
1001         if (i >= adev->usec_timeout)
1002                 r = -ETIMEDOUT;
1003
1004 error_free_scratch:
1005         amdgpu_gfx_scratch_free(adev, scratch);
1006         return r;
1007 }
1008
1009 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1010 {
1011         struct amdgpu_device *adev = ring->adev;
1012         struct amdgpu_ib ib;
1013         struct dma_fence *f = NULL;
1014
1015         unsigned index;
1016         uint64_t gpu_addr;
1017         uint32_t tmp;
1018         long r;
1019
1020         r = amdgpu_device_wb_get(adev, &index);
1021         if (r)
1022                 return r;
1023
1024         gpu_addr = adev->wb.gpu_addr + (index * 4);
1025         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
1026         memset(&ib, 0, sizeof(ib));
1027         r = amdgpu_ib_get(adev, NULL, 16, &ib);
1028         if (r)
1029                 goto err1;
1030
1031         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
1032         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
1033         ib.ptr[2] = lower_32_bits(gpu_addr);
1034         ib.ptr[3] = upper_32_bits(gpu_addr);
1035         ib.ptr[4] = 0xDEADBEEF;
1036         ib.length_dw = 5;
1037
1038         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1039         if (r)
1040                 goto err2;
1041
1042         r = dma_fence_wait_timeout(f, false, timeout);
1043         if (r == 0) {
1044                 r = -ETIMEDOUT;
1045                 goto err2;
1046         } else if (r < 0) {
1047                 goto err2;
1048         }
1049
1050         tmp = adev->wb.wb[index];
1051         if (tmp == 0xDEADBEEF)
1052                 r = 0;
1053         else
1054                 r = -EINVAL;
1055
1056 err2:
1057         amdgpu_ib_free(adev, &ib, NULL);
1058         dma_fence_put(f);
1059 err1:
1060         amdgpu_device_wb_free(adev, index);
1061         return r;
1062 }
1063
1064
1065 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev)
1066 {
1067         release_firmware(adev->gfx.pfp_fw);
1068         adev->gfx.pfp_fw = NULL;
1069         release_firmware(adev->gfx.me_fw);
1070         adev->gfx.me_fw = NULL;
1071         release_firmware(adev->gfx.ce_fw);
1072         adev->gfx.ce_fw = NULL;
1073         release_firmware(adev->gfx.rlc_fw);
1074         adev->gfx.rlc_fw = NULL;
1075         release_firmware(adev->gfx.mec_fw);
1076         adev->gfx.mec_fw = NULL;
1077         release_firmware(adev->gfx.mec2_fw);
1078         adev->gfx.mec2_fw = NULL;
1079
1080         kfree(adev->gfx.rlc.register_list_format);
1081 }
1082
1083 static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
1084 {
1085         const struct rlc_firmware_header_v2_1 *rlc_hdr;
1086
1087         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
1088         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
1089         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
1090         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
1091         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
1092         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
1093         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
1094         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
1095         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
1096         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
1097         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
1098         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
1099         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
1100         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
1101                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
1102 }
1103
1104 static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
1105 {
1106         adev->gfx.me_fw_write_wait = false;
1107         adev->gfx.mec_fw_write_wait = false;
1108
1109         if ((adev->gfx.mec_fw_version < 0x000001a5) ||
1110             (adev->gfx.mec_feature_version < 46) ||
1111             (adev->gfx.pfp_fw_version < 0x000000b7) ||
1112             (adev->gfx.pfp_feature_version < 46))
1113                 DRM_WARN_ONCE("CP firmware version too old, please update!");
1114
1115         switch (adev->asic_type) {
1116         case CHIP_VEGA10:
1117                 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
1118                     (adev->gfx.me_feature_version >= 42) &&
1119                     (adev->gfx.pfp_fw_version >=  0x000000b1) &&
1120                     (adev->gfx.pfp_feature_version >= 42))
1121                         adev->gfx.me_fw_write_wait = true;
1122
1123                 if ((adev->gfx.mec_fw_version >=  0x00000193) &&
1124                     (adev->gfx.mec_feature_version >= 42))
1125                         adev->gfx.mec_fw_write_wait = true;
1126                 break;
1127         case CHIP_VEGA12:
1128                 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
1129                     (adev->gfx.me_feature_version >= 44) &&
1130                     (adev->gfx.pfp_fw_version >=  0x000000b2) &&
1131                     (adev->gfx.pfp_feature_version >= 44))
1132                         adev->gfx.me_fw_write_wait = true;
1133
1134                 if ((adev->gfx.mec_fw_version >=  0x00000196) &&
1135                     (adev->gfx.mec_feature_version >= 44))
1136                         adev->gfx.mec_fw_write_wait = true;
1137                 break;
1138         case CHIP_VEGA20:
1139                 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
1140                     (adev->gfx.me_feature_version >= 44) &&
1141                     (adev->gfx.pfp_fw_version >=  0x000000b2) &&
1142                     (adev->gfx.pfp_feature_version >= 44))
1143                         adev->gfx.me_fw_write_wait = true;
1144
1145                 if ((adev->gfx.mec_fw_version >=  0x00000197) &&
1146                     (adev->gfx.mec_feature_version >= 44))
1147                         adev->gfx.mec_fw_write_wait = true;
1148                 break;
1149         case CHIP_RAVEN:
1150                 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
1151                     (adev->gfx.me_feature_version >= 42) &&
1152                     (adev->gfx.pfp_fw_version >=  0x000000b1) &&
1153                     (adev->gfx.pfp_feature_version >= 42))
1154                         adev->gfx.me_fw_write_wait = true;
1155
1156                 if ((adev->gfx.mec_fw_version >=  0x00000192) &&
1157                     (adev->gfx.mec_feature_version >= 42))
1158                         adev->gfx.mec_fw_write_wait = true;
1159                 break;
1160         default:
1161                 break;
1162         }
1163 }
1164
1165 struct amdgpu_gfxoff_quirk {
1166         u16 chip_vendor;
1167         u16 chip_device;
1168         u16 subsys_vendor;
1169         u16 subsys_device;
1170         u8 revision;
1171 };
1172
1173 static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = {
1174         /* https://bugzilla.kernel.org/show_bug.cgi?id=204689 */
1175         { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1176         { 0, 0, 0, 0, 0 },
1177 };
1178
1179 static bool gfx_v9_0_should_disable_gfxoff(struct pci_dev *pdev)
1180 {
1181         const struct amdgpu_gfxoff_quirk *p = amdgpu_gfxoff_quirk_list;
1182
1183         while (p && p->chip_device != 0) {
1184                 if (pdev->vendor == p->chip_vendor &&
1185                     pdev->device == p->chip_device &&
1186                     pdev->subsystem_vendor == p->subsys_vendor &&
1187                     pdev->subsystem_device == p->subsys_device &&
1188                     pdev->revision == p->revision) {
1189                         return true;
1190                 }
1191                 ++p;
1192         }
1193         return false;
1194 }
1195
1196 static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
1197 {
1198         if (gfx_v9_0_should_disable_gfxoff(adev->pdev))
1199                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
1200
1201         switch (adev->asic_type) {
1202         case CHIP_VEGA10:
1203         case CHIP_VEGA12:
1204         case CHIP_VEGA20:
1205                 break;
1206         case CHIP_RAVEN:
1207                 if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8) &&
1208                     ((adev->gfx.rlc_fw_version != 106 &&
1209                       adev->gfx.rlc_fw_version < 531) ||
1210                      (adev->gfx.rlc_fw_version == 53815) ||
1211                      (adev->gfx.rlc_feature_version < 1) ||
1212                      !adev->gfx.rlc.is_rlc_v2_1))
1213                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
1214
1215                 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
1216                         adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
1217                                 AMD_PG_SUPPORT_CP |
1218                                 AMD_PG_SUPPORT_RLC_SMU_HS;
1219                 break;
1220         case CHIP_RENOIR:
1221                 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
1222                         adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
1223                                 AMD_PG_SUPPORT_CP |
1224                                 AMD_PG_SUPPORT_RLC_SMU_HS;
1225                 break;
1226         default:
1227                 break;
1228         }
1229 }
1230
1231 static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev,
1232                                           const char *chip_name)
1233 {
1234         char fw_name[30];
1235         int err;
1236         struct amdgpu_firmware_info *info = NULL;
1237         const struct common_firmware_header *header = NULL;
1238         const struct gfx_firmware_header_v1_0 *cp_hdr;
1239
1240         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
1241         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
1242         if (err)
1243                 goto out;
1244         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
1245         if (err)
1246                 goto out;
1247         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1248         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1249         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1250
1251         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
1252         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
1253         if (err)
1254                 goto out;
1255         err = amdgpu_ucode_validate(adev->gfx.me_fw);
1256         if (err)
1257                 goto out;
1258         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1259         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1260         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1261
1262         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
1263         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
1264         if (err)
1265                 goto out;
1266         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
1267         if (err)
1268                 goto out;
1269         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1270         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1271         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1272
1273         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1274                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
1275                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
1276                 info->fw = adev->gfx.pfp_fw;
1277                 header = (const struct common_firmware_header *)info->fw->data;
1278                 adev->firmware.fw_size +=
1279                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1280
1281                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
1282                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
1283                 info->fw = adev->gfx.me_fw;
1284                 header = (const struct common_firmware_header *)info->fw->data;
1285                 adev->firmware.fw_size +=
1286                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1287
1288                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
1289                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
1290                 info->fw = adev->gfx.ce_fw;
1291                 header = (const struct common_firmware_header *)info->fw->data;
1292                 adev->firmware.fw_size +=
1293                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1294         }
1295
1296 out:
1297         if (err) {
1298                 dev_err(adev->dev,
1299                         "gfx9: Failed to load firmware \"%s\"\n",
1300                         fw_name);
1301                 release_firmware(adev->gfx.pfp_fw);
1302                 adev->gfx.pfp_fw = NULL;
1303                 release_firmware(adev->gfx.me_fw);
1304                 adev->gfx.me_fw = NULL;
1305                 release_firmware(adev->gfx.ce_fw);
1306                 adev->gfx.ce_fw = NULL;
1307         }
1308         return err;
1309 }
1310
1311 static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev,
1312                                           const char *chip_name)
1313 {
1314         char fw_name[30];
1315         int err;
1316         struct amdgpu_firmware_info *info = NULL;
1317         const struct common_firmware_header *header = NULL;
1318         const struct rlc_firmware_header_v2_0 *rlc_hdr;
1319         unsigned int *tmp = NULL;
1320         unsigned int i = 0;
1321         uint16_t version_major;
1322         uint16_t version_minor;
1323         uint32_t smu_version;
1324
1325         /*
1326          * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin
1327          * instead of picasso_rlc.bin.
1328          * Judgment method:
1329          * PCO AM4: revision >= 0xC8 && revision <= 0xCF
1330          *          or revision >= 0xD8 && revision <= 0xDF
1331          * otherwise is PCO FP5
1332          */
1333         if (!strcmp(chip_name, "picasso") &&
1334                 (((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) ||
1335                 ((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF))))
1336                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name);
1337         else if (!strcmp(chip_name, "raven") && (amdgpu_pm_load_smu_firmware(adev, &smu_version) == 0) &&
1338                 (smu_version >= 0x41e2b))
1339                 /**
1340                 *SMC is loaded by SBIOS on APU and it's able to get the SMU version directly.
1341                 */
1342                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_kicker_rlc.bin", chip_name);
1343         else
1344                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
1345         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
1346         if (err)
1347                 goto out;
1348         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
1349         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1350
1351         version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
1352         version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
1353         if (version_major == 2 && version_minor == 1)
1354                 adev->gfx.rlc.is_rlc_v2_1 = true;
1355
1356         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
1357         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
1358         adev->gfx.rlc.save_and_restore_offset =
1359                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
1360         adev->gfx.rlc.clear_state_descriptor_offset =
1361                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
1362         adev->gfx.rlc.avail_scratch_ram_locations =
1363                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
1364         adev->gfx.rlc.reg_restore_list_size =
1365                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
1366         adev->gfx.rlc.reg_list_format_start =
1367                         le32_to_cpu(rlc_hdr->reg_list_format_start);
1368         adev->gfx.rlc.reg_list_format_separate_start =
1369                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
1370         adev->gfx.rlc.starting_offsets_start =
1371                         le32_to_cpu(rlc_hdr->starting_offsets_start);
1372         adev->gfx.rlc.reg_list_format_size_bytes =
1373                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
1374         adev->gfx.rlc.reg_list_size_bytes =
1375                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
1376         adev->gfx.rlc.register_list_format =
1377                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
1378                                 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
1379         if (!adev->gfx.rlc.register_list_format) {
1380                 err = -ENOMEM;
1381                 goto out;
1382         }
1383
1384         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1385                         le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
1386         for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++)
1387                 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
1388
1389         adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
1390
1391         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1392                         le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
1393         for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++)
1394                 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
1395
1396         if (adev->gfx.rlc.is_rlc_v2_1)
1397                 gfx_v9_0_init_rlc_ext_microcode(adev);
1398
1399         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1400                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
1401                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
1402                 info->fw = adev->gfx.rlc_fw;
1403                 header = (const struct common_firmware_header *)info->fw->data;
1404                 adev->firmware.fw_size +=
1405                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1406
1407                 if (adev->gfx.rlc.is_rlc_v2_1 &&
1408                     adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
1409                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
1410                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
1411                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
1412                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
1413                         info->fw = adev->gfx.rlc_fw;
1414                         adev->firmware.fw_size +=
1415                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
1416
1417                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
1418                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
1419                         info->fw = adev->gfx.rlc_fw;
1420                         adev->firmware.fw_size +=
1421                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
1422
1423                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
1424                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
1425                         info->fw = adev->gfx.rlc_fw;
1426                         adev->firmware.fw_size +=
1427                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
1428                 }
1429         }
1430
1431 out:
1432         if (err) {
1433                 dev_err(adev->dev,
1434                         "gfx9: Failed to load firmware \"%s\"\n",
1435                         fw_name);
1436                 release_firmware(adev->gfx.rlc_fw);
1437                 adev->gfx.rlc_fw = NULL;
1438         }
1439         return err;
1440 }
1441
1442 static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev,
1443                                           const char *chip_name)
1444 {
1445         char fw_name[30];
1446         int err;
1447         struct amdgpu_firmware_info *info = NULL;
1448         const struct common_firmware_header *header = NULL;
1449         const struct gfx_firmware_header_v1_0 *cp_hdr;
1450
1451         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1452         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1453         if (err)
1454                 goto out;
1455         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
1456         if (err)
1457                 goto out;
1458         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1459         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1460         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1461
1462
1463         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1464         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1465         if (!err) {
1466                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
1467                 if (err)
1468                         goto out;
1469                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1470                 adev->gfx.mec2_fw->data;
1471                 adev->gfx.mec2_fw_version =
1472                 le32_to_cpu(cp_hdr->header.ucode_version);
1473                 adev->gfx.mec2_feature_version =
1474                 le32_to_cpu(cp_hdr->ucode_feature_version);
1475         } else {
1476                 err = 0;
1477                 adev->gfx.mec2_fw = NULL;
1478         }
1479
1480         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1481                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
1482                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
1483                 info->fw = adev->gfx.mec_fw;
1484                 header = (const struct common_firmware_header *)info->fw->data;
1485                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
1486                 adev->firmware.fw_size +=
1487                         ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
1488
1489                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
1490                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
1491                 info->fw = adev->gfx.mec_fw;
1492                 adev->firmware.fw_size +=
1493                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
1494
1495                 if (adev->gfx.mec2_fw) {
1496                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
1497                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
1498                         info->fw = adev->gfx.mec2_fw;
1499                         header = (const struct common_firmware_header *)info->fw->data;
1500                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
1501                         adev->firmware.fw_size +=
1502                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
1503
1504                         /* TODO: Determine if MEC2 JT FW loading can be removed
1505                                  for all GFX V9 asic and above */
1506                         if (adev->asic_type != CHIP_ARCTURUS &&
1507                             adev->asic_type != CHIP_RENOIR) {
1508                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
1509                                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
1510                                 info->fw = adev->gfx.mec2_fw;
1511                                 adev->firmware.fw_size +=
1512                                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
1513                                         PAGE_SIZE);
1514                         }
1515                 }
1516         }
1517
1518 out:
1519         gfx_v9_0_check_if_need_gfxoff(adev);
1520         gfx_v9_0_check_fw_write_wait(adev);
1521         if (err) {
1522                 dev_err(adev->dev,
1523                         "gfx9: Failed to load firmware \"%s\"\n",
1524                         fw_name);
1525                 release_firmware(adev->gfx.mec_fw);
1526                 adev->gfx.mec_fw = NULL;
1527                 release_firmware(adev->gfx.mec2_fw);
1528                 adev->gfx.mec2_fw = NULL;
1529         }
1530         return err;
1531 }
1532
1533 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
1534 {
1535         const char *chip_name;
1536         int r;
1537
1538         DRM_DEBUG("\n");
1539
1540         switch (adev->asic_type) {
1541         case CHIP_VEGA10:
1542                 chip_name = "vega10";
1543                 break;
1544         case CHIP_VEGA12:
1545                 chip_name = "vega12";
1546                 break;
1547         case CHIP_VEGA20:
1548                 chip_name = "vega20";
1549                 break;
1550         case CHIP_RAVEN:
1551                 if (adev->rev_id >= 8)
1552                         chip_name = "raven2";
1553                 else if (adev->pdev->device == 0x15d8)
1554                         chip_name = "picasso";
1555                 else
1556                         chip_name = "raven";
1557                 break;
1558         case CHIP_ARCTURUS:
1559                 chip_name = "arcturus";
1560                 break;
1561         case CHIP_RENOIR:
1562                 chip_name = "renoir";
1563                 break;
1564         default:
1565                 BUG();
1566         }
1567
1568         /* No CPG in Arcturus */
1569         if (adev->asic_type != CHIP_ARCTURUS) {
1570                 r = gfx_v9_0_init_cp_gfx_microcode(adev, chip_name);
1571                 if (r)
1572                         return r;
1573         }
1574
1575         r = gfx_v9_0_init_rlc_microcode(adev, chip_name);
1576         if (r)
1577                 return r;
1578
1579         r = gfx_v9_0_init_cp_compute_microcode(adev, chip_name);
1580         if (r)
1581                 return r;
1582
1583         return r;
1584 }
1585
1586 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
1587 {
1588         u32 count = 0;
1589         const struct cs_section_def *sect = NULL;
1590         const struct cs_extent_def *ext = NULL;
1591
1592         /* begin clear state */
1593         count += 2;
1594         /* context control state */
1595         count += 3;
1596
1597         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
1598                 for (ext = sect->section; ext->extent != NULL; ++ext) {
1599                         if (sect->id == SECT_CONTEXT)
1600                                 count += 2 + ext->reg_count;
1601                         else
1602                                 return 0;
1603                 }
1604         }
1605
1606         /* end clear state */
1607         count += 2;
1608         /* clear state */
1609         count += 2;
1610
1611         return count;
1612 }
1613
1614 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
1615                                     volatile u32 *buffer)
1616 {
1617         u32 count = 0, i;
1618         const struct cs_section_def *sect = NULL;
1619         const struct cs_extent_def *ext = NULL;
1620
1621         if (adev->gfx.rlc.cs_data == NULL)
1622                 return;
1623         if (buffer == NULL)
1624                 return;
1625
1626         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1627         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1628
1629         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1630         buffer[count++] = cpu_to_le32(0x80000000);
1631         buffer[count++] = cpu_to_le32(0x80000000);
1632
1633         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1634                 for (ext = sect->section; ext->extent != NULL; ++ext) {
1635                         if (sect->id == SECT_CONTEXT) {
1636                                 buffer[count++] =
1637                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1638                                 buffer[count++] = cpu_to_le32(ext->reg_index -
1639                                                 PACKET3_SET_CONTEXT_REG_START);
1640                                 for (i = 0; i < ext->reg_count; i++)
1641                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
1642                         } else {
1643                                 return;
1644                         }
1645                 }
1646         }
1647
1648         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1649         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
1650
1651         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
1652         buffer[count++] = cpu_to_le32(0);
1653 }
1654
1655 static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev)
1656 {
1657         struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
1658         uint32_t pg_always_on_cu_num = 2;
1659         uint32_t always_on_cu_num;
1660         uint32_t i, j, k;
1661         uint32_t mask, cu_bitmap, counter;
1662
1663         if (adev->flags & AMD_IS_APU)
1664                 always_on_cu_num = 4;
1665         else if (adev->asic_type == CHIP_VEGA12)
1666                 always_on_cu_num = 8;
1667         else
1668                 always_on_cu_num = 12;
1669
1670         mutex_lock(&adev->grbm_idx_mutex);
1671         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1672                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1673                         mask = 1;
1674                         cu_bitmap = 0;
1675                         counter = 0;
1676                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1677
1678                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
1679                                 if (cu_info->bitmap[i][j] & mask) {
1680                                         if (counter == pg_always_on_cu_num)
1681                                                 WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap);
1682                                         if (counter < always_on_cu_num)
1683                                                 cu_bitmap |= mask;
1684                                         else
1685                                                 break;
1686                                         counter++;
1687                                 }
1688                                 mask <<= 1;
1689                         }
1690
1691                         WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, cu_bitmap);
1692                         cu_info->ao_cu_bitmap[i][j] = cu_bitmap;
1693                 }
1694         }
1695         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1696         mutex_unlock(&adev->grbm_idx_mutex);
1697 }
1698
1699 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
1700 {
1701         uint32_t data;
1702
1703         /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
1704         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
1705         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
1706         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
1707         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
1708
1709         /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
1710         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
1711
1712         /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
1713         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
1714
1715         mutex_lock(&adev->grbm_idx_mutex);
1716         /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
1717         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1718         WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
1719
1720         /* set mmRLC_LB_PARAMS = 0x003F_1006 */
1721         data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
1722         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
1723         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
1724         WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
1725
1726         /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
1727         data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
1728         data &= 0x0000FFFF;
1729         data |= 0x00C00000;
1730         WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
1731
1732         /*
1733          * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xF (4 CUs AON for Raven),
1734          * programmed in gfx_v9_0_init_always_on_cu_mask()
1735          */
1736
1737         /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
1738          * but used for RLC_LB_CNTL configuration */
1739         data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
1740         data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
1741         data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
1742         WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
1743         mutex_unlock(&adev->grbm_idx_mutex);
1744
1745         gfx_v9_0_init_always_on_cu_mask(adev);
1746 }
1747
1748 static void gfx_v9_4_init_lbpw(struct amdgpu_device *adev)
1749 {
1750         uint32_t data;
1751
1752         /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
1753         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
1754         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x033388F8);
1755         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
1756         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 | 0x27 << 8 | 0x02FA << 16));
1757
1758         /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
1759         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
1760
1761         /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
1762         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800);
1763
1764         mutex_lock(&adev->grbm_idx_mutex);
1765         /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
1766         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1767         WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
1768
1769         /* set mmRLC_LB_PARAMS = 0x003F_1006 */
1770         data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
1771         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
1772         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
1773         WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
1774
1775         /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
1776         data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
1777         data &= 0x0000FFFF;
1778         data |= 0x00C00000;
1779         WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
1780
1781         /*
1782          * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF (12 CUs AON),
1783          * programmed in gfx_v9_0_init_always_on_cu_mask()
1784          */
1785
1786         /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
1787          * but used for RLC_LB_CNTL configuration */
1788         data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
1789         data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
1790         data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
1791         WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
1792         mutex_unlock(&adev->grbm_idx_mutex);
1793
1794         gfx_v9_0_init_always_on_cu_mask(adev);
1795 }
1796
1797 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
1798 {
1799         WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
1800 }
1801
1802 static int gfx_v9_0_cp_jump_table_num(struct amdgpu_device *adev)
1803 {
1804         return 5;
1805 }
1806
1807 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
1808 {
1809         const struct cs_section_def *cs_data;
1810         int r;
1811
1812         adev->gfx.rlc.cs_data = gfx9_cs_data;
1813
1814         cs_data = adev->gfx.rlc.cs_data;
1815
1816         if (cs_data) {
1817                 /* init clear state block */
1818                 r = amdgpu_gfx_rlc_init_csb(adev);
1819                 if (r)
1820                         return r;
1821         }
1822
1823         if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR) {
1824                 /* TODO: double check the cp_table_size for RV */
1825                 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
1826                 r = amdgpu_gfx_rlc_init_cpt(adev);
1827                 if (r)
1828                         return r;
1829         }
1830
1831         switch (adev->asic_type) {
1832         case CHIP_RAVEN:
1833                 gfx_v9_0_init_lbpw(adev);
1834                 break;
1835         case CHIP_VEGA20:
1836                 gfx_v9_4_init_lbpw(adev);
1837                 break;
1838         default:
1839                 break;
1840         }
1841
1842         return 0;
1843 }
1844
1845 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
1846 {
1847         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1848         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
1849 }
1850
1851 static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
1852 {
1853         int r;
1854         u32 *hpd;
1855         const __le32 *fw_data;
1856         unsigned fw_size;
1857         u32 *fw;
1858         size_t mec_hpd_size;
1859
1860         const struct gfx_firmware_header_v1_0 *mec_hdr;
1861
1862         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1863
1864         /* take ownership of the relevant compute queues */
1865         amdgpu_gfx_compute_queue_acquire(adev);
1866         mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
1867
1868         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1869                                       AMDGPU_GEM_DOMAIN_VRAM,
1870                                       &adev->gfx.mec.hpd_eop_obj,
1871                                       &adev->gfx.mec.hpd_eop_gpu_addr,
1872                                       (void **)&hpd);
1873         if (r) {
1874                 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1875                 gfx_v9_0_mec_fini(adev);
1876                 return r;
1877         }
1878
1879         memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
1880
1881         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1882         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1883
1884         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1885
1886         fw_data = (const __le32 *)
1887                 (adev->gfx.mec_fw->data +
1888                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1889         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
1890
1891         r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
1892                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1893                                       &adev->gfx.mec.mec_fw_obj,
1894                                       &adev->gfx.mec.mec_fw_gpu_addr,
1895                                       (void **)&fw);
1896         if (r) {
1897                 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
1898                 gfx_v9_0_mec_fini(adev);
1899                 return r;
1900         }
1901
1902         memcpy(fw, fw_data, fw_size);
1903
1904         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
1905         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
1906
1907         return 0;
1908 }
1909
1910 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
1911 {
1912         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1913                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1914                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1915                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
1916                 (SQ_IND_INDEX__FORCE_READ_MASK));
1917         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1918 }
1919
1920 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
1921                            uint32_t wave, uint32_t thread,
1922                            uint32_t regno, uint32_t num, uint32_t *out)
1923 {
1924         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1925                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1926                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1927                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
1928                 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
1929                 (SQ_IND_INDEX__FORCE_READ_MASK) |
1930                 (SQ_IND_INDEX__AUTO_INCR_MASK));
1931         while (num--)
1932                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1933 }
1934
1935 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1936 {
1937         /* type 1 wave data */
1938         dst[(*no_fields)++] = 1;
1939         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
1940         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
1941         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
1942         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
1943         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
1944         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
1945         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
1946         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
1947         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
1948         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
1949         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
1950         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
1951         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
1952         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
1953 }
1954
1955 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1956                                      uint32_t wave, uint32_t start,
1957                                      uint32_t size, uint32_t *dst)
1958 {
1959         wave_read_regs(
1960                 adev, simd, wave, 0,
1961                 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
1962 }
1963
1964 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
1965                                      uint32_t wave, uint32_t thread,
1966                                      uint32_t start, uint32_t size,
1967                                      uint32_t *dst)
1968 {
1969         wave_read_regs(
1970                 adev, simd, wave, thread,
1971                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1972 }
1973
1974 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev,
1975                                   u32 me, u32 pipe, u32 q, u32 vm)
1976 {
1977         soc15_grbm_select(adev, me, pipe, q, vm);
1978 }
1979
1980 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
1981         .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
1982         .select_se_sh = &gfx_v9_0_select_se_sh,
1983         .read_wave_data = &gfx_v9_0_read_wave_data,
1984         .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
1985         .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
1986         .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q,
1987         .ras_error_inject = &gfx_v9_0_ras_error_inject,
1988         .query_ras_error_count = &gfx_v9_0_query_ras_error_count
1989 };
1990
1991 static const struct amdgpu_gfx_funcs gfx_v9_4_gfx_funcs = {
1992         .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
1993         .select_se_sh = &gfx_v9_0_select_se_sh,
1994         .read_wave_data = &gfx_v9_0_read_wave_data,
1995         .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
1996         .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
1997         .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q,
1998         .ras_error_inject = &gfx_v9_4_ras_error_inject,
1999         .query_ras_error_count = &gfx_v9_4_query_ras_error_count
2000 };
2001
2002 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
2003 {
2004         u32 gb_addr_config;
2005         int err;
2006
2007         adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
2008
2009         switch (adev->asic_type) {
2010         case CHIP_VEGA10:
2011                 adev->gfx.config.max_hw_contexts = 8;
2012                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2013                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2014                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2015                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
2016                 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
2017                 break;
2018         case CHIP_VEGA12:
2019                 adev->gfx.config.max_hw_contexts = 8;
2020                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2021                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2022                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2023                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
2024                 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN;
2025                 DRM_INFO("fix gfx.config for vega12\n");
2026                 break;
2027         case CHIP_VEGA20:
2028                 adev->gfx.config.max_hw_contexts = 8;
2029                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2030                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2031                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2032                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
2033                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
2034                 gb_addr_config &= ~0xf3e777ff;
2035                 gb_addr_config |= 0x22014042;
2036                 /* check vbios table if gpu info is not available */
2037                 err = amdgpu_atomfirmware_get_gfx_info(adev);
2038                 if (err)
2039                         return err;
2040                 break;
2041         case CHIP_RAVEN:
2042                 adev->gfx.config.max_hw_contexts = 8;
2043                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2044                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2045                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2046                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
2047                 if (adev->rev_id >= 8)
2048                         gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN;
2049                 else
2050                         gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
2051                 break;
2052         case CHIP_ARCTURUS:
2053                 adev->gfx.funcs = &gfx_v9_4_gfx_funcs;
2054                 adev->gfx.config.max_hw_contexts = 8;
2055                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2056                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2057                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2058                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
2059                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
2060                 gb_addr_config &= ~0xf3e777ff;
2061                 gb_addr_config |= 0x22014042;
2062                 break;
2063         case CHIP_RENOIR:
2064                 adev->gfx.config.max_hw_contexts = 8;
2065                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2066                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2067                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80;
2068                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
2069                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
2070                 gb_addr_config &= ~0xf3e777ff;
2071                 gb_addr_config |= 0x22010042;
2072                 break;
2073         default:
2074                 BUG();
2075                 break;
2076         }
2077
2078         adev->gfx.config.gb_addr_config = gb_addr_config;
2079
2080         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
2081                         REG_GET_FIELD(
2082                                         adev->gfx.config.gb_addr_config,
2083                                         GB_ADDR_CONFIG,
2084                                         NUM_PIPES);
2085
2086         adev->gfx.config.max_tile_pipes =
2087                 adev->gfx.config.gb_addr_config_fields.num_pipes;
2088
2089         adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
2090                         REG_GET_FIELD(
2091                                         adev->gfx.config.gb_addr_config,
2092                                         GB_ADDR_CONFIG,
2093                                         NUM_BANKS);
2094         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
2095                         REG_GET_FIELD(
2096                                         adev->gfx.config.gb_addr_config,
2097                                         GB_ADDR_CONFIG,
2098                                         MAX_COMPRESSED_FRAGS);
2099         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
2100                         REG_GET_FIELD(
2101                                         adev->gfx.config.gb_addr_config,
2102                                         GB_ADDR_CONFIG,
2103                                         NUM_RB_PER_SE);
2104         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
2105                         REG_GET_FIELD(
2106                                         adev->gfx.config.gb_addr_config,
2107                                         GB_ADDR_CONFIG,
2108                                         NUM_SHADER_ENGINES);
2109         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
2110                         REG_GET_FIELD(
2111                                         adev->gfx.config.gb_addr_config,
2112                                         GB_ADDR_CONFIG,
2113                                         PIPE_INTERLEAVE_SIZE));
2114
2115         return 0;
2116 }
2117
2118 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
2119                                       int mec, int pipe, int queue)
2120 {
2121         int r;
2122         unsigned irq_type;
2123         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
2124
2125         ring = &adev->gfx.compute_ring[ring_id];
2126
2127         /* mec0 is me1 */
2128         ring->me = mec + 1;
2129         ring->pipe = pipe;
2130         ring->queue = queue;
2131
2132         ring->ring_obj = NULL;
2133         ring->use_doorbell = true;
2134         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
2135         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
2136                                 + (ring_id * GFX9_MEC_HPD_SIZE);
2137         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
2138
2139         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
2140                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
2141                 + ring->pipe;
2142
2143         /* type-2 packets are deprecated on MEC, use type-3 instead */
2144         r = amdgpu_ring_init(adev, ring, 1024,
2145                              &adev->gfx.eop_irq, irq_type);
2146         if (r)
2147                 return r;
2148
2149
2150         return 0;
2151 }
2152
2153 static int gfx_v9_0_sw_init(void *handle)
2154 {
2155         int i, j, k, r, ring_id;
2156         struct amdgpu_ring *ring;
2157         struct amdgpu_kiq *kiq;
2158         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2159
2160         switch (adev->asic_type) {
2161         case CHIP_VEGA10:
2162         case CHIP_VEGA12:
2163         case CHIP_VEGA20:
2164         case CHIP_RAVEN:
2165         case CHIP_ARCTURUS:
2166         case CHIP_RENOIR:
2167                 adev->gfx.mec.num_mec = 2;
2168                 break;
2169         default:
2170                 adev->gfx.mec.num_mec = 1;
2171                 break;
2172         }
2173
2174         adev->gfx.mec.num_pipe_per_mec = 4;
2175         adev->gfx.mec.num_queue_per_pipe = 8;
2176
2177         /* EOP Event */
2178         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq);
2179         if (r)
2180                 return r;
2181
2182         /* Privileged reg */
2183         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,
2184                               &adev->gfx.priv_reg_irq);
2185         if (r)
2186                 return r;
2187
2188         /* Privileged inst */
2189         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT,
2190                               &adev->gfx.priv_inst_irq);
2191         if (r)
2192                 return r;
2193
2194         /* ECC error */
2195         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_ECC_ERROR,
2196                               &adev->gfx.cp_ecc_error_irq);
2197         if (r)
2198                 return r;
2199
2200         /* FUE error */
2201         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_FUE_ERROR,
2202                               &adev->gfx.cp_ecc_error_irq);
2203         if (r)
2204                 return r;
2205
2206         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
2207
2208         gfx_v9_0_scratch_init(adev);
2209
2210         r = gfx_v9_0_init_microcode(adev);
2211         if (r) {
2212                 DRM_ERROR("Failed to load gfx firmware!\n");
2213                 return r;
2214         }
2215
2216         r = adev->gfx.rlc.funcs->init(adev);
2217         if (r) {
2218                 DRM_ERROR("Failed to init rlc BOs!\n");
2219                 return r;
2220         }
2221
2222         r = gfx_v9_0_mec_init(adev);
2223         if (r) {
2224                 DRM_ERROR("Failed to init MEC BOs!\n");
2225                 return r;
2226         }
2227
2228         /* set up the gfx ring */
2229         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2230                 ring = &adev->gfx.gfx_ring[i];
2231                 ring->ring_obj = NULL;
2232                 if (!i)
2233                         sprintf(ring->name, "gfx");
2234                 else
2235                         sprintf(ring->name, "gfx_%d", i);
2236                 ring->use_doorbell = true;
2237                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
2238                 r = amdgpu_ring_init(adev, ring, 1024,
2239                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP);
2240                 if (r)
2241                         return r;
2242         }
2243
2244         /* set up the compute queues - allocate horizontally across pipes */
2245         ring_id = 0;
2246         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
2247                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
2248                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2249                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
2250                                         continue;
2251
2252                                 r = gfx_v9_0_compute_ring_init(adev,
2253                                                                ring_id,
2254                                                                i, k, j);
2255                                 if (r)
2256                                         return r;
2257
2258                                 ring_id++;
2259                         }
2260                 }
2261         }
2262
2263         r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE);
2264         if (r) {
2265                 DRM_ERROR("Failed to init KIQ BOs!\n");
2266                 return r;
2267         }
2268
2269         kiq = &adev->gfx.kiq;
2270         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
2271         if (r)
2272                 return r;
2273
2274         /* create MQD for all compute queues as wel as KIQ for SRIOV case */
2275         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
2276         if (r)
2277                 return r;
2278
2279         adev->gfx.ce_ram_size = 0x8000;
2280
2281         r = gfx_v9_0_gpu_early_init(adev);
2282         if (r)
2283                 return r;
2284
2285         return 0;
2286 }
2287
2288
2289 static int gfx_v9_0_sw_fini(void *handle)
2290 {
2291         int i;
2292         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2293
2294         amdgpu_gfx_ras_fini(adev);
2295
2296         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2297                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
2298         for (i = 0; i < adev->gfx.num_compute_rings; i++)
2299                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
2300
2301         amdgpu_gfx_mqd_sw_fini(adev);
2302         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
2303         amdgpu_gfx_kiq_fini(adev);
2304
2305         gfx_v9_0_mec_fini(adev);
2306         amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
2307         if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR) {
2308                 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
2309                                 &adev->gfx.rlc.cp_table_gpu_addr,
2310                                 (void **)&adev->gfx.rlc.cp_table_ptr);
2311         }
2312         gfx_v9_0_free_microcode(adev);
2313
2314         return 0;
2315 }
2316
2317
2318 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
2319 {
2320         /* TODO */
2321 }
2322
2323 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
2324 {
2325         u32 data;
2326
2327         if (instance == 0xffffffff)
2328                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
2329         else
2330                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
2331
2332         if (se_num == 0xffffffff)
2333                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
2334         else
2335                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
2336
2337         if (sh_num == 0xffffffff)
2338                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
2339         else
2340                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
2341
2342         WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data);
2343 }
2344
2345 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
2346 {
2347         u32 data, mask;
2348
2349         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
2350         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
2351
2352         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
2353         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
2354
2355         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
2356                                          adev->gfx.config.max_sh_per_se);
2357
2358         return (~data) & mask;
2359 }
2360
2361 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
2362 {
2363         int i, j;
2364         u32 data;
2365         u32 active_rbs = 0;
2366         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
2367                                         adev->gfx.config.max_sh_per_se;
2368
2369         mutex_lock(&adev->grbm_idx_mutex);
2370         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2371                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2372                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
2373                         data = gfx_v9_0_get_rb_active_bitmap(adev);
2374                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
2375                                                rb_bitmap_width_per_sh);
2376                 }
2377         }
2378         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2379         mutex_unlock(&adev->grbm_idx_mutex);
2380
2381         adev->gfx.config.backend_enable_mask = active_rbs;
2382         adev->gfx.config.num_rbs = hweight32(active_rbs);
2383 }
2384
2385 #define DEFAULT_SH_MEM_BASES    (0x6000)
2386 #define FIRST_COMPUTE_VMID      (8)
2387 #define LAST_COMPUTE_VMID       (16)
2388 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
2389 {
2390         int i;
2391         uint32_t sh_mem_config;
2392         uint32_t sh_mem_bases;
2393
2394         /*
2395          * Configure apertures:
2396          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
2397          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
2398          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
2399          */
2400         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
2401
2402         sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
2403                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
2404                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
2405
2406         mutex_lock(&adev->srbm_mutex);
2407         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
2408                 soc15_grbm_select(adev, 0, 0, 0, i);
2409                 /* CP and shaders */
2410                 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
2411                 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
2412         }
2413         soc15_grbm_select(adev, 0, 0, 0, 0);
2414         mutex_unlock(&adev->srbm_mutex);
2415
2416         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
2417            acccess. These should be enabled by FW for target VMIDs. */
2418         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
2419                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
2420                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
2421                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
2422                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
2423         }
2424 }
2425
2426 static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev)
2427 {
2428         int vmid;
2429
2430         /*
2431          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
2432          * access. Compute VMIDs should be enabled by FW for target VMIDs,
2433          * the driver can enable them for graphics. VMID0 should maintain
2434          * access so that HWS firmware can save/restore entries.
2435          */
2436         for (vmid = 1; vmid < 16; vmid++) {
2437                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
2438                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
2439                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
2440                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
2441         }
2442 }
2443
2444 static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev)
2445 {
2446         uint32_t tmp;
2447
2448         switch (adev->asic_type) {
2449         case CHIP_ARCTURUS:
2450                 tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG);
2451                 tmp = REG_SET_FIELD(tmp, SQ_CONFIG,
2452                                         DISABLE_BARRIER_WAITCNT, 1);
2453                 WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp);
2454                 break;
2455         default:
2456                 break;
2457         };
2458 }
2459
2460 static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
2461 {
2462         u32 tmp;
2463         int i;
2464
2465         WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
2466
2467         gfx_v9_0_tiling_mode_table_init(adev);
2468
2469         gfx_v9_0_setup_rb(adev);
2470         gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
2471         adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);
2472
2473         /* XXX SH_MEM regs */
2474         /* where to put LDS, scratch, GPUVM in FSA64 space */
2475         mutex_lock(&adev->srbm_mutex);
2476         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
2477                 soc15_grbm_select(adev, 0, 0, 0, i);
2478                 /* CP and shaders */
2479                 if (i == 0) {
2480                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
2481                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2482                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
2483                                             !!amdgpu_noretry);
2484                         WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp);
2485                         WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0);
2486                 } else {
2487                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
2488                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2489                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
2490                                             !!amdgpu_noretry);
2491                         WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp);
2492                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
2493                                 (adev->gmc.private_aperture_start >> 48));
2494                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
2495                                 (adev->gmc.shared_aperture_start >> 48));
2496                         WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp);
2497                 }
2498         }
2499         soc15_grbm_select(adev, 0, 0, 0, 0);
2500
2501         mutex_unlock(&adev->srbm_mutex);
2502
2503         gfx_v9_0_init_compute_vmid(adev);
2504         gfx_v9_0_init_gds_vmid(adev);
2505         gfx_v9_0_init_sq_config(adev);
2506 }
2507
2508 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2509 {
2510         u32 i, j, k;
2511         u32 mask;
2512
2513         mutex_lock(&adev->grbm_idx_mutex);
2514         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2515                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2516                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
2517                         for (k = 0; k < adev->usec_timeout; k++) {
2518                                 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
2519                                         break;
2520                                 udelay(1);
2521                         }
2522                         if (k == adev->usec_timeout) {
2523                                 gfx_v9_0_select_se_sh(adev, 0xffffffff,
2524                                                       0xffffffff, 0xffffffff);
2525                                 mutex_unlock(&adev->grbm_idx_mutex);
2526                                 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
2527                                          i, j);
2528                                 return;
2529                         }
2530                 }
2531         }
2532         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2533         mutex_unlock(&adev->grbm_idx_mutex);
2534
2535         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
2536                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
2537                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
2538                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
2539         for (k = 0; k < adev->usec_timeout; k++) {
2540                 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
2541                         break;
2542                 udelay(1);
2543         }
2544 }
2545
2546 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2547                                                bool enable)
2548 {
2549         u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
2550
2551         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
2552         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
2553         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
2554         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
2555
2556         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
2557 }
2558
2559 static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
2560 {
2561         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
2562         /* csib */
2563         WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
2564                         adev->gfx.rlc.clear_state_gpu_addr >> 32);
2565         WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
2566                         adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
2567         WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
2568                         adev->gfx.rlc.clear_state_size);
2569 }
2570
2571 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format,
2572                                 int indirect_offset,
2573                                 int list_size,
2574                                 int *unique_indirect_regs,
2575                                 int unique_indirect_reg_count,
2576                                 int *indirect_start_offsets,
2577                                 int *indirect_start_offsets_count,
2578                                 int max_start_offsets_count)
2579 {
2580         int idx;
2581
2582         for (; indirect_offset < list_size; indirect_offset++) {
2583                 WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count);
2584                 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
2585                 *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
2586
2587                 while (register_list_format[indirect_offset] != 0xFFFFFFFF) {
2588                         indirect_offset += 2;
2589
2590                         /* look for the matching indice */
2591                         for (idx = 0; idx < unique_indirect_reg_count; idx++) {
2592                                 if (unique_indirect_regs[idx] ==
2593                                         register_list_format[indirect_offset] ||
2594                                         !unique_indirect_regs[idx])
2595                                         break;
2596                         }
2597
2598                         BUG_ON(idx >= unique_indirect_reg_count);
2599
2600                         if (!unique_indirect_regs[idx])
2601                                 unique_indirect_regs[idx] = register_list_format[indirect_offset];
2602
2603                         indirect_offset++;
2604                 }
2605         }
2606 }
2607
2608 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev)
2609 {
2610         int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
2611         int unique_indirect_reg_count = 0;
2612
2613         int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
2614         int indirect_start_offsets_count = 0;
2615
2616         int list_size = 0;
2617         int i = 0, j = 0;
2618         u32 tmp = 0;
2619
2620         u32 *register_list_format =
2621                 kmemdup(adev->gfx.rlc.register_list_format,
2622                         adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
2623         if (!register_list_format)
2624                 return -ENOMEM;
2625
2626         /* setup unique_indirect_regs array and indirect_start_offsets array */
2627         unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs);
2628         gfx_v9_1_parse_ind_reg_list(register_list_format,
2629                                     adev->gfx.rlc.reg_list_format_direct_reg_list_length,
2630                                     adev->gfx.rlc.reg_list_format_size_bytes >> 2,
2631                                     unique_indirect_regs,
2632                                     unique_indirect_reg_count,
2633                                     indirect_start_offsets,
2634                                     &indirect_start_offsets_count,
2635                                     ARRAY_SIZE(indirect_start_offsets));
2636
2637         /* enable auto inc in case it is disabled */
2638         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
2639         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
2640         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
2641
2642         /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
2643         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
2644                 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
2645         for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
2646                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
2647                         adev->gfx.rlc.register_restore[i]);
2648
2649         /* load indirect register */
2650         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2651                 adev->gfx.rlc.reg_list_format_start);
2652
2653         /* direct register portion */
2654         for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++)
2655                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
2656                         register_list_format[i]);
2657
2658         /* indirect register portion */
2659         while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) {
2660                 if (register_list_format[i] == 0xFFFFFFFF) {
2661                         WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2662                         continue;
2663                 }
2664
2665                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2666                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2667
2668                 for (j = 0; j < unique_indirect_reg_count; j++) {
2669                         if (register_list_format[i] == unique_indirect_regs[j]) {
2670                                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j);
2671                                 break;
2672                         }
2673                 }
2674
2675                 BUG_ON(j >= unique_indirect_reg_count);
2676
2677                 i++;
2678         }
2679
2680         /* set save/restore list size */
2681         list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
2682         list_size = list_size >> 1;
2683         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2684                 adev->gfx.rlc.reg_restore_list_size);
2685         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
2686
2687         /* write the starting offsets to RLC scratch ram */
2688         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2689                 adev->gfx.rlc.starting_offsets_start);
2690         for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
2691                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
2692                        indirect_start_offsets[i]);
2693
2694         /* load unique indirect regs*/
2695         for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) {
2696                 if (unique_indirect_regs[i] != 0) {
2697                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0)
2698                                + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i],
2699                                unique_indirect_regs[i] & 0x3FFFF);
2700
2701                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0)
2702                                + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i],
2703                                unique_indirect_regs[i] >> 20);
2704                 }
2705         }
2706
2707         kfree(register_list_format);
2708         return 0;
2709 }
2710
2711 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
2712 {
2713         WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1);
2714 }
2715
2716 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
2717                                              bool enable)
2718 {
2719         uint32_t data = 0;
2720         uint32_t default_data = 0;
2721
2722         default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
2723         if (enable == true) {
2724                 /* enable GFXIP control over CGPG */
2725                 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2726                 if(default_data != data)
2727                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2728
2729                 /* update status */
2730                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
2731                 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
2732                 if(default_data != data)
2733                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2734         } else {
2735                 /* restore GFXIP control over GCPG */
2736                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2737                 if(default_data != data)
2738                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2739         }
2740 }
2741
2742 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
2743 {
2744         uint32_t data = 0;
2745
2746         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2747                               AMD_PG_SUPPORT_GFX_SMG |
2748                               AMD_PG_SUPPORT_GFX_DMG)) {
2749                 /* init IDLE_POLL_COUNT = 60 */
2750                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2751                 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
2752                 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2753                 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2754
2755                 /* init RLC PG Delay */
2756                 data = 0;
2757                 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
2758                 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
2759                 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
2760                 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
2761                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
2762
2763                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
2764                 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
2765                 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
2766                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
2767
2768                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
2769                 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
2770                 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
2771                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
2772
2773                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
2774                 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2775
2776                 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
2777                 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2778                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
2779
2780                 pwr_10_0_gfxip_control_over_cgpg(adev, true);
2781         }
2782 }
2783
2784 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
2785                                                 bool enable)
2786 {
2787         uint32_t data = 0;
2788         uint32_t default_data = 0;
2789
2790         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2791         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2792                              SMU_CLK_SLOWDOWN_ON_PU_ENABLE,
2793                              enable ? 1 : 0);
2794         if (default_data != data)
2795                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2796 }
2797
2798 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
2799                                                 bool enable)
2800 {
2801         uint32_t data = 0;
2802         uint32_t default_data = 0;
2803
2804         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2805         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2806                              SMU_CLK_SLOWDOWN_ON_PD_ENABLE,
2807                              enable ? 1 : 0);
2808         if(default_data != data)
2809                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2810 }
2811
2812 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
2813                                         bool enable)
2814 {
2815         uint32_t data = 0;
2816         uint32_t default_data = 0;
2817
2818         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2819         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2820                              CP_PG_DISABLE,
2821                              enable ? 0 : 1);
2822         if(default_data != data)
2823                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2824 }
2825
2826 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
2827                                                 bool enable)
2828 {
2829         uint32_t data, default_data;
2830
2831         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2832         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2833                              GFX_POWER_GATING_ENABLE,
2834                              enable ? 1 : 0);
2835         if(default_data != data)
2836                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2837 }
2838
2839 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
2840                                                 bool enable)
2841 {
2842         uint32_t data, default_data;
2843
2844         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2845         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2846                              GFX_PIPELINE_PG_ENABLE,
2847                              enable ? 1 : 0);
2848         if(default_data != data)
2849                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2850
2851         if (!enable)
2852                 /* read any GFX register to wake up GFX */
2853                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
2854 }
2855
2856 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
2857                                                        bool enable)
2858 {
2859         uint32_t data, default_data;
2860
2861         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2862         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2863                              STATIC_PER_CU_PG_ENABLE,
2864                              enable ? 1 : 0);
2865         if(default_data != data)
2866                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2867 }
2868
2869 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
2870                                                 bool enable)
2871 {
2872         uint32_t data, default_data;
2873
2874         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2875         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2876                              DYN_PER_CU_PG_ENABLE,
2877                              enable ? 1 : 0);
2878         if(default_data != data)
2879                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2880 }
2881
2882 static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
2883 {
2884         gfx_v9_0_init_csb(adev);
2885
2886         /*
2887          * Rlc save restore list is workable since v2_1.
2888          * And it's needed by gfxoff feature.
2889          */
2890         if (adev->gfx.rlc.is_rlc_v2_1) {
2891                 if (adev->asic_type == CHIP_VEGA12 ||
2892                     (adev->asic_type == CHIP_RAVEN &&
2893                      adev->rev_id >= 8))
2894                         gfx_v9_1_init_rlc_save_restore_list(adev);
2895                 gfx_v9_0_enable_save_restore_machine(adev);
2896         }
2897
2898         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2899                               AMD_PG_SUPPORT_GFX_SMG |
2900                               AMD_PG_SUPPORT_GFX_DMG |
2901                               AMD_PG_SUPPORT_CP |
2902                               AMD_PG_SUPPORT_GDS |
2903                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
2904                 WREG32(mmRLC_JUMP_TABLE_RESTORE,
2905                        adev->gfx.rlc.cp_table_gpu_addr >> 8);
2906                 gfx_v9_0_init_gfx_power_gating(adev);
2907         }
2908 }
2909
2910 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
2911 {
2912         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);
2913         gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2914         gfx_v9_0_wait_for_rlc_serdes(adev);
2915 }
2916
2917 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
2918 {
2919         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2920         udelay(50);
2921         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2922         udelay(50);
2923 }
2924
2925 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
2926 {
2927 #ifdef AMDGPU_RLC_DEBUG_RETRY
2928         u32 rlc_ucode_ver;
2929 #endif
2930
2931         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
2932         udelay(50);
2933
2934         /* carrizo do enable cp interrupt after cp inited */
2935         if (!(adev->flags & AMD_IS_APU)) {
2936                 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2937                 udelay(50);
2938         }
2939
2940 #ifdef AMDGPU_RLC_DEBUG_RETRY
2941         /* RLC_GPM_GENERAL_6 : RLC Ucode version */
2942         rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
2943         if(rlc_ucode_ver == 0x108) {
2944                 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2945                                 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2946                 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2947                  * default is 0x9C4 to create a 100us interval */
2948                 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
2949                 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
2950                  * to disable the page fault retry interrupts, default is
2951                  * 0x100 (256) */
2952                 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
2953         }
2954 #endif
2955 }
2956
2957 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2958 {
2959         const struct rlc_firmware_header_v2_0 *hdr;
2960         const __le32 *fw_data;
2961         unsigned i, fw_size;
2962
2963         if (!adev->gfx.rlc_fw)
2964                 return -EINVAL;
2965
2966         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2967         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2968
2969         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2970                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2971         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2972
2973         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
2974                         RLCG_UCODE_LOADING_START_ADDRESS);
2975         for (i = 0; i < fw_size; i++)
2976                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2977         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2978
2979         return 0;
2980 }
2981
2982 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2983 {
2984         int r;
2985
2986         if (amdgpu_sriov_vf(adev)) {
2987                 gfx_v9_0_init_csb(adev);
2988                 return 0;
2989         }
2990
2991         adev->gfx.rlc.funcs->stop(adev);
2992
2993         /* disable CG */
2994         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
2995
2996         gfx_v9_0_init_pg(adev);
2997
2998         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2999                 /* legacy rlc firmware loading */
3000                 r = gfx_v9_0_rlc_load_microcode(adev);
3001                 if (r)
3002                         return r;
3003         }
3004
3005         switch (adev->asic_type) {
3006         case CHIP_RAVEN:
3007                 if (amdgpu_lbpw == 0)
3008                         gfx_v9_0_enable_lbpw(adev, false);
3009                 else
3010                         gfx_v9_0_enable_lbpw(adev, true);
3011                 break;
3012         case CHIP_VEGA20:
3013                 if (amdgpu_lbpw > 0)
3014                         gfx_v9_0_enable_lbpw(adev, true);
3015                 else
3016                         gfx_v9_0_enable_lbpw(adev, false);
3017                 break;
3018         default:
3019                 break;
3020         }
3021
3022         adev->gfx.rlc.funcs->start(adev);
3023
3024         return 0;
3025 }
3026
3027 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
3028 {
3029         int i;
3030         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
3031
3032         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
3033         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
3034         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
3035         if (!enable) {
3036                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3037                         adev->gfx.gfx_ring[i].sched.ready = false;
3038         }
3039         WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
3040         udelay(50);
3041 }
3042
3043 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
3044 {
3045         const struct gfx_firmware_header_v1_0 *pfp_hdr;
3046         const struct gfx_firmware_header_v1_0 *ce_hdr;
3047         const struct gfx_firmware_header_v1_0 *me_hdr;
3048         const __le32 *fw_data;
3049         unsigned i, fw_size;
3050
3051         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
3052                 return -EINVAL;
3053
3054         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
3055                 adev->gfx.pfp_fw->data;
3056         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
3057                 adev->gfx.ce_fw->data;
3058         me_hdr = (const struct gfx_firmware_header_v1_0 *)
3059                 adev->gfx.me_fw->data;
3060
3061         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
3062         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
3063         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
3064
3065         gfx_v9_0_cp_gfx_enable(adev, false);
3066
3067         /* PFP */
3068         fw_data = (const __le32 *)
3069                 (adev->gfx.pfp_fw->data +
3070                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
3071         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
3072         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
3073         for (i = 0; i < fw_size; i++)
3074                 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
3075         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
3076
3077         /* CE */
3078         fw_data = (const __le32 *)
3079                 (adev->gfx.ce_fw->data +
3080                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
3081         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
3082         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
3083         for (i = 0; i < fw_size; i++)
3084                 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
3085         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
3086
3087         /* ME */
3088         fw_data = (const __le32 *)
3089                 (adev->gfx.me_fw->data +
3090                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
3091         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
3092         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
3093         for (i = 0; i < fw_size; i++)
3094                 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
3095         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
3096
3097         return 0;
3098 }
3099
3100 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
3101 {
3102         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
3103         const struct cs_section_def *sect = NULL;
3104         const struct cs_extent_def *ext = NULL;
3105         int r, i, tmp;
3106
3107         /* init the CP */
3108         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
3109         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
3110
3111         gfx_v9_0_cp_gfx_enable(adev, true);
3112
3113         r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
3114         if (r) {
3115                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
3116                 return r;
3117         }
3118
3119         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3120         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3121
3122         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3123         amdgpu_ring_write(ring, 0x80000000);
3124         amdgpu_ring_write(ring, 0x80000000);
3125
3126         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
3127                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3128                         if (sect->id == SECT_CONTEXT) {
3129                                 amdgpu_ring_write(ring,
3130                                        PACKET3(PACKET3_SET_CONTEXT_REG,
3131                                                ext->reg_count));
3132                                 amdgpu_ring_write(ring,
3133                                        ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
3134                                 for (i = 0; i < ext->reg_count; i++)
3135                                         amdgpu_ring_write(ring, ext->extent[i]);
3136                         }
3137                 }
3138         }
3139
3140         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3141         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3142
3143         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3144         amdgpu_ring_write(ring, 0);
3145
3146         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
3147         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
3148         amdgpu_ring_write(ring, 0x8000);
3149         amdgpu_ring_write(ring, 0x8000);
3150
3151         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));
3152         tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
3153                 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
3154         amdgpu_ring_write(ring, tmp);
3155         amdgpu_ring_write(ring, 0);
3156
3157         amdgpu_ring_commit(ring);
3158
3159         return 0;
3160 }
3161
3162 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
3163 {
3164         struct amdgpu_ring *ring;
3165         u32 tmp;
3166         u32 rb_bufsz;
3167         u64 rb_addr, rptr_addr, wptr_gpu_addr;
3168
3169         /* Set the write pointer delay */
3170         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
3171
3172         /* set the RB to use vmid 0 */
3173         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
3174
3175         /* Set ring buffer size */
3176         ring = &adev->gfx.gfx_ring[0];
3177         rb_bufsz = order_base_2(ring->ring_size / 8);
3178         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
3179         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
3180 #ifdef __BIG_ENDIAN
3181         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
3182 #endif
3183         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
3184
3185         /* Initialize the ring buffer's write pointers */
3186         ring->wptr = 0;
3187         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3188         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
3189
3190         /* set the wb address wether it's enabled or not */
3191         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3192         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
3193         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
3194
3195         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3196         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
3197         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
3198
3199         mdelay(1);
3200         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
3201
3202         rb_addr = ring->gpu_addr >> 8;
3203         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
3204         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
3205
3206         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
3207         if (ring->use_doorbell) {
3208                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3209                                     DOORBELL_OFFSET, ring->doorbell_index);
3210                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3211                                     DOORBELL_EN, 1);
3212         } else {
3213                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
3214         }
3215         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
3216
3217         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
3218                         DOORBELL_RANGE_LOWER, ring->doorbell_index);
3219         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
3220
3221         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
3222                        CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
3223
3224
3225         /* start the ring */
3226         gfx_v9_0_cp_gfx_start(adev);
3227         ring->sched.ready = true;
3228
3229         return 0;
3230 }
3231
3232 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
3233 {
3234         int i;
3235
3236         if (enable) {
3237                 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0);
3238         } else {
3239                 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL,
3240                         (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
3241                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3242                         adev->gfx.compute_ring[i].sched.ready = false;
3243                 adev->gfx.kiq.ring.sched.ready = false;
3244         }
3245         udelay(50);
3246 }
3247
3248 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
3249 {
3250         const struct gfx_firmware_header_v1_0 *mec_hdr;
3251         const __le32 *fw_data;
3252         unsigned i;
3253         u32 tmp;
3254
3255         if (!adev->gfx.mec_fw)
3256                 return -EINVAL;
3257
3258         gfx_v9_0_cp_compute_enable(adev, false);
3259
3260         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3261         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3262
3263         fw_data = (const __le32 *)
3264                 (adev->gfx.mec_fw->data +
3265                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
3266         tmp = 0;
3267         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
3268         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
3269         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
3270
3271         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
3272                 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
3273         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
3274                 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
3275
3276         /* MEC1 */
3277         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
3278                          mec_hdr->jt_offset);
3279         for (i = 0; i < mec_hdr->jt_size; i++)
3280                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
3281                         le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
3282
3283         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
3284                         adev->gfx.mec_fw_version);
3285         /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
3286
3287         return 0;
3288 }
3289
3290 /* KIQ functions */
3291 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
3292 {
3293         uint32_t tmp;
3294         struct amdgpu_device *adev = ring->adev;
3295
3296         /* tell RLC which is KIQ queue */
3297         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
3298         tmp &= 0xffffff00;
3299         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
3300         WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
3301         tmp |= 0x80;
3302         WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
3303 }
3304
3305 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
3306 {
3307         struct amdgpu_device *adev = ring->adev;
3308         struct v9_mqd *mqd = ring->mqd_ptr;
3309         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
3310         uint32_t tmp;
3311
3312         mqd->header = 0xC0310800;
3313         mqd->compute_pipelinestat_enable = 0x00000001;
3314         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3315         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3316         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3317         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3318         mqd->compute_static_thread_mgmt_se4 = 0xffffffff;
3319         mqd->compute_static_thread_mgmt_se5 = 0xffffffff;
3320         mqd->compute_static_thread_mgmt_se6 = 0xffffffff;
3321         mqd->compute_static_thread_mgmt_se7 = 0xffffffff;
3322         mqd->compute_misc_reserved = 0x00000003;
3323
3324         mqd->dynamic_cu_mask_addr_lo =
3325                 lower_32_bits(ring->mqd_gpu_addr
3326                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
3327         mqd->dynamic_cu_mask_addr_hi =
3328                 upper_32_bits(ring->mqd_gpu_addr
3329                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
3330
3331         eop_base_addr = ring->eop_gpu_addr >> 8;
3332         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
3333         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
3334
3335         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3336         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
3337         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3338                         (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
3339
3340         mqd->cp_hqd_eop_control = tmp;
3341
3342         /* enable doorbell? */
3343         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3344
3345         if (ring->use_doorbell) {
3346                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3347                                     DOORBELL_OFFSET, ring->doorbell_index);
3348                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3349                                     DOORBELL_EN, 1);
3350                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3351                                     DOORBELL_SOURCE, 0);
3352                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3353                                     DOORBELL_HIT, 0);
3354         } else {
3355                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3356                                          DOORBELL_EN, 0);
3357         }
3358
3359         mqd->cp_hqd_pq_doorbell_control = tmp;
3360
3361         /* disable the queue if it's active */
3362         ring->wptr = 0;
3363         mqd->cp_hqd_dequeue_request = 0;
3364         mqd->cp_hqd_pq_rptr = 0;
3365         mqd->cp_hqd_pq_wptr_lo = 0;
3366         mqd->cp_hqd_pq_wptr_hi = 0;
3367
3368         /* set the pointer to the MQD */
3369         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
3370         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
3371
3372         /* set MQD vmid to 0 */
3373         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
3374         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3375         mqd->cp_mqd_control = tmp;
3376
3377         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3378         hqd_gpu_addr = ring->gpu_addr >> 8;
3379         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3380         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3381
3382         /* set up the HQD, this is similar to CP_RB0_CNTL */
3383         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
3384         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3385                             (order_base_2(ring->ring_size / 4) - 1));
3386         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3387                         ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3388 #ifdef __BIG_ENDIAN
3389         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3390 #endif
3391         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3392         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3393         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3394         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3395         mqd->cp_hqd_pq_control = tmp;
3396
3397         /* set the wb address whether it's enabled or not */
3398         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3399         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3400         mqd->cp_hqd_pq_rptr_report_addr_hi =
3401                 upper_32_bits(wb_gpu_addr) & 0xffff;
3402
3403         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3404         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3405         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3406         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3407
3408         tmp = 0;
3409         /* enable the doorbell if requested */
3410         if (ring->use_doorbell) {
3411                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3412                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3413                                 DOORBELL_OFFSET, ring->doorbell_index);
3414
3415                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3416                                          DOORBELL_EN, 1);
3417                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3418                                          DOORBELL_SOURCE, 0);
3419                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3420                                          DOORBELL_HIT, 0);
3421         }
3422
3423         mqd->cp_hqd_pq_doorbell_control = tmp;
3424
3425         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3426         ring->wptr = 0;
3427         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
3428
3429         /* set the vmid for the queue */
3430         mqd->cp_hqd_vmid = 0;
3431
3432         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
3433         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3434         mqd->cp_hqd_persistent_state = tmp;
3435
3436         /* set MIN_IB_AVAIL_SIZE */
3437         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
3438         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
3439         mqd->cp_hqd_ib_control = tmp;
3440
3441         /* map_queues packet doesn't need activate the queue,
3442          * so only kiq need set this field.
3443          */
3444         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
3445                 mqd->cp_hqd_active = 1;
3446
3447         return 0;
3448 }
3449
3450 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
3451 {
3452         struct amdgpu_device *adev = ring->adev;
3453         struct v9_mqd *mqd = ring->mqd_ptr;
3454         int j;
3455
3456         /* disable wptr polling */
3457         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3458
3459         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
3460                mqd->cp_hqd_eop_base_addr_lo);
3461         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
3462                mqd->cp_hqd_eop_base_addr_hi);
3463
3464         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3465         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_CONTROL,
3466                mqd->cp_hqd_eop_control);
3467
3468         /* enable doorbell? */
3469         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3470                mqd->cp_hqd_pq_doorbell_control);
3471
3472         /* disable the queue if it's active */
3473         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3474                 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
3475                 for (j = 0; j < adev->usec_timeout; j++) {
3476                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3477                                 break;
3478                         udelay(1);
3479                 }
3480                 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
3481                        mqd->cp_hqd_dequeue_request);
3482                 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR,
3483                        mqd->cp_hqd_pq_rptr);
3484                 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3485                        mqd->cp_hqd_pq_wptr_lo);
3486                 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3487                        mqd->cp_hqd_pq_wptr_hi);
3488         }
3489
3490         /* set the pointer to the MQD */
3491         WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR,
3492                mqd->cp_mqd_base_addr_lo);
3493         WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR_HI,
3494                mqd->cp_mqd_base_addr_hi);
3495
3496         /* set MQD vmid to 0 */
3497         WREG32_SOC15_RLC(GC, 0, mmCP_MQD_CONTROL,
3498                mqd->cp_mqd_control);
3499
3500         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3501         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE,
3502                mqd->cp_hqd_pq_base_lo);
3503         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE_HI,
3504                mqd->cp_hqd_pq_base_hi);
3505
3506         /* set up the HQD, this is similar to CP_RB0_CNTL */
3507         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_CONTROL,
3508                mqd->cp_hqd_pq_control);
3509
3510         /* set the wb address whether it's enabled or not */
3511         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3512                                 mqd->cp_hqd_pq_rptr_report_addr_lo);
3513         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3514                                 mqd->cp_hqd_pq_rptr_report_addr_hi);
3515
3516         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3517         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
3518                mqd->cp_hqd_pq_wptr_poll_addr_lo);
3519         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3520                mqd->cp_hqd_pq_wptr_poll_addr_hi);
3521
3522         /* enable the doorbell if requested */
3523         if (ring->use_doorbell) {
3524                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
3525                                         (adev->doorbell_index.kiq * 2) << 2);
3526                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
3527                                         (adev->doorbell_index.userqueue_end * 2) << 2);
3528         }
3529
3530         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3531                mqd->cp_hqd_pq_doorbell_control);
3532
3533         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3534         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3535                mqd->cp_hqd_pq_wptr_lo);
3536         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3537                mqd->cp_hqd_pq_wptr_hi);
3538
3539         /* set the vmid for the queue */
3540         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3541
3542         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE,
3543                mqd->cp_hqd_persistent_state);
3544
3545         /* activate the queue */
3546         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE,
3547                mqd->cp_hqd_active);
3548
3549         if (ring->use_doorbell)
3550                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3551
3552         return 0;
3553 }
3554
3555 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring)
3556 {
3557         struct amdgpu_device *adev = ring->adev;
3558         int j;
3559
3560         /* disable the queue if it's active */
3561         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3562
3563                 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
3564
3565                 for (j = 0; j < adev->usec_timeout; j++) {
3566                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3567                                 break;
3568                         udelay(1);
3569                 }
3570
3571                 if (j == AMDGPU_MAX_USEC_TIMEOUT) {
3572                         DRM_DEBUG("KIQ dequeue request failed.\n");
3573
3574                         /* Manual disable if dequeue request times out */
3575                         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 0);
3576                 }
3577
3578                 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
3579                       0);
3580         }
3581
3582         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IQ_TIMER, 0);
3583         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0);
3584         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0);
3585         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
3586         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
3587         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 0);
3588         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);
3589         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0);
3590
3591         return 0;
3592 }
3593
3594 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
3595 {
3596         struct amdgpu_device *adev = ring->adev;
3597         struct v9_mqd *mqd = ring->mqd_ptr;
3598         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
3599
3600         gfx_v9_0_kiq_setting(ring);
3601
3602         if (adev->in_gpu_reset) { /* for GPU_RESET case */
3603                 /* reset MQD to a clean status */
3604                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3605                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
3606
3607                 /* reset ring buffer */
3608                 ring->wptr = 0;
3609                 amdgpu_ring_clear_ring(ring);
3610
3611                 mutex_lock(&adev->srbm_mutex);
3612                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3613                 gfx_v9_0_kiq_init_register(ring);
3614                 soc15_grbm_select(adev, 0, 0, 0, 0);
3615                 mutex_unlock(&adev->srbm_mutex);
3616         } else {
3617                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
3618                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
3619                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
3620                 mutex_lock(&adev->srbm_mutex);
3621                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3622                 gfx_v9_0_mqd_init(ring);
3623                 gfx_v9_0_kiq_init_register(ring);
3624                 soc15_grbm_select(adev, 0, 0, 0, 0);
3625                 mutex_unlock(&adev->srbm_mutex);
3626
3627                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3628                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
3629         }
3630
3631         return 0;
3632 }
3633
3634 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
3635 {
3636         struct amdgpu_device *adev = ring->adev;
3637         struct v9_mqd *mqd = ring->mqd_ptr;
3638         int mqd_idx = ring - &adev->gfx.compute_ring[0];
3639
3640         if (!adev->in_gpu_reset && !adev->in_suspend) {
3641                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
3642                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
3643                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
3644                 mutex_lock(&adev->srbm_mutex);
3645                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3646                 gfx_v9_0_mqd_init(ring);
3647                 soc15_grbm_select(adev, 0, 0, 0, 0);
3648                 mutex_unlock(&adev->srbm_mutex);
3649
3650                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3651                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
3652         } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
3653                 /* reset MQD to a clean status */
3654                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3655                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
3656
3657                 /* reset ring buffer */
3658                 ring->wptr = 0;
3659                 amdgpu_ring_clear_ring(ring);
3660         } else {
3661                 amdgpu_ring_clear_ring(ring);
3662         }
3663
3664         return 0;
3665 }
3666
3667 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
3668 {
3669         struct amdgpu_ring *ring;
3670         int r;
3671
3672         ring = &adev->gfx.kiq.ring;
3673
3674         r = amdgpu_bo_reserve(ring->mqd_obj, false);
3675         if (unlikely(r != 0))
3676                 return r;
3677
3678         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3679         if (unlikely(r != 0))
3680                 return r;
3681
3682         gfx_v9_0_kiq_init_queue(ring);
3683         amdgpu_bo_kunmap(ring->mqd_obj);
3684         ring->mqd_ptr = NULL;
3685         amdgpu_bo_unreserve(ring->mqd_obj);
3686         ring->sched.ready = true;
3687         return 0;
3688 }
3689
3690 static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev)
3691 {
3692         struct amdgpu_ring *ring = NULL;
3693         int r = 0, i;
3694
3695         gfx_v9_0_cp_compute_enable(adev, true);
3696
3697         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3698                 ring = &adev->gfx.compute_ring[i];
3699
3700                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3701                 if (unlikely(r != 0))
3702                         goto done;
3703                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3704                 if (!r) {
3705                         r = gfx_v9_0_kcq_init_queue(ring);
3706                         amdgpu_bo_kunmap(ring->mqd_obj);
3707                         ring->mqd_ptr = NULL;
3708                 }
3709                 amdgpu_bo_unreserve(ring->mqd_obj);
3710                 if (r)
3711                         goto done;
3712         }
3713
3714         r = amdgpu_gfx_enable_kcq(adev);
3715 done:
3716         return r;
3717 }
3718
3719 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
3720 {
3721         int r, i;
3722         struct amdgpu_ring *ring;
3723
3724         if (!(adev->flags & AMD_IS_APU))
3725                 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
3726
3727         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
3728                 if (adev->asic_type != CHIP_ARCTURUS) {
3729                         /* legacy firmware loading */
3730                         r = gfx_v9_0_cp_gfx_load_microcode(adev);
3731                         if (r)
3732                                 return r;
3733                 }
3734
3735                 r = gfx_v9_0_cp_compute_load_microcode(adev);
3736                 if (r)
3737                         return r;
3738         }
3739
3740         r = gfx_v9_0_kiq_resume(adev);
3741         if (r)
3742                 return r;
3743
3744         if (adev->asic_type != CHIP_ARCTURUS) {
3745                 r = gfx_v9_0_cp_gfx_resume(adev);
3746                 if (r)
3747                         return r;
3748         }
3749
3750         r = gfx_v9_0_kcq_resume(adev);
3751         if (r)
3752                 return r;
3753
3754         if (adev->asic_type != CHIP_ARCTURUS) {
3755                 ring = &adev->gfx.gfx_ring[0];
3756                 r = amdgpu_ring_test_helper(ring);
3757                 if (r)
3758                         return r;
3759         }
3760
3761         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3762                 ring = &adev->gfx.compute_ring[i];
3763                 amdgpu_ring_test_helper(ring);
3764         }
3765
3766         gfx_v9_0_enable_gui_idle_interrupt(adev, true);
3767
3768         return 0;
3769 }
3770
3771 static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev)
3772 {
3773         u32 tmp;
3774
3775         if (adev->asic_type != CHIP_ARCTURUS)
3776                 return;
3777
3778         tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG);
3779         tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE64KHASH,
3780                                 adev->df.hash_status.hash_64k);
3781         tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE2MHASH,
3782                                 adev->df.hash_status.hash_2m);
3783         tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE1GHASH,
3784                                 adev->df.hash_status.hash_1g);
3785         WREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG, tmp);
3786 }
3787
3788 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
3789 {
3790         if (adev->asic_type != CHIP_ARCTURUS)
3791                 gfx_v9_0_cp_gfx_enable(adev, enable);
3792         gfx_v9_0_cp_compute_enable(adev, enable);
3793 }
3794
3795 static int gfx_v9_0_hw_init(void *handle)
3796 {
3797         int r;
3798         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3799
3800         if (!amdgpu_sriov_vf(adev))
3801                 gfx_v9_0_init_golden_registers(adev);
3802
3803         gfx_v9_0_constants_init(adev);
3804
3805         gfx_v9_0_init_tcp_config(adev);
3806
3807         r = adev->gfx.rlc.funcs->resume(adev);
3808         if (r)
3809                 return r;
3810
3811         r = gfx_v9_0_cp_resume(adev);
3812         if (r)
3813                 return r;
3814
3815         return r;
3816 }
3817
3818 static int gfx_v9_0_hw_fini(void *handle)
3819 {
3820         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3821
3822         amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);
3823         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3824         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3825
3826         /* DF freeze and kcq disable will fail */
3827         if (!amdgpu_ras_intr_triggered())
3828                 /* disable KCQ to avoid CPC touch memory not valid anymore */
3829                 amdgpu_gfx_disable_kcq(adev);
3830
3831         if (amdgpu_sriov_vf(adev)) {
3832                 gfx_v9_0_cp_gfx_enable(adev, false);
3833                 /* must disable polling for SRIOV when hw finished, otherwise
3834                  * CPC engine may still keep fetching WB address which is already
3835                  * invalid after sw finished and trigger DMAR reading error in
3836                  * hypervisor side.
3837                  */
3838                 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3839                 return 0;
3840         }
3841
3842         /* Use deinitialize sequence from CAIL when unbinding device from driver,
3843          * otherwise KIQ is hanging when binding back
3844          */
3845         if (!adev->in_gpu_reset && !adev->in_suspend) {
3846                 mutex_lock(&adev->srbm_mutex);
3847                 soc15_grbm_select(adev, adev->gfx.kiq.ring.me,
3848                                 adev->gfx.kiq.ring.pipe,
3849                                 adev->gfx.kiq.ring.queue, 0);
3850                 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring);
3851                 soc15_grbm_select(adev, 0, 0, 0, 0);
3852                 mutex_unlock(&adev->srbm_mutex);
3853         }
3854
3855         gfx_v9_0_cp_enable(adev, false);
3856         adev->gfx.rlc.funcs->stop(adev);
3857
3858         return 0;
3859 }
3860
3861 static int gfx_v9_0_suspend(void *handle)
3862 {
3863         return gfx_v9_0_hw_fini(handle);
3864 }
3865
3866 static int gfx_v9_0_resume(void *handle)
3867 {
3868         return gfx_v9_0_hw_init(handle);
3869 }
3870
3871 static bool gfx_v9_0_is_idle(void *handle)
3872 {
3873         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3874
3875         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
3876                                 GRBM_STATUS, GUI_ACTIVE))
3877                 return false;
3878         else
3879                 return true;
3880 }
3881
3882 static int gfx_v9_0_wait_for_idle(void *handle)
3883 {
3884         unsigned i;
3885         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3886
3887         for (i = 0; i < adev->usec_timeout; i++) {
3888                 if (gfx_v9_0_is_idle(handle))
3889                         return 0;
3890                 udelay(1);
3891         }
3892         return -ETIMEDOUT;
3893 }
3894
3895 static int gfx_v9_0_soft_reset(void *handle)
3896 {
3897         u32 grbm_soft_reset = 0;
3898         u32 tmp;
3899         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3900
3901         /* GRBM_STATUS */
3902         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
3903         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3904                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3905                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3906                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3907                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3908                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3909                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3910                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3911                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3912                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3913         }
3914
3915         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3916                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3917                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3918         }
3919
3920         /* GRBM_STATUS2 */
3921         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
3922         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3923                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3924                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3925
3926
3927         if (grbm_soft_reset) {
3928                 /* stop the rlc */
3929                 adev->gfx.rlc.funcs->stop(adev);
3930
3931                 if (adev->asic_type != CHIP_ARCTURUS)
3932                         /* Disable GFX parsing/prefetching */
3933                         gfx_v9_0_cp_gfx_enable(adev, false);
3934
3935                 /* Disable MEC parsing/prefetching */
3936                 gfx_v9_0_cp_compute_enable(adev, false);
3937
3938                 if (grbm_soft_reset) {
3939                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3940                         tmp |= grbm_soft_reset;
3941                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3942                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3943                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3944
3945                         udelay(50);
3946
3947                         tmp &= ~grbm_soft_reset;
3948                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3949                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3950                 }
3951
3952                 /* Wait a little for things to settle down */
3953                 udelay(50);
3954         }
3955         return 0;
3956 }
3957
3958 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3959 {
3960         uint64_t clock;
3961
3962         mutex_lock(&adev->gfx.gpu_clock_mutex);
3963         if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)) {
3964                 uint32_t tmp, lsb, msb, i = 0;
3965                 do {
3966                         if (i != 0)
3967                                 udelay(1);
3968                         tmp = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_MSB);
3969                         lsb = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_LSB);
3970                         msb = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_MSB);
3971                         i++;
3972                 } while (unlikely(tmp != msb) && (i < adev->usec_timeout));
3973                 clock = (uint64_t)lsb | ((uint64_t)msb << 32ULL);
3974         } else {
3975                 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3976                 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3977                         ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3978         }
3979         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3980         return clock;
3981 }
3982
3983 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3984                                           uint32_t vmid,
3985                                           uint32_t gds_base, uint32_t gds_size,
3986                                           uint32_t gws_base, uint32_t gws_size,
3987                                           uint32_t oa_base, uint32_t oa_size)
3988 {
3989         struct amdgpu_device *adev = ring->adev;
3990
3991         /* GDS Base */
3992         gfx_v9_0_write_data_to_reg(ring, 0, false,
3993                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
3994                                    gds_base);
3995
3996         /* GDS Size */
3997         gfx_v9_0_write_data_to_reg(ring, 0, false,
3998                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
3999                                    gds_size);
4000
4001         /* GWS */
4002         gfx_v9_0_write_data_to_reg(ring, 0, false,
4003                                    SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
4004                                    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4005
4006         /* OA */
4007         gfx_v9_0_write_data_to_reg(ring, 0, false,
4008                                    SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
4009                                    (1 << (oa_size + oa_base)) - (1 << oa_base));
4010 }
4011
4012 static const u32 vgpr_init_compute_shader[] =
4013 {
4014         0xb07c0000, 0xbe8000ff,
4015         0x000000f8, 0xbf110800,
4016         0x7e000280, 0x7e020280,
4017         0x7e040280, 0x7e060280,
4018         0x7e080280, 0x7e0a0280,
4019         0x7e0c0280, 0x7e0e0280,
4020         0x80808800, 0xbe803200,
4021         0xbf84fff5, 0xbf9c0000,
4022         0xd28c0001, 0x0001007f,
4023         0xd28d0001, 0x0002027e,
4024         0x10020288, 0xb8810904,
4025         0xb7814000, 0xd1196a01,
4026         0x00000301, 0xbe800087,
4027         0xbefc00c1, 0xd89c4000,
4028         0x00020201, 0xd89cc080,
4029         0x00040401, 0x320202ff,
4030         0x00000800, 0x80808100,
4031         0xbf84fff8, 0x7e020280,
4032         0xbf810000, 0x00000000,
4033 };
4034
4035 static const u32 sgpr_init_compute_shader[] =
4036 {
4037         0xb07c0000, 0xbe8000ff,
4038         0x0000005f, 0xbee50080,
4039         0xbe812c65, 0xbe822c65,
4040         0xbe832c65, 0xbe842c65,
4041         0xbe852c65, 0xb77c0005,
4042         0x80808500, 0xbf84fff8,
4043         0xbe800080, 0xbf810000,
4044 };
4045
4046 /* When below register arrays changed, please update gpr_reg_size,
4047   and sec_ded_counter_reg_size in function gfx_v9_0_do_edc_gpr_workarounds,
4048   to cover all gfx9 ASICs */
4049 static const struct soc15_reg_entry vgpr_init_regs[] = {
4050    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
4051    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
4052    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 },
4053    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
4054    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x3f },
4055    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 },  /* 64KB LDS */
4056    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff },
4057    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
4058    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
4059    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
4060    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff },
4061    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff },
4062    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff },
4063    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff },
4064 };
4065
4066 static const struct soc15_reg_entry sgpr1_init_regs[] = {
4067    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
4068    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
4069    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 },
4070    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
4071    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */
4072    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 },
4073    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x000000ff },
4074    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x000000ff },
4075    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x000000ff },
4076    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x000000ff },
4077    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x000000ff },
4078    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x000000ff },
4079    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x000000ff },
4080    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x000000ff },
4081 };
4082
4083 static const struct soc15_reg_entry sgpr2_init_regs[] = {
4084    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
4085    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
4086    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 },
4087    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
4088    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */
4089    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 },
4090    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x0000ff00 },
4091    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x0000ff00 },
4092    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x0000ff00 },
4093    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x0000ff00 },
4094    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x0000ff00 },
4095    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x0000ff00 },
4096    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x0000ff00 },
4097    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x0000ff00 },
4098 };
4099
4100 static const struct soc15_reg_entry gfx_v9_0_edc_counter_regs[] = {
4101    { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1},
4102    { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1},
4103    { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1},
4104    { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1},
4105    { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1, 1},
4106    { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1, 1},
4107    { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1},
4108    { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1},
4109    { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1},
4110    { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1},
4111    { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT), 0, 1, 1},
4112    { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED), 0, 1, 1},
4113    { SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1},
4114    { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 0, 4, 6},
4115    { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT), 0, 4, 16},
4116    { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO), 0, 4, 16},
4117    { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT), 0, 4, 16},
4118    { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16},
4119    { SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16},
4120    { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16},
4121    { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 0, 4, 16},
4122    { SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16},
4123    { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6},
4124    { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 4, 16},
4125    { SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 0, 4, 16},
4126    { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, 1},
4127    { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, 1},
4128    { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 1, 32},
4129    { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 1, 32},
4130    { SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 1, 72},
4131    { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16},
4132    { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2},
4133    { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
4134    { SOC15_REG_ENTRY(HDP, 0, mmHDP_EDC_CNT), 0, 1, 1},
4135 };
4136
4137 static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
4138 {
4139         struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
4140         int i, r;
4141
4142         /* only support when RAS is enabled */
4143         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
4144                 return 0;
4145
4146         r = amdgpu_ring_alloc(ring, 7);
4147         if (r) {
4148                 DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n",
4149                         ring->name, r);
4150                 return r;
4151         }
4152
4153         WREG32_SOC15(GC, 0, mmGDS_VMID0_BASE, 0x00000000);
4154         WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, adev->gds.gds_size);
4155
4156         amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
4157         amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
4158                                 PACKET3_DMA_DATA_DST_SEL(1) |
4159                                 PACKET3_DMA_DATA_SRC_SEL(2) |
4160                                 PACKET3_DMA_DATA_ENGINE(0)));
4161         amdgpu_ring_write(ring, 0);
4162         amdgpu_ring_write(ring, 0);
4163         amdgpu_ring_write(ring, 0);
4164         amdgpu_ring_write(ring, 0);
4165         amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |
4166                                 adev->gds.gds_size);
4167
4168         amdgpu_ring_commit(ring);
4169
4170         for (i = 0; i < adev->usec_timeout; i++) {
4171                 if (ring->wptr == gfx_v9_0_ring_get_rptr_compute(ring))
4172                         break;
4173                 udelay(1);
4174         }
4175
4176         if (i >= adev->usec_timeout)
4177                 r = -ETIMEDOUT;
4178
4179         WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, 0x00000000);
4180
4181         return r;
4182 }
4183
4184 static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
4185 {
4186         struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
4187         struct amdgpu_ib ib;
4188         struct dma_fence *f = NULL;
4189         int r, i;
4190         unsigned total_size, vgpr_offset, sgpr_offset;
4191         u64 gpu_addr;
4192
4193         int compute_dim_x = adev->gfx.config.max_shader_engines *
4194                                                 adev->gfx.config.max_cu_per_sh *
4195                                                 adev->gfx.config.max_sh_per_se;
4196         int sgpr_work_group_size = 5;
4197         int gpr_reg_size = compute_dim_x / 16 + 6;
4198
4199         /* only support when RAS is enabled */
4200         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
4201                 return 0;
4202
4203         /* bail if the compute ring is not ready */
4204         if (!ring->sched.ready)
4205                 return 0;
4206
4207         total_size =
4208                 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* VGPRS */
4209         total_size +=
4210                 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS1 */
4211         total_size +=
4212                 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS2 */
4213         total_size = ALIGN(total_size, 256);
4214         vgpr_offset = total_size;
4215         total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
4216         sgpr_offset = total_size;
4217         total_size += sizeof(sgpr_init_compute_shader);
4218
4219         /* allocate an indirect buffer to put the commands in */
4220         memset(&ib, 0, sizeof(ib));
4221         r = amdgpu_ib_get(adev, NULL, total_size, &ib);
4222         if (r) {
4223                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
4224                 return r;
4225         }
4226
4227         /* load the compute shaders */
4228         for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)
4229                 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];
4230
4231         for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
4232                 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
4233
4234         /* init the ib length to 0 */
4235         ib.length_dw = 0;
4236
4237         /* VGPR */
4238         /* write the register state for the compute dispatch */
4239         for (i = 0; i < gpr_reg_size; i++) {
4240                 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
4241                 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs[i])
4242                                                                 - PACKET3_SET_SH_REG_START;
4243                 ib.ptr[ib.length_dw++] = vgpr_init_regs[i].reg_value;
4244         }
4245         /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
4246         gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
4247         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
4248         ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
4249                                                         - PACKET3_SET_SH_REG_START;
4250         ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
4251         ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
4252
4253         /* write dispatch packet */
4254         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
4255         ib.ptr[ib.length_dw++] = compute_dim_x; /* x */
4256         ib.ptr[ib.length_dw++] = 1; /* y */
4257         ib.ptr[ib.length_dw++] = 1; /* z */
4258         ib.ptr[ib.length_dw++] =
4259                 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
4260
4261         /* write CS partial flush packet */
4262         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
4263         ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
4264
4265         /* SGPR1 */
4266         /* write the register state for the compute dispatch */
4267         for (i = 0; i < gpr_reg_size; i++) {
4268                 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
4269                 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i])
4270                                                                 - PACKET3_SET_SH_REG_START;
4271                 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i].reg_value;
4272         }
4273         /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
4274         gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
4275         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
4276         ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
4277                                                         - PACKET3_SET_SH_REG_START;
4278         ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
4279         ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
4280
4281         /* write dispatch packet */
4282         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
4283         ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */
4284         ib.ptr[ib.length_dw++] = 1; /* y */
4285         ib.ptr[ib.length_dw++] = 1; /* z */
4286         ib.ptr[ib.length_dw++] =
4287                 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
4288
4289         /* write CS partial flush packet */
4290         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
4291         ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
4292
4293         /* SGPR2 */
4294         /* write the register state for the compute dispatch */
4295         for (i = 0; i < gpr_reg_size; i++) {
4296                 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
4297                 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i])
4298                                                                 - PACKET3_SET_SH_REG_START;
4299                 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i].reg_value;
4300         }
4301         /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
4302         gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
4303         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
4304         ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
4305                                                         - PACKET3_SET_SH_REG_START;
4306         ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
4307         ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
4308
4309         /* write dispatch packet */
4310         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
4311         ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */
4312         ib.ptr[ib.length_dw++] = 1; /* y */
4313         ib.ptr[ib.length_dw++] = 1; /* z */
4314         ib.ptr[ib.length_dw++] =
4315                 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
4316
4317         /* write CS partial flush packet */
4318         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
4319         ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
4320
4321         /* shedule the ib on the ring */
4322         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
4323         if (r) {
4324                 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
4325                 goto fail;
4326         }
4327
4328         /* wait for the GPU to finish processing the IB */
4329         r = dma_fence_wait(f, false);
4330         if (r) {
4331                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
4332                 goto fail;
4333         }
4334
4335         switch (adev->asic_type)
4336         {
4337         case CHIP_VEGA20:
4338                 gfx_v9_0_clear_ras_edc_counter(adev);
4339                 break;
4340         case CHIP_ARCTURUS:
4341                 gfx_v9_4_clear_ras_edc_counter(adev);
4342                 break;
4343         default:
4344                 break;
4345         }
4346
4347 fail:
4348         amdgpu_ib_free(adev, &ib, NULL);
4349         dma_fence_put(f);
4350
4351         return r;
4352 }
4353
4354 static int gfx_v9_0_early_init(void *handle)
4355 {
4356         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4357
4358         if (adev->asic_type == CHIP_ARCTURUS)
4359                 adev->gfx.num_gfx_rings = 0;
4360         else
4361                 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
4362         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
4363         gfx_v9_0_set_kiq_pm4_funcs(adev);
4364         gfx_v9_0_set_ring_funcs(adev);
4365         gfx_v9_0_set_irq_funcs(adev);
4366         gfx_v9_0_set_gds_init(adev);
4367         gfx_v9_0_set_rlc_funcs(adev);
4368
4369         return 0;
4370 }
4371
4372 static int gfx_v9_0_ecc_late_init(void *handle)
4373 {
4374         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4375         int r;
4376
4377         r = gfx_v9_0_do_edc_gds_workarounds(adev);
4378         if (r)
4379                 return r;
4380
4381         /* requires IBs so do in late init after IB pool is initialized */
4382         r = gfx_v9_0_do_edc_gpr_workarounds(adev);
4383         if (r)
4384                 return r;
4385
4386         r = amdgpu_gfx_ras_late_init(adev);
4387         if (r)
4388                 return r;
4389
4390         return 0;
4391 }
4392
4393 static int gfx_v9_0_late_init(void *handle)
4394 {
4395         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4396         int r;
4397
4398         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4399         if (r)
4400                 return r;
4401
4402         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4403         if (r)
4404                 return r;
4405
4406         r = gfx_v9_0_ecc_late_init(handle);
4407         if (r)
4408                 return r;
4409
4410         return 0;
4411 }
4412
4413 static bool gfx_v9_0_is_rlc_enabled(struct amdgpu_device *adev)
4414 {
4415         uint32_t rlc_setting;
4416
4417         /* if RLC is not enabled, do nothing */
4418         rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
4419         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
4420                 return false;
4421
4422         return true;
4423 }
4424
4425 static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev)
4426 {
4427         uint32_t data;
4428         unsigned i;
4429
4430         data = RLC_SAFE_MODE__CMD_MASK;
4431         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
4432         WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
4433
4434         /* wait for RLC_SAFE_MODE */
4435         for (i = 0; i < adev->usec_timeout; i++) {
4436                 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
4437                         break;
4438                 udelay(1);
4439         }
4440 }
4441
4442 static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev)
4443 {
4444         uint32_t data;
4445
4446         data = RLC_SAFE_MODE__CMD_MASK;
4447         WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
4448 }
4449
4450 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
4451                                                 bool enable)
4452 {
4453         amdgpu_gfx_rlc_enter_safe_mode(adev);
4454
4455         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
4456                 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
4457                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
4458                         gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
4459         } else {
4460                 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
4461                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
4462                         gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
4463         }
4464
4465         amdgpu_gfx_rlc_exit_safe_mode(adev);
4466 }
4467
4468 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
4469                                                 bool enable)
4470 {
4471         /* TODO: double check if we need to perform under safe mode */
4472         /* gfx_v9_0_enter_rlc_safe_mode(adev); */
4473
4474         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
4475                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
4476         else
4477                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
4478
4479         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
4480                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
4481         else
4482                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
4483
4484         /* gfx_v9_0_exit_rlc_safe_mode(adev); */
4485 }
4486
4487 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
4488                                                       bool enable)
4489 {
4490         uint32_t data, def;
4491
4492         amdgpu_gfx_rlc_enter_safe_mode(adev);
4493
4494         /* It is disabled by HW by default */
4495         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
4496                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
4497                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4498
4499                 if (adev->asic_type != CHIP_VEGA12)
4500                         data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
4501
4502                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4503                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
4504                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
4505
4506                 /* only for Vega10 & Raven1 */
4507                 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
4508
4509                 if (def != data)
4510                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4511
4512                 /* MGLS is a global flag to control all MGLS in GFX */
4513                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
4514                         /* 2 - RLC memory Light sleep */
4515                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
4516                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4517                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4518                                 if (def != data)
4519                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
4520                         }
4521                         /* 3 - CP memory Light sleep */
4522                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
4523                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4524                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4525                                 if (def != data)
4526                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4527                         }
4528                 }
4529         } else {
4530                 /* 1 - MGCG_OVERRIDE */
4531                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4532
4533                 if (adev->asic_type != CHIP_VEGA12)
4534                         data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
4535
4536                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4537                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4538                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
4539                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
4540
4541                 if (def != data)
4542                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4543
4544                 /* 2 - disable MGLS in RLC */
4545                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4546                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
4547                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4548                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
4549                 }
4550
4551                 /* 3 - disable MGLS in CP */
4552                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4553                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
4554                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4555                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4556                 }
4557         }
4558
4559         amdgpu_gfx_rlc_exit_safe_mode(adev);
4560 }
4561
4562 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
4563                                            bool enable)
4564 {
4565         uint32_t data, def;
4566
4567         if (adev->asic_type == CHIP_ARCTURUS)
4568                 return;
4569
4570         amdgpu_gfx_rlc_enter_safe_mode(adev);
4571
4572         /* Enable 3D CGCG/CGLS */
4573         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
4574                 /* write cmd to clear cgcg/cgls ov */
4575                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4576                 /* unset CGCG override */
4577                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
4578                 /* update CGCG and CGLS override bits */
4579                 if (def != data)
4580                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4581
4582                 /* enable 3Dcgcg FSM(0x0000363f) */
4583                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4584
4585                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4586                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4587                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4588                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4589                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4590                 if (def != data)
4591                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
4592
4593                 /* set IDLE_POLL_COUNT(0x00900100) */
4594                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
4595                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4596                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4597                 if (def != data)
4598                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
4599         } else {
4600                 /* Disable CGCG/CGLS */
4601                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4602                 /* disable cgcg, cgls should be disabled */
4603                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
4604                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
4605                 /* disable cgcg and cgls in FSM */
4606                 if (def != data)
4607                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
4608         }
4609
4610         amdgpu_gfx_rlc_exit_safe_mode(adev);
4611 }
4612
4613 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
4614                                                       bool enable)
4615 {
4616         uint32_t def, data;
4617
4618         amdgpu_gfx_rlc_enter_safe_mode(adev);
4619
4620         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
4621                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4622                 /* unset CGCG override */
4623                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
4624                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4625                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4626                 else
4627                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4628                 /* update CGCG and CGLS override bits */
4629                 if (def != data)
4630                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4631
4632                 /* enable cgcg FSM(0x0000363F) */
4633                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4634
4635                 if (adev->asic_type == CHIP_ARCTURUS)
4636                         data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4637                                 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4638                 else
4639                         data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4640                                 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4641                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4642                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4643                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4644                 if (def != data)
4645                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4646
4647                 /* set IDLE_POLL_COUNT(0x00900100) */
4648                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
4649                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4650                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4651                 if (def != data)
4652                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
4653         } else {
4654                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4655                 /* reset CGCG/CGLS bits */
4656                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
4657                 /* disable cgcg and cgls in FSM */
4658                 if (def != data)
4659                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4660         }
4661
4662         amdgpu_gfx_rlc_exit_safe_mode(adev);
4663 }
4664
4665 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
4666                                             bool enable)
4667 {
4668         if (enable) {
4669                 /* CGCG/CGLS should be enabled after MGCG/MGLS
4670                  * ===  MGCG + MGLS ===
4671                  */
4672                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
4673                 /* ===  CGCG /CGLS for GFX 3D Only === */
4674                 gfx_v9_0_update_3d_clock_gating(adev, enable);
4675                 /* ===  CGCG + CGLS === */
4676                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
4677         } else {
4678                 /* CGCG/CGLS should be disabled before MGCG/MGLS
4679                  * ===  CGCG + CGLS ===
4680                  */
4681                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
4682                 /* ===  CGCG /CGLS for GFX 3D Only === */
4683                 gfx_v9_0_update_3d_clock_gating(adev, enable);
4684                 /* ===  MGCG + MGLS === */
4685                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
4686         }
4687         return 0;
4688 }
4689
4690 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
4691         .is_rlc_enabled = gfx_v9_0_is_rlc_enabled,
4692         .set_safe_mode = gfx_v9_0_set_safe_mode,
4693         .unset_safe_mode = gfx_v9_0_unset_safe_mode,
4694         .init = gfx_v9_0_rlc_init,
4695         .get_csb_size = gfx_v9_0_get_csb_size,
4696         .get_csb_buffer = gfx_v9_0_get_csb_buffer,
4697         .get_cp_table_num = gfx_v9_0_cp_jump_table_num,
4698         .resume = gfx_v9_0_rlc_resume,
4699         .stop = gfx_v9_0_rlc_stop,
4700         .reset = gfx_v9_0_rlc_reset,
4701         .start = gfx_v9_0_rlc_start
4702 };
4703
4704 static int gfx_v9_0_set_powergating_state(void *handle,
4705                                           enum amd_powergating_state state)
4706 {
4707         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4708         bool enable = (state == AMD_PG_STATE_GATE);
4709
4710         switch (adev->asic_type) {
4711         case CHIP_RAVEN:
4712         case CHIP_RENOIR:
4713                 if (!enable) {
4714                         amdgpu_gfx_off_ctrl(adev, false);
4715                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
4716                 }
4717                 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
4718                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
4719                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
4720                 } else {
4721                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
4722                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
4723                 }
4724
4725                 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
4726                         gfx_v9_0_enable_cp_power_gating(adev, true);
4727                 else
4728                         gfx_v9_0_enable_cp_power_gating(adev, false);
4729
4730                 /* update gfx cgpg state */
4731                 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
4732
4733                 /* update mgcg state */
4734                 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
4735
4736                 if (enable)
4737                         amdgpu_gfx_off_ctrl(adev, true);
4738                 break;
4739         case CHIP_VEGA12:
4740                 if (!enable) {
4741                         amdgpu_gfx_off_ctrl(adev, false);
4742                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
4743                 } else {
4744                         amdgpu_gfx_off_ctrl(adev, true);
4745                 }
4746                 break;
4747         default:
4748                 break;
4749         }
4750
4751         return 0;
4752 }
4753
4754 static int gfx_v9_0_set_clockgating_state(void *handle,
4755                                           enum amd_clockgating_state state)
4756 {
4757         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4758
4759         if (amdgpu_sriov_vf(adev))
4760                 return 0;
4761
4762         switch (adev->asic_type) {
4763         case CHIP_VEGA10:
4764         case CHIP_VEGA12:
4765         case CHIP_VEGA20:
4766         case CHIP_RAVEN:
4767         case CHIP_ARCTURUS:
4768         case CHIP_RENOIR:
4769                 gfx_v9_0_update_gfx_clock_gating(adev,
4770                                                  state == AMD_CG_STATE_GATE);
4771                 break;
4772         default:
4773                 break;
4774         }
4775         return 0;
4776 }
4777
4778 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
4779 {
4780         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4781         int data;
4782
4783         if (amdgpu_sriov_vf(adev))
4784                 *flags = 0;
4785
4786         /* AMD_CG_SUPPORT_GFX_MGCG */
4787         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
4788         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
4789                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
4790
4791         /* AMD_CG_SUPPORT_GFX_CGCG */
4792         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
4793         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
4794                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
4795
4796         /* AMD_CG_SUPPORT_GFX_CGLS */
4797         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
4798                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
4799
4800         /* AMD_CG_SUPPORT_GFX_RLC_LS */
4801         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
4802         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
4803                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
4804
4805         /* AMD_CG_SUPPORT_GFX_CP_LS */
4806         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
4807         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
4808                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
4809
4810         if (adev->asic_type != CHIP_ARCTURUS) {
4811                 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
4812                 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
4813                 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
4814                         *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
4815
4816                 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
4817                 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
4818                         *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
4819         }
4820 }
4821
4822 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
4823 {
4824         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
4825 }
4826
4827 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
4828 {
4829         struct amdgpu_device *adev = ring->adev;
4830         u64 wptr;
4831
4832         /* XXX check if swapping is necessary on BE */
4833         if (ring->use_doorbell) {
4834                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
4835         } else {
4836                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
4837                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
4838         }
4839
4840         return wptr;
4841 }
4842
4843 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
4844 {
4845         struct amdgpu_device *adev = ring->adev;
4846
4847         if (ring->use_doorbell) {
4848                 /* XXX check if swapping is necessary on BE */
4849                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4850                 WDOORBELL64(ring->doorbell_index, ring->wptr);
4851         } else {
4852                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
4853                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
4854         }
4855 }
4856
4857 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
4858 {
4859         struct amdgpu_device *adev = ring->adev;
4860         u32 ref_and_mask, reg_mem_engine;
4861         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
4862
4863         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
4864                 switch (ring->me) {
4865                 case 1:
4866                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
4867                         break;
4868                 case 2:
4869                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
4870                         break;
4871                 default:
4872                         return;
4873                 }
4874                 reg_mem_engine = 0;
4875         } else {
4876                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
4877                 reg_mem_engine = 1; /* pfp */
4878         }
4879
4880         gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
4881                               adev->nbio.funcs->get_hdp_flush_req_offset(adev),
4882                               adev->nbio.funcs->get_hdp_flush_done_offset(adev),
4883                               ref_and_mask, ref_and_mask, 0x20);
4884 }
4885
4886 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
4887                                         struct amdgpu_job *job,
4888                                         struct amdgpu_ib *ib,
4889                                         uint32_t flags)
4890 {
4891         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4892         u32 header, control = 0;
4893
4894         if (ib->flags & AMDGPU_IB_FLAG_CE)
4895                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
4896         else
4897                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4898
4899         control |= ib->length_dw | (vmid << 24);
4900
4901         if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
4902                 control |= INDIRECT_BUFFER_PRE_ENB(1);
4903
4904                 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
4905                         gfx_v9_0_ring_emit_de_meta(ring);
4906         }
4907
4908         amdgpu_ring_write(ring, header);
4909         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4910         amdgpu_ring_write(ring,
4911 #ifdef __BIG_ENDIAN
4912                 (2 << 0) |
4913 #endif
4914                 lower_32_bits(ib->gpu_addr));
4915         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4916         amdgpu_ring_write(ring, control);
4917 }
4918
4919 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4920                                           struct amdgpu_job *job,
4921                                           struct amdgpu_ib *ib,
4922                                           uint32_t flags)
4923 {
4924         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4925         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
4926
4927         /* Currently, there is a high possibility to get wave ID mismatch
4928          * between ME and GDS, leading to a hw deadlock, because ME generates
4929          * different wave IDs than the GDS expects. This situation happens
4930          * randomly when at least 5 compute pipes use GDS ordered append.
4931          * The wave IDs generated by ME are also wrong after suspend/resume.
4932          * Those are probably bugs somewhere else in the kernel driver.
4933          *
4934          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
4935          * GDS to 0 for this ring (me/pipe).
4936          */
4937         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
4938                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
4939                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
4940                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
4941         }
4942
4943         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
4944         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4945         amdgpu_ring_write(ring,
4946 #ifdef __BIG_ENDIAN
4947                                 (2 << 0) |
4948 #endif
4949                                 lower_32_bits(ib->gpu_addr));
4950         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4951         amdgpu_ring_write(ring, control);
4952 }
4953
4954 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
4955                                      u64 seq, unsigned flags)
4956 {
4957         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4958         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4959         bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
4960
4961         /* RELEASE_MEM - flush caches, send int */
4962         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
4963         amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN |
4964                                                EOP_TC_NC_ACTION_EN) :
4965                                               (EOP_TCL1_ACTION_EN |
4966                                                EOP_TC_ACTION_EN |
4967                                                EOP_TC_WB_ACTION_EN |
4968                                                EOP_TC_MD_ACTION_EN)) |
4969                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4970                                  EVENT_INDEX(5)));
4971         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
4972
4973         /*
4974          * the address should be Qword aligned if 64bit write, Dword
4975          * aligned if only send 32bit data low (discard data high)
4976          */
4977         if (write64bit)
4978                 BUG_ON(addr & 0x7);
4979         else
4980                 BUG_ON(addr & 0x3);
4981         amdgpu_ring_write(ring, lower_32_bits(addr));
4982         amdgpu_ring_write(ring, upper_32_bits(addr));
4983         amdgpu_ring_write(ring, lower_32_bits(seq));
4984         amdgpu_ring_write(ring, upper_32_bits(seq));
4985         amdgpu_ring_write(ring, 0);
4986 }
4987
4988 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
4989 {
4990         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4991         uint32_t seq = ring->fence_drv.sync_seq;
4992         uint64_t addr = ring->fence_drv.gpu_addr;
4993
4994         gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
4995                               lower_32_bits(addr), upper_32_bits(addr),
4996                               seq, 0xffffffff, 4);
4997 }
4998
4999 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
5000                                         unsigned vmid, uint64_t pd_addr)
5001 {
5002         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
5003
5004         /* compute doesn't have PFP */
5005         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
5006                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
5007                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
5008                 amdgpu_ring_write(ring, 0x0);
5009         }
5010 }
5011
5012 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
5013 {
5014         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
5015 }
5016
5017 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
5018 {
5019         u64 wptr;
5020
5021         /* XXX check if swapping is necessary on BE */
5022         if (ring->use_doorbell)
5023                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
5024         else
5025                 BUG();
5026         return wptr;
5027 }
5028
5029 static void gfx_v9_0_ring_set_pipe_percent(struct amdgpu_ring *ring,
5030                                            bool acquire)
5031 {
5032         struct amdgpu_device *adev = ring->adev;
5033         int pipe_num, tmp, reg;
5034         int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1;
5035
5036         pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe;
5037
5038         /* first me only has 2 entries, GFX and HP3D */
5039         if (ring->me > 0)
5040                 pipe_num -= 2;
5041
5042         reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX) + pipe_num;
5043         tmp = RREG32(reg);
5044         tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
5045         WREG32(reg, tmp);
5046 }
5047
5048 static void gfx_v9_0_pipe_reserve_resources(struct amdgpu_device *adev,
5049                                             struct amdgpu_ring *ring,
5050                                             bool acquire)
5051 {
5052         int i, pipe;
5053         bool reserve;
5054         struct amdgpu_ring *iring;
5055
5056         mutex_lock(&adev->gfx.pipe_reserve_mutex);
5057         pipe = amdgpu_gfx_mec_queue_to_bit(adev, ring->me, ring->pipe, 0);
5058         if (acquire)
5059                 set_bit(pipe, adev->gfx.pipe_reserve_bitmap);
5060         else
5061                 clear_bit(pipe, adev->gfx.pipe_reserve_bitmap);
5062
5063         if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) {
5064                 /* Clear all reservations - everyone reacquires all resources */
5065                 for (i = 0; i < adev->gfx.num_gfx_rings; ++i)
5066                         gfx_v9_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i],
5067                                                        true);
5068
5069                 for (i = 0; i < adev->gfx.num_compute_rings; ++i)
5070                         gfx_v9_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i],
5071                                                        true);
5072         } else {
5073                 /* Lower all pipes without a current reservation */
5074                 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) {
5075                         iring = &adev->gfx.gfx_ring[i];
5076                         pipe = amdgpu_gfx_mec_queue_to_bit(adev,
5077                                                            iring->me,
5078                                                            iring->pipe,
5079                                                            0);
5080                         reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
5081                         gfx_v9_0_ring_set_pipe_percent(iring, reserve);
5082                 }
5083
5084                 for (i = 0; i < adev->gfx.num_compute_rings; ++i) {
5085                         iring = &adev->gfx.compute_ring[i];
5086                         pipe = amdgpu_gfx_mec_queue_to_bit(adev,
5087                                                            iring->me,
5088                                                            iring->pipe,
5089                                                            0);
5090                         reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
5091                         gfx_v9_0_ring_set_pipe_percent(iring, reserve);
5092                 }
5093         }
5094
5095         mutex_unlock(&adev->gfx.pipe_reserve_mutex);
5096 }
5097
5098 static void gfx_v9_0_hqd_set_priority(struct amdgpu_device *adev,
5099                                       struct amdgpu_ring *ring,
5100                                       bool acquire)
5101 {
5102         uint32_t pipe_priority = acquire ? 0x2 : 0x0;
5103         uint32_t queue_priority = acquire ? 0xf : 0x0;
5104
5105         mutex_lock(&adev->srbm_mutex);
5106         soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5107
5108         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PIPE_PRIORITY, pipe_priority);
5109         WREG32_SOC15_RLC(GC, 0, mmCP_HQD_QUEUE_PRIORITY, queue_priority);
5110
5111         soc15_grbm_select(adev, 0, 0, 0, 0);
5112         mutex_unlock(&adev->srbm_mutex);
5113 }
5114
5115 static void gfx_v9_0_ring_set_priority_compute(struct amdgpu_ring *ring,
5116                                                enum drm_sched_priority priority)
5117 {
5118         struct amdgpu_device *adev = ring->adev;
5119         bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW;
5120
5121         if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
5122                 return;
5123
5124         gfx_v9_0_hqd_set_priority(adev, ring, acquire);
5125         gfx_v9_0_pipe_reserve_resources(adev, ring, acquire);
5126 }
5127
5128 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
5129 {
5130         struct amdgpu_device *adev = ring->adev;
5131
5132         /* XXX check if swapping is necessary on BE */
5133         if (ring->use_doorbell) {
5134                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
5135                 WDOORBELL64(ring->doorbell_index, ring->wptr);
5136         } else{
5137                 BUG(); /* only DOORBELL method supported on gfx9 now */
5138         }
5139 }
5140
5141 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
5142                                          u64 seq, unsigned int flags)
5143 {
5144         struct amdgpu_device *adev = ring->adev;
5145
5146         /* we only allocate 32bit for each seq wb address */
5147         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
5148
5149         /* write fence seq to the "addr" */
5150         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5151         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5152                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
5153         amdgpu_ring_write(ring, lower_32_bits(addr));
5154         amdgpu_ring_write(ring, upper_32_bits(addr));
5155         amdgpu_ring_write(ring, lower_32_bits(seq));
5156
5157         if (flags & AMDGPU_FENCE_FLAG_INT) {
5158                 /* set register to trigger INT */
5159                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5160                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5161                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
5162                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
5163                 amdgpu_ring_write(ring, 0);
5164                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
5165         }
5166 }
5167
5168 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
5169 {
5170         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
5171         amdgpu_ring_write(ring, 0);
5172 }
5173
5174 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
5175 {
5176         struct v9_ce_ib_state ce_payload = {0};
5177         uint64_t csa_addr;
5178         int cnt;
5179
5180         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
5181         csa_addr = amdgpu_csa_vaddr(ring->adev);
5182
5183         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
5184         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
5185                                  WRITE_DATA_DST_SEL(8) |
5186                                  WR_CONFIRM) |
5187                                  WRITE_DATA_CACHE_POLICY(0));
5188         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
5189         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
5190         amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
5191 }
5192
5193 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
5194 {
5195         struct v9_de_ib_state de_payload = {0};
5196         uint64_t csa_addr, gds_addr;
5197         int cnt;
5198
5199         csa_addr = amdgpu_csa_vaddr(ring->adev);
5200         gds_addr = csa_addr + 4096;
5201         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
5202         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
5203
5204         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
5205         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
5206         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5207                                  WRITE_DATA_DST_SEL(8) |
5208                                  WR_CONFIRM) |
5209                                  WRITE_DATA_CACHE_POLICY(0));
5210         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
5211         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
5212         amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
5213 }
5214
5215 static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
5216 {
5217         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
5218         amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
5219 }
5220
5221 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
5222 {
5223         uint32_t dw2 = 0;
5224
5225         if (amdgpu_sriov_vf(ring->adev))
5226                 gfx_v9_0_ring_emit_ce_meta(ring);
5227
5228         gfx_v9_0_ring_emit_tmz(ring, true);
5229
5230         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
5231         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
5232                 /* set load_global_config & load_global_uconfig */
5233                 dw2 |= 0x8001;
5234                 /* set load_cs_sh_regs */
5235                 dw2 |= 0x01000000;
5236                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
5237                 dw2 |= 0x10002;
5238
5239                 /* set load_ce_ram if preamble presented */
5240                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
5241                         dw2 |= 0x10000000;
5242         } else {
5243                 /* still load_ce_ram if this is the first time preamble presented
5244                  * although there is no context switch happens.
5245                  */
5246                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
5247                         dw2 |= 0x10000000;
5248         }
5249
5250         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5251         amdgpu_ring_write(ring, dw2);
5252         amdgpu_ring_write(ring, 0);
5253 }
5254
5255 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
5256 {
5257         unsigned ret;
5258         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
5259         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
5260         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
5261         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
5262         ret = ring->wptr & ring->buf_mask;
5263         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
5264         return ret;
5265 }
5266
5267 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
5268 {
5269         unsigned cur;
5270         BUG_ON(offset > ring->buf_mask);
5271         BUG_ON(ring->ring[offset] != 0x55aa55aa);
5272
5273         cur = (ring->wptr & ring->buf_mask) - 1;
5274         if (likely(cur > offset))
5275                 ring->ring[offset] = cur - offset;
5276         else
5277                 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
5278 }
5279
5280 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
5281 {
5282         struct amdgpu_device *adev = ring->adev;
5283         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
5284
5285         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
5286         amdgpu_ring_write(ring, 0 |     /* src: register*/
5287                                 (5 << 8) |      /* dst: memory */
5288                                 (1 << 20));     /* write confirm */
5289         amdgpu_ring_write(ring, reg);
5290         amdgpu_ring_write(ring, 0);
5291         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
5292                                 kiq->reg_val_offs * 4));
5293         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
5294                                 kiq->reg_val_offs * 4));
5295 }
5296
5297 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
5298                                     uint32_t val)
5299 {
5300         uint32_t cmd = 0;
5301
5302         switch (ring->funcs->type) {
5303         case AMDGPU_RING_TYPE_GFX:
5304                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
5305                 break;
5306         case AMDGPU_RING_TYPE_KIQ:
5307                 cmd = (1 << 16); /* no inc addr */
5308                 break;
5309         default:
5310                 cmd = WR_CONFIRM;
5311                 break;
5312         }
5313         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5314         amdgpu_ring_write(ring, cmd);
5315         amdgpu_ring_write(ring, reg);
5316         amdgpu_ring_write(ring, 0);
5317         amdgpu_ring_write(ring, val);
5318 }
5319
5320 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
5321                                         uint32_t val, uint32_t mask)
5322 {
5323         gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
5324 }
5325
5326 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
5327                                                   uint32_t reg0, uint32_t reg1,
5328                                                   uint32_t ref, uint32_t mask)
5329 {
5330         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
5331         struct amdgpu_device *adev = ring->adev;
5332         bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ?
5333                 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait;
5334
5335         if (fw_version_ok)
5336                 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
5337                                       ref, mask, 0x20);
5338         else
5339                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
5340                                                            ref, mask);
5341 }
5342
5343 static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
5344 {
5345         struct amdgpu_device *adev = ring->adev;
5346         uint32_t value = 0;
5347
5348         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
5349         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
5350         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
5351         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
5352         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
5353 }
5354
5355 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
5356                                                  enum amdgpu_interrupt_state state)
5357 {
5358         switch (state) {
5359         case AMDGPU_IRQ_STATE_DISABLE:
5360         case AMDGPU_IRQ_STATE_ENABLE:
5361                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5362                                TIME_STAMP_INT_ENABLE,
5363                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5364                 break;
5365         default:
5366                 break;
5367         }
5368 }
5369
5370 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
5371                                                      int me, int pipe,
5372                                                      enum amdgpu_interrupt_state state)
5373 {
5374         u32 mec_int_cntl, mec_int_cntl_reg;
5375
5376         /*
5377          * amdgpu controls only the first MEC. That's why this function only
5378          * handles the setting of interrupts for this specific MEC. All other
5379          * pipes' interrupts are set by amdkfd.
5380          */
5381
5382         if (me == 1) {
5383                 switch (pipe) {
5384                 case 0:
5385                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
5386                         break;
5387                 case 1:
5388                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
5389                         break;
5390                 case 2:
5391                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
5392                         break;
5393                 case 3:
5394                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
5395                         break;
5396                 default:
5397                         DRM_DEBUG("invalid pipe %d\n", pipe);
5398                         return;
5399                 }
5400         } else {
5401                 DRM_DEBUG("invalid me %d\n", me);
5402                 return;
5403         }
5404
5405         switch (state) {
5406         case AMDGPU_IRQ_STATE_DISABLE:
5407                 mec_int_cntl = RREG32(mec_int_cntl_reg);
5408                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5409                                              TIME_STAMP_INT_ENABLE, 0);
5410                 WREG32(mec_int_cntl_reg, mec_int_cntl);
5411                 break;
5412         case AMDGPU_IRQ_STATE_ENABLE:
5413                 mec_int_cntl = RREG32(mec_int_cntl_reg);
5414                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5415                                              TIME_STAMP_INT_ENABLE, 1);
5416                 WREG32(mec_int_cntl_reg, mec_int_cntl);
5417                 break;
5418         default:
5419                 break;
5420         }
5421 }
5422
5423 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
5424                                              struct amdgpu_irq_src *source,
5425                                              unsigned type,
5426                                              enum amdgpu_interrupt_state state)
5427 {
5428         switch (state) {
5429         case AMDGPU_IRQ_STATE_DISABLE:
5430         case AMDGPU_IRQ_STATE_ENABLE:
5431                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5432                                PRIV_REG_INT_ENABLE,
5433                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5434                 break;
5435         default:
5436                 break;
5437         }
5438
5439         return 0;
5440 }
5441
5442 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
5443                                               struct amdgpu_irq_src *source,
5444                                               unsigned type,
5445                                               enum amdgpu_interrupt_state state)
5446 {
5447         switch (state) {
5448         case AMDGPU_IRQ_STATE_DISABLE:
5449         case AMDGPU_IRQ_STATE_ENABLE:
5450                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5451                                PRIV_INSTR_INT_ENABLE,
5452                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5453         default:
5454                 break;
5455         }
5456
5457         return 0;
5458 }
5459
5460 #define ENABLE_ECC_ON_ME_PIPE(me, pipe)                         \
5461         WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\
5462                         CP_ECC_ERROR_INT_ENABLE, 1)
5463
5464 #define DISABLE_ECC_ON_ME_PIPE(me, pipe)                        \
5465         WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\
5466                         CP_ECC_ERROR_INT_ENABLE, 0)
5467
5468 static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev,
5469                                               struct amdgpu_irq_src *source,
5470                                               unsigned type,
5471                                               enum amdgpu_interrupt_state state)
5472 {
5473         switch (state) {
5474         case AMDGPU_IRQ_STATE_DISABLE:
5475                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5476                                 CP_ECC_ERROR_INT_ENABLE, 0);
5477                 DISABLE_ECC_ON_ME_PIPE(1, 0);
5478                 DISABLE_ECC_ON_ME_PIPE(1, 1);
5479                 DISABLE_ECC_ON_ME_PIPE(1, 2);
5480                 DISABLE_ECC_ON_ME_PIPE(1, 3);
5481                 break;
5482
5483         case AMDGPU_IRQ_STATE_ENABLE:
5484                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5485                                 CP_ECC_ERROR_INT_ENABLE, 1);
5486                 ENABLE_ECC_ON_ME_PIPE(1, 0);
5487                 ENABLE_ECC_ON_ME_PIPE(1, 1);
5488                 ENABLE_ECC_ON_ME_PIPE(1, 2);
5489                 ENABLE_ECC_ON_ME_PIPE(1, 3);
5490                 break;
5491         default:
5492                 break;
5493         }
5494
5495         return 0;
5496 }
5497
5498
5499 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
5500                                             struct amdgpu_irq_src *src,
5501                                             unsigned type,
5502                                             enum amdgpu_interrupt_state state)
5503 {
5504         switch (type) {
5505         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
5506                 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
5507                 break;
5508         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
5509                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
5510                 break;
5511         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
5512                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
5513                 break;
5514         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
5515                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
5516                 break;
5517         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
5518                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
5519                 break;
5520         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
5521                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
5522                 break;
5523         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
5524                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
5525                 break;
5526         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
5527                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
5528                 break;
5529         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
5530                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
5531                 break;
5532         default:
5533                 break;
5534         }
5535         return 0;
5536 }
5537
5538 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
5539                             struct amdgpu_irq_src *source,
5540                             struct amdgpu_iv_entry *entry)
5541 {
5542         int i;
5543         u8 me_id, pipe_id, queue_id;
5544         struct amdgpu_ring *ring;
5545
5546         DRM_DEBUG("IH: CP EOP\n");
5547         me_id = (entry->ring_id & 0x0c) >> 2;
5548         pipe_id = (entry->ring_id & 0x03) >> 0;
5549         queue_id = (entry->ring_id & 0x70) >> 4;
5550
5551         switch (me_id) {
5552         case 0:
5553                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
5554                 break;
5555         case 1:
5556         case 2:
5557                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5558                         ring = &adev->gfx.compute_ring[i];
5559                         /* Per-queue interrupt is supported for MEC starting from VI.
5560                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
5561                           */
5562                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
5563                                 amdgpu_fence_process(ring);
5564                 }
5565                 break;
5566         }
5567         return 0;
5568 }
5569
5570 static void gfx_v9_0_fault(struct amdgpu_device *adev,
5571                            struct amdgpu_iv_entry *entry)
5572 {
5573         u8 me_id, pipe_id, queue_id;
5574         struct amdgpu_ring *ring;
5575         int i;
5576
5577         me_id = (entry->ring_id & 0x0c) >> 2;
5578         pipe_id = (entry->ring_id & 0x03) >> 0;
5579         queue_id = (entry->ring_id & 0x70) >> 4;
5580
5581         switch (me_id) {
5582         case 0:
5583                 drm_sched_fault(&adev->gfx.gfx_ring[0].sched);
5584                 break;
5585         case 1:
5586         case 2:
5587                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5588                         ring = &adev->gfx.compute_ring[i];
5589                         if (ring->me == me_id && ring->pipe == pipe_id &&
5590                             ring->queue == queue_id)
5591                                 drm_sched_fault(&ring->sched);
5592                 }
5593                 break;
5594         }
5595 }
5596
5597 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
5598                                  struct amdgpu_irq_src *source,
5599                                  struct amdgpu_iv_entry *entry)
5600 {
5601         DRM_ERROR("Illegal register access in command stream\n");
5602         gfx_v9_0_fault(adev, entry);
5603         return 0;
5604 }
5605
5606 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
5607                                   struct amdgpu_irq_src *source,
5608                                   struct amdgpu_iv_entry *entry)
5609 {
5610         DRM_ERROR("Illegal instruction in command stream\n");
5611         gfx_v9_0_fault(adev, entry);
5612         return 0;
5613 }
5614
5615
5616 static const struct soc15_ras_field_entry gfx_v9_0_ras_fields[] = {
5617         { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT),
5618           SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT),
5619           SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT)
5620         },
5621         { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT),
5622           SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT),
5623           SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT)
5624         },
5625         { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
5626           SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME1),
5627           0, 0
5628         },
5629         { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
5630           SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME2),
5631           0, 0
5632         },
5633         { "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT),
5634           SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT),
5635           SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT)
5636         },
5637         { "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT),
5638           SOC15_REG_FIELD(CPG_EDC_DMA_CNT, ROQ_COUNT),
5639           0, 0
5640         },
5641         { "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT),
5642           SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_SEC_COUNT),
5643           SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_DED_COUNT)
5644         },
5645         { "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT),
5646           SOC15_REG_FIELD(CPG_EDC_TAG_CNT, SEC_COUNT),
5647           SOC15_REG_FIELD(CPG_EDC_TAG_CNT, DED_COUNT)
5648         },
5649         { "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
5650           SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, COUNT_ME1),
5651           0, 0
5652         },
5653         { "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
5654           SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, COUNT_ME1),
5655           0, 0
5656         },
5657         { "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT),
5658           SOC15_REG_FIELD(DC_EDC_STATE_CNT, COUNT_ME1),
5659           0, 0
5660         },
5661         { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT),
5662           SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC),
5663           SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED)
5664         },
5665         { "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT),
5666           SOC15_REG_FIELD(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED),
5667           0, 0
5668         },
5669         { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
5670           SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC),
5671           SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED)
5672         },
5673         { "GDS_OA_PHY_PHY_CMD_RAM_MEM",
5674           SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
5675           SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC),
5676           SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED)
5677         },
5678         { "GDS_OA_PHY_PHY_DATA_RAM_MEM",
5679           SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
5680           SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED),
5681           0, 0
5682         },
5683         { "GDS_OA_PIPE_ME1_PIPE0_PIPE_MEM",
5684           SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
5685           SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC),
5686           SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED)
5687         },
5688         { "GDS_OA_PIPE_ME1_PIPE1_PIPE_MEM",
5689           SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
5690           SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC),
5691           SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED)
5692         },
5693         { "GDS_OA_PIPE_ME1_PIPE2_PIPE_MEM",
5694           SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
5695           SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC),
5696           SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED)
5697         },
5698         { "GDS_OA_PIPE_ME1_PIPE3_PIPE_MEM",
5699           SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
5700           SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC),
5701           SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED)
5702         },
5703         { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
5704           SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT),
5705           0, 0
5706         },
5707         { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
5708           SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT),
5709           SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT)
5710         },
5711         { "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
5712           SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT),
5713           0, 0
5714         },
5715         { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
5716           SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT),
5717           0, 0
5718         },
5719         { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
5720           SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT),
5721           0, 0
5722         },
5723         { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
5724           SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT),
5725           0, 0
5726         },
5727         { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT),
5728           SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT),
5729           0, 0
5730         },
5731         { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT),
5732           SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SED_COUNT),
5733           0, 0
5734         },
5735         { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
5736           SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT),
5737           SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT)
5738         },
5739         { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
5740           SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT),
5741           SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT)
5742         },
5743         { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
5744           SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT),
5745           SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT)
5746         },
5747         { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
5748           SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT),
5749           SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT)
5750         },
5751         { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
5752           SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT),
5753           SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT)
5754         },
5755         { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
5756           SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT),
5757           0, 0
5758         },
5759         { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
5760           SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT),
5761           0, 0
5762         },
5763         { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
5764           SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT),
5765           0, 0
5766         },
5767         { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
5768           SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_DATA_SED_COUNT),
5769           0, 0
5770         },
5771         { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
5772           SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT),
5773           0, 0
5774         },
5775         { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
5776           SOC15_REG_FIELD(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT),
5777           0, 0
5778         },
5779         { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
5780           SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT),
5781           0, 0
5782         },
5783         { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
5784           SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT),
5785           0, 0
5786         },
5787         { "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
5788           SOC15_REG_FIELD(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT),
5789           0, 0
5790         },
5791         { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
5792           SOC15_REG_FIELD(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT),
5793           0, 0
5794         },
5795         { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
5796           SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT),
5797           0, 0
5798         },
5799         { "TCC_WRRET_TAG_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
5800           SOC15_REG_FIELD(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT),
5801           0, 0
5802         },
5803         { "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
5804           SOC15_REG_FIELD(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT),
5805           0, 0
5806         },
5807         { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT),
5808           SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SED_COUNT),
5809           0, 0
5810         },
5811         { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
5812           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT),
5813           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT)
5814         },
5815         { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
5816           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT),
5817           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT)
5818         },
5819         { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
5820           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT),
5821           0, 0
5822         },
5823         { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
5824           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT),
5825           0, 0
5826         },
5827         { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
5828           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT),
5829           0, 0
5830         },
5831         { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
5832           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT),
5833           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT)
5834         },
5835         { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
5836           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT),
5837           SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT)
5838         },
5839         { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
5840           SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT),
5841           SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT)
5842         },
5843         { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
5844           SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT),
5845           SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT)
5846         },
5847         { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
5848           SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SED_COUNT),
5849           0, 0
5850         },
5851         { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
5852           SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT),
5853           SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT)
5854         },
5855         { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
5856           SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT),
5857           SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT)
5858         },
5859         { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
5860           SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT),
5861           SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT)
5862         },
5863         { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
5864           SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT),
5865           SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT)
5866         },
5867         { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
5868           SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT),
5869           SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT)
5870         },
5871         { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
5872           SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT),
5873           SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT)
5874         },
5875         { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
5876           SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT),
5877           SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT)
5878         },
5879         { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
5880           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT),
5881           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT)
5882         },
5883         { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
5884           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT),
5885           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT)
5886         },
5887         { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
5888           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT),
5889           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT)
5890         },
5891         { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
5892           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT),
5893           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT)
5894         },
5895         { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
5896           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT),
5897           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT)
5898         },
5899         { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
5900           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT),
5901           SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT)
5902         },
5903         { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
5904           SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT),
5905           SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT)
5906         },
5907         { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
5908           SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT),
5909           SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT)
5910         },
5911         { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
5912           SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT),
5913           SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT)
5914         },
5915         { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
5916           SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT),
5917           SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT)
5918         },
5919         { "SQC_INST_BANKA_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
5920           SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT),
5921           0, 0
5922         },
5923         { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
5924           SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT),
5925           0, 0
5926         },
5927         { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
5928           SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT),
5929           0, 0
5930         },
5931         { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
5932           SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT),
5933           0, 0
5934         },
5935         { "SQC_DATA_BANKA_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
5936           SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT),
5937           0, 0
5938         },
5939         { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
5940           SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT),
5941           SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT)
5942         },
5943         { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
5944           SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT),
5945           SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT)
5946         },
5947         { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
5948           SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT),
5949           SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT)
5950         },
5951         { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
5952           SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT),
5953           SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT)
5954         },
5955         { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
5956           SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT),
5957           SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT)
5958         },
5959         { "SQC_INST_BANKB_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
5960           SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT),
5961           0, 0
5962         },
5963         { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
5964           SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT),
5965           0, 0
5966         },
5967         { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
5968           SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT),
5969           0, 0
5970         },
5971         { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
5972           SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT),
5973           0, 0
5974         },
5975         { "SQC_DATA_BANKB_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
5976           SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT),
5977           0, 0
5978         },
5979         { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
5980           SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
5981           SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT)
5982         },
5983         { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
5984           SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
5985           SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT)
5986         },
5987         { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
5988           SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
5989           SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT)
5990         },
5991         { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
5992           SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
5993           SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT)
5994         },
5995         { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
5996           SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
5997           SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT)
5998         },
5999         { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6000           SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
6001           0, 0
6002         },
6003         { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6004           SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
6005           0, 0
6006         },
6007         { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6008           SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT),
6009           0, 0
6010         },
6011         { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6012           SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
6013           0, 0
6014         },
6015         { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6016           SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
6017           0, 0
6018         },
6019         { "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6020           SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
6021           SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT)
6022         },
6023         { "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6024           SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
6025           SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT)
6026         },
6027         { "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6028           SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
6029           SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT)
6030         },
6031         { "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6032           SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
6033           0, 0
6034         },
6035         { "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6036           SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
6037           0, 0
6038         },
6039         { "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6040           SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT),
6041           0, 0
6042         },
6043         { "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6044           SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT),
6045           0, 0
6046         },
6047         { "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6048           SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT),
6049           0, 0
6050         },
6051         { "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6052           SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT),
6053           0, 0
6054         }
6055 };
6056
6057 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
6058                                      void *inject_if)
6059 {
6060         struct ras_inject_if *info = (struct ras_inject_if *)inject_if;
6061         int ret;
6062         struct ta_ras_trigger_error_input block_info = { 0 };
6063
6064         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
6065                 return -EINVAL;
6066
6067         if (info->head.sub_block_index >= ARRAY_SIZE(ras_gfx_subblocks))
6068                 return -EINVAL;
6069
6070         if (!ras_gfx_subblocks[info->head.sub_block_index].name)
6071                 return -EPERM;
6072
6073         if (!(ras_gfx_subblocks[info->head.sub_block_index].hw_supported_error_type &
6074               info->head.type)) {
6075                 DRM_ERROR("GFX Subblock %s, hardware do not support type 0x%x\n",
6076                         ras_gfx_subblocks[info->head.sub_block_index].name,
6077                         info->head.type);
6078                 return -EPERM;
6079         }
6080
6081         if (!(ras_gfx_subblocks[info->head.sub_block_index].sw_supported_error_type &
6082               info->head.type)) {
6083                 DRM_ERROR("GFX Subblock %s, driver do not support type 0x%x\n",
6084                         ras_gfx_subblocks[info->head.sub_block_index].name,
6085                         info->head.type);
6086                 return -EPERM;
6087         }
6088
6089         block_info.block_id = amdgpu_ras_block_to_ta(info->head.block);
6090         block_info.sub_block_index =
6091                 ras_gfx_subblocks[info->head.sub_block_index].ta_subblock;
6092         block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type);
6093         block_info.address = info->address;
6094         block_info.value = info->value;
6095
6096         mutex_lock(&adev->grbm_idx_mutex);
6097         ret = psp_ras_trigger_error(&adev->psp, &block_info);
6098         mutex_unlock(&adev->grbm_idx_mutex);
6099
6100         return ret;
6101 }
6102
6103 static const char *vml2_mems[] = {
6104         "UTC_VML2_BANK_CACHE_0_BIGK_MEM0",
6105         "UTC_VML2_BANK_CACHE_0_BIGK_MEM1",
6106         "UTC_VML2_BANK_CACHE_0_4K_MEM0",
6107         "UTC_VML2_BANK_CACHE_0_4K_MEM1",
6108         "UTC_VML2_BANK_CACHE_1_BIGK_MEM0",
6109         "UTC_VML2_BANK_CACHE_1_BIGK_MEM1",
6110         "UTC_VML2_BANK_CACHE_1_4K_MEM0",
6111         "UTC_VML2_BANK_CACHE_1_4K_MEM1",
6112         "UTC_VML2_BANK_CACHE_2_BIGK_MEM0",
6113         "UTC_VML2_BANK_CACHE_2_BIGK_MEM1",
6114         "UTC_VML2_BANK_CACHE_2_4K_MEM0",
6115         "UTC_VML2_BANK_CACHE_2_4K_MEM1",
6116         "UTC_VML2_BANK_CACHE_3_BIGK_MEM0",
6117         "UTC_VML2_BANK_CACHE_3_BIGK_MEM1",
6118         "UTC_VML2_BANK_CACHE_3_4K_MEM0",
6119         "UTC_VML2_BANK_CACHE_3_4K_MEM1",
6120 };
6121
6122 static const char *vml2_walker_mems[] = {
6123         "UTC_VML2_CACHE_PDE0_MEM0",
6124         "UTC_VML2_CACHE_PDE0_MEM1",
6125         "UTC_VML2_CACHE_PDE1_MEM0",
6126         "UTC_VML2_CACHE_PDE1_MEM1",
6127         "UTC_VML2_CACHE_PDE2_MEM0",
6128         "UTC_VML2_CACHE_PDE2_MEM1",
6129         "UTC_VML2_RDIF_LOG_FIFO",
6130 };
6131
6132 static const char *atc_l2_cache_2m_mems[] = {
6133         "UTC_ATCL2_CACHE_2M_BANK0_WAY0_MEM",
6134         "UTC_ATCL2_CACHE_2M_BANK0_WAY1_MEM",
6135         "UTC_ATCL2_CACHE_2M_BANK1_WAY0_MEM",
6136         "UTC_ATCL2_CACHE_2M_BANK1_WAY1_MEM",
6137 };
6138
6139 static const char *atc_l2_cache_4k_mems[] = {
6140         "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0",
6141         "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1",
6142         "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2",
6143         "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3",
6144         "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4",
6145         "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5",
6146         "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6",
6147         "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7",
6148         "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0",
6149         "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1",
6150         "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2",
6151         "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3",
6152         "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4",
6153         "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5",
6154         "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6",
6155         "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7",
6156         "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0",
6157         "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1",
6158         "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2",
6159         "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3",
6160         "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4",
6161         "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5",
6162         "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6",
6163         "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7",
6164         "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0",
6165         "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1",
6166         "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2",
6167         "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3",
6168         "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4",
6169         "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5",
6170         "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6",
6171         "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7",
6172 };
6173
6174 static int gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev,
6175                                          struct ras_err_data *err_data)
6176 {
6177         uint32_t i, data;
6178         uint32_t sec_count, ded_count;
6179
6180         WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255);
6181         WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0);
6182         WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255);
6183         WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0);
6184         WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255);
6185         WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0);
6186         WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255);
6187         WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0);
6188
6189         for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) {
6190                 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i);
6191                 data = RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT);
6192
6193                 sec_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, SEC_COUNT);
6194                 if (sec_count) {
6195                         DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
6196                                  vml2_mems[i], sec_count);
6197                         err_data->ce_count += sec_count;
6198                 }
6199
6200                 ded_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, DED_COUNT);
6201                 if (ded_count) {
6202                         DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,
6203                                  vml2_mems[i], ded_count);
6204                         err_data->ue_count += ded_count;
6205                 }
6206         }
6207
6208         for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) {
6209                 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i);
6210                 data = RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT);
6211
6212                 sec_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT,
6213                                                 SEC_COUNT);
6214                 if (sec_count) {
6215                         DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
6216                                  vml2_walker_mems[i], sec_count);
6217                         err_data->ce_count += sec_count;
6218                 }
6219
6220                 ded_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT,
6221                                                 DED_COUNT);
6222                 if (ded_count) {
6223                         DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,
6224                                  vml2_walker_mems[i], ded_count);
6225                         err_data->ue_count += ded_count;
6226                 }
6227         }
6228
6229         for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) {
6230                 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i);
6231                 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT);
6232
6233                 sec_count = (data & 0x00006000L) >> 0xd;
6234                 if (sec_count) {
6235                         DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
6236                                  atc_l2_cache_2m_mems[i], sec_count);
6237                         err_data->ce_count += sec_count;
6238                 }
6239         }
6240
6241         for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) {
6242                 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i);
6243                 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT);
6244
6245                 sec_count = (data & 0x00006000L) >> 0xd;
6246                 if (sec_count) {
6247                         DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
6248                                  atc_l2_cache_4k_mems[i], sec_count);
6249                         err_data->ce_count += sec_count;
6250                 }
6251
6252                 ded_count = (data & 0x00018000L) >> 0xf;
6253                 if (ded_count) {
6254                         DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,
6255                                  atc_l2_cache_4k_mems[i], ded_count);
6256                         err_data->ue_count += ded_count;
6257                 }
6258         }
6259
6260         WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255);
6261         WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255);
6262         WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255);
6263         WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255);
6264
6265         return 0;
6266 }
6267
6268 static int gfx_v9_0_ras_error_count(const struct soc15_reg_entry *reg,
6269         uint32_t se_id, uint32_t inst_id, uint32_t value,
6270         uint32_t *sec_count, uint32_t *ded_count)
6271 {
6272         uint32_t i;
6273         uint32_t sec_cnt, ded_cnt;
6274
6275         for (i = 0; i < ARRAY_SIZE(gfx_v9_0_ras_fields); i++) {
6276                 if(gfx_v9_0_ras_fields[i].reg_offset != reg->reg_offset ||
6277                         gfx_v9_0_ras_fields[i].seg != reg->seg ||
6278                         gfx_v9_0_ras_fields[i].inst != reg->inst)
6279                         continue;
6280
6281                 sec_cnt = (value &
6282                                 gfx_v9_0_ras_fields[i].sec_count_mask) >>
6283                                 gfx_v9_0_ras_fields[i].sec_count_shift;
6284                 if (sec_cnt) {
6285                         DRM_INFO("GFX SubBlock %s, Instance[%d][%d], SEC %d\n",
6286                                 gfx_v9_0_ras_fields[i].name,
6287                                 se_id, inst_id,
6288                                 sec_cnt);
6289                         *sec_count += sec_cnt;
6290                 }
6291
6292                 ded_cnt = (value &
6293                                 gfx_v9_0_ras_fields[i].ded_count_mask) >>
6294                                 gfx_v9_0_ras_fields[i].ded_count_shift;
6295                 if (ded_cnt) {
6296                         DRM_INFO("GFX SubBlock %s, Instance[%d][%d], DED %d\n",
6297                                 gfx_v9_0_ras_fields[i].name,
6298                                 se_id, inst_id,
6299                                 ded_cnt);
6300                         *ded_count += ded_cnt;
6301                 }
6302         }
6303
6304         return 0;
6305 }
6306
6307 static void gfx_v9_0_clear_ras_edc_counter(struct amdgpu_device *adev)
6308 {
6309         int i, j, k;
6310
6311         /* read back registers to clear the counters */
6312         mutex_lock(&adev->grbm_idx_mutex);
6313         for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) {
6314                 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) {
6315                         for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) {
6316                                 gfx_v9_0_select_se_sh(adev, j, 0x0, k);
6317                                 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i]));
6318                         }
6319                 }
6320         }
6321         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
6322         mutex_unlock(&adev->grbm_idx_mutex);
6323
6324         WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255);
6325         WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0);
6326         WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255);
6327         WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0);
6328         WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255);
6329         WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0);
6330         WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255);
6331         WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0);
6332
6333         for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) {
6334                 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i);
6335                 RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT);
6336         }
6337
6338         for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) {
6339                 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i);
6340                 RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT);
6341         }
6342
6343         for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) {
6344                 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i);
6345                 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT);
6346         }
6347
6348         for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) {
6349                 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i);
6350                 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT);
6351         }
6352
6353         WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255);
6354         WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255);
6355         WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255);
6356         WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255);
6357 }
6358
6359 static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
6360                                           void *ras_error_status)
6361 {
6362         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
6363         uint32_t sec_count = 0, ded_count = 0;
6364         uint32_t i, j, k;
6365         uint32_t reg_value;
6366
6367         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
6368                 return -EINVAL;
6369
6370         err_data->ue_count = 0;
6371         err_data->ce_count = 0;
6372
6373         mutex_lock(&adev->grbm_idx_mutex);
6374
6375         for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) {
6376                 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) {
6377                         for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) {
6378                                 gfx_v9_0_select_se_sh(adev, j, 0, k);
6379                                 reg_value =
6380                                         RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i]));
6381                                 if (reg_value)
6382                                         gfx_v9_0_ras_error_count(&gfx_v9_0_edc_counter_regs[i],
6383                                                         j, k, reg_value,
6384                                                         &sec_count, &ded_count);
6385                         }
6386                 }
6387         }
6388
6389         err_data->ce_count += sec_count;
6390         err_data->ue_count += ded_count;
6391
6392         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
6393         mutex_unlock(&adev->grbm_idx_mutex);
6394
6395         gfx_v9_0_query_utc_edc_status(adev, err_data);
6396
6397         return 0;
6398 }
6399
6400 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
6401         .name = "gfx_v9_0",
6402         .early_init = gfx_v9_0_early_init,
6403         .late_init = gfx_v9_0_late_init,
6404         .sw_init = gfx_v9_0_sw_init,
6405         .sw_fini = gfx_v9_0_sw_fini,
6406         .hw_init = gfx_v9_0_hw_init,
6407         .hw_fini = gfx_v9_0_hw_fini,
6408         .suspend = gfx_v9_0_suspend,
6409         .resume = gfx_v9_0_resume,
6410         .is_idle = gfx_v9_0_is_idle,
6411         .wait_for_idle = gfx_v9_0_wait_for_idle,
6412         .soft_reset = gfx_v9_0_soft_reset,
6413         .set_clockgating_state = gfx_v9_0_set_clockgating_state,
6414         .set_powergating_state = gfx_v9_0_set_powergating_state,
6415         .get_clockgating_state = gfx_v9_0_get_clockgating_state,
6416 };
6417
6418 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
6419         .type = AMDGPU_RING_TYPE_GFX,
6420         .align_mask = 0xff,
6421         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6422         .support_64bit_ptrs = true,
6423         .vmhub = AMDGPU_GFXHUB_0,
6424         .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
6425         .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
6426         .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
6427         .emit_frame_size = /* totally 242 maximum if 16 IBs */
6428                 5 +  /* COND_EXEC */
6429                 7 +  /* PIPELINE_SYNC */
6430                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6431                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6432                 2 + /* VM_FLUSH */
6433                 8 +  /* FENCE for VM_FLUSH */
6434                 20 + /* GDS switch */
6435                 4 + /* double SWITCH_BUFFER,
6436                        the first COND_EXEC jump to the place just
6437                            prior to this double SWITCH_BUFFER  */
6438                 5 + /* COND_EXEC */
6439                 7 +      /*     HDP_flush */
6440                 4 +      /*     VGT_flush */
6441                 14 + /* CE_META */
6442                 31 + /* DE_META */
6443                 3 + /* CNTX_CTRL */
6444                 5 + /* HDP_INVL */
6445                 8 + 8 + /* FENCE x2 */
6446                 2, /* SWITCH_BUFFER */
6447         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
6448         .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
6449         .emit_fence = gfx_v9_0_ring_emit_fence,
6450         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
6451         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
6452         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
6453         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
6454         .test_ring = gfx_v9_0_ring_test_ring,
6455         .test_ib = gfx_v9_0_ring_test_ib,
6456         .insert_nop = amdgpu_ring_insert_nop,
6457         .pad_ib = amdgpu_ring_generic_pad_ib,
6458         .emit_switch_buffer = gfx_v9_ring_emit_sb,
6459         .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
6460         .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
6461         .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
6462         .emit_tmz = gfx_v9_0_ring_emit_tmz,
6463         .emit_wreg = gfx_v9_0_ring_emit_wreg,
6464         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
6465         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
6466         .soft_recovery = gfx_v9_0_ring_soft_recovery,
6467 };
6468
6469 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
6470         .type = AMDGPU_RING_TYPE_COMPUTE,
6471         .align_mask = 0xff,
6472         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6473         .support_64bit_ptrs = true,
6474         .vmhub = AMDGPU_GFXHUB_0,
6475         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
6476         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
6477         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
6478         .emit_frame_size =
6479                 20 + /* gfx_v9_0_ring_emit_gds_switch */
6480                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
6481                 5 + /* hdp invalidate */
6482                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
6483                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6484                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6485                 2 + /* gfx_v9_0_ring_emit_vm_flush */
6486                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
6487         .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */
6488         .emit_ib = gfx_v9_0_ring_emit_ib_compute,
6489         .emit_fence = gfx_v9_0_ring_emit_fence,
6490         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
6491         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
6492         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
6493         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
6494         .test_ring = gfx_v9_0_ring_test_ring,
6495         .test_ib = gfx_v9_0_ring_test_ib,
6496         .insert_nop = amdgpu_ring_insert_nop,
6497         .pad_ib = amdgpu_ring_generic_pad_ib,
6498         .set_priority = gfx_v9_0_ring_set_priority_compute,
6499         .emit_wreg = gfx_v9_0_ring_emit_wreg,
6500         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
6501         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
6502 };
6503
6504 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
6505         .type = AMDGPU_RING_TYPE_KIQ,
6506         .align_mask = 0xff,
6507         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6508         .support_64bit_ptrs = true,
6509         .vmhub = AMDGPU_GFXHUB_0,
6510         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
6511         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
6512         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
6513         .emit_frame_size =
6514                 20 + /* gfx_v9_0_ring_emit_gds_switch */
6515                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
6516                 5 + /* hdp invalidate */
6517                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
6518                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6519                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6520                 2 + /* gfx_v9_0_ring_emit_vm_flush */
6521                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
6522         .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */
6523         .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
6524         .test_ring = gfx_v9_0_ring_test_ring,
6525         .insert_nop = amdgpu_ring_insert_nop,
6526         .pad_ib = amdgpu_ring_generic_pad_ib,
6527         .emit_rreg = gfx_v9_0_ring_emit_rreg,
6528         .emit_wreg = gfx_v9_0_ring_emit_wreg,
6529         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
6530         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
6531 };
6532
6533 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
6534 {
6535         int i;
6536
6537         adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
6538
6539         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6540                 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
6541
6542         for (i = 0; i < adev->gfx.num_compute_rings; i++)
6543                 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
6544 }
6545
6546 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
6547         .set = gfx_v9_0_set_eop_interrupt_state,
6548         .process = gfx_v9_0_eop_irq,
6549 };
6550
6551 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
6552         .set = gfx_v9_0_set_priv_reg_fault_state,
6553         .process = gfx_v9_0_priv_reg_irq,
6554 };
6555
6556 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
6557         .set = gfx_v9_0_set_priv_inst_fault_state,
6558         .process = gfx_v9_0_priv_inst_irq,
6559 };
6560
6561 static const struct amdgpu_irq_src_funcs gfx_v9_0_cp_ecc_error_irq_funcs = {
6562         .set = gfx_v9_0_set_cp_ecc_error_state,
6563         .process = amdgpu_gfx_cp_ecc_error_irq,
6564 };
6565
6566
6567 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
6568 {
6569         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
6570         adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
6571
6572         adev->gfx.priv_reg_irq.num_types = 1;
6573         adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
6574
6575         adev->gfx.priv_inst_irq.num_types = 1;
6576         adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
6577
6578         adev->gfx.cp_ecc_error_irq.num_types = 2; /*C5 ECC error and C9 FUE error*/
6579         adev->gfx.cp_ecc_error_irq.funcs = &gfx_v9_0_cp_ecc_error_irq_funcs;
6580 }
6581
6582 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
6583 {
6584         switch (adev->asic_type) {
6585         case CHIP_VEGA10:
6586         case CHIP_VEGA12:
6587         case CHIP_VEGA20:
6588         case CHIP_RAVEN:
6589         case CHIP_ARCTURUS:
6590         case CHIP_RENOIR:
6591                 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
6592                 break;
6593         default:
6594                 break;
6595         }
6596 }
6597
6598 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
6599 {
6600         /* init asci gds info */
6601         switch (adev->asic_type) {
6602         case CHIP_VEGA10:
6603         case CHIP_VEGA12:
6604         case CHIP_VEGA20:
6605                 adev->gds.gds_size = 0x10000;
6606                 break;
6607         case CHIP_RAVEN:
6608         case CHIP_ARCTURUS:
6609                 adev->gds.gds_size = 0x1000;
6610                 break;
6611         default:
6612                 adev->gds.gds_size = 0x10000;
6613                 break;
6614         }
6615
6616         switch (adev->asic_type) {
6617         case CHIP_VEGA10:
6618         case CHIP_VEGA20:
6619                 adev->gds.gds_compute_max_wave_id = 0x7ff;
6620                 break;
6621         case CHIP_VEGA12:
6622                 adev->gds.gds_compute_max_wave_id = 0x27f;
6623                 break;
6624         case CHIP_RAVEN:
6625                 if (adev->rev_id >= 0x8)
6626                         adev->gds.gds_compute_max_wave_id = 0x77; /* raven2 */
6627                 else
6628                         adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */
6629                 break;
6630         case CHIP_ARCTURUS:
6631                 adev->gds.gds_compute_max_wave_id = 0xfff;
6632                 break;
6633         default:
6634                 /* this really depends on the chip */
6635                 adev->gds.gds_compute_max_wave_id = 0x7ff;
6636                 break;
6637         }
6638
6639         adev->gds.gws_size = 64;
6640         adev->gds.oa_size = 16;
6641 }
6642
6643 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
6644                                                  u32 bitmap)
6645 {
6646         u32 data;
6647
6648         if (!bitmap)
6649                 return;
6650
6651         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
6652         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
6653
6654         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
6655 }
6656
6657 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
6658 {
6659         u32 data, mask;
6660
6661         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
6662         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
6663
6664         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
6665         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
6666
6667         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
6668
6669         return (~data) & mask;
6670 }
6671
6672 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
6673                                  struct amdgpu_cu_info *cu_info)
6674 {
6675         int i, j, k, counter, active_cu_number = 0;
6676         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
6677         unsigned disable_masks[4 * 4];
6678
6679         if (!adev || !cu_info)
6680                 return -EINVAL;
6681
6682         /*
6683          * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs
6684          */
6685         if (adev->gfx.config.max_shader_engines *
6686                 adev->gfx.config.max_sh_per_se > 16)
6687                 return -EINVAL;
6688
6689         amdgpu_gfx_parse_disable_cu(disable_masks,
6690                                     adev->gfx.config.max_shader_engines,
6691                                     adev->gfx.config.max_sh_per_se);
6692
6693         mutex_lock(&adev->grbm_idx_mutex);
6694         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
6695                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
6696                         mask = 1;
6697                         ao_bitmap = 0;
6698                         counter = 0;
6699                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
6700                         gfx_v9_0_set_user_cu_inactive_bitmap(
6701                                 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]);
6702                         bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
6703
6704                         /*
6705                          * The bitmap(and ao_cu_bitmap) in cu_info structure is
6706                          * 4x4 size array, and it's usually suitable for Vega
6707                          * ASICs which has 4*2 SE/SH layout.
6708                          * But for Arcturus, SE/SH layout is changed to 8*1.
6709                          * To mostly reduce the impact, we make it compatible
6710                          * with current bitmap array as below:
6711                          *    SE4,SH0 --> bitmap[0][1]
6712                          *    SE5,SH0 --> bitmap[1][1]
6713                          *    SE6,SH0 --> bitmap[2][1]
6714                          *    SE7,SH0 --> bitmap[3][1]
6715                          */
6716                         cu_info->bitmap[i % 4][j + i / 4] = bitmap;
6717
6718                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
6719                                 if (bitmap & mask) {
6720                                         if (counter < adev->gfx.config.max_cu_per_sh)
6721                                                 ao_bitmap |= mask;
6722                                         counter ++;
6723                                 }
6724                                 mask <<= 1;
6725                         }
6726                         active_cu_number += counter;
6727                         if (i < 2 && j < 2)
6728                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
6729                         cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap;
6730                 }
6731         }
6732         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
6733         mutex_unlock(&adev->grbm_idx_mutex);
6734
6735         cu_info->number = active_cu_number;
6736         cu_info->ao_cu_mask = ao_cu_mask;
6737         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
6738
6739         return 0;
6740 }
6741
6742 const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
6743 {
6744         .type = AMD_IP_BLOCK_TYPE_GFX,
6745         .major = 9,
6746         .minor = 0,
6747         .rev = 0,
6748         .funcs = &gfx_v9_0_ip_funcs,
6749 };