drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/kernel.h>
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_gfx.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "amdgpu_atomfirmware.h"
  31
  32 #include "gc/gc_9_0_offset.h"
  33 #include "gc/gc_9_0_sh_mask.h"
  34 #include "vega10_enum.h"
  35 #include "hdp/hdp_4_0_offset.h"
  36
  37 #include "soc15_common.h"
  38 #include "clearstate_gfx9.h"
  39 #include "v9_structs.h"
  40
  41 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
  42
  43 #define GFX9_NUM_GFX_RINGS     1
  44 #define GFX9_MEC_HPD_SIZE 2048
  45 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
  46 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
  47
  48 #define mmPWR_MISC_CNTL_STATUS                                  0x0183
  49 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX                         0
  50 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT        0x0
  51 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT          0x1
  52 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK          0x00000001L
  53 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK            0x00000006L
  54
  55 MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
  56 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
  57 MODULE_FIRMWARE("amdgpu/vega10_me.bin");
  58 MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
  59 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
  60 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
  61
  62 MODULE_FIRMWARE("amdgpu/vega12_ce.bin");
  63 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin");
  64 MODULE_FIRMWARE("amdgpu/vega12_me.bin");
  65 MODULE_FIRMWARE("amdgpu/vega12_mec.bin");
  66 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin");
  67 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin");
  68
  69 MODULE_FIRMWARE("amdgpu/vega20_ce.bin");
  70 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin");
  71 MODULE_FIRMWARE("amdgpu/vega20_me.bin");
  72 MODULE_FIRMWARE("amdgpu/vega20_mec.bin");
  73 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin");
  74 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin");
  75
  76 MODULE_FIRMWARE("amdgpu/raven_ce.bin");
  77 MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
  78 MODULE_FIRMWARE("amdgpu/raven_me.bin");
  79 MODULE_FIRMWARE("amdgpu/raven_mec.bin");
  80 MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
  81 MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
  82
  83 MODULE_FIRMWARE("amdgpu/picasso_ce.bin");
  84 MODULE_FIRMWARE("amdgpu/picasso_pfp.bin");
  85 MODULE_FIRMWARE("amdgpu/picasso_me.bin");
  86 MODULE_FIRMWARE("amdgpu/picasso_mec.bin");
  87 MODULE_FIRMWARE("amdgpu/picasso_mec2.bin");
  88 MODULE_FIRMWARE("amdgpu/picasso_rlc.bin");
  89
  90 MODULE_FIRMWARE("amdgpu/raven2_ce.bin");
  91 MODULE_FIRMWARE("amdgpu/raven2_pfp.bin");
  92 MODULE_FIRMWARE("amdgpu/raven2_me.bin");
  93 MODULE_FIRMWARE("amdgpu/raven2_mec.bin");
  94 MODULE_FIRMWARE("amdgpu/raven2_mec2.bin");
  95 MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
  96
  97 static const struct soc15_reg_golden golden_settings_gc_9_0[] =
  98 {
  99         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
 100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
 110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
 112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
 113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
 115 };
 116
 117 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
 118 {
 119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107),
 120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
 122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
 123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
 124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
 125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042),
 126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
 127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000),
 128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
 129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
 130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
 131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
 132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
 133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
 134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107),
 135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800),
 136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080),
 137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
 138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
 139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
 140 };
 141
 142 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] =
 143 {
 144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080),
 145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
 146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042),
 148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042),
 149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400),
 150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000),
 151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000),
 152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107),
 153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000),
 154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000)
 155 };
 156
 157 static const struct soc15_reg_golden golden_settings_gc_9_1[] =
 158 {
 159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
 161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
 162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
 163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
 164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
 166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
 170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
 171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
 172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
 173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
 174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
 177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
 179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080),
 180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
 181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
 182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
 183 };
 184
 185 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] =
 186 {
 187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042),
 189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042),
 190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000),
 191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000),
 192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
 193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800)
 194 };
 195
 196 static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] =
 197 {
 198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000),
 199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000),
 201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080),
 202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080),
 203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080),
 204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041),
 205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041),
 206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
 207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
 208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080),
 209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080),
 210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080),
 211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080),
 212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080),
 213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010),
 215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000),
 216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
 217 };
 218
 219 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] =
 220 {
 221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000),
 222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382)
 223 };
 224
 225 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] =
 226 {
 227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
 228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
 233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
 234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
 235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
 236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
 237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
 238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
 240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
 241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
 243 };
 244
 245 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] =
 246 {
 247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080),
 248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
 260 };
 261
 262 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
 263 {
 264         mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 265         mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 266         mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 267         mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 268         mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 269         mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 270         mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 271         mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 272 };
 273
 274 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
 275 {
 276         mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 277         mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 278         mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 279         mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 280         mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 281         mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 282         mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 283         mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 284 };
 285
 286 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
 287 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041
 288 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
 289 #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041
 290
 291 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
 292 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
 293 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
 294 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
 295 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
 296                                  struct amdgpu_cu_info *cu_info);
 297 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 298 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
 299 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
 300
 301 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
 302 {
 303         switch (adev->asic_type) {
 304         case CHIP_VEGA10:
 305                 soc15_program_register_sequence(adev,
 306                                                  golden_settings_gc_9_0,
 307                                                  ARRAY_SIZE(golden_settings_gc_9_0));
 308                 soc15_program_register_sequence(adev,
 309                                                  golden_settings_gc_9_0_vg10,
 310                                                  ARRAY_SIZE(golden_settings_gc_9_0_vg10));
 311                 break;
 312         case CHIP_VEGA12:
 313                 soc15_program_register_sequence(adev,
 314                                                 golden_settings_gc_9_2_1,
 315                                                 ARRAY_SIZE(golden_settings_gc_9_2_1));
 316                 soc15_program_register_sequence(adev,
 317                                                 golden_settings_gc_9_2_1_vg12,
 318                                                 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12));
 319                 break;
 320         case CHIP_VEGA20:
 321                 soc15_program_register_sequence(adev,
 322                                                 golden_settings_gc_9_0,
 323                                                 ARRAY_SIZE(golden_settings_gc_9_0));
 324                 soc15_program_register_sequence(adev,
 325                                                 golden_settings_gc_9_0_vg20,
 326                                                 ARRAY_SIZE(golden_settings_gc_9_0_vg20));
 327                 break;
 328         case CHIP_RAVEN:
 329                 soc15_program_register_sequence(adev, golden_settings_gc_9_1,
 330                                                 ARRAY_SIZE(golden_settings_gc_9_1));
 331                 if (adev->rev_id >= 8)
 332                         soc15_program_register_sequence(adev,
 333                                                         golden_settings_gc_9_1_rv2,
 334                                                         ARRAY_SIZE(golden_settings_gc_9_1_rv2));
 335                 else
 336                         soc15_program_register_sequence(adev,
 337                                                         golden_settings_gc_9_1_rv1,
 338                                                         ARRAY_SIZE(golden_settings_gc_9_1_rv1));
 339                 break;
 340         default:
 341                 break;
 342         }
 343
 344         soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
 345                                         (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
 346 }
 347
 348 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
 349 {
 350         adev->gfx.scratch.num_reg = 8;
 351         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
 352         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
 353 }
 354
 355 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 356                                        bool wc, uint32_t reg, uint32_t val)
 357 {
 358         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 359         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 360                                 WRITE_DATA_DST_SEL(0) |
 361                                 (wc ? WR_CONFIRM : 0));
 362         amdgpu_ring_write(ring, reg);
 363         amdgpu_ring_write(ring, 0);
 364         amdgpu_ring_write(ring, val);
 365 }
 366
 367 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 368                                   int mem_space, int opt, uint32_t addr0,
 369                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 370                                   uint32_t inv)
 371 {
 372         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 373         amdgpu_ring_write(ring,
 374                                  /* memory (1) or register (0) */
 375                                  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 376                                  WAIT_REG_MEM_OPERATION(opt) | /* wait */
 377                                  WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 378                                  WAIT_REG_MEM_ENGINE(eng_sel)));
 379
 380         if (mem_space)
 381                 BUG_ON(addr0 & 0x3); /* Dword align */
 382         amdgpu_ring_write(ring, addr0);
 383         amdgpu_ring_write(ring, addr1);
 384         amdgpu_ring_write(ring, ref);
 385         amdgpu_ring_write(ring, mask);
 386         amdgpu_ring_write(ring, inv); /* poll interval */
 387 }
 388
 389 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
 390 {
 391         struct amdgpu_device *adev = ring->adev;
 392         uint32_t scratch;
 393         uint32_t tmp = 0;
 394         unsigned i;
 395         int r;
 396
 397         r = amdgpu_gfx_scratch_get(adev, &scratch);
 398         if (r) {
 399                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
 400                 return r;
 401         }
 402         WREG32(scratch, 0xCAFEDEAD);
 403         r = amdgpu_ring_alloc(ring, 3);
 404         if (r) {
 405                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 406                           ring->idx, r);
 407                 amdgpu_gfx_scratch_free(adev, scratch);
 408                 return r;
 409         }
 410         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 411         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 412         amdgpu_ring_write(ring, 0xDEADBEEF);
 413         amdgpu_ring_commit(ring);
 414
 415         for (i = 0; i < adev->usec_timeout; i++) {
 416                 tmp = RREG32(scratch);
 417                 if (tmp == 0xDEADBEEF)
 418                         break;
 419                 DRM_UDELAY(1);
 420         }
 421         if (i < adev->usec_timeout) {
 422                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
 423                          ring->idx, i);
 424         } else {
 425                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
 426                           ring->idx, scratch, tmp);
 427                 r = -EINVAL;
 428         }
 429         amdgpu_gfx_scratch_free(adev, scratch);
 430         return r;
 431 }
 432
 433 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 434 {
 435         struct amdgpu_device *adev = ring->adev;
 436         struct amdgpu_ib ib;
 437         struct dma_fence *f = NULL;
 438
 439         unsigned index;
 440         uint64_t gpu_addr;
 441         uint32_t tmp;
 442         long r;
 443
 444         r = amdgpu_device_wb_get(adev, &index);
 445         if (r) {
 446                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 447                 return r;
 448         }
 449
 450         gpu_addr = adev->wb.gpu_addr + (index * 4);
 451         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
 452         memset(&ib, 0, sizeof(ib));
 453         r = amdgpu_ib_get(adev, NULL, 16, &ib);
 454         if (r) {
 455                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 456                 goto err1;
 457         }
 458         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
 459         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
 460         ib.ptr[2] = lower_32_bits(gpu_addr);
 461         ib.ptr[3] = upper_32_bits(gpu_addr);
 462         ib.ptr[4] = 0xDEADBEEF;
 463         ib.length_dw = 5;
 464
 465         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 466         if (r)
 467                 goto err2;
 468
 469         r = dma_fence_wait_timeout(f, false, timeout);
 470         if (r == 0) {
 471                         DRM_ERROR("amdgpu: IB test timed out.\n");
 472                         r = -ETIMEDOUT;
 473                         goto err2;
 474         } else if (r < 0) {
 475                         DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 476                         goto err2;
 477         }
 478
 479         tmp = adev->wb.wb[index];
 480         if (tmp == 0xDEADBEEF) {
 481                         DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 482                         r = 0;
 483         } else {
 484                         DRM_ERROR("ib test on ring %d failed\n", ring->idx);
 485                         r = -EINVAL;
 486         }
 487
 488 err2:
 489         amdgpu_ib_free(adev, &ib, NULL);
 490         dma_fence_put(f);
 491 err1:
 492         amdgpu_device_wb_free(adev, index);
 493         return r;
 494 }
 495
 496
 497 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev)
 498 {
 499         release_firmware(adev->gfx.pfp_fw);
 500         adev->gfx.pfp_fw = NULL;
 501         release_firmware(adev->gfx.me_fw);
 502         adev->gfx.me_fw = NULL;
 503         release_firmware(adev->gfx.ce_fw);
 504         adev->gfx.ce_fw = NULL;
 505         release_firmware(adev->gfx.rlc_fw);
 506         adev->gfx.rlc_fw = NULL;
 507         release_firmware(adev->gfx.mec_fw);
 508         adev->gfx.mec_fw = NULL;
 509         release_firmware(adev->gfx.mec2_fw);
 510         adev->gfx.mec2_fw = NULL;
 511
 512         kfree(adev->gfx.rlc.register_list_format);
 513 }
 514
 515 static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
 516 {
 517         const struct rlc_firmware_header_v2_1 *rlc_hdr;
 518
 519         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
 520         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
 521         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
 522         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
 523         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
 524         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
 525         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
 526         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
 527         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
 528         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
 529         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
 530         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
 531         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
 532         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
 533                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
 534 }
 535
 536 static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
 537 {
 538         adev->gfx.me_fw_write_wait = false;
 539         adev->gfx.mec_fw_write_wait = false;
 540
 541         switch (adev->asic_type) {
 542         case CHIP_VEGA10:
 543                 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
 544                     (adev->gfx.me_feature_version >= 42) &&
 545                     (adev->gfx.pfp_fw_version >=  0x000000b1) &&
 546                     (adev->gfx.pfp_feature_version >= 42))
 547                         adev->gfx.me_fw_write_wait = true;
 548
 549                 if ((adev->gfx.mec_fw_version >=  0x00000193) &&
 550                     (adev->gfx.mec_feature_version >= 42))
 551                         adev->gfx.mec_fw_write_wait = true;
 552                 break;
 553         case CHIP_VEGA12:
 554                 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
 555                     (adev->gfx.me_feature_version >= 44) &&
 556                     (adev->gfx.pfp_fw_version >=  0x000000b2) &&
 557                     (adev->gfx.pfp_feature_version >= 44))
 558                         adev->gfx.me_fw_write_wait = true;
 559
 560                 if ((adev->gfx.mec_fw_version >=  0x00000196) &&
 561                     (adev->gfx.mec_feature_version >= 44))
 562                         adev->gfx.mec_fw_write_wait = true;
 563                 break;
 564         case CHIP_VEGA20:
 565                 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
 566                     (adev->gfx.me_feature_version >= 44) &&
 567                     (adev->gfx.pfp_fw_version >=  0x000000b2) &&
 568                     (adev->gfx.pfp_feature_version >= 44))
 569                         adev->gfx.me_fw_write_wait = true;
 570
 571                 if ((adev->gfx.mec_fw_version >=  0x00000197) &&
 572                     (adev->gfx.mec_feature_version >= 44))
 573                         adev->gfx.mec_fw_write_wait = true;
 574                 break;
 575         case CHIP_RAVEN:
 576                 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
 577                     (adev->gfx.me_feature_version >= 42) &&
 578                     (adev->gfx.pfp_fw_version >=  0x000000b1) &&
 579                     (adev->gfx.pfp_feature_version >= 42))
 580                         adev->gfx.me_fw_write_wait = true;
 581
 582                 if ((adev->gfx.mec_fw_version >=  0x00000192) &&
 583                     (adev->gfx.mec_feature_version >= 42))
 584                         adev->gfx.mec_fw_write_wait = true;
 585                 break;
 586         default:
 587                 break;
 588         }
 589 }
 590
 591 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
 592 {
 593         const char *chip_name;
 594         char fw_name[30];
 595         int err;
 596         struct amdgpu_firmware_info *info = NULL;
 597         const struct common_firmware_header *header = NULL;
 598         const struct gfx_firmware_header_v1_0 *cp_hdr;
 599         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 600         unsigned int *tmp = NULL;
 601         unsigned int i = 0;
 602         uint16_t version_major;
 603         uint16_t version_minor;
 604
 605         DRM_DEBUG("\n");
 606
 607         switch (adev->asic_type) {
 608         case CHIP_VEGA10:
 609                 chip_name = "vega10";
 610                 break;
 611         case CHIP_VEGA12:
 612                 chip_name = "vega12";
 613                 break;
 614         case CHIP_VEGA20:
 615                 chip_name = "vega20";
 616                 break;
 617         case CHIP_RAVEN:
 618                 if (adev->rev_id >= 8)
 619                         chip_name = "raven2";
 620                 else if (adev->pdev->device == 0x15d8)
 621                         chip_name = "picasso";
 622                 else
 623                         chip_name = "raven";
 624                 break;
 625         default:
 626                 BUG();
 627         }
 628
 629         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
 630         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 631         if (err)
 632                 goto out;
 633         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 634         if (err)
 635                 goto out;
 636         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 637         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 638         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 639
 640         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
 641         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 642         if (err)
 643                 goto out;
 644         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 645         if (err)
 646                 goto out;
 647         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 648         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 649         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 650
 651         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
 652         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 653         if (err)
 654                 goto out;
 655         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 656         if (err)
 657                 goto out;
 658         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 659         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 660         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 661
 662         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 663         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 664         if (err)
 665                 goto out;
 666         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 667         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 668
 669         version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
 670         version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
 671         if (version_major == 2 && version_minor == 1)
 672                 adev->gfx.rlc.is_rlc_v2_1 = true;
 673
 674         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
 675         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
 676         adev->gfx.rlc.save_and_restore_offset =
 677                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
 678         adev->gfx.rlc.clear_state_descriptor_offset =
 679                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
 680         adev->gfx.rlc.avail_scratch_ram_locations =
 681                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
 682         adev->gfx.rlc.reg_restore_list_size =
 683                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
 684         adev->gfx.rlc.reg_list_format_start =
 685                         le32_to_cpu(rlc_hdr->reg_list_format_start);
 686         adev->gfx.rlc.reg_list_format_separate_start =
 687                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
 688         adev->gfx.rlc.starting_offsets_start =
 689                         le32_to_cpu(rlc_hdr->starting_offsets_start);
 690         adev->gfx.rlc.reg_list_format_size_bytes =
 691                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
 692         adev->gfx.rlc.reg_list_size_bytes =
 693                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
 694         adev->gfx.rlc.register_list_format =
 695                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
 696                                 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
 697         if (!adev->gfx.rlc.register_list_format) {
 698                 err = -ENOMEM;
 699                 goto out;
 700         }
 701
 702         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 703                         le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
 704         for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++)
 705                 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
 706
 707         adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
 708
 709         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 710                         le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
 711         for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++)
 712                 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
 713
 714         if (adev->gfx.rlc.is_rlc_v2_1)
 715                 gfx_v9_0_init_rlc_ext_microcode(adev);
 716
 717         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 718         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 719         if (err)
 720                 goto out;
 721         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 722         if (err)
 723                 goto out;
 724         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 725         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 726         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 727
 728
 729         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
 730         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 731         if (!err) {
 732                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 733                 if (err)
 734                         goto out;
 735                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 736                 adev->gfx.mec2_fw->data;
 737                 adev->gfx.mec2_fw_version =
 738                 le32_to_cpu(cp_hdr->header.ucode_version);
 739                 adev->gfx.mec2_feature_version =
 740                 le32_to_cpu(cp_hdr->ucode_feature_version);
 741         } else {
 742                 err = 0;
 743                 adev->gfx.mec2_fw = NULL;
 744         }
 745
 746         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 747                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 748                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 749                 info->fw = adev->gfx.pfp_fw;
 750                 header = (const struct common_firmware_header *)info->fw->data;
 751                 adev->firmware.fw_size +=
 752                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 753
 754                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 755                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 756                 info->fw = adev->gfx.me_fw;
 757                 header = (const struct common_firmware_header *)info->fw->data;
 758                 adev->firmware.fw_size +=
 759                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 760
 761                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 762                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 763                 info->fw = adev->gfx.ce_fw;
 764                 header = (const struct common_firmware_header *)info->fw->data;
 765                 adev->firmware.fw_size +=
 766                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 767
 768                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 769                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 770                 info->fw = adev->gfx.rlc_fw;
 771                 header = (const struct common_firmware_header *)info->fw->data;
 772                 adev->firmware.fw_size +=
 773                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 774
 775                 if (adev->gfx.rlc.is_rlc_v2_1 &&
 776                     adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
 777                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
 778                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
 779                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
 780                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
 781                         info->fw = adev->gfx.rlc_fw;
 782                         adev->firmware.fw_size +=
 783                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
 784
 785                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
 786                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
 787                         info->fw = adev->gfx.rlc_fw;
 788                         adev->firmware.fw_size +=
 789                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
 790
 791                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
 792                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
 793                         info->fw = adev->gfx.rlc_fw;
 794                         adev->firmware.fw_size +=
 795                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
 796                 }
 797
 798                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 799                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 800                 info->fw = adev->gfx.mec_fw;
 801                 header = (const struct common_firmware_header *)info->fw->data;
 802                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 803                 adev->firmware.fw_size +=
 804                         ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 805
 806                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
 807                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
 808                 info->fw = adev->gfx.mec_fw;
 809                 adev->firmware.fw_size +=
 810                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 811
 812                 if (adev->gfx.mec2_fw) {
 813                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
 814                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 815                         info->fw = adev->gfx.mec2_fw;
 816                         header = (const struct common_firmware_header *)info->fw->data;
 817                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 818                         adev->firmware.fw_size +=
 819                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 820                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
 821                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
 822                         info->fw = adev->gfx.mec2_fw;
 823                         adev->firmware.fw_size +=
 824                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 825                 }
 826
 827         }
 828
 829 out:
 830         gfx_v9_0_check_fw_write_wait(adev);
 831         if (err) {
 832                 dev_err(adev->dev,
 833                         "gfx9: Failed to load firmware \"%s\"\n",
 834                         fw_name);
 835                 release_firmware(adev->gfx.pfp_fw);
 836                 adev->gfx.pfp_fw = NULL;
 837                 release_firmware(adev->gfx.me_fw);
 838                 adev->gfx.me_fw = NULL;
 839                 release_firmware(adev->gfx.ce_fw);
 840                 adev->gfx.ce_fw = NULL;
 841                 release_firmware(adev->gfx.rlc_fw);
 842                 adev->gfx.rlc_fw = NULL;
 843                 release_firmware(adev->gfx.mec_fw);
 844                 adev->gfx.mec_fw = NULL;
 845                 release_firmware(adev->gfx.mec2_fw);
 846                 adev->gfx.mec2_fw = NULL;
 847         }
 848         return err;
 849 }
 850
 851 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
 852 {
 853         u32 count = 0;
 854         const struct cs_section_def *sect = NULL;
 855         const struct cs_extent_def *ext = NULL;
 856
 857         /* begin clear state */
 858         count += 2;
 859         /* context control state */
 860         count += 3;
 861
 862         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
 863                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 864                         if (sect->id == SECT_CONTEXT)
 865                                 count += 2 + ext->reg_count;
 866                         else
 867                                 return 0;
 868                 }
 869         }
 870
 871         /* end clear state */
 872         count += 2;
 873         /* clear state */
 874         count += 2;
 875
 876         return count;
 877 }
 878
 879 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
 880                                     volatile u32 *buffer)
 881 {
 882         u32 count = 0, i;
 883         const struct cs_section_def *sect = NULL;
 884         const struct cs_extent_def *ext = NULL;
 885
 886         if (adev->gfx.rlc.cs_data == NULL)
 887                 return;
 888         if (buffer == NULL)
 889                 return;
 890
 891         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 892         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 893
 894         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 895         buffer[count++] = cpu_to_le32(0x80000000);
 896         buffer[count++] = cpu_to_le32(0x80000000);
 897
 898         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
 899                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 900                         if (sect->id == SECT_CONTEXT) {
 901                                 buffer[count++] =
 902                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
 903                                 buffer[count++] = cpu_to_le32(ext->reg_index -
 904                                                 PACKET3_SET_CONTEXT_REG_START);
 905                                 for (i = 0; i < ext->reg_count; i++)
 906                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
 907                         } else {
 908                                 return;
 909                         }
 910                 }
 911         }
 912
 913         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 914         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
 915
 916         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
 917         buffer[count++] = cpu_to_le32(0);
 918 }
 919
 920 static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev)
 921 {
 922         struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
 923         uint32_t pg_always_on_cu_num = 2;
 924         uint32_t always_on_cu_num;
 925         uint32_t i, j, k;
 926         uint32_t mask, cu_bitmap, counter;
 927
 928         if (adev->flags & AMD_IS_APU)
 929                 always_on_cu_num = 4;
 930         else if (adev->asic_type == CHIP_VEGA12)
 931                 always_on_cu_num = 8;
 932         else
 933                 always_on_cu_num = 12;
 934
 935         mutex_lock(&adev->grbm_idx_mutex);
 936         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
 937                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
 938                         mask = 1;
 939                         cu_bitmap = 0;
 940                         counter = 0;
 941                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
 942
 943                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
 944                                 if (cu_info->bitmap[i][j] & mask) {
 945                                         if (counter == pg_always_on_cu_num)
 946                                                 WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap);
 947                                         if (counter < always_on_cu_num)
 948                                                 cu_bitmap |= mask;
 949                                         else
 950                                                 break;
 951                                         counter++;
 952                                 }
 953                                 mask <<= 1;
 954                         }
 955
 956                         WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, cu_bitmap);
 957                         cu_info->ao_cu_bitmap[i][j] = cu_bitmap;
 958                 }
 959         }
 960         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 961         mutex_unlock(&adev->grbm_idx_mutex);
 962 }
 963
 964 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
 965 {
 966         uint32_t data;
 967
 968         /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
 969         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
 970         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
 971         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
 972         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
 973
 974         /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
 975         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
 976
 977         /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
 978         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
 979
 980         mutex_lock(&adev->grbm_idx_mutex);
 981         /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
 982         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 983         WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
 984
 985         /* set mmRLC_LB_PARAMS = 0x003F_1006 */
 986         data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
 987         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
 988         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
 989         WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
 990
 991         /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
 992         data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
 993         data &= 0x0000FFFF;
 994         data |= 0x00C00000;
 995         WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
 996
 997         /*
 998          * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xF (4 CUs AON for Raven),
 999          * programmed in gfx_v9_0_init_always_on_cu_mask()
1000          */
1001
1002         /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
1003          * but used for RLC_LB_CNTL configuration */
1004         data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
1005         data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
1006         data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
1007         WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
1008         mutex_unlock(&adev->grbm_idx_mutex);
1009
1010         gfx_v9_0_init_always_on_cu_mask(adev);
1011 }
1012
1013 static void gfx_v9_4_init_lbpw(struct amdgpu_device *adev)
1014 {
1015         uint32_t data;
1016
1017         /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
1018         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
1019         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x033388F8);
1020         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
1021         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 | 0x27 << 8 | 0x02FA << 16));
1022
1023         /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
1024         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
1025
1026         /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
1027         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800);
1028
1029         mutex_lock(&adev->grbm_idx_mutex);
1030         /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
1031         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1032         WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
1033
1034         /* set mmRLC_LB_PARAMS = 0x003F_1006 */
1035         data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
1036         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
1037         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
1038         WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
1039
1040         /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
1041         data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
1042         data &= 0x0000FFFF;
1043         data |= 0x00C00000;
1044         WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
1045
1046         /*
1047          * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF (12 CUs AON),
1048          * programmed in gfx_v9_0_init_always_on_cu_mask()
1049          */
1050
1051         /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
1052          * but used for RLC_LB_CNTL configuration */
1053         data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
1054         data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
1055         data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
1056         WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
1057         mutex_unlock(&adev->grbm_idx_mutex);
1058
1059         gfx_v9_0_init_always_on_cu_mask(adev);
1060 }
1061
1062 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
1063 {
1064         WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
1065 }
1066
1067 static void rv_init_cp_jump_table(struct amdgpu_device *adev)
1068 {
1069         const __le32 *fw_data;
1070         volatile u32 *dst_ptr;
1071         int me, i, max_me = 5;
1072         u32 bo_offset = 0;
1073         u32 table_offset, table_size;
1074
1075         /* write the cp table buffer */
1076         dst_ptr = adev->gfx.rlc.cp_table_ptr;
1077         for (me = 0; me < max_me; me++) {
1078                 if (me == 0) {
1079                         const struct gfx_firmware_header_v1_0 *hdr =
1080                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1081                         fw_data = (const __le32 *)
1082                                 (adev->gfx.ce_fw->data +
1083                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1084                         table_offset = le32_to_cpu(hdr->jt_offset);
1085                         table_size = le32_to_cpu(hdr->jt_size);
1086                 } else if (me == 1) {
1087                         const struct gfx_firmware_header_v1_0 *hdr =
1088                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1089                         fw_data = (const __le32 *)
1090                                 (adev->gfx.pfp_fw->data +
1091                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1092                         table_offset = le32_to_cpu(hdr->jt_offset);
1093                         table_size = le32_to_cpu(hdr->jt_size);
1094                 } else if (me == 2) {
1095                         const struct gfx_firmware_header_v1_0 *hdr =
1096                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1097                         fw_data = (const __le32 *)
1098                                 (adev->gfx.me_fw->data +
1099                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1100                         table_offset = le32_to_cpu(hdr->jt_offset);
1101                         table_size = le32_to_cpu(hdr->jt_size);
1102                 } else if (me == 3) {
1103                         const struct gfx_firmware_header_v1_0 *hdr =
1104                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1105                         fw_data = (const __le32 *)
1106                                 (adev->gfx.mec_fw->data +
1107                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1108                         table_offset = le32_to_cpu(hdr->jt_offset);
1109                         table_size = le32_to_cpu(hdr->jt_size);
1110                 } else  if (me == 4) {
1111                         const struct gfx_firmware_header_v1_0 *hdr =
1112                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
1113                         fw_data = (const __le32 *)
1114                                 (adev->gfx.mec2_fw->data +
1115                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1116                         table_offset = le32_to_cpu(hdr->jt_offset);
1117                         table_size = le32_to_cpu(hdr->jt_size);
1118                 }
1119
1120                 for (i = 0; i < table_size; i ++) {
1121                         dst_ptr[bo_offset + i] =
1122                                 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
1123                 }
1124
1125                 bo_offset += table_size;
1126         }
1127 }
1128
1129 static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
1130 {
1131         /* clear state block */
1132         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
1133                         &adev->gfx.rlc.clear_state_gpu_addr,
1134                         (void **)&adev->gfx.rlc.cs_ptr);
1135
1136         /* jump table block */
1137         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
1138                         &adev->gfx.rlc.cp_table_gpu_addr,
1139                         (void **)&adev->gfx.rlc.cp_table_ptr);
1140 }
1141
1142 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
1143 {
1144         volatile u32 *dst_ptr;
1145         u32 dws;
1146         const struct cs_section_def *cs_data;
1147         int r;
1148
1149         adev->gfx.rlc.cs_data = gfx9_cs_data;
1150
1151         cs_data = adev->gfx.rlc.cs_data;
1152
1153         if (cs_data) {
1154                 /* clear state block */
1155                 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
1156                 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
1157                                               AMDGPU_GEM_DOMAIN_VRAM,
1158                                               &adev->gfx.rlc.clear_state_obj,
1159                                               &adev->gfx.rlc.clear_state_gpu_addr,
1160                                               (void **)&adev->gfx.rlc.cs_ptr);
1161                 if (r) {
1162                         dev_err(adev->dev, "(%d) failed to create rlc csb bo\n",
1163                                 r);
1164                         gfx_v9_0_rlc_fini(adev);
1165                         return r;
1166                 }
1167                 /* set up the cs buffer */
1168                 dst_ptr = adev->gfx.rlc.cs_ptr;
1169                 gfx_v9_0_get_csb_buffer(adev, dst_ptr);
1170                 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
1171                 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1172                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1173         }
1174
1175         if (adev->asic_type == CHIP_RAVEN) {
1176                 /* TODO: double check the cp_table_size for RV */
1177                 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
1178                 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
1179                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1180                                               &adev->gfx.rlc.cp_table_obj,
1181                                               &adev->gfx.rlc.cp_table_gpu_addr,
1182                                               (void **)&adev->gfx.rlc.cp_table_ptr);
1183                 if (r) {
1184                         dev_err(adev->dev,
1185                                 "(%d) failed to create cp table bo\n", r);
1186                         gfx_v9_0_rlc_fini(adev);
1187                         return r;
1188                 }
1189
1190                 rv_init_cp_jump_table(adev);
1191                 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
1192                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
1193         }
1194
1195         switch (adev->asic_type) {
1196         case CHIP_RAVEN:
1197                 gfx_v9_0_init_lbpw(adev);
1198                 break;
1199         case CHIP_VEGA20:
1200                 gfx_v9_4_init_lbpw(adev);
1201                 break;
1202         default:
1203                 break;
1204         }
1205
1206         return 0;
1207 }
1208
1209 static int gfx_v9_0_csb_vram_pin(struct amdgpu_device *adev)
1210 {
1211         int r;
1212
1213         r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1214         if (unlikely(r != 0))
1215                 return r;
1216
1217         r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
1218                         AMDGPU_GEM_DOMAIN_VRAM);
1219         if (!r)
1220                 adev->gfx.rlc.clear_state_gpu_addr =
1221                         amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
1222
1223         amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1224
1225         return r;
1226 }
1227
1228 static void gfx_v9_0_csb_vram_unpin(struct amdgpu_device *adev)
1229 {
1230         int r;
1231
1232         if (!adev->gfx.rlc.clear_state_obj)
1233                 return;
1234
1235         r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
1236         if (likely(r == 0)) {
1237                 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1238                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1239         }
1240 }
1241
1242 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
1243 {
1244         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1245         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
1246 }
1247
1248 static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
1249 {
1250         int r;
1251         u32 *hpd;
1252         const __le32 *fw_data;
1253         unsigned fw_size;
1254         u32 *fw;
1255         size_t mec_hpd_size;
1256
1257         const struct gfx_firmware_header_v1_0 *mec_hdr;
1258
1259         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1260
1261         /* take ownership of the relevant compute queues */
1262         amdgpu_gfx_compute_queue_acquire(adev);
1263         mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
1264
1265         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1266                                       AMDGPU_GEM_DOMAIN_GTT,
1267                                       &adev->gfx.mec.hpd_eop_obj,
1268                                       &adev->gfx.mec.hpd_eop_gpu_addr,
1269                                       (void **)&hpd);
1270         if (r) {
1271                 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1272                 gfx_v9_0_mec_fini(adev);
1273                 return r;
1274         }
1275
1276         memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
1277
1278         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1279         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1280
1281         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1282
1283         fw_data = (const __le32 *)
1284                 (adev->gfx.mec_fw->data +
1285                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1286         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
1287
1288         r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
1289                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1290                                       &adev->gfx.mec.mec_fw_obj,
1291                                       &adev->gfx.mec.mec_fw_gpu_addr,
1292                                       (void **)&fw);
1293         if (r) {
1294                 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
1295                 gfx_v9_0_mec_fini(adev);
1296                 return r;
1297         }
1298
1299         memcpy(fw, fw_data, fw_size);
1300
1301         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
1302         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
1303
1304         return 0;
1305 }
1306
1307 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
1308 {
1309         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1310                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1311                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1312                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
1313                 (SQ_IND_INDEX__FORCE_READ_MASK));
1314         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1315 }
1316
1317 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
1318                            uint32_t wave, uint32_t thread,
1319                            uint32_t regno, uint32_t num, uint32_t *out)
1320 {
1321         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1322                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1323                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1324                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
1325                 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
1326                 (SQ_IND_INDEX__FORCE_READ_MASK) |
1327                 (SQ_IND_INDEX__AUTO_INCR_MASK));
1328         while (num--)
1329                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1330 }
1331
1332 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1333 {
1334         /* type 1 wave data */
1335         dst[(*no_fields)++] = 1;
1336         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
1337         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
1338         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
1339         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
1340         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
1341         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
1342         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
1343         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
1344         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
1345         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
1346         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
1347         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
1348         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
1349         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
1350 }
1351
1352 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1353                                      uint32_t wave, uint32_t start,
1354                                      uint32_t size, uint32_t *dst)
1355 {
1356         wave_read_regs(
1357                 adev, simd, wave, 0,
1358                 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
1359 }
1360
1361 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
1362                                      uint32_t wave, uint32_t thread,
1363                                      uint32_t start, uint32_t size,
1364                                      uint32_t *dst)
1365 {
1366         wave_read_regs(
1367                 adev, simd, wave, thread,
1368                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1369 }
1370
1371 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev,
1372                                   u32 me, u32 pipe, u32 q)
1373 {
1374         soc15_grbm_select(adev, me, pipe, q, 0);
1375 }
1376
1377 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
1378         .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
1379         .select_se_sh = &gfx_v9_0_select_se_sh,
1380         .read_wave_data = &gfx_v9_0_read_wave_data,
1381         .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
1382         .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
1383         .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q
1384 };
1385
1386 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
1387 {
1388         u32 gb_addr_config;
1389         int err;
1390
1391         adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
1392
1393         switch (adev->asic_type) {
1394         case CHIP_VEGA10:
1395                 adev->gfx.config.max_hw_contexts = 8;
1396                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1397                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1398                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1399                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1400                 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
1401                 break;
1402         case CHIP_VEGA12:
1403                 adev->gfx.config.max_hw_contexts = 8;
1404                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1405                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1406                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1407                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1408                 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN;
1409                 DRM_INFO("fix gfx.config for vega12\n");
1410                 break;
1411         case CHIP_VEGA20:
1412                 adev->gfx.config.max_hw_contexts = 8;
1413                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1414                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1415                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1416                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1417                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1418                 gb_addr_config &= ~0xf3e777ff;
1419                 gb_addr_config |= 0x22014042;
1420                 /* check vbios table if gpu info is not available */
1421                 err = amdgpu_atomfirmware_get_gfx_info(adev);
1422                 if (err)
1423                         return err;
1424                 break;
1425         case CHIP_RAVEN:
1426                 adev->gfx.config.max_hw_contexts = 8;
1427                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1428                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1429                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1430                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1431                 if (adev->rev_id >= 8)
1432                         gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN;
1433                 else
1434                         gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
1435                 break;
1436         default:
1437                 BUG();
1438                 break;
1439         }
1440
1441         adev->gfx.config.gb_addr_config = gb_addr_config;
1442
1443         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1444                         REG_GET_FIELD(
1445                                         adev->gfx.config.gb_addr_config,
1446                                         GB_ADDR_CONFIG,
1447                                         NUM_PIPES);
1448
1449         adev->gfx.config.max_tile_pipes =
1450                 adev->gfx.config.gb_addr_config_fields.num_pipes;
1451
1452         adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
1453                         REG_GET_FIELD(
1454                                         adev->gfx.config.gb_addr_config,
1455                                         GB_ADDR_CONFIG,
1456                                         NUM_BANKS);
1457         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1458                         REG_GET_FIELD(
1459                                         adev->gfx.config.gb_addr_config,
1460                                         GB_ADDR_CONFIG,
1461                                         MAX_COMPRESSED_FRAGS);
1462         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1463                         REG_GET_FIELD(
1464                                         adev->gfx.config.gb_addr_config,
1465                                         GB_ADDR_CONFIG,
1466                                         NUM_RB_PER_SE);
1467         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1468                         REG_GET_FIELD(
1469                                         adev->gfx.config.gb_addr_config,
1470                                         GB_ADDR_CONFIG,
1471                                         NUM_SHADER_ENGINES);
1472         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1473                         REG_GET_FIELD(
1474                                         adev->gfx.config.gb_addr_config,
1475                                         GB_ADDR_CONFIG,
1476                                         PIPE_INTERLEAVE_SIZE));
1477
1478         return 0;
1479 }
1480
1481 static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
1482                                    struct amdgpu_ngg_buf *ngg_buf,
1483                                    int size_se,
1484                                    int default_size_se)
1485 {
1486         int r;
1487
1488         if (size_se < 0) {
1489                 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
1490                 return -EINVAL;
1491         }
1492         size_se = size_se ? size_se : default_size_se;
1493
1494         ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
1495         r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
1496                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1497                                     &ngg_buf->bo,
1498                                     &ngg_buf->gpu_addr,
1499                                     NULL);
1500         if (r) {
1501                 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
1502                 return r;
1503         }
1504         ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
1505
1506         return r;
1507 }
1508
1509 static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
1510 {
1511         int i;
1512
1513         for (i = 0; i < NGG_BUF_MAX; i++)
1514                 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
1515                                       &adev->gfx.ngg.buf[i].gpu_addr,
1516                                       NULL);
1517
1518         memset(&adev->gfx.ngg.buf[0], 0,
1519                         sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
1520
1521         adev->gfx.ngg.init = false;
1522
1523         return 0;
1524 }
1525
1526 static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
1527 {
1528         int r;
1529
1530         if (!amdgpu_ngg || adev->gfx.ngg.init == true)
1531                 return 0;
1532
1533         /* GDS reserve memory: 64 bytes alignment */
1534         adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
1535         adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
1536         adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
1537         adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);
1538         adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
1539
1540         /* Primitive Buffer */
1541         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
1542                                     amdgpu_prim_buf_per_se,
1543                                     64 * 1024);
1544         if (r) {
1545                 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
1546                 goto err;
1547         }
1548
1549         /* Position Buffer */
1550         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
1551                                     amdgpu_pos_buf_per_se,
1552                                     256 * 1024);
1553         if (r) {
1554                 dev_err(adev->dev, "Failed to create Position Buffer\n");
1555                 goto err;
1556         }
1557
1558         /* Control Sideband */
1559         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
1560                                     amdgpu_cntl_sb_buf_per_se,
1561                                     256);
1562         if (r) {
1563                 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
1564                 goto err;
1565         }
1566
1567         /* Parameter Cache, not created by default */
1568         if (amdgpu_param_buf_per_se <= 0)
1569                 goto out;
1570
1571         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
1572                                     amdgpu_param_buf_per_se,
1573                                     512 * 1024);
1574         if (r) {
1575                 dev_err(adev->dev, "Failed to create Parameter Cache\n");
1576                 goto err;
1577         }
1578
1579 out:
1580         adev->gfx.ngg.init = true;
1581         return 0;
1582 err:
1583         gfx_v9_0_ngg_fini(adev);
1584         return r;
1585 }
1586
1587 static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1588 {
1589         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1590         int r;
1591         u32 data, base;
1592
1593         if (!amdgpu_ngg)
1594                 return 0;
1595
1596         /* Program buffer size */
1597         data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE,
1598                              adev->gfx.ngg.buf[NGG_PRIM].size >> 8);
1599         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE,
1600                              adev->gfx.ngg.buf[NGG_POS].size >> 8);
1601         WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
1602
1603         data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE,
1604                              adev->gfx.ngg.buf[NGG_CNTL].size >> 8);
1605         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE,
1606                              adev->gfx.ngg.buf[NGG_PARAM].size >> 10);
1607         WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
1608
1609         /* Program buffer base address */
1610         base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1611         data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
1612         WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
1613
1614         base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1615         data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
1616         WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
1617
1618         base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1619         data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
1620         WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
1621
1622         base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1623         data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
1624         WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
1625
1626         base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1627         data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
1628         WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
1629
1630         base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1631         data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
1632         WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
1633
1634         /* Clear GDS reserved memory */
1635         r = amdgpu_ring_alloc(ring, 17);
1636         if (r) {
1637                 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
1638                           ring->idx, r);
1639                 return r;
1640         }
1641
1642         gfx_v9_0_write_data_to_reg(ring, 0, false,
1643                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
1644                                    (adev->gds.mem.total_size +
1645                                     adev->gfx.ngg.gds_reserve_size));
1646
1647         amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1648         amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1649                                 PACKET3_DMA_DATA_DST_SEL(1) |
1650                                 PACKET3_DMA_DATA_SRC_SEL(2)));
1651         amdgpu_ring_write(ring, 0);
1652         amdgpu_ring_write(ring, 0);
1653         amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1654         amdgpu_ring_write(ring, 0);
1655         amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |
1656                                 adev->gfx.ngg.gds_reserve_size);
1657
1658         gfx_v9_0_write_data_to_reg(ring, 0, false,
1659                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
1660
1661         amdgpu_ring_commit(ring);
1662
1663         return 0;
1664 }
1665
1666 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1667                                       int mec, int pipe, int queue)
1668 {
1669         int r;
1670         unsigned irq_type;
1671         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1672
1673         ring = &adev->gfx.compute_ring[ring_id];
1674
1675         /* mec0 is me1 */
1676         ring->me = mec + 1;
1677         ring->pipe = pipe;
1678         ring->queue = queue;
1679
1680         ring->ring_obj = NULL;
1681         ring->use_doorbell = true;
1682         ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1;
1683         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1684                                 + (ring_id * GFX9_MEC_HPD_SIZE);
1685         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1686
1687         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1688                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1689                 + ring->pipe;
1690
1691         /* type-2 packets are deprecated on MEC, use type-3 instead */
1692         r = amdgpu_ring_init(adev, ring, 1024,
1693                              &adev->gfx.eop_irq, irq_type);
1694         if (r)
1695                 return r;
1696
1697
1698         return 0;
1699 }
1700
1701 static int gfx_v9_0_sw_init(void *handle)
1702 {
1703         int i, j, k, r, ring_id;
1704         struct amdgpu_ring *ring;
1705         struct amdgpu_kiq *kiq;
1706         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1707
1708         switch (adev->asic_type) {
1709         case CHIP_VEGA10:
1710         case CHIP_VEGA12:
1711         case CHIP_VEGA20:
1712         case CHIP_RAVEN:
1713                 adev->gfx.mec.num_mec = 2;
1714                 break;
1715         default:
1716                 adev->gfx.mec.num_mec = 1;
1717                 break;
1718         }
1719
1720         adev->gfx.mec.num_pipe_per_mec = 4;
1721         adev->gfx.mec.num_queue_per_pipe = 8;
1722
1723         /* EOP Event */
1724         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq);
1725         if (r)
1726                 return r;
1727
1728         /* Privileged reg */
1729         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,
1730                               &adev->gfx.priv_reg_irq);
1731         if (r)
1732                 return r;
1733
1734         /* Privileged inst */
1735         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT,
1736                               &adev->gfx.priv_inst_irq);
1737         if (r)
1738                 return r;
1739
1740         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1741
1742         gfx_v9_0_scratch_init(adev);
1743
1744         r = gfx_v9_0_init_microcode(adev);
1745         if (r) {
1746                 DRM_ERROR("Failed to load gfx firmware!\n");
1747                 return r;
1748         }
1749
1750         r = gfx_v9_0_rlc_init(adev);
1751         if (r) {
1752                 DRM_ERROR("Failed to init rlc BOs!\n");
1753                 return r;
1754         }
1755
1756         r = gfx_v9_0_mec_init(adev);
1757         if (r) {
1758                 DRM_ERROR("Failed to init MEC BOs!\n");
1759                 return r;
1760         }
1761
1762         /* set up the gfx ring */
1763         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1764                 ring = &adev->gfx.gfx_ring[i];
1765                 ring->ring_obj = NULL;
1766                 if (!i)
1767                         sprintf(ring->name, "gfx");
1768                 else
1769                         sprintf(ring->name, "gfx_%d", i);
1770                 ring->use_doorbell = true;
1771                 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1772                 r = amdgpu_ring_init(adev, ring, 1024,
1773                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1774                 if (r)
1775                         return r;
1776         }
1777
1778         /* set up the compute queues - allocate horizontally across pipes */
1779         ring_id = 0;
1780         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1781                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1782                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1783                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
1784                                         continue;
1785
1786                                 r = gfx_v9_0_compute_ring_init(adev,
1787                                                                ring_id,
1788                                                                i, k, j);
1789                                 if (r)
1790                                         return r;
1791
1792                                 ring_id++;
1793                         }
1794                 }
1795         }
1796
1797         r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE);
1798         if (r) {
1799                 DRM_ERROR("Failed to init KIQ BOs!\n");
1800                 return r;
1801         }
1802
1803         kiq = &adev->gfx.kiq;
1804         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1805         if (r)
1806                 return r;
1807
1808         /* create MQD for all compute queues as wel as KIQ for SRIOV case */
1809         r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
1810         if (r)
1811                 return r;
1812
1813         adev->gfx.ce_ram_size = 0x8000;
1814
1815         r = gfx_v9_0_gpu_early_init(adev);
1816         if (r)
1817                 return r;
1818
1819         r = gfx_v9_0_ngg_init(adev);
1820         if (r)
1821                 return r;
1822
1823         return 0;
1824 }
1825
1826
1827 static int gfx_v9_0_sw_fini(void *handle)
1828 {
1829         int i;
1830         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1831
1832         amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1833         amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1834         amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1835
1836         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1837                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1838         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1839                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1840
1841         amdgpu_gfx_compute_mqd_sw_fini(adev);
1842         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1843         amdgpu_gfx_kiq_fini(adev);
1844
1845         gfx_v9_0_mec_fini(adev);
1846         gfx_v9_0_ngg_fini(adev);
1847         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
1848                                 &adev->gfx.rlc.clear_state_gpu_addr,
1849                                 (void **)&adev->gfx.rlc.cs_ptr);
1850         if (adev->asic_type == CHIP_RAVEN) {
1851                 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
1852                                 &adev->gfx.rlc.cp_table_gpu_addr,
1853                                 (void **)&adev->gfx.rlc.cp_table_ptr);
1854         }
1855         gfx_v9_0_free_microcode(adev);
1856
1857         return 0;
1858 }
1859
1860
1861 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1862 {
1863         /* TODO */
1864 }
1865
1866 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1867 {
1868         u32 data;
1869
1870         if (instance == 0xffffffff)
1871                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1872         else
1873                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1874
1875         if (se_num == 0xffffffff)
1876                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1877         else
1878                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1879
1880         if (sh_num == 0xffffffff)
1881                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1882         else
1883                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1884
1885         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1886 }
1887
1888 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1889 {
1890         u32 data, mask;
1891
1892         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1893         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1894
1895         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1896         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1897
1898         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1899                                          adev->gfx.config.max_sh_per_se);
1900
1901         return (~data) & mask;
1902 }
1903
1904 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1905 {
1906         int i, j;
1907         u32 data;
1908         u32 active_rbs = 0;
1909         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1910                                         adev->gfx.config.max_sh_per_se;
1911
1912         mutex_lock(&adev->grbm_idx_mutex);
1913         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1914                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1915                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1916                         data = gfx_v9_0_get_rb_active_bitmap(adev);
1917                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1918                                                rb_bitmap_width_per_sh);
1919                 }
1920         }
1921         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1922         mutex_unlock(&adev->grbm_idx_mutex);
1923
1924         adev->gfx.config.backend_enable_mask = active_rbs;
1925         adev->gfx.config.num_rbs = hweight32(active_rbs);
1926 }
1927
1928 #define DEFAULT_SH_MEM_BASES    (0x6000)
1929 #define FIRST_COMPUTE_VMID      (8)
1930 #define LAST_COMPUTE_VMID       (16)
1931 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1932 {
1933         int i;
1934         uint32_t sh_mem_config;
1935         uint32_t sh_mem_bases;
1936
1937         /*
1938          * Configure apertures:
1939          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1940          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1941          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1942          */
1943         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1944
1945         sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1946                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1947                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1948
1949         mutex_lock(&adev->srbm_mutex);
1950         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1951                 soc15_grbm_select(adev, 0, 0, 0, i);
1952                 /* CP and shaders */
1953                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1954                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1955         }
1956         soc15_grbm_select(adev, 0, 0, 0, 0);
1957         mutex_unlock(&adev->srbm_mutex);
1958 }
1959
1960 static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
1961 {
1962         u32 tmp;
1963         int i;
1964
1965         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1966
1967         gfx_v9_0_tiling_mode_table_init(adev);
1968
1969         gfx_v9_0_setup_rb(adev);
1970         gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1971         adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);
1972
1973         /* XXX SH_MEM regs */
1974         /* where to put LDS, scratch, GPUVM in FSA64 space */
1975         mutex_lock(&adev->srbm_mutex);
1976         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) {
1977                 soc15_grbm_select(adev, 0, 0, 0, i);
1978                 /* CP and shaders */
1979                 if (i == 0) {
1980                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1981                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1982                         WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1983                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
1984                 } else {
1985                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1986                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1987                         WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1988                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1989                                 (adev->gmc.private_aperture_start >> 48));
1990                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1991                                 (adev->gmc.shared_aperture_start >> 48));
1992                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
1993                 }
1994         }
1995         soc15_grbm_select(adev, 0, 0, 0, 0);
1996
1997         mutex_unlock(&adev->srbm_mutex);
1998
1999         gfx_v9_0_init_compute_vmid(adev);
2000
2001         mutex_lock(&adev->grbm_idx_mutex);
2002         /*
2003          * making sure that the following register writes will be broadcasted
2004          * to all the shaders
2005          */
2006         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2007
2008         WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
2009                    (adev->gfx.config.sc_prim_fifo_size_frontend <<
2010                         PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
2011                    (adev->gfx.config.sc_prim_fifo_size_backend <<
2012                         PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
2013                    (adev->gfx.config.sc_hiz_tile_fifo_size <<
2014                         PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
2015                    (adev->gfx.config.sc_earlyz_tile_fifo_size <<
2016                         PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
2017         mutex_unlock(&adev->grbm_idx_mutex);
2018
2019 }
2020
2021 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2022 {
2023         u32 i, j, k;
2024         u32 mask;
2025
2026         mutex_lock(&adev->grbm_idx_mutex);
2027         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2028                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2029                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
2030                         for (k = 0; k < adev->usec_timeout; k++) {
2031                                 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
2032                                         break;
2033                                 udelay(1);
2034                         }
2035                         if (k == adev->usec_timeout) {
2036                                 gfx_v9_0_select_se_sh(adev, 0xffffffff,
2037                                                       0xffffffff, 0xffffffff);
2038                                 mutex_unlock(&adev->grbm_idx_mutex);
2039                                 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
2040                                          i, j);
2041                                 return;
2042                         }
2043                 }
2044         }
2045         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2046         mutex_unlock(&adev->grbm_idx_mutex);
2047
2048         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
2049                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
2050                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
2051                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
2052         for (k = 0; k < adev->usec_timeout; k++) {
2053                 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
2054                         break;
2055                 udelay(1);
2056         }
2057 }
2058
2059 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2060                                                bool enable)
2061 {
2062         u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
2063
2064         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
2065         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
2066         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
2067         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
2068
2069         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
2070 }
2071
2072 static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
2073 {
2074         /* csib */
2075         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
2076                         adev->gfx.rlc.clear_state_gpu_addr >> 32);
2077         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
2078                         adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
2079         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
2080                         adev->gfx.rlc.clear_state_size);
2081 }
2082
2083 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format,
2084                                 int indirect_offset,
2085                                 int list_size,
2086                                 int *unique_indirect_regs,
2087                                 int unique_indirect_reg_count,
2088                                 int *indirect_start_offsets,
2089                                 int *indirect_start_offsets_count,
2090                                 int max_start_offsets_count)
2091 {
2092         int idx;
2093
2094         for (; indirect_offset < list_size; indirect_offset++) {
2095                 WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count);
2096                 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
2097                 *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
2098
2099                 while (register_list_format[indirect_offset] != 0xFFFFFFFF) {
2100                         indirect_offset += 2;
2101
2102                         /* look for the matching indice */
2103                         for (idx = 0; idx < unique_indirect_reg_count; idx++) {
2104                                 if (unique_indirect_regs[idx] ==
2105                                         register_list_format[indirect_offset] ||
2106                                         !unique_indirect_regs[idx])
2107                                         break;
2108                         }
2109
2110                         BUG_ON(idx >= unique_indirect_reg_count);
2111
2112                         if (!unique_indirect_regs[idx])
2113                                 unique_indirect_regs[idx] = register_list_format[indirect_offset];
2114
2115                         indirect_offset++;
2116                 }
2117         }
2118 }
2119
2120 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev)
2121 {
2122         int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
2123         int unique_indirect_reg_count = 0;
2124
2125         int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
2126         int indirect_start_offsets_count = 0;
2127
2128         int list_size = 0;
2129         int i = 0, j = 0;
2130         u32 tmp = 0;
2131
2132         u32 *register_list_format =
2133                 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
2134         if (!register_list_format)
2135                 return -ENOMEM;
2136         memcpy(register_list_format, adev->gfx.rlc.register_list_format,
2137                 adev->gfx.rlc.reg_list_format_size_bytes);
2138
2139         /* setup unique_indirect_regs array and indirect_start_offsets array */
2140         unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs);
2141         gfx_v9_1_parse_ind_reg_list(register_list_format,
2142                                     adev->gfx.rlc.reg_list_format_direct_reg_list_length,
2143                                     adev->gfx.rlc.reg_list_format_size_bytes >> 2,
2144                                     unique_indirect_regs,
2145                                     unique_indirect_reg_count,
2146                                     indirect_start_offsets,
2147                                     &indirect_start_offsets_count,
2148                                     ARRAY_SIZE(indirect_start_offsets));
2149
2150         /* enable auto inc in case it is disabled */
2151         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
2152         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
2153         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
2154
2155         /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
2156         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
2157                 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
2158         for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
2159                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
2160                         adev->gfx.rlc.register_restore[i]);
2161
2162         /* load indirect register */
2163         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2164                 adev->gfx.rlc.reg_list_format_start);
2165
2166         /* direct register portion */
2167         for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++)
2168                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
2169                         register_list_format[i]);
2170
2171         /* indirect register portion */
2172         while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) {
2173                 if (register_list_format[i] == 0xFFFFFFFF) {
2174                         WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2175                         continue;
2176                 }
2177
2178                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2179                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2180
2181                 for (j = 0; j < unique_indirect_reg_count; j++) {
2182                         if (register_list_format[i] == unique_indirect_regs[j]) {
2183                                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j);
2184                                 break;
2185                         }
2186                 }
2187
2188                 BUG_ON(j >= unique_indirect_reg_count);
2189
2190                 i++;
2191         }
2192
2193         /* set save/restore list size */
2194         list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
2195         list_size = list_size >> 1;
2196         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2197                 adev->gfx.rlc.reg_restore_list_size);
2198         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
2199
2200         /* write the starting offsets to RLC scratch ram */
2201         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2202                 adev->gfx.rlc.starting_offsets_start);
2203         for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
2204                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
2205                        indirect_start_offsets[i]);
2206
2207         /* load unique indirect regs*/
2208         for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) {
2209                 if (unique_indirect_regs[i] != 0) {
2210                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0)
2211                                + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i],
2212                                unique_indirect_regs[i] & 0x3FFFF);
2213
2214                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0)
2215                                + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i],
2216                                unique_indirect_regs[i] >> 20);
2217                 }
2218         }
2219
2220         kfree(register_list_format);
2221         return 0;
2222 }
2223
2224 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
2225 {
2226         WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1);
2227 }
2228
2229 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
2230                                              bool enable)
2231 {
2232         uint32_t data = 0;
2233         uint32_t default_data = 0;
2234
2235         default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
2236         if (enable == true) {
2237                 /* enable GFXIP control over CGPG */
2238                 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2239                 if(default_data != data)
2240                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2241
2242                 /* update status */
2243                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
2244                 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
2245                 if(default_data != data)
2246                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2247         } else {
2248                 /* restore GFXIP control over GCPG */
2249                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2250                 if(default_data != data)
2251                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2252         }
2253 }
2254
2255 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
2256 {
2257         uint32_t data = 0;
2258
2259         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2260                               AMD_PG_SUPPORT_GFX_SMG |
2261                               AMD_PG_SUPPORT_GFX_DMG)) {
2262                 /* init IDLE_POLL_COUNT = 60 */
2263                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2264                 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
2265                 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2266                 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2267
2268                 /* init RLC PG Delay */
2269                 data = 0;
2270                 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
2271                 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
2272                 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
2273                 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
2274                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
2275
2276                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
2277                 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
2278                 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
2279                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
2280
2281                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
2282                 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
2283                 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
2284                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
2285
2286                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
2287                 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2288
2289                 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
2290                 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2291                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
2292
2293                 pwr_10_0_gfxip_control_over_cgpg(adev, true);
2294         }
2295 }
2296
2297 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
2298                                                 bool enable)
2299 {
2300         uint32_t data = 0;
2301         uint32_t default_data = 0;
2302
2303         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2304         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2305                              SMU_CLK_SLOWDOWN_ON_PU_ENABLE,
2306                              enable ? 1 : 0);
2307         if (default_data != data)
2308                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2309 }
2310
2311 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
2312                                                 bool enable)
2313 {
2314         uint32_t data = 0;
2315         uint32_t default_data = 0;
2316
2317         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2318         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2319                              SMU_CLK_SLOWDOWN_ON_PD_ENABLE,
2320                              enable ? 1 : 0);
2321         if(default_data != data)
2322                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2323 }
2324
2325 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
2326                                         bool enable)
2327 {
2328         uint32_t data = 0;
2329         uint32_t default_data = 0;
2330
2331         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2332         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2333                              CP_PG_DISABLE,
2334                              enable ? 0 : 1);
2335         if(default_data != data)
2336                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2337 }
2338
2339 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
2340                                                 bool enable)
2341 {
2342         uint32_t data, default_data;
2343
2344         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2345         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2346                              GFX_POWER_GATING_ENABLE,
2347                              enable ? 1 : 0);
2348         if(default_data != data)
2349                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2350 }
2351
2352 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
2353                                                 bool enable)
2354 {
2355         uint32_t data, default_data;
2356
2357         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2358         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2359                              GFX_PIPELINE_PG_ENABLE,
2360                              enable ? 1 : 0);
2361         if(default_data != data)
2362                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2363
2364         if (!enable)
2365                 /* read any GFX register to wake up GFX */
2366                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
2367 }
2368
2369 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
2370                                                        bool enable)
2371 {
2372         uint32_t data, default_data;
2373
2374         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2375         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2376                              STATIC_PER_CU_PG_ENABLE,
2377                              enable ? 1 : 0);
2378         if(default_data != data)
2379                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2380 }
2381
2382 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
2383                                                 bool enable)
2384 {
2385         uint32_t data, default_data;
2386
2387         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2388         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2389                              DYN_PER_CU_PG_ENABLE,
2390                              enable ? 1 : 0);
2391         if(default_data != data)
2392                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2393 }
2394
2395 static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
2396 {
2397         gfx_v9_0_init_csb(adev);
2398
2399         /*
2400          * Rlc save restore list is workable since v2_1.
2401          * And it's needed by gfxoff feature.
2402          */
2403         if (adev->gfx.rlc.is_rlc_v2_1) {
2404                 gfx_v9_1_init_rlc_save_restore_list(adev);
2405                 gfx_v9_0_enable_save_restore_machine(adev);
2406         }
2407
2408         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2409                               AMD_PG_SUPPORT_GFX_SMG |
2410                               AMD_PG_SUPPORT_GFX_DMG |
2411                               AMD_PG_SUPPORT_CP |
2412                               AMD_PG_SUPPORT_GDS |
2413                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
2414                 WREG32(mmRLC_JUMP_TABLE_RESTORE,
2415                        adev->gfx.rlc.cp_table_gpu_addr >> 8);
2416                 gfx_v9_0_init_gfx_power_gating(adev);
2417         }
2418 }
2419
2420 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
2421 {
2422         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);
2423         gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2424         gfx_v9_0_wait_for_rlc_serdes(adev);
2425 }
2426
2427 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
2428 {
2429         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2430         udelay(50);
2431         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2432         udelay(50);
2433 }
2434
2435 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
2436 {
2437 #ifdef AMDGPU_RLC_DEBUG_RETRY
2438         u32 rlc_ucode_ver;
2439 #endif
2440
2441         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
2442
2443         /* carrizo do enable cp interrupt after cp inited */
2444         if (!(adev->flags & AMD_IS_APU))
2445                 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2446
2447         udelay(50);
2448
2449 #ifdef AMDGPU_RLC_DEBUG_RETRY
2450         /* RLC_GPM_GENERAL_6 : RLC Ucode version */
2451         rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
2452         if(rlc_ucode_ver == 0x108) {
2453                 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2454                                 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2455                 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2456                  * default is 0x9C4 to create a 100us interval */
2457                 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
2458                 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
2459                  * to disable the page fault retry interrupts, default is
2460                  * 0x100 (256) */
2461                 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
2462         }
2463 #endif
2464 }
2465
2466 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2467 {
2468         const struct rlc_firmware_header_v2_0 *hdr;
2469         const __le32 *fw_data;
2470         unsigned i, fw_size;
2471
2472         if (!adev->gfx.rlc_fw)
2473                 return -EINVAL;
2474
2475         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2476         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2477
2478         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2479                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2480         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2481
2482         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
2483                         RLCG_UCODE_LOADING_START_ADDRESS);
2484         for (i = 0; i < fw_size; i++)
2485                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2486         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2487
2488         return 0;
2489 }
2490
2491 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2492 {
2493         int r;
2494
2495         if (amdgpu_sriov_vf(adev)) {
2496                 gfx_v9_0_init_csb(adev);
2497                 return 0;
2498         }
2499
2500         gfx_v9_0_rlc_stop(adev);
2501
2502         /* disable CG */
2503         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
2504
2505         gfx_v9_0_rlc_reset(adev);
2506
2507         gfx_v9_0_init_pg(adev);
2508
2509         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2510                 /* legacy rlc firmware loading */
2511                 r = gfx_v9_0_rlc_load_microcode(adev);
2512                 if (r)
2513                         return r;
2514         }
2515
2516         if (adev->asic_type == CHIP_RAVEN ||
2517             adev->asic_type == CHIP_VEGA20) {
2518                 if (amdgpu_lbpw != 0)
2519                         gfx_v9_0_enable_lbpw(adev, true);
2520                 else
2521                         gfx_v9_0_enable_lbpw(adev, false);
2522         }
2523
2524         gfx_v9_0_rlc_start(adev);
2525
2526         return 0;
2527 }
2528
2529 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2530 {
2531         int i;
2532         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2533
2534         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2535         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2536         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2537         if (!enable) {
2538                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2539                         adev->gfx.gfx_ring[i].ready = false;
2540         }
2541         WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
2542         udelay(50);
2543 }
2544
2545 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2546 {
2547         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2548         const struct gfx_firmware_header_v1_0 *ce_hdr;
2549         const struct gfx_firmware_header_v1_0 *me_hdr;
2550         const __le32 *fw_data;
2551         unsigned i, fw_size;
2552
2553         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2554                 return -EINVAL;
2555
2556         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2557                 adev->gfx.pfp_fw->data;
2558         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2559                 adev->gfx.ce_fw->data;
2560         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2561                 adev->gfx.me_fw->data;
2562
2563         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2564         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2565         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2566
2567         gfx_v9_0_cp_gfx_enable(adev, false);
2568
2569         /* PFP */
2570         fw_data = (const __le32 *)
2571                 (adev->gfx.pfp_fw->data +
2572                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2573         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2574         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
2575         for (i = 0; i < fw_size; i++)
2576                 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2577         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2578
2579         /* CE */
2580         fw_data = (const __le32 *)
2581                 (adev->gfx.ce_fw->data +
2582                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2583         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2584         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
2585         for (i = 0; i < fw_size; i++)
2586                 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2587         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2588
2589         /* ME */
2590         fw_data = (const __le32 *)
2591                 (adev->gfx.me_fw->data +
2592                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2593         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2594         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
2595         for (i = 0; i < fw_size; i++)
2596                 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2597         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2598
2599         return 0;
2600 }
2601
2602 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
2603 {
2604         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2605         const struct cs_section_def *sect = NULL;
2606         const struct cs_extent_def *ext = NULL;
2607         int r, i, tmp;
2608
2609         /* init the CP */
2610         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2611         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
2612
2613         gfx_v9_0_cp_gfx_enable(adev, true);
2614
2615         r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
2616         if (r) {
2617                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2618                 return r;
2619         }
2620
2621         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2622         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2623
2624         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2625         amdgpu_ring_write(ring, 0x80000000);
2626         amdgpu_ring_write(ring, 0x80000000);
2627
2628         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
2629                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2630                         if (sect->id == SECT_CONTEXT) {
2631                                 amdgpu_ring_write(ring,
2632                                        PACKET3(PACKET3_SET_CONTEXT_REG,
2633                                                ext->reg_count));
2634                                 amdgpu_ring_write(ring,
2635                                        ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2636                                 for (i = 0; i < ext->reg_count; i++)
2637                                         amdgpu_ring_write(ring, ext->extent[i]);
2638                         }
2639                 }
2640         }
2641
2642         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2643         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2644
2645         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2646         amdgpu_ring_write(ring, 0);
2647
2648         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2649         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2650         amdgpu_ring_write(ring, 0x8000);
2651         amdgpu_ring_write(ring, 0x8000);
2652
2653         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));
2654         tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
2655                 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
2656         amdgpu_ring_write(ring, tmp);
2657         amdgpu_ring_write(ring, 0);
2658
2659         amdgpu_ring_commit(ring);
2660
2661         return 0;
2662 }
2663
2664 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
2665 {
2666         struct amdgpu_ring *ring;
2667         u32 tmp;
2668         u32 rb_bufsz;
2669         u64 rb_addr, rptr_addr, wptr_gpu_addr;
2670
2671         /* Set the write pointer delay */
2672         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
2673
2674         /* set the RB to use vmid 0 */
2675         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
2676
2677         /* Set ring buffer size */
2678         ring = &adev->gfx.gfx_ring[0];
2679         rb_bufsz = order_base_2(ring->ring_size / 8);
2680         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2681         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2682 #ifdef __BIG_ENDIAN
2683         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2684 #endif
2685         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2686
2687         /* Initialize the ring buffer's write pointers */
2688         ring->wptr = 0;
2689         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2690         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2691
2692         /* set the wb address wether it's enabled or not */
2693         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2694         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2695         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2696
2697         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2698         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
2699         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
2700
2701         mdelay(1);
2702         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2703
2704         rb_addr = ring->gpu_addr >> 8;
2705         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2706         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2707
2708         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2709         if (ring->use_doorbell) {
2710                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2711                                     DOORBELL_OFFSET, ring->doorbell_index);
2712                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2713                                     DOORBELL_EN, 1);
2714         } else {
2715                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
2716         }
2717         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
2718
2719         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2720                         DOORBELL_RANGE_LOWER, ring->doorbell_index);
2721         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2722
2723         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
2724                        CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2725
2726
2727         /* start the ring */
2728         gfx_v9_0_cp_gfx_start(adev);
2729         ring->ready = true;
2730
2731         return 0;
2732 }
2733
2734 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2735 {
2736         int i;
2737
2738         if (enable) {
2739                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2740         } else {
2741                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
2742                         (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2743                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2744                         adev->gfx.compute_ring[i].ready = false;
2745                 adev->gfx.kiq.ring.ready = false;
2746         }
2747         udelay(50);
2748 }
2749
2750 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2751 {
2752         const struct gfx_firmware_header_v1_0 *mec_hdr;
2753         const __le32 *fw_data;
2754         unsigned i;
2755         u32 tmp;
2756
2757         if (!adev->gfx.mec_fw)
2758                 return -EINVAL;
2759
2760         gfx_v9_0_cp_compute_enable(adev, false);
2761
2762         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2763         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2764
2765         fw_data = (const __le32 *)
2766                 (adev->gfx.mec_fw->data +
2767                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2768         tmp = 0;
2769         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2770         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2771         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
2772
2773         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
2774                 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
2775         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2776                 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2777
2778         /* MEC1 */
2779         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2780                          mec_hdr->jt_offset);
2781         for (i = 0; i < mec_hdr->jt_size; i++)
2782                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
2783                         le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2784
2785         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2786                         adev->gfx.mec_fw_version);
2787         /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2788
2789         return 0;
2790 }
2791
2792 /* KIQ functions */
2793 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
2794 {
2795         uint32_t tmp;
2796         struct amdgpu_device *adev = ring->adev;
2797
2798         /* tell RLC which is KIQ queue */
2799         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
2800         tmp &= 0xffffff00;
2801         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2802         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2803         tmp |= 0x80;
2804         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2805 }
2806
2807 static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
2808 {
2809         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2810         uint64_t queue_mask = 0;
2811         int r, i;
2812
2813         for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
2814                 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
2815                         continue;
2816
2817                 /* This situation may be hit in the future if a new HW
2818                  * generation exposes more than 64 queues. If so, the
2819                  * definition of queue_mask needs updating */
2820                 if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
2821                         DRM_ERROR("Invalid KCQ enabled: %d\n", i);
2822                         break;
2823                 }
2824
2825                 queue_mask |= (1ull << i);
2826         }
2827
2828         r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 8);
2829         if (r) {
2830                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2831                 return r;
2832         }
2833
2834         /* set resources */
2835         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
2836         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
2837                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
2838         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
2839         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
2840         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
2841         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
2842         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
2843         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
2844         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2845                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2846                 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
2847                 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2848
2849                 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
2850                 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
2851                 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2852                                   PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
2853                                   PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
2854                                   PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
2855                                   PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
2856                                   PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
2857                                   PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
2858                                   PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
2859                                   PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
2860                                   PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
2861                 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
2862                 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
2863                 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
2864                 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
2865                 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
2866         }
2867
2868         r = amdgpu_ring_test_ring(kiq_ring);
2869         if (r) {
2870                 DRM_ERROR("KCQ enable failed\n");
2871                 kiq_ring->ready = false;
2872         }
2873
2874         return r;
2875 }
2876
2877 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
2878 {
2879         struct amdgpu_device *adev = ring->adev;
2880         struct v9_mqd *mqd = ring->mqd_ptr;
2881         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
2882         uint32_t tmp;
2883
2884         mqd->header = 0xC0310800;
2885         mqd->compute_pipelinestat_enable = 0x00000001;
2886         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2887         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2888         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2889         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2890         mqd->compute_misc_reserved = 0x00000003;
2891
2892         mqd->dynamic_cu_mask_addr_lo =
2893                 lower_32_bits(ring->mqd_gpu_addr
2894                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2895         mqd->dynamic_cu_mask_addr_hi =
2896                 upper_32_bits(ring->mqd_gpu_addr
2897                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2898
2899         eop_base_addr = ring->eop_gpu_addr >> 8;
2900         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
2901         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
2902
2903         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2904         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
2905         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
2906                         (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
2907
2908         mqd->cp_hqd_eop_control = tmp;
2909
2910         /* enable doorbell? */
2911         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2912
2913         if (ring->use_doorbell) {
2914                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2915                                     DOORBELL_OFFSET, ring->doorbell_index);
2916                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2917                                     DOORBELL_EN, 1);
2918                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2919                                     DOORBELL_SOURCE, 0);
2920                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2921                                     DOORBELL_HIT, 0);
2922         } else {
2923                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2924                                          DOORBELL_EN, 0);
2925         }
2926
2927         mqd->cp_hqd_pq_doorbell_control = tmp;
2928
2929         /* disable the queue if it's active */
2930         ring->wptr = 0;
2931         mqd->cp_hqd_dequeue_request = 0;
2932         mqd->cp_hqd_pq_rptr = 0;
2933         mqd->cp_hqd_pq_wptr_lo = 0;
2934         mqd->cp_hqd_pq_wptr_hi = 0;
2935
2936         /* set the pointer to the MQD */
2937         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
2938         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
2939
2940         /* set MQD vmid to 0 */
2941         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
2942         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2943         mqd->cp_mqd_control = tmp;
2944
2945         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2946         hqd_gpu_addr = ring->gpu_addr >> 8;
2947         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2948         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2949
2950         /* set up the HQD, this is similar to CP_RB0_CNTL */
2951         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
2952         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
2953                             (order_base_2(ring->ring_size / 4) - 1));
2954         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
2955                         ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
2956 #ifdef __BIG_ENDIAN
2957         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
2958 #endif
2959         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
2960         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
2961         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
2962         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
2963         mqd->cp_hqd_pq_control = tmp;
2964
2965         /* set the wb address whether it's enabled or not */
2966         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2967         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2968         mqd->cp_hqd_pq_rptr_report_addr_hi =
2969                 upper_32_bits(wb_gpu_addr) & 0xffff;
2970
2971         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2972         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2973         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2974         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2975
2976         tmp = 0;
2977         /* enable the doorbell if requested */
2978         if (ring->use_doorbell) {
2979                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2980                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2981                                 DOORBELL_OFFSET, ring->doorbell_index);
2982
2983                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2984                                          DOORBELL_EN, 1);
2985                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2986                                          DOORBELL_SOURCE, 0);
2987                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2988                                          DOORBELL_HIT, 0);
2989         }
2990
2991         mqd->cp_hqd_pq_doorbell_control = tmp;
2992
2993         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2994         ring->wptr = 0;
2995         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
2996
2997         /* set the vmid for the queue */
2998         mqd->cp_hqd_vmid = 0;
2999
3000         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
3001         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3002         mqd->cp_hqd_persistent_state = tmp;
3003
3004         /* set MIN_IB_AVAIL_SIZE */
3005         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
3006         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
3007         mqd->cp_hqd_ib_control = tmp;
3008
3009         /* activate the queue */
3010         mqd->cp_hqd_active = 1;
3011
3012         return 0;
3013 }
3014
3015 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
3016 {
3017         struct amdgpu_device *adev = ring->adev;
3018         struct v9_mqd *mqd = ring->mqd_ptr;
3019         int j;
3020
3021         /* disable wptr polling */
3022         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3023
3024         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
3025                mqd->cp_hqd_eop_base_addr_lo);
3026         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
3027                mqd->cp_hqd_eop_base_addr_hi);
3028
3029         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3030         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
3031                mqd->cp_hqd_eop_control);
3032
3033         /* enable doorbell? */
3034         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3035                mqd->cp_hqd_pq_doorbell_control);
3036
3037         /* disable the queue if it's active */
3038         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3039                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
3040                 for (j = 0; j < adev->usec_timeout; j++) {
3041                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3042                                 break;
3043                         udelay(1);
3044                 }
3045                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
3046                        mqd->cp_hqd_dequeue_request);
3047                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
3048                        mqd->cp_hqd_pq_rptr);
3049                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3050                        mqd->cp_hqd_pq_wptr_lo);
3051                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3052                        mqd->cp_hqd_pq_wptr_hi);
3053         }
3054
3055         /* set the pointer to the MQD */
3056         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
3057                mqd->cp_mqd_base_addr_lo);
3058         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
3059                mqd->cp_mqd_base_addr_hi);
3060
3061         /* set MQD vmid to 0 */
3062         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
3063                mqd->cp_mqd_control);
3064
3065         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3066         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
3067                mqd->cp_hqd_pq_base_lo);
3068         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
3069                mqd->cp_hqd_pq_base_hi);
3070
3071         /* set up the HQD, this is similar to CP_RB0_CNTL */
3072         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
3073                mqd->cp_hqd_pq_control);
3074
3075         /* set the wb address whether it's enabled or not */
3076         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3077                                 mqd->cp_hqd_pq_rptr_report_addr_lo);
3078         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3079                                 mqd->cp_hqd_pq_rptr_report_addr_hi);
3080
3081         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3082         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
3083                mqd->cp_hqd_pq_wptr_poll_addr_lo);
3084         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3085                mqd->cp_hqd_pq_wptr_poll_addr_hi);
3086
3087         /* enable the doorbell if requested */
3088         if (ring->use_doorbell) {
3089                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
3090                                         (AMDGPU_DOORBELL64_KIQ *2) << 2);
3091                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
3092                                         (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
3093         }
3094
3095         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3096                mqd->cp_hqd_pq_doorbell_control);
3097
3098         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3099         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3100                mqd->cp_hqd_pq_wptr_lo);
3101         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3102                mqd->cp_hqd_pq_wptr_hi);
3103
3104         /* set the vmid for the queue */
3105         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3106
3107         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
3108                mqd->cp_hqd_persistent_state);
3109
3110         /* activate the queue */
3111         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
3112                mqd->cp_hqd_active);
3113
3114         if (ring->use_doorbell)
3115                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3116
3117         return 0;
3118 }
3119
3120 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring)
3121 {
3122         struct amdgpu_device *adev = ring->adev;
3123         int j;
3124
3125         /* disable the queue if it's active */
3126         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3127
3128                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
3129
3130                 for (j = 0; j < adev->usec_timeout; j++) {
3131                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3132                                 break;
3133                         udelay(1);
3134                 }
3135
3136                 if (j == AMDGPU_MAX_USEC_TIMEOUT) {
3137                         DRM_DEBUG("KIQ dequeue request failed.\n");
3138
3139                         /* Manual disable if dequeue request times out */
3140                         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
3141                 }
3142
3143                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
3144                       0);
3145         }
3146
3147         WREG32_SOC15(GC, 0, mmCP_HQD_IQ_TIMER, 0);
3148         WREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL, 0);
3149         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0);
3150         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
3151         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
3152         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 0);
3153         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);
3154         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0);
3155
3156         return 0;
3157 }
3158
3159 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
3160 {
3161         struct amdgpu_device *adev = ring->adev;
3162         struct v9_mqd *mqd = ring->mqd_ptr;
3163         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
3164
3165         gfx_v9_0_kiq_setting(ring);
3166
3167         if (adev->in_gpu_reset) { /* for GPU_RESET case */
3168                 /* reset MQD to a clean status */
3169                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3170                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
3171
3172                 /* reset ring buffer */
3173                 ring->wptr = 0;
3174                 amdgpu_ring_clear_ring(ring);
3175
3176                 mutex_lock(&adev->srbm_mutex);
3177                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3178                 gfx_v9_0_kiq_init_register(ring);
3179                 soc15_grbm_select(adev, 0, 0, 0, 0);
3180                 mutex_unlock(&adev->srbm_mutex);
3181         } else {
3182                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
3183                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
3184                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
3185                 mutex_lock(&adev->srbm_mutex);
3186                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3187                 gfx_v9_0_mqd_init(ring);
3188                 gfx_v9_0_kiq_init_register(ring);
3189                 soc15_grbm_select(adev, 0, 0, 0, 0);
3190                 mutex_unlock(&adev->srbm_mutex);
3191
3192                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3193                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
3194         }
3195
3196         return 0;
3197 }
3198
3199 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
3200 {
3201         struct amdgpu_device *adev = ring->adev;
3202         struct v9_mqd *mqd = ring->mqd_ptr;
3203         int mqd_idx = ring - &adev->gfx.compute_ring[0];
3204
3205         if (!adev->in_gpu_reset && !adev->in_suspend) {
3206                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
3207                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
3208                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
3209                 mutex_lock(&adev->srbm_mutex);
3210                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3211                 gfx_v9_0_mqd_init(ring);
3212                 soc15_grbm_select(adev, 0, 0, 0, 0);
3213                 mutex_unlock(&adev->srbm_mutex);
3214
3215                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3216                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
3217         } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
3218                 /* reset MQD to a clean status */
3219                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3220                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
3221
3222                 /* reset ring buffer */
3223                 ring->wptr = 0;
3224                 amdgpu_ring_clear_ring(ring);
3225         } else {
3226                 amdgpu_ring_clear_ring(ring);
3227         }
3228
3229         return 0;
3230 }
3231
3232 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
3233 {
3234         struct amdgpu_ring *ring;
3235         int r;
3236
3237         ring = &adev->gfx.kiq.ring;
3238
3239         r = amdgpu_bo_reserve(ring->mqd_obj, false);
3240         if (unlikely(r != 0))
3241                 return r;
3242
3243         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3244         if (unlikely(r != 0))
3245                 return r;
3246
3247         gfx_v9_0_kiq_init_queue(ring);
3248         amdgpu_bo_kunmap(ring->mqd_obj);
3249         ring->mqd_ptr = NULL;
3250         amdgpu_bo_unreserve(ring->mqd_obj);
3251         ring->ready = true;
3252         return 0;
3253 }
3254
3255 static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev)
3256 {
3257         struct amdgpu_ring *ring = NULL;
3258         int r = 0, i;
3259
3260         gfx_v9_0_cp_compute_enable(adev, true);
3261
3262         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3263                 ring = &adev->gfx.compute_ring[i];
3264
3265                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3266                 if (unlikely(r != 0))
3267                         goto done;
3268                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3269                 if (!r) {
3270                         r = gfx_v9_0_kcq_init_queue(ring);
3271                         amdgpu_bo_kunmap(ring->mqd_obj);
3272                         ring->mqd_ptr = NULL;
3273                 }
3274                 amdgpu_bo_unreserve(ring->mqd_obj);
3275                 if (r)
3276                         goto done;
3277         }
3278
3279         r = gfx_v9_0_kiq_kcq_enable(adev);
3280 done:
3281         return r;
3282 }
3283
3284 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
3285 {
3286         int r, i;
3287         struct amdgpu_ring *ring;
3288
3289         if (!(adev->flags & AMD_IS_APU))
3290                 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
3291
3292         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
3293                 /* legacy firmware loading */
3294                 r = gfx_v9_0_cp_gfx_load_microcode(adev);
3295                 if (r)
3296                         return r;
3297
3298                 r = gfx_v9_0_cp_compute_load_microcode(adev);
3299                 if (r)
3300                         return r;
3301         }
3302
3303         r = gfx_v9_0_kiq_resume(adev);
3304         if (r)
3305                 return r;
3306
3307         r = gfx_v9_0_cp_gfx_resume(adev);
3308         if (r)
3309                 return r;
3310
3311         r = gfx_v9_0_kcq_resume(adev);
3312         if (r)
3313                 return r;
3314
3315         ring = &adev->gfx.gfx_ring[0];
3316         r = amdgpu_ring_test_ring(ring);
3317         if (r) {
3318                 ring->ready = false;
3319                 return r;
3320         }
3321
3322         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3323                 ring = &adev->gfx.compute_ring[i];
3324
3325                 ring->ready = true;
3326                 r = amdgpu_ring_test_ring(ring);
3327                 if (r)
3328                         ring->ready = false;
3329         }
3330
3331         gfx_v9_0_enable_gui_idle_interrupt(adev, true);
3332
3333         return 0;
3334 }
3335
3336 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
3337 {
3338         gfx_v9_0_cp_gfx_enable(adev, enable);
3339         gfx_v9_0_cp_compute_enable(adev, enable);
3340 }
3341
3342 static int gfx_v9_0_hw_init(void *handle)
3343 {
3344         int r;
3345         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3346
3347         gfx_v9_0_init_golden_registers(adev);
3348
3349         gfx_v9_0_constants_init(adev);
3350
3351         r = gfx_v9_0_csb_vram_pin(adev);
3352         if (r)
3353                 return r;
3354
3355         r = gfx_v9_0_rlc_resume(adev);
3356         if (r)
3357                 return r;
3358
3359         r = gfx_v9_0_cp_resume(adev);
3360         if (r)
3361                 return r;
3362
3363         r = gfx_v9_0_ngg_en(adev);
3364         if (r)
3365                 return r;
3366
3367         return r;
3368 }
3369
3370 static int gfx_v9_0_kcq_disable(struct amdgpu_device *adev)
3371 {
3372         int r, i;
3373         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
3374
3375         r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings);
3376         if (r)
3377                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
3378
3379         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3380                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3381
3382                 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3383                 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3384                                                 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
3385                                                 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3386                                                 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
3387                                                 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3388                 amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3389                 amdgpu_ring_write(kiq_ring, 0);
3390                 amdgpu_ring_write(kiq_ring, 0);
3391                 amdgpu_ring_write(kiq_ring, 0);
3392         }
3393         r = amdgpu_ring_test_ring(kiq_ring);
3394         if (r)
3395                 DRM_ERROR("KCQ disable failed\n");
3396
3397         return r;
3398 }
3399
3400 static int gfx_v9_0_hw_fini(void *handle)
3401 {
3402         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3403
3404         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3405         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3406
3407         /* disable KCQ to avoid CPC touch memory not valid anymore */
3408         gfx_v9_0_kcq_disable(adev);
3409
3410         if (amdgpu_sriov_vf(adev)) {
3411                 gfx_v9_0_cp_gfx_enable(adev, false);
3412                 /* must disable polling for SRIOV when hw finished, otherwise
3413                  * CPC engine may still keep fetching WB address which is already
3414                  * invalid after sw finished and trigger DMAR reading error in
3415                  * hypervisor side.
3416                  */
3417                 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3418                 return 0;
3419         }
3420
3421         /* Use deinitialize sequence from CAIL when unbinding device from driver,
3422          * otherwise KIQ is hanging when binding back
3423          */
3424         if (!adev->in_gpu_reset && !adev->in_suspend) {
3425                 mutex_lock(&adev->srbm_mutex);
3426                 soc15_grbm_select(adev, adev->gfx.kiq.ring.me,
3427                                 adev->gfx.kiq.ring.pipe,
3428                                 adev->gfx.kiq.ring.queue, 0);
3429                 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring);
3430                 soc15_grbm_select(adev, 0, 0, 0, 0);
3431                 mutex_unlock(&adev->srbm_mutex);
3432         }
3433
3434         gfx_v9_0_cp_enable(adev, false);
3435         gfx_v9_0_rlc_stop(adev);
3436
3437         gfx_v9_0_csb_vram_unpin(adev);
3438
3439         return 0;
3440 }
3441
3442 static int gfx_v9_0_suspend(void *handle)
3443 {
3444         return gfx_v9_0_hw_fini(handle);
3445 }
3446
3447 static int gfx_v9_0_resume(void *handle)
3448 {
3449         return gfx_v9_0_hw_init(handle);
3450 }
3451
3452 static bool gfx_v9_0_is_idle(void *handle)
3453 {
3454         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3455
3456         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
3457                                 GRBM_STATUS, GUI_ACTIVE))
3458                 return false;
3459         else
3460                 return true;
3461 }
3462
3463 static int gfx_v9_0_wait_for_idle(void *handle)
3464 {
3465         unsigned i;
3466         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3467
3468         for (i = 0; i < adev->usec_timeout; i++) {
3469                 if (gfx_v9_0_is_idle(handle))
3470                         return 0;
3471                 udelay(1);
3472         }
3473         return -ETIMEDOUT;
3474 }
3475
3476 static int gfx_v9_0_soft_reset(void *handle)
3477 {
3478         u32 grbm_soft_reset = 0;
3479         u32 tmp;
3480         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3481
3482         /* GRBM_STATUS */
3483         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
3484         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3485                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3486                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3487                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3488                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3489                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3490                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3491                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3492                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3493                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3494         }
3495
3496         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3497                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3498                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3499         }
3500
3501         /* GRBM_STATUS2 */
3502         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
3503         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3504                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3505                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3506
3507
3508         if (grbm_soft_reset) {
3509                 /* stop the rlc */
3510                 gfx_v9_0_rlc_stop(adev);
3511
3512                 /* Disable GFX parsing/prefetching */
3513                 gfx_v9_0_cp_gfx_enable(adev, false);
3514
3515                 /* Disable MEC parsing/prefetching */
3516                 gfx_v9_0_cp_compute_enable(adev, false);
3517
3518                 if (grbm_soft_reset) {
3519                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3520                         tmp |= grbm_soft_reset;
3521                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3522                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3523                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3524
3525                         udelay(50);
3526
3527                         tmp &= ~grbm_soft_reset;
3528                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3529                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3530                 }
3531
3532                 /* Wait a little for things to settle down */
3533                 udelay(50);
3534         }
3535         return 0;
3536 }
3537
3538 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3539 {
3540         uint64_t clock;
3541
3542         mutex_lock(&adev->gfx.gpu_clock_mutex);
3543         WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3544         clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3545                 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3546         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3547         return clock;
3548 }
3549
3550 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3551                                           uint32_t vmid,
3552                                           uint32_t gds_base, uint32_t gds_size,
3553                                           uint32_t gws_base, uint32_t gws_size,
3554                                           uint32_t oa_base, uint32_t oa_size)
3555 {
3556         struct amdgpu_device *adev = ring->adev;
3557
3558         /* GDS Base */
3559         gfx_v9_0_write_data_to_reg(ring, 0, false,
3560                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
3561                                    gds_base);
3562
3563         /* GDS Size */
3564         gfx_v9_0_write_data_to_reg(ring, 0, false,
3565                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
3566                                    gds_size);
3567
3568         /* GWS */
3569         gfx_v9_0_write_data_to_reg(ring, 0, false,
3570                                    SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
3571                                    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3572
3573         /* OA */
3574         gfx_v9_0_write_data_to_reg(ring, 0, false,
3575                                    SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
3576                                    (1 << (oa_size + oa_base)) - (1 << oa_base));
3577 }
3578
3579 static int gfx_v9_0_early_init(void *handle)
3580 {
3581         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3582
3583         adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
3584         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3585         gfx_v9_0_set_ring_funcs(adev);
3586         gfx_v9_0_set_irq_funcs(adev);
3587         gfx_v9_0_set_gds_init(adev);
3588         gfx_v9_0_set_rlc_funcs(adev);
3589
3590         return 0;
3591 }
3592
3593 static int gfx_v9_0_late_init(void *handle)
3594 {
3595         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3596         int r;
3597
3598         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3599         if (r)
3600                 return r;
3601
3602         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3603         if (r)
3604                 return r;
3605
3606         return 0;
3607 }
3608
3609 static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3610 {
3611         uint32_t rlc_setting, data;
3612         unsigned i;
3613
3614         if (adev->gfx.rlc.in_safe_mode)
3615                 return;
3616
3617         /* if RLC is not enabled, do nothing */
3618         rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3619         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3620                 return;
3621
3622         if (adev->cg_flags &
3623             (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
3624              AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3625                 data = RLC_SAFE_MODE__CMD_MASK;
3626                 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
3627                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3628
3629                 /* wait for RLC_SAFE_MODE */
3630                 for (i = 0; i < adev->usec_timeout; i++) {
3631                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3632                                 break;
3633                         udelay(1);
3634                 }
3635                 adev->gfx.rlc.in_safe_mode = true;
3636         }
3637 }
3638
3639 static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3640 {
3641         uint32_t rlc_setting, data;
3642
3643         if (!adev->gfx.rlc.in_safe_mode)
3644                 return;
3645
3646         /* if RLC is not enabled, do nothing */
3647         rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3648         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3649                 return;
3650
3651         if (adev->cg_flags &
3652             (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
3653                 /*
3654                  * Try to exit safe mode only if it is already in safe
3655                  * mode.
3656                  */
3657                 data = RLC_SAFE_MODE__CMD_MASK;
3658                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3659                 adev->gfx.rlc.in_safe_mode = false;
3660         }
3661 }
3662
3663 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3664                                                 bool enable)
3665 {
3666         gfx_v9_0_enter_rlc_safe_mode(adev);
3667
3668         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3669                 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
3670                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
3671                         gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
3672         } else {
3673                 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
3674                 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3675         }
3676
3677         gfx_v9_0_exit_rlc_safe_mode(adev);
3678 }
3679
3680 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
3681                                                 bool enable)
3682 {
3683         /* TODO: double check if we need to perform under safe mode */
3684         /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3685
3686         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
3687                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
3688         else
3689                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
3690
3691         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
3692                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
3693         else
3694                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
3695
3696         /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3697 }
3698
3699 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3700                                                       bool enable)
3701 {
3702         uint32_t data, def;
3703
3704         /* It is disabled by HW by default */
3705         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3706                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
3707                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3708
3709                 if (adev->asic_type != CHIP_VEGA12)
3710                         data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
3711
3712                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3713                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3714                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3715
3716                 /* only for Vega10 & Raven1 */
3717                 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
3718
3719                 if (def != data)
3720                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3721
3722                 /* MGLS is a global flag to control all MGLS in GFX */
3723                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3724                         /* 2 - RLC memory Light sleep */
3725                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
3726                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3727                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3728                                 if (def != data)
3729                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3730                         }
3731                         /* 3 - CP memory Light sleep */
3732                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3733                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3734                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3735                                 if (def != data)
3736                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3737                         }
3738                 }
3739         } else {
3740                 /* 1 - MGCG_OVERRIDE */
3741                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3742
3743                 if (adev->asic_type != CHIP_VEGA12)
3744                         data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
3745
3746                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
3747                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3748                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3749                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3750
3751                 if (def != data)
3752                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3753
3754                 /* 2 - disable MGLS in RLC */
3755                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3756                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3757                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3758                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3759                 }
3760
3761                 /* 3 - disable MGLS in CP */
3762                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3763                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3764                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3765                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3766                 }
3767         }
3768 }
3769
3770 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
3771                                            bool enable)
3772 {
3773         uint32_t data, def;
3774
3775         adev->gfx.rlc.funcs->enter_safe_mode(adev);
3776
3777         /* Enable 3D CGCG/CGLS */
3778         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3779                 /* write cmd to clear cgcg/cgls ov */
3780                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3781                 /* unset CGCG override */
3782                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3783                 /* update CGCG and CGLS override bits */
3784                 if (def != data)
3785                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3786
3787                 /* enable 3Dcgcg FSM(0x0000363f) */
3788                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3789
3790                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3791                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3792                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3793                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3794                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3795                 if (def != data)
3796                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3797
3798                 /* set IDLE_POLL_COUNT(0x00900100) */
3799                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3800                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3801                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3802                 if (def != data)
3803                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3804         } else {
3805                 /* Disable CGCG/CGLS */
3806                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3807                 /* disable cgcg, cgls should be disabled */
3808                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
3809                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
3810                 /* disable cgcg and cgls in FSM */
3811                 if (def != data)
3812                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3813         }
3814
3815         adev->gfx.rlc.funcs->exit_safe_mode(adev);
3816 }
3817
3818 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3819                                                       bool enable)
3820 {
3821         uint32_t def, data;
3822
3823         adev->gfx.rlc.funcs->enter_safe_mode(adev);
3824
3825         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3826                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3827                 /* unset CGCG override */
3828                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3829                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3830                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3831                 else
3832                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3833                 /* update CGCG and CGLS override bits */
3834                 if (def != data)
3835                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3836
3837                 /* enable cgcg FSM(0x0000363F) */
3838                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3839
3840                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3841                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3842                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3843                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3844                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3845                 if (def != data)
3846                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3847
3848                 /* set IDLE_POLL_COUNT(0x00900100) */
3849                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3850                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3851                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3852                 if (def != data)
3853                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3854         } else {
3855                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3856                 /* reset CGCG/CGLS bits */
3857                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3858                 /* disable cgcg and cgls in FSM */
3859                 if (def != data)
3860                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3861         }
3862
3863         adev->gfx.rlc.funcs->exit_safe_mode(adev);
3864 }
3865
3866 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3867                                             bool enable)
3868 {
3869         if (enable) {
3870                 /* CGCG/CGLS should be enabled after MGCG/MGLS
3871                  * ===  MGCG + MGLS ===
3872                  */
3873                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3874                 /* ===  CGCG /CGLS for GFX 3D Only === */
3875                 gfx_v9_0_update_3d_clock_gating(adev, enable);
3876                 /* ===  CGCG + CGLS === */
3877                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3878         } else {
3879                 /* CGCG/CGLS should be disabled before MGCG/MGLS
3880                  * ===  CGCG + CGLS ===
3881                  */
3882                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3883                 /* ===  CGCG /CGLS for GFX 3D Only === */
3884                 gfx_v9_0_update_3d_clock_gating(adev, enable);
3885                 /* ===  MGCG + MGLS === */
3886                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3887         }
3888         return 0;
3889 }
3890
3891 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3892         .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
3893         .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
3894 };
3895
3896 static int gfx_v9_0_set_powergating_state(void *handle,
3897                                           enum amd_powergating_state state)
3898 {
3899         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3900         bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
3901
3902         switch (adev->asic_type) {
3903         case CHIP_RAVEN:
3904                 if (!enable) {
3905                         amdgpu_gfx_off_ctrl(adev, false);
3906                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
3907                 }
3908                 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3909                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
3910                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
3911                 } else {
3912                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
3913                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
3914                 }
3915
3916                 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
3917                         gfx_v9_0_enable_cp_power_gating(adev, true);
3918                 else
3919                         gfx_v9_0_enable_cp_power_gating(adev, false);
3920
3921                 /* update gfx cgpg state */
3922                 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
3923
3924                 /* update mgcg state */
3925                 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
3926
3927                 if (enable)
3928                         amdgpu_gfx_off_ctrl(adev, true);
3929                 break;
3930         case CHIP_VEGA12:
3931                 if (!enable) {
3932                         amdgpu_gfx_off_ctrl(adev, false);
3933                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
3934                 } else {
3935                         amdgpu_gfx_off_ctrl(adev, true);
3936                 }
3937                 break;
3938         default:
3939                 break;
3940         }
3941
3942         return 0;
3943 }
3944
3945 static int gfx_v9_0_set_clockgating_state(void *handle,
3946                                           enum amd_clockgating_state state)
3947 {
3948         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3949
3950         if (amdgpu_sriov_vf(adev))
3951                 return 0;
3952
3953         switch (adev->asic_type) {
3954         case CHIP_VEGA10:
3955         case CHIP_VEGA12:
3956         case CHIP_VEGA20:
3957         case CHIP_RAVEN:
3958                 gfx_v9_0_update_gfx_clock_gating(adev,
3959                                                  state == AMD_CG_STATE_GATE ? true : false);
3960                 break;
3961         default:
3962                 break;
3963         }
3964         return 0;
3965 }
3966
3967 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
3968 {
3969         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3970         int data;
3971
3972         if (amdgpu_sriov_vf(adev))
3973                 *flags = 0;
3974
3975         /* AMD_CG_SUPPORT_GFX_MGCG */
3976         data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3977         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
3978                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
3979
3980         /* AMD_CG_SUPPORT_GFX_CGCG */
3981         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3982         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
3983                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
3984
3985         /* AMD_CG_SUPPORT_GFX_CGLS */
3986         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
3987                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
3988
3989         /* AMD_CG_SUPPORT_GFX_RLC_LS */
3990         data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3991         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
3992                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
3993
3994         /* AMD_CG_SUPPORT_GFX_CP_LS */
3995         data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3996         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
3997                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
3998
3999         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
4000         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4001         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
4002                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
4003
4004         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
4005         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
4006                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
4007 }
4008
4009 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
4010 {
4011         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
4012 }
4013
4014 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
4015 {
4016         struct amdgpu_device *adev = ring->adev;
4017         u64 wptr;
4018
4019         /* XXX check if swapping is necessary on BE */
4020         if (ring->use_doorbell) {
4021                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
4022         } else {
4023                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
4024                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
4025         }
4026
4027         return wptr;
4028 }
4029
4030 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
4031 {
4032         struct amdgpu_device *adev = ring->adev;
4033
4034         if (ring->use_doorbell) {
4035                 /* XXX check if swapping is necessary on BE */
4036                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4037                 WDOORBELL64(ring->doorbell_index, ring->wptr);
4038         } else {
4039                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
4040                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
4041         }
4042 }
4043
4044 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
4045 {
4046         struct amdgpu_device *adev = ring->adev;
4047         u32 ref_and_mask, reg_mem_engine;
4048         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
4049
4050         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
4051                 switch (ring->me) {
4052                 case 1:
4053                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
4054                         break;
4055                 case 2:
4056                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
4057                         break;
4058                 default:
4059                         return;
4060                 }
4061                 reg_mem_engine = 0;
4062         } else {
4063                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
4064                 reg_mem_engine = 1; /* pfp */
4065         }
4066
4067         gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
4068                               adev->nbio_funcs->get_hdp_flush_req_offset(adev),
4069                               adev->nbio_funcs->get_hdp_flush_done_offset(adev),
4070                               ref_and_mask, ref_and_mask, 0x20);
4071 }
4072
4073 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
4074                                       struct amdgpu_ib *ib,
4075                                       unsigned vmid, bool ctx_switch)
4076 {
4077         u32 header, control = 0;
4078
4079         if (ib->flags & AMDGPU_IB_FLAG_CE)
4080                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
4081         else
4082                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4083
4084         control |= ib->length_dw | (vmid << 24);
4085
4086         if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
4087                 control |= INDIRECT_BUFFER_PRE_ENB(1);
4088
4089                 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
4090                         gfx_v9_0_ring_emit_de_meta(ring);
4091         }
4092
4093         amdgpu_ring_write(ring, header);
4094         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4095         amdgpu_ring_write(ring,
4096 #ifdef __BIG_ENDIAN
4097                 (2 << 0) |
4098 #endif
4099                 lower_32_bits(ib->gpu_addr));
4100         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4101         amdgpu_ring_write(ring, control);
4102 }
4103
4104 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4105                                           struct amdgpu_ib *ib,
4106                                           unsigned vmid, bool ctx_switch)
4107 {
4108         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
4109
4110         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
4111         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4112         amdgpu_ring_write(ring,
4113 #ifdef __BIG_ENDIAN
4114                                 (2 << 0) |
4115 #endif
4116                                 lower_32_bits(ib->gpu_addr));
4117         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4118         amdgpu_ring_write(ring, control);
4119 }
4120
4121 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
4122                                      u64 seq, unsigned flags)
4123 {
4124         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4125         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4126         bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
4127
4128         /* RELEASE_MEM - flush caches, send int */
4129         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
4130         amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN |
4131                                                EOP_TC_NC_ACTION_EN) :
4132                                               (EOP_TCL1_ACTION_EN |
4133                                                EOP_TC_ACTION_EN |
4134                                                EOP_TC_WB_ACTION_EN |
4135                                                EOP_TC_MD_ACTION_EN)) |
4136                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4137                                  EVENT_INDEX(5)));
4138         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
4139
4140         /*
4141          * the address should be Qword aligned if 64bit write, Dword
4142          * aligned if only send 32bit data low (discard data high)
4143          */
4144         if (write64bit)
4145                 BUG_ON(addr & 0x7);
4146         else
4147                 BUG_ON(addr & 0x3);
4148         amdgpu_ring_write(ring, lower_32_bits(addr));
4149         amdgpu_ring_write(ring, upper_32_bits(addr));
4150         amdgpu_ring_write(ring, lower_32_bits(seq));
4151         amdgpu_ring_write(ring, upper_32_bits(seq));
4152         amdgpu_ring_write(ring, 0);
4153 }
4154
4155 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
4156 {
4157         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4158         uint32_t seq = ring->fence_drv.sync_seq;
4159         uint64_t addr = ring->fence_drv.gpu_addr;
4160
4161         gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
4162                               lower_32_bits(addr), upper_32_bits(addr),
4163                               seq, 0xffffffff, 4);
4164 }
4165
4166 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4167                                         unsigned vmid, uint64_t pd_addr)
4168 {
4169         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
4170
4171         /* compute doesn't have PFP */
4172         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
4173                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4174                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4175                 amdgpu_ring_write(ring, 0x0);
4176         }
4177 }
4178
4179 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4180 {
4181         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
4182 }
4183
4184 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4185 {
4186         u64 wptr;
4187
4188         /* XXX check if swapping is necessary on BE */
4189         if (ring->use_doorbell)
4190                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
4191         else
4192                 BUG();
4193         return wptr;
4194 }
4195
4196 static void gfx_v9_0_ring_set_pipe_percent(struct amdgpu_ring *ring,
4197                                            bool acquire)
4198 {
4199         struct amdgpu_device *adev = ring->adev;
4200         int pipe_num, tmp, reg;
4201         int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1;
4202
4203         pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe;
4204
4205         /* first me only has 2 entries, GFX and HP3D */
4206         if (ring->me > 0)
4207                 pipe_num -= 2;
4208
4209         reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX) + pipe_num;
4210         tmp = RREG32(reg);
4211         tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
4212         WREG32(reg, tmp);
4213 }
4214
4215 static void gfx_v9_0_pipe_reserve_resources(struct amdgpu_device *adev,
4216                                             struct amdgpu_ring *ring,
4217                                             bool acquire)
4218 {
4219         int i, pipe;
4220         bool reserve;
4221         struct amdgpu_ring *iring;
4222
4223         mutex_lock(&adev->gfx.pipe_reserve_mutex);
4224         pipe = amdgpu_gfx_queue_to_bit(adev, ring->me, ring->pipe, 0);
4225         if (acquire)
4226                 set_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4227         else
4228                 clear_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4229
4230         if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) {
4231                 /* Clear all reservations - everyone reacquires all resources */
4232                 for (i = 0; i < adev->gfx.num_gfx_rings; ++i)
4233                         gfx_v9_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i],
4234                                                        true);
4235
4236                 for (i = 0; i < adev->gfx.num_compute_rings; ++i)
4237                         gfx_v9_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i],
4238                                                        true);
4239         } else {
4240                 /* Lower all pipes without a current reservation */
4241                 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) {
4242                         iring = &adev->gfx.gfx_ring[i];
4243                         pipe = amdgpu_gfx_queue_to_bit(adev,
4244                                                        iring->me,
4245                                                        iring->pipe,
4246                                                        0);
4247                         reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4248                         gfx_v9_0_ring_set_pipe_percent(iring, reserve);
4249                 }
4250
4251                 for (i = 0; i < adev->gfx.num_compute_rings; ++i) {
4252                         iring = &adev->gfx.compute_ring[i];
4253                         pipe = amdgpu_gfx_queue_to_bit(adev,
4254                                                        iring->me,
4255                                                        iring->pipe,
4256                                                        0);
4257                         reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4258                         gfx_v9_0_ring_set_pipe_percent(iring, reserve);
4259                 }
4260         }
4261
4262         mutex_unlock(&adev->gfx.pipe_reserve_mutex);
4263 }
4264
4265 static void gfx_v9_0_hqd_set_priority(struct amdgpu_device *adev,
4266                                       struct amdgpu_ring *ring,
4267                                       bool acquire)
4268 {
4269         uint32_t pipe_priority = acquire ? 0x2 : 0x0;
4270         uint32_t queue_priority = acquire ? 0xf : 0x0;
4271
4272         mutex_lock(&adev->srbm_mutex);
4273         soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4274
4275         WREG32_SOC15(GC, 0, mmCP_HQD_PIPE_PRIORITY, pipe_priority);
4276         WREG32_SOC15(GC, 0, mmCP_HQD_QUEUE_PRIORITY, queue_priority);
4277
4278         soc15_grbm_select(adev, 0, 0, 0, 0);
4279         mutex_unlock(&adev->srbm_mutex);
4280 }
4281
4282 static void gfx_v9_0_ring_set_priority_compute(struct amdgpu_ring *ring,
4283                                                enum drm_sched_priority priority)
4284 {
4285         struct amdgpu_device *adev = ring->adev;
4286         bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW;
4287
4288         if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
4289                 return;
4290
4291         gfx_v9_0_hqd_set_priority(adev, ring, acquire);
4292         gfx_v9_0_pipe_reserve_resources(adev, ring, acquire);
4293 }
4294
4295 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4296 {
4297         struct amdgpu_device *adev = ring->adev;
4298
4299         /* XXX check if swapping is necessary on BE */
4300         if (ring->use_doorbell) {
4301                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4302                 WDOORBELL64(ring->doorbell_index, ring->wptr);
4303         } else{
4304                 BUG(); /* only DOORBELL method supported on gfx9 now */
4305         }
4306 }
4307
4308 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
4309                                          u64 seq, unsigned int flags)
4310 {
4311         struct amdgpu_device *adev = ring->adev;
4312
4313         /* we only allocate 32bit for each seq wb address */
4314         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
4315
4316         /* write fence seq to the "addr" */
4317         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4318         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4319                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
4320         amdgpu_ring_write(ring, lower_32_bits(addr));
4321         amdgpu_ring_write(ring, upper_32_bits(addr));
4322         amdgpu_ring_write(ring, lower_32_bits(seq));
4323
4324         if (flags & AMDGPU_FENCE_FLAG_INT) {
4325                 /* set register to trigger INT */
4326                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4327                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4328                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
4329                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
4330                 amdgpu_ring_write(ring, 0);
4331                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
4332         }
4333 }
4334
4335 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
4336 {
4337         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4338         amdgpu_ring_write(ring, 0);
4339 }
4340
4341 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
4342 {
4343         struct v9_ce_ib_state ce_payload = {0};
4344         uint64_t csa_addr;
4345         int cnt;
4346
4347         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
4348         csa_addr = amdgpu_csa_vaddr(ring->adev);
4349
4350         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4351         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
4352                                  WRITE_DATA_DST_SEL(8) |
4353                                  WR_CONFIRM) |
4354                                  WRITE_DATA_CACHE_POLICY(0));
4355         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
4356         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
4357         amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
4358 }
4359
4360 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
4361 {
4362         struct v9_de_ib_state de_payload = {0};
4363         uint64_t csa_addr, gds_addr;
4364         int cnt;
4365
4366         csa_addr = amdgpu_csa_vaddr(ring->adev);
4367         gds_addr = csa_addr + 4096;
4368         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
4369         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
4370
4371         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
4372         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4373         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
4374                                  WRITE_DATA_DST_SEL(8) |
4375                                  WR_CONFIRM) |
4376                                  WRITE_DATA_CACHE_POLICY(0));
4377         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
4378         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
4379         amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
4380 }
4381
4382 static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
4383 {
4384         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
4385         amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
4386 }
4387
4388 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
4389 {
4390         uint32_t dw2 = 0;
4391
4392         if (amdgpu_sriov_vf(ring->adev))
4393                 gfx_v9_0_ring_emit_ce_meta(ring);
4394
4395         gfx_v9_0_ring_emit_tmz(ring, true);
4396
4397         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
4398         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4399                 /* set load_global_config & load_global_uconfig */
4400                 dw2 |= 0x8001;
4401                 /* set load_cs_sh_regs */
4402                 dw2 |= 0x01000000;
4403                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
4404                 dw2 |= 0x10002;
4405
4406                 /* set load_ce_ram if preamble presented */
4407                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
4408                         dw2 |= 0x10000000;
4409         } else {
4410                 /* still load_ce_ram if this is the first time preamble presented
4411                  * although there is no context switch happens.
4412                  */
4413                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
4414                         dw2 |= 0x10000000;
4415         }
4416
4417         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4418         amdgpu_ring_write(ring, dw2);
4419         amdgpu_ring_write(ring, 0);
4420 }
4421
4422 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
4423 {
4424         unsigned ret;
4425         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4426         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
4427         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
4428         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
4429         ret = ring->wptr & ring->buf_mask;
4430         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
4431         return ret;
4432 }
4433
4434 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
4435 {
4436         unsigned cur;
4437         BUG_ON(offset > ring->buf_mask);
4438         BUG_ON(ring->ring[offset] != 0x55aa55aa);
4439
4440         cur = (ring->wptr & ring->buf_mask) - 1;
4441         if (likely(cur > offset))
4442                 ring->ring[offset] = cur - offset;
4443         else
4444                 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
4445 }
4446
4447 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
4448 {
4449         struct amdgpu_device *adev = ring->adev;
4450
4451         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4452         amdgpu_ring_write(ring, 0 |     /* src: register*/
4453                                 (5 << 8) |      /* dst: memory */
4454                                 (1 << 20));     /* write confirm */
4455         amdgpu_ring_write(ring, reg);
4456         amdgpu_ring_write(ring, 0);
4457         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4458                                 adev->virt.reg_val_offs * 4));
4459         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4460                                 adev->virt.reg_val_offs * 4));
4461 }
4462
4463 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
4464                                     uint32_t val)
4465 {
4466         uint32_t cmd = 0;
4467
4468         switch (ring->funcs->type) {
4469         case AMDGPU_RING_TYPE_GFX:
4470                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
4471                 break;
4472         case AMDGPU_RING_TYPE_KIQ:
4473                 cmd = (1 << 16); /* no inc addr */
4474                 break;
4475         default:
4476                 cmd = WR_CONFIRM;
4477                 break;
4478         }
4479         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4480         amdgpu_ring_write(ring, cmd);
4481         amdgpu_ring_write(ring, reg);
4482         amdgpu_ring_write(ring, 0);
4483         amdgpu_ring_write(ring, val);
4484 }
4485
4486 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4487                                         uint32_t val, uint32_t mask)
4488 {
4489         gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4490 }
4491
4492 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
4493                                                   uint32_t reg0, uint32_t reg1,
4494                                                   uint32_t ref, uint32_t mask)
4495 {
4496         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4497         struct amdgpu_device *adev = ring->adev;
4498         bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ?
4499                 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait;
4500
4501         if (fw_version_ok)
4502                 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
4503                                       ref, mask, 0x20);
4504         else
4505                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
4506                                                            ref, mask);
4507 }
4508
4509 static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
4510 {
4511         struct amdgpu_device *adev = ring->adev;
4512         uint32_t value = 0;
4513
4514         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
4515         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
4516         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
4517         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
4518         WREG32(mmSQ_CMD, value);
4519 }
4520
4521 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4522                                                  enum amdgpu_interrupt_state state)
4523 {
4524         switch (state) {
4525         case AMDGPU_IRQ_STATE_DISABLE:
4526         case AMDGPU_IRQ_STATE_ENABLE:
4527                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4528                                TIME_STAMP_INT_ENABLE,
4529                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4530                 break;
4531         default:
4532                 break;
4533         }
4534 }
4535
4536 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4537                                                      int me, int pipe,
4538                                                      enum amdgpu_interrupt_state state)
4539 {
4540         u32 mec_int_cntl, mec_int_cntl_reg;
4541
4542         /*
4543          * amdgpu controls only the first MEC. That's why this function only
4544          * handles the setting of interrupts for this specific MEC. All other
4545          * pipes' interrupts are set by amdkfd.
4546          */
4547
4548         if (me == 1) {
4549                 switch (pipe) {
4550                 case 0:
4551                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4552                         break;
4553                 case 1:
4554                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
4555                         break;
4556                 case 2:
4557                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
4558                         break;
4559                 case 3:
4560                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
4561                         break;
4562                 default:
4563                         DRM_DEBUG("invalid pipe %d\n", pipe);
4564                         return;
4565                 }
4566         } else {
4567                 DRM_DEBUG("invalid me %d\n", me);
4568                 return;
4569         }
4570
4571         switch (state) {
4572         case AMDGPU_IRQ_STATE_DISABLE:
4573                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4574                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4575                                              TIME_STAMP_INT_ENABLE, 0);
4576                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4577                 break;
4578         case AMDGPU_IRQ_STATE_ENABLE:
4579                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4580                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4581                                              TIME_STAMP_INT_ENABLE, 1);
4582                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4583                 break;
4584         default:
4585                 break;
4586         }
4587 }
4588
4589 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4590                                              struct amdgpu_irq_src *source,
4591                                              unsigned type,
4592                                              enum amdgpu_interrupt_state state)
4593 {
4594         switch (state) {
4595         case AMDGPU_IRQ_STATE_DISABLE:
4596         case AMDGPU_IRQ_STATE_ENABLE:
4597                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4598                                PRIV_REG_INT_ENABLE,
4599                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4600                 break;
4601         default:
4602                 break;
4603         }
4604
4605         return 0;
4606 }
4607
4608 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4609                                               struct amdgpu_irq_src *source,
4610                                               unsigned type,
4611                                               enum amdgpu_interrupt_state state)
4612 {
4613         switch (state) {
4614         case AMDGPU_IRQ_STATE_DISABLE:
4615         case AMDGPU_IRQ_STATE_ENABLE:
4616                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4617                                PRIV_INSTR_INT_ENABLE,
4618                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4619         default:
4620                 break;
4621         }
4622
4623         return 0;
4624 }
4625
4626 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4627                                             struct amdgpu_irq_src *src,
4628                                             unsigned type,
4629                                             enum amdgpu_interrupt_state state)
4630 {
4631         switch (type) {
4632         case AMDGPU_CP_IRQ_GFX_EOP:
4633                 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
4634                 break;
4635         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4636                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4637                 break;
4638         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4639                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4640                 break;
4641         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4642                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4643                 break;
4644         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4645                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4646                 break;
4647         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4648                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4649                 break;
4650         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4651                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4652                 break;
4653         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4654                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4655                 break;
4656         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4657                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4658                 break;
4659         default:
4660                 break;
4661         }
4662         return 0;
4663 }
4664
4665 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
4666                             struct amdgpu_irq_src *source,
4667                             struct amdgpu_iv_entry *entry)
4668 {
4669         int i;
4670         u8 me_id, pipe_id, queue_id;
4671         struct amdgpu_ring *ring;
4672
4673         DRM_DEBUG("IH: CP EOP\n");
4674         me_id = (entry->ring_id & 0x0c) >> 2;
4675         pipe_id = (entry->ring_id & 0x03) >> 0;
4676         queue_id = (entry->ring_id & 0x70) >> 4;
4677
4678         switch (me_id) {
4679         case 0:
4680                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4681                 break;
4682         case 1:
4683         case 2:
4684                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4685                         ring = &adev->gfx.compute_ring[i];
4686                         /* Per-queue interrupt is supported for MEC starting from VI.
4687                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
4688                           */
4689                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4690                                 amdgpu_fence_process(ring);
4691                 }
4692                 break;
4693         }
4694         return 0;
4695 }
4696
4697 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
4698                                  struct amdgpu_irq_src *source,
4699                                  struct amdgpu_iv_entry *entry)
4700 {
4701         DRM_ERROR("Illegal register access in command stream\n");
4702         schedule_work(&adev->reset_work);
4703         return 0;
4704 }
4705
4706 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
4707                                   struct amdgpu_irq_src *source,
4708                                   struct amdgpu_iv_entry *entry)
4709 {
4710         DRM_ERROR("Illegal instruction in command stream\n");
4711         schedule_work(&adev->reset_work);
4712         return 0;
4713 }
4714
4715 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
4716         .name = "gfx_v9_0",
4717         .early_init = gfx_v9_0_early_init,
4718         .late_init = gfx_v9_0_late_init,
4719         .sw_init = gfx_v9_0_sw_init,
4720         .sw_fini = gfx_v9_0_sw_fini,
4721         .hw_init = gfx_v9_0_hw_init,
4722         .hw_fini = gfx_v9_0_hw_fini,
4723         .suspend = gfx_v9_0_suspend,
4724         .resume = gfx_v9_0_resume,
4725         .is_idle = gfx_v9_0_is_idle,
4726         .wait_for_idle = gfx_v9_0_wait_for_idle,
4727         .soft_reset = gfx_v9_0_soft_reset,
4728         .set_clockgating_state = gfx_v9_0_set_clockgating_state,
4729         .set_powergating_state = gfx_v9_0_set_powergating_state,
4730         .get_clockgating_state = gfx_v9_0_get_clockgating_state,
4731 };
4732
4733 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
4734         .type = AMDGPU_RING_TYPE_GFX,
4735         .align_mask = 0xff,
4736         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4737         .support_64bit_ptrs = true,
4738         .vmhub = AMDGPU_GFXHUB,
4739         .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
4740         .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
4741         .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
4742         .emit_frame_size = /* totally 242 maximum if 16 IBs */
4743                 5 +  /* COND_EXEC */
4744                 7 +  /* PIPELINE_SYNC */
4745                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4746                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4747                 2 + /* VM_FLUSH */
4748                 8 +  /* FENCE for VM_FLUSH */
4749                 20 + /* GDS switch */
4750                 4 + /* double SWITCH_BUFFER,
4751                        the first COND_EXEC jump to the place just
4752                            prior to this double SWITCH_BUFFER  */
4753                 5 + /* COND_EXEC */
4754                 7 +      /*     HDP_flush */
4755                 4 +      /*     VGT_flush */
4756                 14 + /* CE_META */
4757                 31 + /* DE_META */
4758                 3 + /* CNTX_CTRL */
4759                 5 + /* HDP_INVL */
4760                 8 + 8 + /* FENCE x2 */
4761                 2, /* SWITCH_BUFFER */
4762         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
4763         .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
4764         .emit_fence = gfx_v9_0_ring_emit_fence,
4765         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4766         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4767         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4768         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4769         .test_ring = gfx_v9_0_ring_test_ring,
4770         .test_ib = gfx_v9_0_ring_test_ib,
4771         .insert_nop = amdgpu_ring_insert_nop,
4772         .pad_ib = amdgpu_ring_generic_pad_ib,
4773         .emit_switch_buffer = gfx_v9_ring_emit_sb,
4774         .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
4775         .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
4776         .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
4777         .emit_tmz = gfx_v9_0_ring_emit_tmz,
4778         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4779         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4780         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4781         .soft_recovery = gfx_v9_0_ring_soft_recovery,
4782 };
4783
4784 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
4785         .type = AMDGPU_RING_TYPE_COMPUTE,
4786         .align_mask = 0xff,
4787         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4788         .support_64bit_ptrs = true,
4789         .vmhub = AMDGPU_GFXHUB,
4790         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4791         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4792         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4793         .emit_frame_size =
4794                 20 + /* gfx_v9_0_ring_emit_gds_switch */
4795                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4796                 5 + /* hdp invalidate */
4797                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4798                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4799                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4800                 2 + /* gfx_v9_0_ring_emit_vm_flush */
4801                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4802         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4803         .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4804         .emit_fence = gfx_v9_0_ring_emit_fence,
4805         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4806         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4807         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4808         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4809         .test_ring = gfx_v9_0_ring_test_ring,
4810         .test_ib = gfx_v9_0_ring_test_ib,
4811         .insert_nop = amdgpu_ring_insert_nop,
4812         .pad_ib = amdgpu_ring_generic_pad_ib,
4813         .set_priority = gfx_v9_0_ring_set_priority_compute,
4814         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4815         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4816         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4817 };
4818
4819 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
4820         .type = AMDGPU_RING_TYPE_KIQ,
4821         .align_mask = 0xff,
4822         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4823         .support_64bit_ptrs = true,
4824         .vmhub = AMDGPU_GFXHUB,
4825         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4826         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4827         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4828         .emit_frame_size =
4829                 20 + /* gfx_v9_0_ring_emit_gds_switch */
4830                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4831                 5 + /* hdp invalidate */
4832                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4833                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4834                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4835                 2 + /* gfx_v9_0_ring_emit_vm_flush */
4836                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4837         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4838         .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4839         .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
4840         .test_ring = gfx_v9_0_ring_test_ring,
4841         .test_ib = gfx_v9_0_ring_test_ib,
4842         .insert_nop = amdgpu_ring_insert_nop,
4843         .pad_ib = amdgpu_ring_generic_pad_ib,
4844         .emit_rreg = gfx_v9_0_ring_emit_rreg,
4845         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4846         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4847         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4848 };
4849
4850 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
4851 {
4852         int i;
4853
4854         adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
4855
4856         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4857                 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
4858
4859         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4860                 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
4861 }
4862
4863 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
4864         .set = gfx_v9_0_set_eop_interrupt_state,
4865         .process = gfx_v9_0_eop_irq,
4866 };
4867
4868 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
4869         .set = gfx_v9_0_set_priv_reg_fault_state,
4870         .process = gfx_v9_0_priv_reg_irq,
4871 };
4872
4873 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
4874         .set = gfx_v9_0_set_priv_inst_fault_state,
4875         .process = gfx_v9_0_priv_inst_irq,
4876 };
4877
4878 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
4879 {
4880         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4881         adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
4882
4883         adev->gfx.priv_reg_irq.num_types = 1;
4884         adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
4885
4886         adev->gfx.priv_inst_irq.num_types = 1;
4887         adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
4888 }
4889
4890 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4891 {
4892         switch (adev->asic_type) {
4893         case CHIP_VEGA10:
4894         case CHIP_VEGA12:
4895         case CHIP_VEGA20:
4896         case CHIP_RAVEN:
4897                 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
4898                 break;
4899         default:
4900                 break;
4901         }
4902 }
4903
4904 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4905 {
4906         /* init asci gds info */
4907         adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
4908         adev->gds.gws.total_size = 64;
4909         adev->gds.oa.total_size = 16;
4910
4911         if (adev->gds.mem.total_size == 64 * 1024) {
4912                 adev->gds.mem.gfx_partition_size = 4096;
4913                 adev->gds.mem.cs_partition_size = 4096;
4914
4915                 adev->gds.gws.gfx_partition_size = 4;
4916                 adev->gds.gws.cs_partition_size = 4;
4917
4918                 adev->gds.oa.gfx_partition_size = 4;
4919                 adev->gds.oa.cs_partition_size = 1;
4920         } else {
4921                 adev->gds.mem.gfx_partition_size = 1024;
4922                 adev->gds.mem.cs_partition_size = 1024;
4923
4924                 adev->gds.gws.gfx_partition_size = 16;
4925                 adev->gds.gws.cs_partition_size = 16;
4926
4927                 adev->gds.oa.gfx_partition_size = 4;
4928                 adev->gds.oa.cs_partition_size = 4;
4929         }
4930 }
4931
4932 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4933                                                  u32 bitmap)
4934 {
4935         u32 data;
4936
4937         if (!bitmap)
4938                 return;
4939
4940         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4941         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4942
4943         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
4944 }
4945
4946 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4947 {
4948         u32 data, mask;
4949
4950         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
4951         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
4952
4953         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4954         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4955
4956         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
4957
4958         return (~data) & mask;
4959 }
4960
4961 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4962                                  struct amdgpu_cu_info *cu_info)
4963 {
4964         int i, j, k, counter, active_cu_number = 0;
4965         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4966         unsigned disable_masks[4 * 2];
4967
4968         if (!adev || !cu_info)
4969                 return -EINVAL;
4970
4971         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
4972
4973         mutex_lock(&adev->grbm_idx_mutex);
4974         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4975                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4976                         mask = 1;
4977                         ao_bitmap = 0;
4978                         counter = 0;
4979                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
4980                         if (i < 4 && j < 2)
4981                                 gfx_v9_0_set_user_cu_inactive_bitmap(
4982                                         adev, disable_masks[i * 2 + j]);
4983                         bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
4984                         cu_info->bitmap[i][j] = bitmap;
4985
4986                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4987                                 if (bitmap & mask) {
4988                                         if (counter < adev->gfx.config.max_cu_per_sh)
4989                                                 ao_bitmap |= mask;
4990                                         counter ++;
4991                                 }
4992                                 mask <<= 1;
4993                         }
4994                         active_cu_number += counter;
4995                         if (i < 2 && j < 2)
4996                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4997                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
4998                 }
4999         }
5000         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5001         mutex_unlock(&adev->grbm_idx_mutex);
5002
5003         cu_info->number = active_cu_number;
5004         cu_info->ao_cu_mask = ao_cu_mask;
5005         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
5006
5007         return 0;
5008 }
5009
5010 const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
5011 {
5012         .type = AMD_IP_BLOCK_TYPE_GFX,
5013         .major = 9,
5014         .minor = 0,
5015         .rev = 0,
5016         .funcs = &gfx_v9_0_ip_funcs,
5017 };