drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "gmc_v6_0.h"
  27 #include "amdgpu_ucode.h"
  28
  29 #include "bif/bif_3_0_d.h"
  30 #include "bif/bif_3_0_sh_mask.h"
  31 #include "oss/oss_1_0_d.h"
  32 #include "oss/oss_1_0_sh_mask.h"
  33 #include "gmc/gmc_6_0_d.h"
  34 #include "gmc/gmc_6_0_sh_mask.h"
  35 #include "dce/dce_6_0_d.h"
  36 #include "dce/dce_6_0_sh_mask.h"
  37 #include "si_enums.h"
  38
  39 static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev);
  40 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  41 static int gmc_v6_0_wait_for_idle(void *handle);
  42
  43 MODULE_FIRMWARE("radeon/tahiti_mc.bin");
  44 MODULE_FIRMWARE("radeon/pitcairn_mc.bin");
  45 MODULE_FIRMWARE("radeon/verde_mc.bin");
  46 MODULE_FIRMWARE("radeon/oland_mc.bin");
  47
  48 #define MC_SEQ_MISC0__MT__MASK   0xf0000000
  49 #define MC_SEQ_MISC0__MT__GDDR1  0x10000000
  50 #define MC_SEQ_MISC0__MT__DDR2   0x20000000
  51 #define MC_SEQ_MISC0__MT__GDDR3  0x30000000
  52 #define MC_SEQ_MISC0__MT__GDDR4  0x40000000
  53 #define MC_SEQ_MISC0__MT__GDDR5  0x50000000
  54 #define MC_SEQ_MISC0__MT__HBM    0x60000000
  55 #define MC_SEQ_MISC0__MT__DDR3   0xB0000000
  56
  57
  58 static const u32 crtc_offsets[6] =
  59 {
  60         SI_CRTC0_REGISTER_OFFSET,
  61         SI_CRTC1_REGISTER_OFFSET,
  62         SI_CRTC2_REGISTER_OFFSET,
  63         SI_CRTC3_REGISTER_OFFSET,
  64         SI_CRTC4_REGISTER_OFFSET,
  65         SI_CRTC5_REGISTER_OFFSET
  66 };
  67
  68 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev,
  69                              struct amdgpu_mode_mc_save *save)
  70 {
  71         u32 blackout;
  72
  73         if (adev->mode_info.num_crtc)
  74                 amdgpu_display_stop_mc_access(adev, save);
  75
  76         gmc_v6_0_wait_for_idle((void *)adev);
  77
  78         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  79         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
  80                 /* Block CPU access */
  81                 WREG32(mmBIF_FB_EN, 0);
  82                 /* blackout the MC */
  83                 blackout = REG_SET_FIELD(blackout,
  84                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
  85                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
  86         }
  87         /* wait for the MC to settle */
  88         udelay(100);
  89
  90 }
  91
  92 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev,
  93                                struct amdgpu_mode_mc_save *save)
  94 {
  95         u32 tmp;
  96
  97         /* unblackout the MC */
  98         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  99         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 100         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 101         /* allow CPU access */
 102         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 103         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 104         WREG32(mmBIF_FB_EN, tmp);
 105
 106         if (adev->mode_info.num_crtc)
 107                 amdgpu_display_resume_mc_access(adev, save);
 108
 109 }
 110
 111 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
 112 {
 113         const char *chip_name;
 114         char fw_name[30];
 115         int err;
 116
 117         DRM_DEBUG("\n");
 118
 119         switch (adev->asic_type) {
 120         case CHIP_TAHITI:
 121                 chip_name = "tahiti";
 122                 break;
 123         case CHIP_PITCAIRN:
 124                 chip_name = "pitcairn";
 125                 break;
 126         case CHIP_VERDE:
 127                 chip_name = "verde";
 128                 break;
 129         case CHIP_OLAND:
 130                 chip_name = "oland";
 131                 break;
 132         case CHIP_HAINAN:
 133                 chip_name = "hainan";
 134                 break;
 135         default: BUG();
 136         }
 137
 138         snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 139         err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
 140         if (err)
 141                 goto out;
 142
 143         err = amdgpu_ucode_validate(adev->mc.fw);
 144
 145 out:
 146         if (err) {
 147                 dev_err(adev->dev,
 148                        "si_mc: Failed to load firmware \"%s\"\n",
 149                        fw_name);
 150                 release_firmware(adev->mc.fw);
 151                 adev->mc.fw = NULL;
 152         }
 153         return err;
 154 }
 155
 156 static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
 157 {
 158         const __le32 *new_fw_data = NULL;
 159         u32 running;
 160         const __le32 *new_io_mc_regs = NULL;
 161         int i, regs_size, ucode_size;
 162         const struct mc_firmware_header_v1_0 *hdr;
 163
 164         if (!adev->mc.fw)
 165                 return -EINVAL;
 166
 167         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 168
 169         amdgpu_ucode_print_mc_hdr(&hdr->header);
 170
 171         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 172         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 173         new_io_mc_regs = (const __le32 *)
 174                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 175         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 176         new_fw_data = (const __le32 *)
 177                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 178
 179         running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
 180
 181         if (running == 0) {
 182
 183                 /* reset the engine and set to writable */
 184                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 185                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 186
 187                 /* load mc io regs */
 188                 for (i = 0; i < regs_size; i++) {
 189                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
 190                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
 191                 }
 192                 /* load the MC ucode */
 193                 for (i = 0; i < ucode_size; i++) {
 194                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
 195                 }
 196
 197                 /* put the engine back into the active state */
 198                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 199                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 200                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 201
 202                 /* wait for training to complete */
 203                 for (i = 0; i < adev->usec_timeout; i++) {
 204                         if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
 205                                 break;
 206                         udelay(1);
 207                 }
 208                 for (i = 0; i < adev->usec_timeout; i++) {
 209                         if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
 210                                 break;
 211                         udelay(1);
 212                 }
 213
 214         }
 215
 216         return 0;
 217 }
 218
 219 static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
 220                                        struct amdgpu_mc *mc)
 221 {
 222         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 223                 dev_warn(adev->dev, "limiting VRAM\n");
 224                 mc->real_vram_size = 0xFFC0000000ULL;
 225                 mc->mc_vram_size = 0xFFC0000000ULL;
 226         }
 227         amdgpu_vram_location(adev, &adev->mc, 0);
 228         adev->mc.gtt_base_align = 0;
 229         amdgpu_gtt_location(adev, mc);
 230 }
 231
 232 static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
 233 {
 234         struct amdgpu_mode_mc_save save;
 235         u32 tmp;
 236         int i, j;
 237
 238         /* Initialize HDP */
 239         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 240                 WREG32((0xb05 + j), 0x00000000);
 241                 WREG32((0xb06 + j), 0x00000000);
 242                 WREG32((0xb07 + j), 0x00000000);
 243                 WREG32((0xb08 + j), 0x00000000);
 244                 WREG32((0xb09 + j), 0x00000000);
 245         }
 246         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 247
 248         gmc_v6_0_mc_stop(adev, &save);
 249
 250         if (gmc_v6_0_wait_for_idle((void *)adev)) {
 251                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 252         }
 253
 254         WREG32(mmVGA_HDP_CONTROL, VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK);
 255         /* Update configuration */
 256         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 257                adev->mc.vram_start >> 12);
 258         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 259                adev->mc.vram_end >> 12);
 260         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 261                adev->vram_scratch.gpu_addr >> 12);
 262         tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
 263         tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
 264         WREG32(mmMC_VM_FB_LOCATION, tmp);
 265         /* XXX double check these! */
 266         WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
 267         WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 268         WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 269         WREG32(mmMC_VM_AGP_BASE, 0);
 270         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 271         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 272
 273         if (gmc_v6_0_wait_for_idle((void *)adev)) {
 274                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 275         }
 276         gmc_v6_0_mc_resume(adev, &save);
 277         amdgpu_display_set_vga_render_state(adev, false);
 278 }
 279
 280 static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
 281 {
 282
 283         u32 tmp;
 284         int chansize, numchan;
 285
 286         tmp = RREG32(mmMC_ARB_RAMCFG);
 287         if (tmp & (1 << 11)) {
 288                 chansize = 16;
 289         } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) {
 290                 chansize = 64;
 291         } else {
 292                 chansize = 32;
 293         }
 294         tmp = RREG32(mmMC_SHARED_CHMAP);
 295         switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
 296         case 0:
 297         default:
 298                 numchan = 1;
 299                 break;
 300         case 1:
 301                 numchan = 2;
 302                 break;
 303         case 2:
 304                 numchan = 4;
 305                 break;
 306         case 3:
 307                 numchan = 8;
 308                 break;
 309         case 4:
 310                 numchan = 3;
 311                 break;
 312         case 5:
 313                 numchan = 6;
 314                 break;
 315         case 6:
 316                 numchan = 10;
 317                 break;
 318         case 7:
 319                 numchan = 12;
 320                 break;
 321         case 8:
 322                 numchan = 16;
 323                 break;
 324         }
 325         adev->mc.vram_width = numchan * chansize;
 326         /* Could aper size report 0 ? */
 327         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 328         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 329         /* size in MB on si */
 330         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 331         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 332         adev->mc.visible_vram_size = adev->mc.aper_size;
 333
 334         /* unless the user had overridden it, set the gart
 335          * size equal to the 1024 or vram, whichever is larger.
 336          */
 337         if (amdgpu_gart_size == -1)
 338                 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
 339         else
 340                 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
 341
 342         gmc_v6_0_vram_gtt_location(adev, &adev->mc);
 343
 344         return 0;
 345 }
 346
 347 static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 348                                         uint32_t vmid)
 349 {
 350         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 351
 352         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 353 }
 354
 355 static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev,
 356                                      void *cpu_pt_addr,
 357                                      uint32_t gpu_page_idx,
 358                                      uint64_t addr,
 359                                      uint32_t flags)
 360 {
 361         void __iomem *ptr = (void *)cpu_pt_addr;
 362         uint64_t value;
 363
 364         value = addr & 0xFFFFFFFFFFFFF000ULL;
 365         value |= flags;
 366         writeq(value, ptr + (gpu_page_idx * 8));
 367
 368         return 0;
 369 }
 370
 371 static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
 372                                               bool value)
 373 {
 374         u32 tmp;
 375
 376         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 377         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 378                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 379         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 380                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 381         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 382                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 383         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 384                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 385         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 386                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 387         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 388                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 389         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 390 }
 391
 392 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 393 {
 394         int r, i;
 395
 396         if (adev->gart.robj == NULL) {
 397                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 398                 return -EINVAL;
 399         }
 400         r = amdgpu_gart_table_vram_pin(adev);
 401         if (r)
 402                 return r;
 403         /* Setup TLB control */
 404         WREG32(mmMC_VM_MX_L1_TLB_CNTL,
 405                (0xA << 7) |
 406                MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK |
 407                MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK |
 408                MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
 409                MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK |
 410                (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
 411         /* Setup L2 cache */
 412         WREG32(mmVM_L2_CNTL,
 413                VM_L2_CNTL__ENABLE_L2_CACHE_MASK |
 414                VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK |
 415                VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 416                VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 417                (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
 418                (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
 419         WREG32(mmVM_L2_CNTL2,
 420                VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
 421                VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
 422         WREG32(mmVM_L2_CNTL3,
 423                VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
 424                (4UL << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
 425                (4UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
 426         /* setup context0 */
 427         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
 428         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
 429         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 430         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 431                         (u32)(adev->dummy_page.addr >> 12));
 432         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 433         WREG32(mmVM_CONTEXT0_CNTL,
 434                VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
 435                (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
 436                VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
 437
 438         WREG32(0x575, 0);
 439         WREG32(0x576, 0);
 440         WREG32(0x577, 0);
 441
 442         /* empty context1-15 */
 443         /* set vm size, must be a multiple of 4 */
 444         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 445         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 446         /* Assign the pt base to something valid for now; the pts used for
 447          * the VMs are determined by the application and setup and assigned
 448          * on the fly in the vm part of radeon_gart.c
 449          */
 450         for (i = 1; i < 16; i++) {
 451                 if (i < 8)
 452                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 453                                adev->gart.table_addr >> 12);
 454                 else
 455                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 456                                adev->gart.table_addr >> 12);
 457         }
 458
 459         /* enable context1-15 */
 460         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 461                (u32)(adev->dummy_page.addr >> 12));
 462         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 463         WREG32(mmVM_CONTEXT1_CNTL,
 464                VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
 465                (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
 466                ((amdgpu_vm_block_size - 9) << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT) |
 467                VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 468                VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
 469                VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 470                VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
 471                VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 472                VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
 473                VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 474                VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
 475                VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 476                VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
 477                VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 478                VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
 479
 480         gmc_v6_0_gart_flush_gpu_tlb(adev, 0);
 481         dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
 482                  (unsigned)(adev->mc.gtt_size >> 20),
 483                  (unsigned long long)adev->gart.table_addr);
 484         adev->gart.ready = true;
 485         return 0;
 486 }
 487
 488 static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
 489 {
 490         int r;
 491
 492         if (adev->gart.robj) {
 493                 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
 494                 return 0;
 495         }
 496         r = amdgpu_gart_init(adev);
 497         if (r)
 498                 return r;
 499         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 500         return amdgpu_gart_table_vram_alloc(adev);
 501 }
 502
 503 static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
 504 {
 505         /*unsigned i;
 506
 507         for (i = 1; i < 16; ++i) {
 508                 uint32_t reg;
 509                 if (i < 8)
 510                         reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ;
 511                 else
 512                         reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8);
 513                 adev->vm_manager.saved_table_addr[i] = RREG32(reg);
 514         }*/
 515
 516         /* Disable all tables */
 517         WREG32(mmVM_CONTEXT0_CNTL, 0);
 518         WREG32(mmVM_CONTEXT1_CNTL, 0);
 519         /* Setup TLB control */
 520         WREG32(mmMC_VM_MX_L1_TLB_CNTL,
 521                MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
 522                (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
 523         /* Setup L2 cache */
 524         WREG32(mmVM_L2_CNTL,
 525                VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 526                VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 527                (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
 528                (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
 529         WREG32(mmVM_L2_CNTL2, 0);
 530         WREG32(mmVM_L2_CNTL3,
 531                VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
 532                (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
 533         amdgpu_gart_table_vram_unpin(adev);
 534 }
 535
 536 static void gmc_v6_0_gart_fini(struct amdgpu_device *adev)
 537 {
 538         amdgpu_gart_table_vram_free(adev);
 539         amdgpu_gart_fini(adev);
 540 }
 541
 542 static int gmc_v6_0_vm_init(struct amdgpu_device *adev)
 543 {
 544         /*
 545          * number of VMs
 546          * VMID 0 is reserved for System
 547          * amdgpu graphics/compute will use VMIDs 1-7
 548          * amdkfd will use VMIDs 8-15
 549          */
 550         adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
 551         amdgpu_vm_manager_init(adev);
 552
 553         /* base offset of vram pages */
 554         if (adev->flags & AMD_IS_APU) {
 555                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
 556                 tmp <<= 22;
 557                 adev->vm_manager.vram_base_offset = tmp;
 558         } else
 559                 adev->vm_manager.vram_base_offset = 0;
 560
 561         return 0;
 562 }
 563
 564 static void gmc_v6_0_vm_fini(struct amdgpu_device *adev)
 565 {
 566 }
 567
 568 static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
 569                                      u32 status, u32 addr, u32 mc_client)
 570 {
 571         u32 mc_id;
 572         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 573         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 574                                         PROTECTIONS);
 575         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 576                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 577
 578         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 579                               MEMORY_CLIENT_ID);
 580
 581         dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 582                protections, vmid, addr,
 583                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 584                              MEMORY_CLIENT_RW) ?
 585                "write" : "read", block, mc_client, mc_id);
 586 }
 587
 588 /*
 589 static const u32 mc_cg_registers[] = {
 590         MC_HUB_MISC_HUB_CG,
 591         MC_HUB_MISC_SIP_CG,
 592         MC_HUB_MISC_VM_CG,
 593         MC_XPB_CLK_GAT,
 594         ATC_MISC_CG,
 595         MC_CITF_MISC_WR_CG,
 596         MC_CITF_MISC_RD_CG,
 597         MC_CITF_MISC_VM_CG,
 598         VM_L2_CG,
 599 };
 600
 601 static const u32 mc_cg_ls_en[] = {
 602         MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
 603         MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
 604         MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 605         MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
 606         ATC_MISC_CG__MEM_LS_ENABLE_MASK,
 607         MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
 608         MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
 609         MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 610         VM_L2_CG__MEM_LS_ENABLE_MASK,
 611 };
 612
 613 static const u32 mc_cg_en[] = {
 614         MC_HUB_MISC_HUB_CG__ENABLE_MASK,
 615         MC_HUB_MISC_SIP_CG__ENABLE_MASK,
 616         MC_HUB_MISC_VM_CG__ENABLE_MASK,
 617         MC_XPB_CLK_GAT__ENABLE_MASK,
 618         ATC_MISC_CG__ENABLE_MASK,
 619         MC_CITF_MISC_WR_CG__ENABLE_MASK,
 620         MC_CITF_MISC_RD_CG__ENABLE_MASK,
 621         MC_CITF_MISC_VM_CG__ENABLE_MASK,
 622         VM_L2_CG__ENABLE_MASK,
 623 };
 624
 625 static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev,
 626                                   bool enable)
 627 {
 628         int i;
 629         u32 orig, data;
 630
 631         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 632                 orig = data = RREG32(mc_cg_registers[i]);
 633                 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
 634                         data |= mc_cg_ls_en[i];
 635                 else
 636                         data &= ~mc_cg_ls_en[i];
 637                 if (data != orig)
 638                         WREG32(mc_cg_registers[i], data);
 639         }
 640 }
 641
 642 static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev,
 643                                     bool enable)
 644 {
 645         int i;
 646         u32 orig, data;
 647
 648         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 649                 orig = data = RREG32(mc_cg_registers[i]);
 650                 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
 651                         data |= mc_cg_en[i];
 652                 else
 653                         data &= ~mc_cg_en[i];
 654                 if (data != orig)
 655                         WREG32(mc_cg_registers[i], data);
 656         }
 657 }
 658
 659 static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev,
 660                                      bool enable)
 661 {
 662         u32 orig, data;
 663
 664         orig = data = RREG32_PCIE(ixPCIE_CNTL2);
 665
 666         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
 667                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
 668                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
 669                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
 670                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
 671         } else {
 672                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
 673                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
 674                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
 675                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
 676         }
 677
 678         if (orig != data)
 679                 WREG32_PCIE(ixPCIE_CNTL2, data);
 680 }
 681
 682 static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
 683                                      bool enable)
 684 {
 685         u32 orig, data;
 686
 687         orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
 688
 689         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
 690                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
 691         else
 692                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
 693
 694         if (orig != data)
 695                 WREG32(mmHDP_HOST_PATH_CNTL, data);
 696 }
 697
 698 static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
 699                                    bool enable)
 700 {
 701         u32 orig, data;
 702
 703         orig = data = RREG32(mmHDP_MEM_POWER_LS);
 704
 705         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
 706                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
 707         else
 708                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
 709
 710         if (orig != data)
 711                 WREG32(mmHDP_MEM_POWER_LS, data);
 712 }
 713 */
 714
 715 static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type)
 716 {
 717         switch (mc_seq_vram_type) {
 718         case MC_SEQ_MISC0__MT__GDDR1:
 719                 return AMDGPU_VRAM_TYPE_GDDR1;
 720         case MC_SEQ_MISC0__MT__DDR2:
 721                 return AMDGPU_VRAM_TYPE_DDR2;
 722         case MC_SEQ_MISC0__MT__GDDR3:
 723                 return AMDGPU_VRAM_TYPE_GDDR3;
 724         case MC_SEQ_MISC0__MT__GDDR4:
 725                 return AMDGPU_VRAM_TYPE_GDDR4;
 726         case MC_SEQ_MISC0__MT__GDDR5:
 727                 return AMDGPU_VRAM_TYPE_GDDR5;
 728         case MC_SEQ_MISC0__MT__DDR3:
 729                 return AMDGPU_VRAM_TYPE_DDR3;
 730         default:
 731                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 732         }
 733 }
 734
 735 static int gmc_v6_0_early_init(void *handle)
 736 {
 737         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 738
 739         gmc_v6_0_set_gart_funcs(adev);
 740         gmc_v6_0_set_irq_funcs(adev);
 741
 742         if (adev->flags & AMD_IS_APU) {
 743                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 744         } else {
 745                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 746                 tmp &= MC_SEQ_MISC0__MT__MASK;
 747                 adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp);
 748         }
 749
 750         return 0;
 751 }
 752
 753 static int gmc_v6_0_late_init(void *handle)
 754 {
 755         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 756
 757         return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 758 }
 759
 760 static int gmc_v6_0_sw_init(void *handle)
 761 {
 762         int r;
 763         int dma_bits;
 764         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 765
 766         r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
 767         if (r)
 768                 return r;
 769
 770         r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
 771         if (r)
 772                 return r;
 773
 774         adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
 775
 776         adev->mc.mc_mask = 0xffffffffffULL;
 777
 778         adev->need_dma32 = false;
 779         dma_bits = adev->need_dma32 ? 32 : 40;
 780         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 781         if (r) {
 782                 adev->need_dma32 = true;
 783                 dma_bits = 32;
 784                 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
 785         }
 786         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 787         if (r) {
 788                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 789                 dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
 790         }
 791
 792         r = gmc_v6_0_init_microcode(adev);
 793         if (r) {
 794                 dev_err(adev->dev, "Failed to load mc firmware!\n");
 795                 return r;
 796         }
 797
 798         r = gmc_v6_0_mc_init(adev);
 799         if (r)
 800                 return r;
 801
 802         r = amdgpu_bo_init(adev);
 803         if (r)
 804                 return r;
 805
 806         r = gmc_v6_0_gart_init(adev);
 807         if (r)
 808                 return r;
 809
 810         if (!adev->vm_manager.enabled) {
 811                 r = gmc_v6_0_vm_init(adev);
 812                 if (r) {
 813                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
 814                         return r;
 815                 }
 816                 adev->vm_manager.enabled = true;
 817         }
 818
 819         return r;
 820 }
 821
 822 static int gmc_v6_0_sw_fini(void *handle)
 823 {
 824         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 825
 826         if (adev->vm_manager.enabled) {
 827                 gmc_v6_0_vm_fini(adev);
 828                 adev->vm_manager.enabled = false;
 829         }
 830         gmc_v6_0_gart_fini(adev);
 831         amdgpu_gem_force_release(adev);
 832         amdgpu_bo_fini(adev);
 833
 834         return 0;
 835 }
 836
 837 static int gmc_v6_0_hw_init(void *handle)
 838 {
 839         int r;
 840         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 841
 842         gmc_v6_0_mc_program(adev);
 843
 844         if (!(adev->flags & AMD_IS_APU)) {
 845                 r = gmc_v6_0_mc_load_microcode(adev);
 846                 if (r) {
 847                         dev_err(adev->dev, "Failed to load MC firmware!\n");
 848                         return r;
 849                 }
 850         }
 851
 852         r = gmc_v6_0_gart_enable(adev);
 853         if (r)
 854                 return r;
 855
 856         return r;
 857 }
 858
 859 static int gmc_v6_0_hw_fini(void *handle)
 860 {
 861         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 862
 863         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
 864         gmc_v6_0_gart_disable(adev);
 865
 866         return 0;
 867 }
 868
 869 static int gmc_v6_0_suspend(void *handle)
 870 {
 871         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 872
 873         if (adev->vm_manager.enabled) {
 874                 gmc_v6_0_vm_fini(adev);
 875                 adev->vm_manager.enabled = false;
 876         }
 877         gmc_v6_0_hw_fini(adev);
 878
 879         return 0;
 880 }
 881
 882 static int gmc_v6_0_resume(void *handle)
 883 {
 884         int r;
 885         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 886
 887         r = gmc_v6_0_hw_init(adev);
 888         if (r)
 889                 return r;
 890
 891         if (!adev->vm_manager.enabled) {
 892                 r = gmc_v6_0_vm_init(adev);
 893                 if (r) {
 894                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
 895                         return r;
 896                 }
 897                 adev->vm_manager.enabled = true;
 898         }
 899
 900         return r;
 901 }
 902
 903 static bool gmc_v6_0_is_idle(void *handle)
 904 {
 905         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 906         u32 tmp = RREG32(mmSRBM_STATUS);
 907
 908         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
 909                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
 910                 return false;
 911
 912         return true;
 913 }
 914
 915 static int gmc_v6_0_wait_for_idle(void *handle)
 916 {
 917         unsigned i;
 918         u32 tmp;
 919         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 920
 921         for (i = 0; i < adev->usec_timeout; i++) {
 922                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
 923                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
 924                                                SRBM_STATUS__MCC_BUSY_MASK |
 925                                                SRBM_STATUS__MCD_BUSY_MASK |
 926                                                SRBM_STATUS__VMC_BUSY_MASK);
 927                 if (!tmp)
 928                         return 0;
 929                 udelay(1);
 930         }
 931         return -ETIMEDOUT;
 932
 933 }
 934
 935 static int gmc_v6_0_soft_reset(void *handle)
 936 {
 937         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 938         struct amdgpu_mode_mc_save save;
 939         u32 srbm_soft_reset = 0;
 940         u32 tmp = RREG32(mmSRBM_STATUS);
 941
 942         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
 943                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
 944                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
 945
 946         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
 947                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
 948                 if (!(adev->flags & AMD_IS_APU))
 949                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
 950                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
 951         }
 952
 953         if (srbm_soft_reset) {
 954                 gmc_v6_0_mc_stop(adev, &save);
 955                 if (gmc_v6_0_wait_for_idle(adev)) {
 956                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
 957                 }
 958
 959
 960                 tmp = RREG32(mmSRBM_SOFT_RESET);
 961                 tmp |= srbm_soft_reset;
 962                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 963                 WREG32(mmSRBM_SOFT_RESET, tmp);
 964                 tmp = RREG32(mmSRBM_SOFT_RESET);
 965
 966                 udelay(50);
 967
 968                 tmp &= ~srbm_soft_reset;
 969                 WREG32(mmSRBM_SOFT_RESET, tmp);
 970                 tmp = RREG32(mmSRBM_SOFT_RESET);
 971
 972                 udelay(50);
 973
 974                 gmc_v6_0_mc_resume(adev, &save);
 975                 udelay(50);
 976         }
 977
 978         return 0;
 979 }
 980
 981 static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 982                                              struct amdgpu_irq_src *src,
 983                                              unsigned type,
 984                                              enum amdgpu_interrupt_state state)
 985 {
 986         u32 tmp;
 987         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 988                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 989                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 990                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 991                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 992                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
 993
 994         switch (state) {
 995         case AMDGPU_IRQ_STATE_DISABLE:
 996                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
 997                 tmp &= ~bits;
 998                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
 999                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1000                 tmp &= ~bits;
1001                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1002                 break;
1003         case AMDGPU_IRQ_STATE_ENABLE:
1004                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1005                 tmp |= bits;
1006                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1007                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1008                 tmp |= bits;
1009                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1010                 break;
1011         default:
1012                 break;
1013         }
1014
1015         return 0;
1016 }
1017
1018 static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
1019                                       struct amdgpu_irq_src *source,
1020                                       struct amdgpu_iv_entry *entry)
1021 {
1022         u32 addr, status;
1023
1024         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1025         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1026         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1027
1028         if (!addr && !status)
1029                 return 0;
1030
1031         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1032                 gmc_v6_0_set_fault_enable_default(adev, false);
1033
1034         if (printk_ratelimit()) {
1035                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1036                         entry->src_id, entry->src_data);
1037                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1038                         addr);
1039                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1040                         status);
1041                 gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
1042         }
1043
1044         return 0;
1045 }
1046
1047 static int gmc_v6_0_set_clockgating_state(void *handle,
1048                                           enum amd_clockgating_state state)
1049 {
1050         return 0;
1051 }
1052
1053 static int gmc_v6_0_set_powergating_state(void *handle,
1054                                           enum amd_powergating_state state)
1055 {
1056         return 0;
1057 }
1058
1059 static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
1060         .name = "gmc_v6_0",
1061         .early_init = gmc_v6_0_early_init,
1062         .late_init = gmc_v6_0_late_init,
1063         .sw_init = gmc_v6_0_sw_init,
1064         .sw_fini = gmc_v6_0_sw_fini,
1065         .hw_init = gmc_v6_0_hw_init,
1066         .hw_fini = gmc_v6_0_hw_fini,
1067         .suspend = gmc_v6_0_suspend,
1068         .resume = gmc_v6_0_resume,
1069         .is_idle = gmc_v6_0_is_idle,
1070         .wait_for_idle = gmc_v6_0_wait_for_idle,
1071         .soft_reset = gmc_v6_0_soft_reset,
1072         .set_clockgating_state = gmc_v6_0_set_clockgating_state,
1073         .set_powergating_state = gmc_v6_0_set_powergating_state,
1074 };
1075
1076 static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = {
1077         .flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
1078         .set_pte_pde = gmc_v6_0_gart_set_pte_pde,
1079 };
1080
1081 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
1082         .set = gmc_v6_0_vm_fault_interrupt_state,
1083         .process = gmc_v6_0_process_interrupt,
1084 };
1085
1086 static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev)
1087 {
1088         if (adev->gart.gart_funcs == NULL)
1089                 adev->gart.gart_funcs = &gmc_v6_0_gart_funcs;
1090 }
1091
1092 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1093 {
1094         adev->mc.vm_fault.num_types = 1;
1095         adev->mc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
1096 }
1097
1098 const struct amdgpu_ip_block_version gmc_v6_0_ip_block =
1099 {
1100         .type = AMD_IP_BLOCK_TYPE_GMC,
1101         .major = 6,
1102         .minor = 0,
1103         .rev = 0,
1104         .funcs = &gmc_v6_0_ip_funcs,
1105 };