drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drmP.h>
  25 #include "amdgpu.h"
  26 #include "gmc_v6_0.h"
  27 #include "amdgpu_ucode.h"
  28
  29 #include "bif/bif_3_0_d.h"
  30 #include "bif/bif_3_0_sh_mask.h"
  31 #include "oss/oss_1_0_d.h"
  32 #include "oss/oss_1_0_sh_mask.h"
  33 #include "gmc/gmc_6_0_d.h"
  34 #include "gmc/gmc_6_0_sh_mask.h"
  35 #include "dce/dce_6_0_d.h"
  36 #include "dce/dce_6_0_sh_mask.h"
  37 #include "si_enums.h"
  38
  39 static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev);
  40 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  41 static int gmc_v6_0_wait_for_idle(void *handle);
  42
  43 MODULE_FIRMWARE("radeon/tahiti_mc.bin");
  44 MODULE_FIRMWARE("radeon/pitcairn_mc.bin");
  45 MODULE_FIRMWARE("radeon/verde_mc.bin");
  46 MODULE_FIRMWARE("radeon/oland_mc.bin");
  47 MODULE_FIRMWARE("radeon/si58_mc.bin");
  48
  49 #define MC_SEQ_MISC0__MT__MASK   0xf0000000
  50 #define MC_SEQ_MISC0__MT__GDDR1  0x10000000
  51 #define MC_SEQ_MISC0__MT__DDR2   0x20000000
  52 #define MC_SEQ_MISC0__MT__GDDR3  0x30000000
  53 #define MC_SEQ_MISC0__MT__GDDR4  0x40000000
  54 #define MC_SEQ_MISC0__MT__GDDR5  0x50000000
  55 #define MC_SEQ_MISC0__MT__HBM    0x60000000
  56 #define MC_SEQ_MISC0__MT__DDR3   0xB0000000
  57
  58
  59 static const u32 crtc_offsets[6] =
  60 {
  61         SI_CRTC0_REGISTER_OFFSET,
  62         SI_CRTC1_REGISTER_OFFSET,
  63         SI_CRTC2_REGISTER_OFFSET,
  64         SI_CRTC3_REGISTER_OFFSET,
  65         SI_CRTC4_REGISTER_OFFSET,
  66         SI_CRTC5_REGISTER_OFFSET
  67 };
  68
  69 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev)
  70 {
  71         u32 blackout;
  72
  73         gmc_v6_0_wait_for_idle((void *)adev);
  74
  75         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  76         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
  77                 /* Block CPU access */
  78                 WREG32(mmBIF_FB_EN, 0);
  79                 /* blackout the MC */
  80                 blackout = REG_SET_FIELD(blackout,
  81                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
  82                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
  83         }
  84         /* wait for the MC to settle */
  85         udelay(100);
  86
  87 }
  88
  89 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev)
  90 {
  91         u32 tmp;
  92
  93         /* unblackout the MC */
  94         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  95         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
  96         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
  97         /* allow CPU access */
  98         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
  99         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 100         WREG32(mmBIF_FB_EN, tmp);
 101 }
 102
 103 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
 104 {
 105         const char *chip_name;
 106         char fw_name[30];
 107         int err;
 108         bool is_58_fw = false;
 109
 110         DRM_DEBUG("\n");
 111
 112         switch (adev->asic_type) {
 113         case CHIP_TAHITI:
 114                 chip_name = "tahiti";
 115                 break;
 116         case CHIP_PITCAIRN:
 117                 chip_name = "pitcairn";
 118                 break;
 119         case CHIP_VERDE:
 120                 chip_name = "verde";
 121                 break;
 122         case CHIP_OLAND:
 123                 chip_name = "oland";
 124                 break;
 125         case CHIP_HAINAN:
 126                 chip_name = "hainan";
 127                 break;
 128         default: BUG();
 129         }
 130
 131         /* this memory configuration requires special firmware */
 132         if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
 133                 is_58_fw = true;
 134
 135         if (is_58_fw)
 136                 snprintf(fw_name, sizeof(fw_name), "radeon/si58_mc.bin");
 137         else
 138                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 139         err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
 140         if (err)
 141                 goto out;
 142
 143         err = amdgpu_ucode_validate(adev->mc.fw);
 144
 145 out:
 146         if (err) {
 147                 dev_err(adev->dev,
 148                        "si_mc: Failed to load firmware \"%s\"\n",
 149                        fw_name);
 150                 release_firmware(adev->mc.fw);
 151                 adev->mc.fw = NULL;
 152         }
 153         return err;
 154 }
 155
 156 static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
 157 {
 158         const __le32 *new_fw_data = NULL;
 159         u32 running;
 160         const __le32 *new_io_mc_regs = NULL;
 161         int i, regs_size, ucode_size;
 162         const struct mc_firmware_header_v1_0 *hdr;
 163
 164         if (!adev->mc.fw)
 165                 return -EINVAL;
 166
 167         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 168
 169         amdgpu_ucode_print_mc_hdr(&hdr->header);
 170
 171         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 172         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 173         new_io_mc_regs = (const __le32 *)
 174                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 175         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 176         new_fw_data = (const __le32 *)
 177                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 178
 179         running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
 180
 181         if (running == 0) {
 182
 183                 /* reset the engine and set to writable */
 184                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 185                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 186
 187                 /* load mc io regs */
 188                 for (i = 0; i < regs_size; i++) {
 189                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
 190                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
 191                 }
 192                 /* load the MC ucode */
 193                 for (i = 0; i < ucode_size; i++) {
 194                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
 195                 }
 196
 197                 /* put the engine back into the active state */
 198                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 199                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 200                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 201
 202                 /* wait for training to complete */
 203                 for (i = 0; i < adev->usec_timeout; i++) {
 204                         if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
 205                                 break;
 206                         udelay(1);
 207                 }
 208                 for (i = 0; i < adev->usec_timeout; i++) {
 209                         if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
 210                                 break;
 211                         udelay(1);
 212                 }
 213
 214         }
 215
 216         return 0;
 217 }
 218
 219 static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
 220                                        struct amdgpu_mc *mc)
 221 {
 222         u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 223         base <<= 24;
 224
 225         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 226                 dev_warn(adev->dev, "limiting VRAM\n");
 227                 mc->real_vram_size = 0xFFC0000000ULL;
 228                 mc->mc_vram_size = 0xFFC0000000ULL;
 229         }
 230         amdgpu_vram_location(adev, &adev->mc, base);
 231         amdgpu_gart_location(adev, mc);
 232 }
 233
 234 static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
 235 {
 236         int i, j;
 237
 238         /* Initialize HDP */
 239         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 240                 WREG32((0xb05 + j), 0x00000000);
 241                 WREG32((0xb06 + j), 0x00000000);
 242                 WREG32((0xb07 + j), 0x00000000);
 243                 WREG32((0xb08 + j), 0x00000000);
 244                 WREG32((0xb09 + j), 0x00000000);
 245         }
 246         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 247
 248         if (gmc_v6_0_wait_for_idle((void *)adev)) {
 249                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 250         }
 251
 252         if (adev->mode_info.num_crtc) {
 253                 u32 tmp;
 254
 255                 /* Lockout access through VGA aperture*/
 256                 tmp = RREG32(mmVGA_HDP_CONTROL);
 257                 tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK;
 258                 WREG32(mmVGA_HDP_CONTROL, tmp);
 259
 260                 /* disable VGA render */
 261                 tmp = RREG32(mmVGA_RENDER_CONTROL);
 262                 tmp &= ~VGA_VSTATUS_CNTL;
 263                 WREG32(mmVGA_RENDER_CONTROL, tmp);
 264         }
 265         /* Update configuration */
 266         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 267                adev->mc.vram_start >> 12);
 268         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 269                adev->mc.vram_end >> 12);
 270         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 271                adev->vram_scratch.gpu_addr >> 12);
 272         WREG32(mmMC_VM_AGP_BASE, 0);
 273         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 274         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 275
 276         if (gmc_v6_0_wait_for_idle((void *)adev)) {
 277                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 278         }
 279 }
 280
 281 static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
 282 {
 283
 284         u32 tmp;
 285         int chansize, numchan;
 286         int r;
 287
 288         tmp = RREG32(mmMC_ARB_RAMCFG);
 289         if (tmp & (1 << 11)) {
 290                 chansize = 16;
 291         } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) {
 292                 chansize = 64;
 293         } else {
 294                 chansize = 32;
 295         }
 296         tmp = RREG32(mmMC_SHARED_CHMAP);
 297         switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
 298         case 0:
 299         default:
 300                 numchan = 1;
 301                 break;
 302         case 1:
 303                 numchan = 2;
 304                 break;
 305         case 2:
 306                 numchan = 4;
 307                 break;
 308         case 3:
 309                 numchan = 8;
 310                 break;
 311         case 4:
 312                 numchan = 3;
 313                 break;
 314         case 5:
 315                 numchan = 6;
 316                 break;
 317         case 6:
 318                 numchan = 10;
 319                 break;
 320         case 7:
 321                 numchan = 12;
 322                 break;
 323         case 8:
 324                 numchan = 16;
 325                 break;
 326         }
 327         adev->mc.vram_width = numchan * chansize;
 328         /* size in MB on si */
 329         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 330         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 331
 332         if (!(adev->flags & AMD_IS_APU)) {
 333                 r = amdgpu_device_resize_fb_bar(adev);
 334                 if (r)
 335                         return r;
 336         }
 337         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 338         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 339         adev->mc.visible_vram_size = adev->mc.aper_size;
 340
 341         /* set the gart size */
 342         if (amdgpu_gart_size == -1) {
 343                 switch (adev->asic_type) {
 344                 case CHIP_HAINAN:    /* no MM engines */
 345                 default:
 346                         adev->mc.gart_size = 256ULL << 20;
 347                         break;
 348                 case CHIP_VERDE:    /* UVD, VCE do not support GPUVM */
 349                 case CHIP_TAHITI:   /* UVD, VCE do not support GPUVM */
 350                 case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */
 351                 case CHIP_OLAND:    /* UVD, VCE do not support GPUVM */
 352                         adev->mc.gart_size = 1024ULL << 20;
 353                         break;
 354                 }
 355         } else {
 356                 adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
 357         }
 358
 359         gmc_v6_0_vram_gtt_location(adev, &adev->mc);
 360
 361         return 0;
 362 }
 363
 364 static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 365                                         uint32_t vmid)
 366 {
 367         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 368
 369         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 370 }
 371
 372 static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev,
 373                                      void *cpu_pt_addr,
 374                                      uint32_t gpu_page_idx,
 375                                      uint64_t addr,
 376                                      uint64_t flags)
 377 {
 378         void __iomem *ptr = (void *)cpu_pt_addr;
 379         uint64_t value;
 380
 381         value = addr & 0xFFFFFFFFFFFFF000ULL;
 382         value |= flags;
 383         writeq(value, ptr + (gpu_page_idx * 8));
 384
 385         return 0;
 386 }
 387
 388 static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev,
 389                                           uint32_t flags)
 390 {
 391         uint64_t pte_flag = 0;
 392
 393         if (flags & AMDGPU_VM_PAGE_READABLE)
 394                 pte_flag |= AMDGPU_PTE_READABLE;
 395         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 396                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 397         if (flags & AMDGPU_VM_PAGE_PRT)
 398                 pte_flag |= AMDGPU_PTE_PRT;
 399
 400         return pte_flag;
 401 }
 402
 403 static uint64_t gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr)
 404 {
 405         BUG_ON(addr & 0xFFFFFF0000000FFFULL);
 406         return addr;
 407 }
 408
 409 static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
 410                                               bool value)
 411 {
 412         u32 tmp;
 413
 414         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 415         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 416                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 417         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 418                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 419         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 420                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 421         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 422                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 423         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 424                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 425         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 426                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 427         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 428 }
 429
 430  /**
 431    + * gmc_v8_0_set_prt - set PRT VM fault
 432    + *
 433    + * @adev: amdgpu_device pointer
 434    + * @enable: enable/disable VM fault handling for PRT
 435    +*/
 436 static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
 437 {
 438         u32 tmp;
 439
 440         if (enable && !adev->mc.prt_warning) {
 441                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 442                 adev->mc.prt_warning = true;
 443         }
 444
 445         tmp = RREG32(mmVM_PRT_CNTL);
 446         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 447                             CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
 448                             enable);
 449         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 450                             TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
 451                             enable);
 452         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 453                             L2_CACHE_STORE_INVALID_ENTRIES,
 454                             enable);
 455         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 456                             L1_TLB_STORE_INVALID_ENTRIES,
 457                             enable);
 458         WREG32(mmVM_PRT_CNTL, tmp);
 459
 460         if (enable) {
 461                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 462                 uint32_t high = adev->vm_manager.max_pfn;
 463
 464                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 465                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 466                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 467                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 468                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 469                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 470                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 471                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 472         } else {
 473                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 474                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 475                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 476                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 477                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 478                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 479                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 480                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 481         }
 482 }
 483
 484 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 485 {
 486         int i;
 487         u32 field;
 488
 489         if (adev->gart.robj == NULL) {
 490                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 491                 return -EINVAL;
 492         }
 493
 494         /* Setup TLB control */
 495         WREG32(mmMC_VM_MX_L1_TLB_CNTL,
 496                (0xA << 7) |
 497                MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK |
 498                MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK |
 499                MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
 500                MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK |
 501                (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
 502         /* Setup L2 cache */
 503         WREG32(mmVM_L2_CNTL,
 504                VM_L2_CNTL__ENABLE_L2_CACHE_MASK |
 505                VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK |
 506                VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 507                VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 508                (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
 509                (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
 510         WREG32(mmVM_L2_CNTL2,
 511                VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
 512                VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
 513
 514         field = adev->vm_manager.fragment_size;
 515         WREG32(mmVM_L2_CNTL3,
 516                VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
 517                (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
 518                (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
 519         /* setup context0 */
 520         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12);
 521         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gart_end >> 12);
 522         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 523         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 524                         (u32)(adev->dummy_page.addr >> 12));
 525         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 526         WREG32(mmVM_CONTEXT0_CNTL,
 527                VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
 528                (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
 529                VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
 530
 531         WREG32(0x575, 0);
 532         WREG32(0x576, 0);
 533         WREG32(0x577, 0);
 534
 535         /* empty context1-15 */
 536         /* set vm size, must be a multiple of 4 */
 537         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 538         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 539         /* Assign the pt base to something valid for now; the pts used for
 540          * the VMs are determined by the application and setup and assigned
 541          * on the fly in the vm part of radeon_gart.c
 542          */
 543         for (i = 1; i < 16; i++) {
 544                 if (i < 8)
 545                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 546                                adev->gart.table_addr >> 12);
 547                 else
 548                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 549                                adev->gart.table_addr >> 12);
 550         }
 551
 552         /* enable context1-15 */
 553         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 554                (u32)(adev->dummy_page.addr >> 12));
 555         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 556         WREG32(mmVM_CONTEXT1_CNTL,
 557                VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
 558                (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
 559                ((adev->vm_manager.block_size - 9)
 560                << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT));
 561         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 562                 gmc_v6_0_set_fault_enable_default(adev, false);
 563         else
 564                 gmc_v6_0_set_fault_enable_default(adev, true);
 565
 566         gmc_v6_0_gart_flush_gpu_tlb(adev, 0);
 567         dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
 568                  (unsigned)(adev->mc.gart_size >> 20),
 569                  (unsigned long long)adev->gart.table_addr);
 570         adev->gart.ready = true;
 571         return 0;
 572 }
 573
 574 static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
 575 {
 576         int r;
 577
 578         if (adev->gart.robj) {
 579                 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
 580                 return 0;
 581         }
 582         r = amdgpu_gart_init(adev);
 583         if (r)
 584                 return r;
 585         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 586         adev->gart.gart_pte_flags = 0;
 587         return amdgpu_gart_table_vram_alloc(adev);
 588 }
 589
 590 static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
 591 {
 592         /*unsigned i;
 593
 594         for (i = 1; i < 16; ++i) {
 595                 uint32_t reg;
 596                 if (i < 8)
 597                         reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ;
 598                 else
 599                         reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8);
 600                 adev->vm_manager.saved_table_addr[i] = RREG32(reg);
 601         }*/
 602
 603         /* Disable all tables */
 604         WREG32(mmVM_CONTEXT0_CNTL, 0);
 605         WREG32(mmVM_CONTEXT1_CNTL, 0);
 606         /* Setup TLB control */
 607         WREG32(mmMC_VM_MX_L1_TLB_CNTL,
 608                MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
 609                (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
 610         /* Setup L2 cache */
 611         WREG32(mmVM_L2_CNTL,
 612                VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 613                VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 614                (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
 615                (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
 616         WREG32(mmVM_L2_CNTL2, 0);
 617         WREG32(mmVM_L2_CNTL3,
 618                VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
 619                (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
 620 }
 621
 622 static void gmc_v6_0_gart_fini(struct amdgpu_device *adev)
 623 {
 624         amdgpu_gart_table_vram_free(adev);
 625         amdgpu_gart_fini(adev);
 626 }
 627
 628 static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
 629                                      u32 status, u32 addr, u32 mc_client)
 630 {
 631         u32 mc_id;
 632         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 633         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 634                                         PROTECTIONS);
 635         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 636                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 637
 638         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 639                               MEMORY_CLIENT_ID);
 640
 641         dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 642                protections, vmid, addr,
 643                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 644                              MEMORY_CLIENT_RW) ?
 645                "write" : "read", block, mc_client, mc_id);
 646 }
 647
 648 /*
 649 static const u32 mc_cg_registers[] = {
 650         MC_HUB_MISC_HUB_CG,
 651         MC_HUB_MISC_SIP_CG,
 652         MC_HUB_MISC_VM_CG,
 653         MC_XPB_CLK_GAT,
 654         ATC_MISC_CG,
 655         MC_CITF_MISC_WR_CG,
 656         MC_CITF_MISC_RD_CG,
 657         MC_CITF_MISC_VM_CG,
 658         VM_L2_CG,
 659 };
 660
 661 static const u32 mc_cg_ls_en[] = {
 662         MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
 663         MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
 664         MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 665         MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
 666         ATC_MISC_CG__MEM_LS_ENABLE_MASK,
 667         MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
 668         MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
 669         MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 670         VM_L2_CG__MEM_LS_ENABLE_MASK,
 671 };
 672
 673 static const u32 mc_cg_en[] = {
 674         MC_HUB_MISC_HUB_CG__ENABLE_MASK,
 675         MC_HUB_MISC_SIP_CG__ENABLE_MASK,
 676         MC_HUB_MISC_VM_CG__ENABLE_MASK,
 677         MC_XPB_CLK_GAT__ENABLE_MASK,
 678         ATC_MISC_CG__ENABLE_MASK,
 679         MC_CITF_MISC_WR_CG__ENABLE_MASK,
 680         MC_CITF_MISC_RD_CG__ENABLE_MASK,
 681         MC_CITF_MISC_VM_CG__ENABLE_MASK,
 682         VM_L2_CG__ENABLE_MASK,
 683 };
 684
 685 static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev,
 686                                   bool enable)
 687 {
 688         int i;
 689         u32 orig, data;
 690
 691         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 692                 orig = data = RREG32(mc_cg_registers[i]);
 693                 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
 694                         data |= mc_cg_ls_en[i];
 695                 else
 696                         data &= ~mc_cg_ls_en[i];
 697                 if (data != orig)
 698                         WREG32(mc_cg_registers[i], data);
 699         }
 700 }
 701
 702 static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev,
 703                                     bool enable)
 704 {
 705         int i;
 706         u32 orig, data;
 707
 708         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 709                 orig = data = RREG32(mc_cg_registers[i]);
 710                 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
 711                         data |= mc_cg_en[i];
 712                 else
 713                         data &= ~mc_cg_en[i];
 714                 if (data != orig)
 715                         WREG32(mc_cg_registers[i], data);
 716         }
 717 }
 718
 719 static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev,
 720                                      bool enable)
 721 {
 722         u32 orig, data;
 723
 724         orig = data = RREG32_PCIE(ixPCIE_CNTL2);
 725
 726         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
 727                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
 728                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
 729                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
 730                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
 731         } else {
 732                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
 733                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
 734                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
 735                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
 736         }
 737
 738         if (orig != data)
 739                 WREG32_PCIE(ixPCIE_CNTL2, data);
 740 }
 741
 742 static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
 743                                      bool enable)
 744 {
 745         u32 orig, data;
 746
 747         orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
 748
 749         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
 750                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
 751         else
 752                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
 753
 754         if (orig != data)
 755                 WREG32(mmHDP_HOST_PATH_CNTL, data);
 756 }
 757
 758 static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
 759                                    bool enable)
 760 {
 761         u32 orig, data;
 762
 763         orig = data = RREG32(mmHDP_MEM_POWER_LS);
 764
 765         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
 766                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
 767         else
 768                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
 769
 770         if (orig != data)
 771                 WREG32(mmHDP_MEM_POWER_LS, data);
 772 }
 773 */
 774
 775 static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type)
 776 {
 777         switch (mc_seq_vram_type) {
 778         case MC_SEQ_MISC0__MT__GDDR1:
 779                 return AMDGPU_VRAM_TYPE_GDDR1;
 780         case MC_SEQ_MISC0__MT__DDR2:
 781                 return AMDGPU_VRAM_TYPE_DDR2;
 782         case MC_SEQ_MISC0__MT__GDDR3:
 783                 return AMDGPU_VRAM_TYPE_GDDR3;
 784         case MC_SEQ_MISC0__MT__GDDR4:
 785                 return AMDGPU_VRAM_TYPE_GDDR4;
 786         case MC_SEQ_MISC0__MT__GDDR5:
 787                 return AMDGPU_VRAM_TYPE_GDDR5;
 788         case MC_SEQ_MISC0__MT__DDR3:
 789                 return AMDGPU_VRAM_TYPE_DDR3;
 790         default:
 791                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 792         }
 793 }
 794
 795 static int gmc_v6_0_early_init(void *handle)
 796 {
 797         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 798
 799         gmc_v6_0_set_gart_funcs(adev);
 800         gmc_v6_0_set_irq_funcs(adev);
 801
 802         return 0;
 803 }
 804
 805 static int gmc_v6_0_late_init(void *handle)
 806 {
 807         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 808
 809         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 810                 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 811         else
 812                 return 0;
 813 }
 814
 815 static int gmc_v6_0_sw_init(void *handle)
 816 {
 817         int r;
 818         int dma_bits;
 819         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 820
 821         if (adev->flags & AMD_IS_APU) {
 822                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 823         } else {
 824                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 825                 tmp &= MC_SEQ_MISC0__MT__MASK;
 826                 adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp);
 827         }
 828
 829         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault);
 830         if (r)
 831                 return r;
 832
 833         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault);
 834         if (r)
 835                 return r;
 836
 837         amdgpu_vm_adjust_size(adev, 64, 9);
 838
 839         adev->mc.mc_mask = 0xffffffffffULL;
 840
 841         adev->mc.stolen_size = 256 * 1024;
 842
 843         adev->need_dma32 = false;
 844         dma_bits = adev->need_dma32 ? 32 : 40;
 845         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 846         if (r) {
 847                 adev->need_dma32 = true;
 848                 dma_bits = 32;
 849                 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
 850         }
 851         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 852         if (r) {
 853                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 854                 dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
 855         }
 856
 857         r = gmc_v6_0_init_microcode(adev);
 858         if (r) {
 859                 dev_err(adev->dev, "Failed to load mc firmware!\n");
 860                 return r;
 861         }
 862
 863         r = gmc_v6_0_mc_init(adev);
 864         if (r)
 865                 return r;
 866
 867         r = amdgpu_bo_init(adev);
 868         if (r)
 869                 return r;
 870
 871         r = gmc_v6_0_gart_init(adev);
 872         if (r)
 873                 return r;
 874
 875         /*
 876          * number of VMs
 877          * VMID 0 is reserved for System
 878          * amdgpu graphics/compute will use VMIDs 1-7
 879          * amdkfd will use VMIDs 8-15
 880          */
 881         adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
 882         adev->vm_manager.num_level = 1;
 883         amdgpu_vm_manager_init(adev);
 884
 885         /* base offset of vram pages */
 886         if (adev->flags & AMD_IS_APU) {
 887                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
 888
 889                 tmp <<= 22;
 890                 adev->vm_manager.vram_base_offset = tmp;
 891         } else {
 892                 adev->vm_manager.vram_base_offset = 0;
 893         }
 894
 895         return 0;
 896 }
 897
 898 static int gmc_v6_0_sw_fini(void *handle)
 899 {
 900         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 901
 902         amdgpu_gem_force_release(adev);
 903         amdgpu_vm_manager_fini(adev);
 904         gmc_v6_0_gart_fini(adev);
 905         amdgpu_bo_fini(adev);
 906         release_firmware(adev->mc.fw);
 907         adev->mc.fw = NULL;
 908
 909         return 0;
 910 }
 911
 912 static int gmc_v6_0_hw_init(void *handle)
 913 {
 914         int r;
 915         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 916
 917         gmc_v6_0_mc_program(adev);
 918
 919         if (!(adev->flags & AMD_IS_APU)) {
 920                 r = gmc_v6_0_mc_load_microcode(adev);
 921                 if (r) {
 922                         dev_err(adev->dev, "Failed to load MC firmware!\n");
 923                         return r;
 924                 }
 925         }
 926
 927         r = gmc_v6_0_gart_enable(adev);
 928         if (r)
 929                 return r;
 930
 931         return r;
 932 }
 933
 934 static int gmc_v6_0_hw_fini(void *handle)
 935 {
 936         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 937
 938         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
 939         gmc_v6_0_gart_disable(adev);
 940
 941         return 0;
 942 }
 943
 944 static int gmc_v6_0_suspend(void *handle)
 945 {
 946         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 947
 948         gmc_v6_0_hw_fini(adev);
 949
 950         return 0;
 951 }
 952
 953 static int gmc_v6_0_resume(void *handle)
 954 {
 955         int r;
 956         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 957
 958         r = gmc_v6_0_hw_init(adev);
 959         if (r)
 960                 return r;
 961
 962         amdgpu_vm_reset_all_ids(adev);
 963
 964         return 0;
 965 }
 966
 967 static bool gmc_v6_0_is_idle(void *handle)
 968 {
 969         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 970         u32 tmp = RREG32(mmSRBM_STATUS);
 971
 972         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
 973                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
 974                 return false;
 975
 976         return true;
 977 }
 978
 979 static int gmc_v6_0_wait_for_idle(void *handle)
 980 {
 981         unsigned i;
 982         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 983
 984         for (i = 0; i < adev->usec_timeout; i++) {
 985                 if (gmc_v6_0_is_idle(handle))
 986                         return 0;
 987                 udelay(1);
 988         }
 989         return -ETIMEDOUT;
 990
 991 }
 992
 993 static int gmc_v6_0_soft_reset(void *handle)
 994 {
 995         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 996         u32 srbm_soft_reset = 0;
 997         u32 tmp = RREG32(mmSRBM_STATUS);
 998
 999         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1000                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1001                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1002
1003         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1004                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1005                 if (!(adev->flags & AMD_IS_APU))
1006                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1007                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1008         }
1009
1010         if (srbm_soft_reset) {
1011                 gmc_v6_0_mc_stop(adev);
1012                 if (gmc_v6_0_wait_for_idle(adev)) {
1013                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1014                 }
1015
1016
1017                 tmp = RREG32(mmSRBM_SOFT_RESET);
1018                 tmp |= srbm_soft_reset;
1019                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1020                 WREG32(mmSRBM_SOFT_RESET, tmp);
1021                 tmp = RREG32(mmSRBM_SOFT_RESET);
1022
1023                 udelay(50);
1024
1025                 tmp &= ~srbm_soft_reset;
1026                 WREG32(mmSRBM_SOFT_RESET, tmp);
1027                 tmp = RREG32(mmSRBM_SOFT_RESET);
1028
1029                 udelay(50);
1030
1031                 gmc_v6_0_mc_resume(adev);
1032                 udelay(50);
1033         }
1034
1035         return 0;
1036 }
1037
1038 static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1039                                              struct amdgpu_irq_src *src,
1040                                              unsigned type,
1041                                              enum amdgpu_interrupt_state state)
1042 {
1043         u32 tmp;
1044         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1045                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1046                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1047                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1048                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1049                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1050
1051         switch (state) {
1052         case AMDGPU_IRQ_STATE_DISABLE:
1053                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1054                 tmp &= ~bits;
1055                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1056                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1057                 tmp &= ~bits;
1058                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1059                 break;
1060         case AMDGPU_IRQ_STATE_ENABLE:
1061                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1062                 tmp |= bits;
1063                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1064                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1065                 tmp |= bits;
1066                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1067                 break;
1068         default:
1069                 break;
1070         }
1071
1072         return 0;
1073 }
1074
1075 static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
1076                                       struct amdgpu_irq_src *source,
1077                                       struct amdgpu_iv_entry *entry)
1078 {
1079         u32 addr, status;
1080
1081         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1082         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1083         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1084
1085         if (!addr && !status)
1086                 return 0;
1087
1088         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1089                 gmc_v6_0_set_fault_enable_default(adev, false);
1090
1091         if (printk_ratelimit()) {
1092                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1093                         entry->src_id, entry->src_data[0]);
1094                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1095                         addr);
1096                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1097                         status);
1098                 gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
1099         }
1100
1101         return 0;
1102 }
1103
1104 static int gmc_v6_0_set_clockgating_state(void *handle,
1105                                           enum amd_clockgating_state state)
1106 {
1107         return 0;
1108 }
1109
1110 static int gmc_v6_0_set_powergating_state(void *handle,
1111                                           enum amd_powergating_state state)
1112 {
1113         return 0;
1114 }
1115
1116 static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
1117         .name = "gmc_v6_0",
1118         .early_init = gmc_v6_0_early_init,
1119         .late_init = gmc_v6_0_late_init,
1120         .sw_init = gmc_v6_0_sw_init,
1121         .sw_fini = gmc_v6_0_sw_fini,
1122         .hw_init = gmc_v6_0_hw_init,
1123         .hw_fini = gmc_v6_0_hw_fini,
1124         .suspend = gmc_v6_0_suspend,
1125         .resume = gmc_v6_0_resume,
1126         .is_idle = gmc_v6_0_is_idle,
1127         .wait_for_idle = gmc_v6_0_wait_for_idle,
1128         .soft_reset = gmc_v6_0_soft_reset,
1129         .set_clockgating_state = gmc_v6_0_set_clockgating_state,
1130         .set_powergating_state = gmc_v6_0_set_powergating_state,
1131 };
1132
1133 static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = {
1134         .flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
1135         .set_pte_pde = gmc_v6_0_gart_set_pte_pde,
1136         .set_prt = gmc_v6_0_set_prt,
1137         .get_vm_pde = gmc_v6_0_get_vm_pde,
1138         .get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags
1139 };
1140
1141 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
1142         .set = gmc_v6_0_vm_fault_interrupt_state,
1143         .process = gmc_v6_0_process_interrupt,
1144 };
1145
1146 static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev)
1147 {
1148         if (adev->gart.gart_funcs == NULL)
1149                 adev->gart.gart_funcs = &gmc_v6_0_gart_funcs;
1150 }
1151
1152 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1153 {
1154         adev->mc.vm_fault.num_types = 1;
1155         adev->mc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
1156 }
1157
1158 const struct amdgpu_ip_block_version gmc_v6_0_ip_block =
1159 {
1160         .type = AMD_IP_BLOCK_TYPE_GMC,
1161         .major = 6,
1162         .minor = 0,
1163         .rev = 0,
1164         .funcs = &gmc_v6_0_ip_funcs,
1165 };