2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
25 #include <linux/pci.h>
27 #include <drm/drm_cache.h>
31 #include "amdgpu_atomfirmware.h"
32 #include "amdgpu_gem.h"
34 #include "hdp/hdp_4_0_offset.h"
35 #include "hdp/hdp_4_0_sh_mask.h"
36 #include "gc/gc_9_0_sh_mask.h"
37 #include "dce/dce_12_0_offset.h"
38 #include "dce/dce_12_0_sh_mask.h"
39 #include "vega10_enum.h"
40 #include "mmhub/mmhub_1_0_offset.h"
41 #include "athub/athub_1_0_offset.h"
42 #include "oss/osssys_4_0_offset.h"
45 #include "soc15_common.h"
46 #include "umc/umc_6_0_sh_mask.h"
48 #include "gfxhub_v1_0.h"
49 #include "mmhub_v1_0.h"
50 #include "athub_v1_0.h"
51 #include "gfxhub_v1_1.h"
52 #include "mmhub_v9_4.h"
56 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
58 #include "amdgpu_ras.h"
59 #include "amdgpu_xgmi.h"
61 /* add these here since we already include dce12 headers and these are for DCN */
62 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d
63 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
64 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0
65 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10
66 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL
67 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
69 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
70 #define AMDGPU_NUM_OF_VMIDS 8
72 static const u32 golden_settings_vega10_hdp[] =
74 0xf64, 0x0fffffff, 0x00000000,
75 0xf65, 0x0fffffff, 0x00000000,
76 0xf66, 0x0fffffff, 0x00000000,
77 0xf67, 0x0fffffff, 0x00000000,
78 0xf68, 0x0fffffff, 0x00000000,
79 0xf6a, 0x0fffffff, 0x00000000,
80 0xf6b, 0x0fffffff, 0x00000000,
81 0xf6c, 0x0fffffff, 0x00000000,
82 0xf6d, 0x0fffffff, 0x00000000,
83 0xf6e, 0x0fffffff, 0x00000000,
86 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
88 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
89 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
92 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
94 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
95 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
98 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = {
99 (0x000143c0 + 0x00000000),
100 (0x000143c0 + 0x00000800),
101 (0x000143c0 + 0x00001000),
102 (0x000143c0 + 0x00001800),
103 (0x000543c0 + 0x00000000),
104 (0x000543c0 + 0x00000800),
105 (0x000543c0 + 0x00001000),
106 (0x000543c0 + 0x00001800),
107 (0x000943c0 + 0x00000000),
108 (0x000943c0 + 0x00000800),
109 (0x000943c0 + 0x00001000),
110 (0x000943c0 + 0x00001800),
111 (0x000d43c0 + 0x00000000),
112 (0x000d43c0 + 0x00000800),
113 (0x000d43c0 + 0x00001000),
114 (0x000d43c0 + 0x00001800),
115 (0x001143c0 + 0x00000000),
116 (0x001143c0 + 0x00000800),
117 (0x001143c0 + 0x00001000),
118 (0x001143c0 + 0x00001800),
119 (0x001543c0 + 0x00000000),
120 (0x001543c0 + 0x00000800),
121 (0x001543c0 + 0x00001000),
122 (0x001543c0 + 0x00001800),
123 (0x001943c0 + 0x00000000),
124 (0x001943c0 + 0x00000800),
125 (0x001943c0 + 0x00001000),
126 (0x001943c0 + 0x00001800),
127 (0x001d43c0 + 0x00000000),
128 (0x001d43c0 + 0x00000800),
129 (0x001d43c0 + 0x00001000),
130 (0x001d43c0 + 0x00001800),
133 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {
134 (0x000143e0 + 0x00000000),
135 (0x000143e0 + 0x00000800),
136 (0x000143e0 + 0x00001000),
137 (0x000143e0 + 0x00001800),
138 (0x000543e0 + 0x00000000),
139 (0x000543e0 + 0x00000800),
140 (0x000543e0 + 0x00001000),
141 (0x000543e0 + 0x00001800),
142 (0x000943e0 + 0x00000000),
143 (0x000943e0 + 0x00000800),
144 (0x000943e0 + 0x00001000),
145 (0x000943e0 + 0x00001800),
146 (0x000d43e0 + 0x00000000),
147 (0x000d43e0 + 0x00000800),
148 (0x000d43e0 + 0x00001000),
149 (0x000d43e0 + 0x00001800),
150 (0x001143e0 + 0x00000000),
151 (0x001143e0 + 0x00000800),
152 (0x001143e0 + 0x00001000),
153 (0x001143e0 + 0x00001800),
154 (0x001543e0 + 0x00000000),
155 (0x001543e0 + 0x00000800),
156 (0x001543e0 + 0x00001000),
157 (0x001543e0 + 0x00001800),
158 (0x001943e0 + 0x00000000),
159 (0x001943e0 + 0x00000800),
160 (0x001943e0 + 0x00001000),
161 (0x001943e0 + 0x00001800),
162 (0x001d43e0 + 0x00000000),
163 (0x001d43e0 + 0x00000800),
164 (0x001d43e0 + 0x00001000),
165 (0x001d43e0 + 0x00001800),
168 static const uint32_t ecc_umc_mcumc_status_addrs[] = {
169 (0x000143c2 + 0x00000000),
170 (0x000143c2 + 0x00000800),
171 (0x000143c2 + 0x00001000),
172 (0x000143c2 + 0x00001800),
173 (0x000543c2 + 0x00000000),
174 (0x000543c2 + 0x00000800),
175 (0x000543c2 + 0x00001000),
176 (0x000543c2 + 0x00001800),
177 (0x000943c2 + 0x00000000),
178 (0x000943c2 + 0x00000800),
179 (0x000943c2 + 0x00001000),
180 (0x000943c2 + 0x00001800),
181 (0x000d43c2 + 0x00000000),
182 (0x000d43c2 + 0x00000800),
183 (0x000d43c2 + 0x00001000),
184 (0x000d43c2 + 0x00001800),
185 (0x001143c2 + 0x00000000),
186 (0x001143c2 + 0x00000800),
187 (0x001143c2 + 0x00001000),
188 (0x001143c2 + 0x00001800),
189 (0x001543c2 + 0x00000000),
190 (0x001543c2 + 0x00000800),
191 (0x001543c2 + 0x00001000),
192 (0x001543c2 + 0x00001800),
193 (0x001943c2 + 0x00000000),
194 (0x001943c2 + 0x00000800),
195 (0x001943c2 + 0x00001000),
196 (0x001943c2 + 0x00001800),
197 (0x001d43c2 + 0x00000000),
198 (0x001d43c2 + 0x00000800),
199 (0x001d43c2 + 0x00001000),
200 (0x001d43c2 + 0x00001800),
203 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
204 struct amdgpu_irq_src *src,
206 enum amdgpu_interrupt_state state)
208 u32 bits, i, tmp, reg;
210 /* Devices newer then VEGA10/12 shall have these programming
211 sequences performed by PSP BL */
212 if (adev->asic_type >= CHIP_VEGA20)
218 case AMDGPU_IRQ_STATE_DISABLE:
219 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
220 reg = ecc_umc_mcumc_ctrl_addrs[i];
225 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
226 reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
232 case AMDGPU_IRQ_STATE_ENABLE:
233 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
234 reg = ecc_umc_mcumc_ctrl_addrs[i];
239 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
240 reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
253 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
254 struct amdgpu_irq_src *src,
256 enum amdgpu_interrupt_state state)
258 struct amdgpu_vmhub *hub;
259 u32 tmp, reg, bits, i, j;
261 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
262 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
263 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
264 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
265 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
266 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
267 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
270 case AMDGPU_IRQ_STATE_DISABLE:
271 for (j = 0; j < adev->num_vmhubs; j++) {
272 hub = &adev->vmhub[j];
273 for (i = 0; i < 16; i++) {
274 reg = hub->vm_context0_cntl + i;
281 case AMDGPU_IRQ_STATE_ENABLE:
282 for (j = 0; j < adev->num_vmhubs; j++) {
283 hub = &adev->vmhub[j];
284 for (i = 0; i < 16; i++) {
285 reg = hub->vm_context0_cntl + i;
298 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
299 struct amdgpu_irq_src *source,
300 struct amdgpu_iv_entry *entry)
302 struct amdgpu_vmhub *hub;
303 bool retry_fault = !!(entry->src_data[1] & 0x80);
308 addr = (u64)entry->src_data[0] << 12;
309 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
311 if (retry_fault && amdgpu_gmc_filter_faults(adev, addr, entry->pasid,
313 return 1; /* This also prevents sending it to KFD */
315 if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
316 snprintf(hub_name, sizeof(hub_name), "mmhub0");
317 hub = &adev->vmhub[AMDGPU_MMHUB_0];
318 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
319 snprintf(hub_name, sizeof(hub_name), "mmhub1");
320 hub = &adev->vmhub[AMDGPU_MMHUB_1];
322 snprintf(hub_name, sizeof(hub_name), "gfxhub0");
323 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
326 /* If it's the first fault for this address, process it normally */
327 if (retry_fault && !in_interrupt() &&
328 amdgpu_vm_handle_fault(adev, entry->pasid, addr))
329 return 1; /* This also prevents sending it to KFD */
331 if (!amdgpu_sriov_vf(adev)) {
333 * Issue a dummy read to wait for the status register to
334 * be updated to avoid reading an incorrect value due to
335 * the new fast GRBM interface.
337 if (entry->vmid_src == AMDGPU_GFXHUB_0)
338 RREG32(hub->vm_l2_pro_fault_status);
340 status = RREG32(hub->vm_l2_pro_fault_status);
341 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
344 if (printk_ratelimit()) {
345 struct amdgpu_task_info task_info;
347 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
348 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
351 "[%s] %s page fault (src_id:%u ring:%u vmid:%u "
352 "pasid:%u, for process %s pid %d thread %s pid %d)\n",
353 hub_name, retry_fault ? "retry" : "no-retry",
354 entry->src_id, entry->ring_id, entry->vmid,
355 entry->pasid, task_info.process_name, task_info.tgid,
356 task_info.task_name, task_info.pid);
357 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n",
358 addr, entry->client_id);
359 if (!amdgpu_sriov_vf(adev)) {
361 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
363 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
364 REG_GET_FIELD(status,
365 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
366 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
367 REG_GET_FIELD(status,
368 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
369 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
370 REG_GET_FIELD(status,
371 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
372 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
373 REG_GET_FIELD(status,
374 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
375 dev_err(adev->dev, "\t RW: 0x%lx\n",
376 REG_GET_FIELD(status,
377 VM_L2_PROTECTION_FAULT_STATUS, RW));
385 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
386 .set = gmc_v9_0_vm_fault_interrupt_state,
387 .process = gmc_v9_0_process_interrupt,
391 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = {
392 .set = gmc_v9_0_ecc_interrupt_state,
393 .process = amdgpu_umc_process_ecc_irq,
396 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
398 adev->gmc.vm_fault.num_types = 1;
399 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
401 adev->gmc.ecc_irq.num_types = 1;
402 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;
405 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
410 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
411 PER_VMID_INVALIDATE_REQ, 1 << vmid);
412 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
413 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
414 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
415 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
416 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
417 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
418 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
419 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
425 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
427 * @adev: amdgpu_device pointer
431 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
434 return ((vmhub == AMDGPU_MMHUB_0 ||
435 vmhub == AMDGPU_MMHUB_1) &&
436 (!amdgpu_sriov_vf(adev)) &&
437 (!(adev->asic_type == CHIP_RAVEN &&
438 adev->rev_id < 0x8 &&
439 adev->pdev->device == 0x15d8)));
444 * VMID 0 is the physical GPU addresses as used by the kernel.
445 * VMIDs 1-15 are used for userspace clients and are handled
446 * by the amdgpu vm/hsa code.
450 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
452 * @adev: amdgpu_device pointer
453 * @vmid: vm instance to flush
454 * @flush_type: the flush type
456 * Flush the TLB for the requested page table using certain type.
458 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
459 uint32_t vmhub, uint32_t flush_type)
461 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
462 const unsigned eng = 17;
464 struct amdgpu_vmhub *hub;
466 BUG_ON(vmhub >= adev->num_vmhubs);
468 hub = &adev->vmhub[vmhub];
469 tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type);
471 /* This is necessary for a HW workaround under SRIOV as well
472 * as GFXOFF under bare metal
474 if (adev->gfx.kiq.ring.sched.ready &&
475 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
476 !adev->in_gpu_reset) {
477 uint32_t req = hub->vm_inv_eng0_req + eng;
478 uint32_t ack = hub->vm_inv_eng0_ack + eng;
480 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp,
485 spin_lock(&adev->gmc.invalidate_lock);
488 * It may lose gpuvm invalidate acknowldege state across power-gating
489 * off cycle, add semaphore acquire before invalidation and semaphore
490 * release after invalidation to avoid entering power gated state
494 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
496 for (j = 0; j < adev->usec_timeout; j++) {
497 /* a read return value of 1 means semaphore acuqire */
498 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
504 if (j >= adev->usec_timeout)
505 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
508 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
511 * Issue a dummy read to wait for the ACK register to be cleared
512 * to avoid a false ACK due to the new fast GRBM interface.
514 if (vmhub == AMDGPU_GFXHUB_0)
515 RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng);
517 for (j = 0; j < adev->usec_timeout; j++) {
518 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
519 if (tmp & (1 << vmid))
524 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
527 * add semaphore release after invalidation,
528 * write with 0 means semaphore release
530 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0);
532 spin_unlock(&adev->gmc.invalidate_lock);
534 if (j < adev->usec_timeout)
537 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
540 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
541 unsigned vmid, uint64_t pd_addr)
543 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
544 struct amdgpu_device *adev = ring->adev;
545 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
546 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
547 unsigned eng = ring->vm_inv_eng;
550 * It may lose gpuvm invalidate acknowldege state across power-gating
551 * off cycle, add semaphore acquire before invalidation and semaphore
552 * release after invalidation to avoid entering power gated state
556 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
558 /* a read return value of 1 means semaphore acuqire */
559 amdgpu_ring_emit_reg_wait(ring,
560 hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
562 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
563 lower_32_bits(pd_addr));
565 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
566 upper_32_bits(pd_addr));
568 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
569 hub->vm_inv_eng0_ack + eng,
572 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
575 * add semaphore release after invalidation,
576 * write with 0 means semaphore release
578 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + eng, 0);
583 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
586 struct amdgpu_device *adev = ring->adev;
589 /* Do nothing because there's no lut register for mmhub1. */
590 if (ring->funcs->vmhub == AMDGPU_MMHUB_1)
593 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
594 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
596 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
598 amdgpu_ring_emit_wreg(ring, reg, pasid);
602 * PTE format on VEGA 10:
611 * 47:12 4k physical page base address
621 * PDE format on VEGA 10:
622 * 63:59 block fragment size
626 * 47:6 physical base address of PD or PTE
633 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
637 case AMDGPU_VM_MTYPE_DEFAULT:
638 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
639 case AMDGPU_VM_MTYPE_NC:
640 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
641 case AMDGPU_VM_MTYPE_WC:
642 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC);
643 case AMDGPU_VM_MTYPE_RW:
644 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW);
645 case AMDGPU_VM_MTYPE_CC:
646 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);
647 case AMDGPU_VM_MTYPE_UC:
648 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC);
650 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
654 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
655 uint64_t *addr, uint64_t *flags)
657 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
658 *addr = adev->vm_manager.vram_base_offset + *addr -
659 adev->gmc.vram_start;
660 BUG_ON(*addr & 0xFFFF00000000003FULL);
662 if (!adev->gmc.translate_further)
665 if (level == AMDGPU_VM_PDB1) {
666 /* Set the block fragment size */
667 if (!(*flags & AMDGPU_PDE_PTE))
668 *flags |= AMDGPU_PDE_BFS(0x9);
670 } else if (level == AMDGPU_VM_PDB0) {
671 if (*flags & AMDGPU_PDE_PTE)
672 *flags &= ~AMDGPU_PDE_PTE;
674 *flags |= AMDGPU_PTE_TF;
678 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
679 struct amdgpu_bo_va_mapping *mapping,
682 *flags &= ~AMDGPU_PTE_EXECUTABLE;
683 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
685 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
686 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK;
688 if (mapping->flags & AMDGPU_PTE_PRT) {
689 *flags |= AMDGPU_PTE_PRT;
690 *flags &= ~AMDGPU_PTE_VALID;
693 if (adev->asic_type == CHIP_ARCTURUS &&
694 !(*flags & AMDGPU_PTE_SYSTEM) &&
695 mapping->bo_va->is_xgmi)
696 *flags |= AMDGPU_PTE_SNOOPED;
699 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
700 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
701 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
702 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
703 .map_mtype = gmc_v9_0_map_mtype,
704 .get_vm_pde = gmc_v9_0_get_vm_pde,
705 .get_vm_pte = gmc_v9_0_get_vm_pte
708 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
710 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
713 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
715 switch (adev->asic_type) {
717 adev->umc.funcs = &umc_v6_0_funcs;
720 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
721 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
722 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
723 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;
724 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
725 adev->umc.funcs = &umc_v6_1_funcs;
728 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
729 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
730 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
731 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT;
732 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
733 adev->umc.funcs = &umc_v6_1_funcs;
740 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
742 switch (adev->asic_type) {
744 adev->mmhub.funcs = &mmhub_v1_0_funcs;
747 adev->mmhub.funcs = &mmhub_v9_4_funcs;
754 static int gmc_v9_0_early_init(void *handle)
756 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
758 gmc_v9_0_set_gmc_funcs(adev);
759 gmc_v9_0_set_irq_funcs(adev);
760 gmc_v9_0_set_umc_funcs(adev);
761 gmc_v9_0_set_mmhub_funcs(adev);
763 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
764 adev->gmc.shared_aperture_end =
765 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
766 adev->gmc.private_aperture_start = 0x1000000000000000ULL;
767 adev->gmc.private_aperture_end =
768 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
773 static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev)
778 * Currently there is a bug where some memory client outside
779 * of the driver writes to first 8M of VRAM on S3 resume,
780 * this overrides GART which by default gets placed in first 8M and
781 * causes VM_FAULTS once GTT is accessed.
782 * Keep the stolen memory reservation until the while this is not solved.
783 * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init
785 switch (adev->asic_type) {
798 static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev)
800 struct amdgpu_ring *ring;
801 unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] =
802 {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP,
803 GFXHUB_FREE_VM_INV_ENGS_BITMAP};
805 unsigned vmhub, inv_eng;
807 for (i = 0; i < adev->num_rings; ++i) {
808 ring = adev->rings[i];
809 vmhub = ring->funcs->vmhub;
811 inv_eng = ffs(vm_inv_engs[vmhub]);
813 dev_err(adev->dev, "no VM inv eng for ring %s\n",
818 ring->vm_inv_eng = inv_eng - 1;
819 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng);
821 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n",
822 ring->name, ring->vm_inv_eng, ring->funcs->vmhub);
828 static int gmc_v9_0_late_init(void *handle)
830 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
833 if (!gmc_v9_0_keep_stolen_memory(adev))
834 amdgpu_bo_late_init(adev);
836 r = gmc_v9_0_allocate_vm_inv_eng(adev);
839 /* Check if ecc is available */
840 if (!amdgpu_sriov_vf(adev)) {
841 switch (adev->asic_type) {
845 r = amdgpu_atomfirmware_mem_ecc_supported(adev);
847 DRM_INFO("ECC is not present.\n");
848 if (adev->df_funcs->enable_ecc_force_par_wr_rmw)
849 adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false);
851 DRM_INFO("ECC is active.\n");
854 r = amdgpu_atomfirmware_sram_ecc_supported(adev);
856 DRM_INFO("SRAM ECC is not present.\n");
858 DRM_INFO("SRAM ECC is active.\n");
866 r = amdgpu_gmc_ras_late_init(adev);
870 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
873 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
874 struct amdgpu_gmc *mc)
878 if (adev->asic_type == CHIP_ARCTURUS)
879 base = mmhub_v9_4_get_fb_location(adev);
880 else if (!amdgpu_sriov_vf(adev))
881 base = mmhub_v1_0_get_fb_location(adev);
883 /* add the xgmi offset of the physical node */
884 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
885 amdgpu_gmc_vram_location(adev, mc, base);
886 amdgpu_gmc_gart_location(adev, mc);
887 amdgpu_gmc_agp_location(adev, mc);
888 /* base offset of vram pages */
889 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
891 /* XXX: add the xgmi offset of the physical node? */
892 adev->vm_manager.vram_base_offset +=
893 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
897 * gmc_v9_0_mc_init - initialize the memory controller driver params
899 * @adev: amdgpu_device pointer
901 * Look up the amount of vram, vram width, and decide how to place
902 * vram and gart within the GPU's physical address space.
903 * Returns 0 for success.
905 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
909 /* size in MB on si */
910 adev->gmc.mc_vram_size =
911 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
912 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
914 if (!(adev->flags & AMD_IS_APU)) {
915 r = amdgpu_device_resize_fb_bar(adev);
919 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
920 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
923 if (adev->flags & AMD_IS_APU) {
924 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev);
925 adev->gmc.aper_size = adev->gmc.real_vram_size;
928 /* In case the PCI BAR is larger than the actual amount of vram */
929 adev->gmc.visible_vram_size = adev->gmc.aper_size;
930 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
931 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
933 /* set the gart size */
934 if (amdgpu_gart_size == -1) {
935 switch (adev->asic_type) {
936 case CHIP_VEGA10: /* all engines support GPUVM */
937 case CHIP_VEGA12: /* all engines support GPUVM */
941 adev->gmc.gart_size = 512ULL << 20;
943 case CHIP_RAVEN: /* DCE SG support */
945 adev->gmc.gart_size = 1024ULL << 20;
949 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
952 gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
957 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
962 WARN(1, "VEGA10 PCIE GART already initialized\n");
965 /* Initialize common gart structure */
966 r = amdgpu_gart_init(adev);
969 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
970 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) |
971 AMDGPU_PTE_EXECUTABLE;
972 return amdgpu_gart_table_vram_alloc(adev);
975 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
981 * TODO Remove once GART corruption is resolved
982 * Check related code in gmc_v9_0_sw_fini
984 if (gmc_v9_0_keep_stolen_memory(adev))
985 return 9 * 1024 * 1024;
987 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
988 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
989 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
993 switch (adev->asic_type) {
996 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
997 size = (REG_GET_FIELD(viewport,
998 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
999 REG_GET_FIELD(viewport,
1000 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1007 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
1008 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1009 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1014 /* return 0 if the pre-OS buffer uses up most of vram */
1015 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
1021 static int gmc_v9_0_sw_init(void *handle)
1023 int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
1024 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1026 gfxhub_v1_0_init(adev);
1027 if (adev->asic_type == CHIP_ARCTURUS)
1028 mmhub_v9_4_init(adev);
1030 mmhub_v1_0_init(adev);
1032 spin_lock_init(&adev->gmc.invalidate_lock);
1034 r = amdgpu_atomfirmware_get_vram_info(adev,
1035 &vram_width, &vram_type, &vram_vendor);
1036 if (amdgpu_sriov_vf(adev))
1037 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
1038 * and DF related registers is not readable, seems hardcord is the
1039 * only way to set the correct vram_width
1041 adev->gmc.vram_width = 2048;
1042 else if (amdgpu_emu_mode != 1)
1043 adev->gmc.vram_width = vram_width;
1045 if (!adev->gmc.vram_width) {
1046 int chansize, numchan;
1048 /* hbm memory channel size */
1049 if (adev->flags & AMD_IS_APU)
1054 numchan = adev->df_funcs->get_hbm_channel_number(adev);
1055 adev->gmc.vram_width = numchan * chansize;
1058 adev->gmc.vram_type = vram_type;
1059 adev->gmc.vram_vendor = vram_vendor;
1060 switch (adev->asic_type) {
1062 adev->num_vmhubs = 2;
1064 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
1065 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1067 /* vm_size is 128TB + 512GB for legacy 3-level page support */
1068 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
1069 adev->gmc.translate_further =
1070 adev->vm_manager.num_level > 1;
1077 adev->num_vmhubs = 2;
1081 * To fulfill 4-level page support,
1082 * vm size is 256TB (48bit), maximum size of Vega10,
1083 * block size 512 (9bit)
1085 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */
1086 if (amdgpu_sriov_vf(adev))
1087 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47);
1089 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1092 adev->num_vmhubs = 3;
1094 /* Keep the vm size same with Vega20 */
1095 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1101 /* This interrupt is VMC page fault.*/
1102 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
1103 &adev->gmc.vm_fault);
1107 if (adev->asic_type == CHIP_ARCTURUS) {
1108 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT,
1109 &adev->gmc.vm_fault);
1114 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
1115 &adev->gmc.vm_fault);
1120 /* interrupt sent to DF. */
1121 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
1122 &adev->gmc.ecc_irq);
1126 /* Set the internal MC address mask
1127 * This is the max address of the GPU's
1128 * internal address space.
1130 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
1132 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
1134 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
1137 adev->need_swiotlb = drm_need_swiotlb(44);
1139 if (adev->gmc.xgmi.supported) {
1140 r = gfxhub_v1_1_get_xgmi_info(adev);
1145 r = gmc_v9_0_mc_init(adev);
1149 adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev);
1151 /* Memory manager */
1152 r = amdgpu_bo_init(adev);
1156 r = gmc_v9_0_gart_init(adev);
1162 * VMID 0 is reserved for System
1163 * amdgpu graphics/compute will use VMIDs 1-7
1164 * amdkfd will use VMIDs 8-15
1166 adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
1167 adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
1168 adev->vm_manager.id_mgr[AMDGPU_MMHUB_1].num_ids = AMDGPU_NUM_OF_VMIDS;
1170 amdgpu_vm_manager_init(adev);
1175 static int gmc_v9_0_sw_fini(void *handle)
1177 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1178 void *stolen_vga_buf;
1180 amdgpu_gmc_ras_fini(adev);
1181 amdgpu_gem_force_release(adev);
1182 amdgpu_vm_manager_fini(adev);
1184 if (gmc_v9_0_keep_stolen_memory(adev))
1185 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
1187 amdgpu_gart_table_vram_free(adev);
1188 amdgpu_bo_fini(adev);
1189 amdgpu_gart_fini(adev);
1194 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
1197 switch (adev->asic_type) {
1199 if (amdgpu_sriov_vf(adev))
1203 soc15_program_register_sequence(adev,
1204 golden_settings_mmhub_1_0_0,
1205 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
1206 soc15_program_register_sequence(adev,
1207 golden_settings_athub_1_0_0,
1208 ARRAY_SIZE(golden_settings_athub_1_0_0));
1213 /* TODO for renoir */
1214 soc15_program_register_sequence(adev,
1215 golden_settings_athub_1_0_0,
1216 ARRAY_SIZE(golden_settings_athub_1_0_0));
1224 * gmc_v9_0_gart_enable - gart enable
1226 * @adev: amdgpu_device pointer
1228 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
1232 if (adev->gart.bo == NULL) {
1233 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1236 r = amdgpu_gart_table_vram_pin(adev);
1240 r = gfxhub_v1_0_gart_enable(adev);
1244 if (adev->asic_type == CHIP_ARCTURUS)
1245 r = mmhub_v9_4_gart_enable(adev);
1247 r = mmhub_v1_0_gart_enable(adev);
1251 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1252 (unsigned)(adev->gmc.gart_size >> 20),
1253 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1254 adev->gart.ready = true;
1258 static int gmc_v9_0_hw_init(void *handle)
1260 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1265 /* The sequence of these two function calls matters.*/
1266 gmc_v9_0_init_golden_registers(adev);
1268 if (adev->mode_info.num_crtc) {
1269 if (adev->asic_type != CHIP_ARCTURUS) {
1270 /* Lockout access through VGA aperture*/
1271 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
1273 /* disable VGA render */
1274 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
1278 amdgpu_device_program_register_sequence(adev,
1279 golden_settings_vega10_hdp,
1280 ARRAY_SIZE(golden_settings_vega10_hdp));
1282 switch (adev->asic_type) {
1284 /* TODO for renoir */
1285 mmhub_v1_0_update_power_gating(adev, true);
1288 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
1294 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
1296 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
1297 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
1299 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
1300 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
1302 /* After HDP is initialized, flush HDP.*/
1303 adev->nbio.funcs->hdp_flush(adev, NULL);
1305 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
1310 gfxhub_v1_0_set_fault_enable_default(adev, value);
1311 if (!amdgpu_sriov_vf(adev)) {
1312 if (adev->asic_type == CHIP_ARCTURUS)
1313 mmhub_v9_4_set_fault_enable_default(adev, value);
1315 mmhub_v1_0_set_fault_enable_default(adev, value);
1317 for (i = 0; i < adev->num_vmhubs; ++i)
1318 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
1320 if (adev->umc.funcs && adev->umc.funcs->init_registers)
1321 adev->umc.funcs->init_registers(adev);
1323 r = gmc_v9_0_gart_enable(adev);
1329 * gmc_v9_0_gart_disable - gart disable
1331 * @adev: amdgpu_device pointer
1333 * This disables all VM page table.
1335 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1337 gfxhub_v1_0_gart_disable(adev);
1338 if (adev->asic_type == CHIP_ARCTURUS)
1339 mmhub_v9_4_gart_disable(adev);
1341 mmhub_v1_0_gart_disable(adev);
1342 amdgpu_gart_table_vram_unpin(adev);
1345 static int gmc_v9_0_hw_fini(void *handle)
1347 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1349 if (amdgpu_sriov_vf(adev)) {
1350 /* full access mode, so don't touch any GMC register */
1351 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1355 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
1356 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1357 gmc_v9_0_gart_disable(adev);
1362 static int gmc_v9_0_suspend(void *handle)
1364 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1366 return gmc_v9_0_hw_fini(adev);
1369 static int gmc_v9_0_resume(void *handle)
1372 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1374 r = gmc_v9_0_hw_init(adev);
1378 amdgpu_vmid_reset_all(adev);
1383 static bool gmc_v9_0_is_idle(void *handle)
1385 /* MC is always ready in GMC v9.*/
1389 static int gmc_v9_0_wait_for_idle(void *handle)
1391 /* There is no need to wait for MC idle in GMC v9.*/
1395 static int gmc_v9_0_soft_reset(void *handle)
1397 /* XXX for emulation.*/
1401 static int gmc_v9_0_set_clockgating_state(void *handle,
1402 enum amd_clockgating_state state)
1404 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1406 if (adev->asic_type == CHIP_ARCTURUS)
1407 mmhub_v9_4_set_clockgating(adev, state);
1409 mmhub_v1_0_set_clockgating(adev, state);
1411 athub_v1_0_set_clockgating(adev, state);
1416 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1418 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1420 if (adev->asic_type == CHIP_ARCTURUS)
1421 mmhub_v9_4_get_clockgating(adev, flags);
1423 mmhub_v1_0_get_clockgating(adev, flags);
1425 athub_v1_0_get_clockgating(adev, flags);
1428 static int gmc_v9_0_set_powergating_state(void *handle,
1429 enum amd_powergating_state state)
1434 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1436 .early_init = gmc_v9_0_early_init,
1437 .late_init = gmc_v9_0_late_init,
1438 .sw_init = gmc_v9_0_sw_init,
1439 .sw_fini = gmc_v9_0_sw_fini,
1440 .hw_init = gmc_v9_0_hw_init,
1441 .hw_fini = gmc_v9_0_hw_fini,
1442 .suspend = gmc_v9_0_suspend,
1443 .resume = gmc_v9_0_resume,
1444 .is_idle = gmc_v9_0_is_idle,
1445 .wait_for_idle = gmc_v9_0_wait_for_idle,
1446 .soft_reset = gmc_v9_0_soft_reset,
1447 .set_clockgating_state = gmc_v9_0_set_clockgating_state,
1448 .set_powergating_state = gmc_v9_0_set_powergating_state,
1449 .get_clockgating_state = gmc_v9_0_get_clockgating_state,
1452 const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1454 .type = AMD_IP_BLOCK_TYPE_GMC,
1458 .funcs = &gmc_v9_0_ip_funcs,