drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drm_cache.h>
  25 #include "amdgpu.h"
  26 #include "gmc_v9_0.h"
  27 #include "amdgpu_atomfirmware.h"
  28 #include "amdgpu_gem.h"
  29
  30 #include "hdp/hdp_4_0_offset.h"
  31 #include "hdp/hdp_4_0_sh_mask.h"
  32 #include "gc/gc_9_0_sh_mask.h"
  33 #include "dce/dce_12_0_offset.h"
  34 #include "dce/dce_12_0_sh_mask.h"
  35 #include "vega10_enum.h"
  36 #include "mmhub/mmhub_1_0_offset.h"
  37 #include "athub/athub_1_0_offset.h"
  38 #include "oss/osssys_4_0_offset.h"
  39
  40 #include "soc15.h"
  41 #include "soc15_common.h"
  42 #include "umc/umc_6_0_sh_mask.h"
  43
  44 #include "gfxhub_v1_0.h"
  45 #include "mmhub_v1_0.h"
  46 #include "gfxhub_v1_1.h"
  47
  48 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
  49
  50 /* add these here since we already include dce12 headers and these are for DCN */
  51 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x055d
  52 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
  53 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
  54 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
  55 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
  56 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
  57
  58 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
  59 #define AMDGPU_NUM_OF_VMIDS                     8
  60
  61 static const u32 golden_settings_vega10_hdp[] =
  62 {
  63         0xf64, 0x0fffffff, 0x00000000,
  64         0xf65, 0x0fffffff, 0x00000000,
  65         0xf66, 0x0fffffff, 0x00000000,
  66         0xf67, 0x0fffffff, 0x00000000,
  67         0xf68, 0x0fffffff, 0x00000000,
  68         0xf6a, 0x0fffffff, 0x00000000,
  69         0xf6b, 0x0fffffff, 0x00000000,
  70         0xf6c, 0x0fffffff, 0x00000000,
  71         0xf6d, 0x0fffffff, 0x00000000,
  72         0xf6e, 0x0fffffff, 0x00000000,
  73 };
  74
  75 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
  76 {
  77         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
  78         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
  79 };
  80
  81 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
  82 {
  83         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
  84         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
  85 };
  86
  87 /* Ecc related register addresses, (BASE + reg offset) */
  88 /* Universal Memory Controller caps (may be fused). */
  89 /* UMCCH:UmcLocalCap */
  90 #define UMCLOCALCAPS_ADDR0      (0x00014306 + 0x00000000)
  91 #define UMCLOCALCAPS_ADDR1      (0x00014306 + 0x00000800)
  92 #define UMCLOCALCAPS_ADDR2      (0x00014306 + 0x00001000)
  93 #define UMCLOCALCAPS_ADDR3      (0x00014306 + 0x00001800)
  94 #define UMCLOCALCAPS_ADDR4      (0x00054306 + 0x00000000)
  95 #define UMCLOCALCAPS_ADDR5      (0x00054306 + 0x00000800)
  96 #define UMCLOCALCAPS_ADDR6      (0x00054306 + 0x00001000)
  97 #define UMCLOCALCAPS_ADDR7      (0x00054306 + 0x00001800)
  98 #define UMCLOCALCAPS_ADDR8      (0x00094306 + 0x00000000)
  99 #define UMCLOCALCAPS_ADDR9      (0x00094306 + 0x00000800)
 100 #define UMCLOCALCAPS_ADDR10     (0x00094306 + 0x00001000)
 101 #define UMCLOCALCAPS_ADDR11     (0x00094306 + 0x00001800)
 102 #define UMCLOCALCAPS_ADDR12     (0x000d4306 + 0x00000000)
 103 #define UMCLOCALCAPS_ADDR13     (0x000d4306 + 0x00000800)
 104 #define UMCLOCALCAPS_ADDR14     (0x000d4306 + 0x00001000)
 105 #define UMCLOCALCAPS_ADDR15     (0x000d4306 + 0x00001800)
 106
 107 /* Universal Memory Controller Channel config. */
 108 /* UMCCH:UMC_CONFIG */
 109 #define UMCCH_UMC_CONFIG_ADDR0  (0x00014040 + 0x00000000)
 110 #define UMCCH_UMC_CONFIG_ADDR1  (0x00014040 + 0x00000800)
 111 #define UMCCH_UMC_CONFIG_ADDR2  (0x00014040 + 0x00001000)
 112 #define UMCCH_UMC_CONFIG_ADDR3  (0x00014040 + 0x00001800)
 113 #define UMCCH_UMC_CONFIG_ADDR4  (0x00054040 + 0x00000000)
 114 #define UMCCH_UMC_CONFIG_ADDR5  (0x00054040 + 0x00000800)
 115 #define UMCCH_UMC_CONFIG_ADDR6  (0x00054040 + 0x00001000)
 116 #define UMCCH_UMC_CONFIG_ADDR7  (0x00054040 + 0x00001800)
 117 #define UMCCH_UMC_CONFIG_ADDR8  (0x00094040 + 0x00000000)
 118 #define UMCCH_UMC_CONFIG_ADDR9  (0x00094040 + 0x00000800)
 119 #define UMCCH_UMC_CONFIG_ADDR10 (0x00094040 + 0x00001000)
 120 #define UMCCH_UMC_CONFIG_ADDR11 (0x00094040 + 0x00001800)
 121 #define UMCCH_UMC_CONFIG_ADDR12 (0x000d4040 + 0x00000000)
 122 #define UMCCH_UMC_CONFIG_ADDR13 (0x000d4040 + 0x00000800)
 123 #define UMCCH_UMC_CONFIG_ADDR14 (0x000d4040 + 0x00001000)
 124 #define UMCCH_UMC_CONFIG_ADDR15 (0x000d4040 + 0x00001800)
 125
 126 /* Universal Memory Controller Channel Ecc config. */
 127 /* UMCCH:EccCtrl */
 128 #define UMCCH_ECCCTRL_ADDR0     (0x00014053 + 0x00000000)
 129 #define UMCCH_ECCCTRL_ADDR1     (0x00014053 + 0x00000800)
 130 #define UMCCH_ECCCTRL_ADDR2     (0x00014053 + 0x00001000)
 131 #define UMCCH_ECCCTRL_ADDR3     (0x00014053 + 0x00001800)
 132 #define UMCCH_ECCCTRL_ADDR4     (0x00054053 + 0x00000000)
 133 #define UMCCH_ECCCTRL_ADDR5     (0x00054053 + 0x00000800)
 134 #define UMCCH_ECCCTRL_ADDR6     (0x00054053 + 0x00001000)
 135 #define UMCCH_ECCCTRL_ADDR7     (0x00054053 + 0x00001800)
 136 #define UMCCH_ECCCTRL_ADDR8     (0x00094053 + 0x00000000)
 137 #define UMCCH_ECCCTRL_ADDR9     (0x00094053 + 0x00000800)
 138 #define UMCCH_ECCCTRL_ADDR10    (0x00094053 + 0x00001000)
 139 #define UMCCH_ECCCTRL_ADDR11    (0x00094053 + 0x00001800)
 140 #define UMCCH_ECCCTRL_ADDR12    (0x000d4053 + 0x00000000)
 141 #define UMCCH_ECCCTRL_ADDR13    (0x000d4053 + 0x00000800)
 142 #define UMCCH_ECCCTRL_ADDR14    (0x000d4053 + 0x00001000)
 143 #define UMCCH_ECCCTRL_ADDR15    (0x000d4053 + 0x00001800)
 144
 145 static const uint32_t ecc_umclocalcap_addrs[] = {
 146         UMCLOCALCAPS_ADDR0,
 147         UMCLOCALCAPS_ADDR1,
 148         UMCLOCALCAPS_ADDR2,
 149         UMCLOCALCAPS_ADDR3,
 150         UMCLOCALCAPS_ADDR4,
 151         UMCLOCALCAPS_ADDR5,
 152         UMCLOCALCAPS_ADDR6,
 153         UMCLOCALCAPS_ADDR7,
 154         UMCLOCALCAPS_ADDR8,
 155         UMCLOCALCAPS_ADDR9,
 156         UMCLOCALCAPS_ADDR10,
 157         UMCLOCALCAPS_ADDR11,
 158         UMCLOCALCAPS_ADDR12,
 159         UMCLOCALCAPS_ADDR13,
 160         UMCLOCALCAPS_ADDR14,
 161         UMCLOCALCAPS_ADDR15,
 162 };
 163
 164 static const uint32_t ecc_umcch_umc_config_addrs[] = {
 165         UMCCH_UMC_CONFIG_ADDR0,
 166         UMCCH_UMC_CONFIG_ADDR1,
 167         UMCCH_UMC_CONFIG_ADDR2,
 168         UMCCH_UMC_CONFIG_ADDR3,
 169         UMCCH_UMC_CONFIG_ADDR4,
 170         UMCCH_UMC_CONFIG_ADDR5,
 171         UMCCH_UMC_CONFIG_ADDR6,
 172         UMCCH_UMC_CONFIG_ADDR7,
 173         UMCCH_UMC_CONFIG_ADDR8,
 174         UMCCH_UMC_CONFIG_ADDR9,
 175         UMCCH_UMC_CONFIG_ADDR10,
 176         UMCCH_UMC_CONFIG_ADDR11,
 177         UMCCH_UMC_CONFIG_ADDR12,
 178         UMCCH_UMC_CONFIG_ADDR13,
 179         UMCCH_UMC_CONFIG_ADDR14,
 180         UMCCH_UMC_CONFIG_ADDR15,
 181 };
 182
 183 static const uint32_t ecc_umcch_eccctrl_addrs[] = {
 184         UMCCH_ECCCTRL_ADDR0,
 185         UMCCH_ECCCTRL_ADDR1,
 186         UMCCH_ECCCTRL_ADDR2,
 187         UMCCH_ECCCTRL_ADDR3,
 188         UMCCH_ECCCTRL_ADDR4,
 189         UMCCH_ECCCTRL_ADDR5,
 190         UMCCH_ECCCTRL_ADDR6,
 191         UMCCH_ECCCTRL_ADDR7,
 192         UMCCH_ECCCTRL_ADDR8,
 193         UMCCH_ECCCTRL_ADDR9,
 194         UMCCH_ECCCTRL_ADDR10,
 195         UMCCH_ECCCTRL_ADDR11,
 196         UMCCH_ECCCTRL_ADDR12,
 197         UMCCH_ECCCTRL_ADDR13,
 198         UMCCH_ECCCTRL_ADDR14,
 199         UMCCH_ECCCTRL_ADDR15,
 200 };
 201
 202 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 203                                         struct amdgpu_irq_src *src,
 204                                         unsigned type,
 205                                         enum amdgpu_interrupt_state state)
 206 {
 207         struct amdgpu_vmhub *hub;
 208         u32 tmp, reg, bits, i, j;
 209
 210         bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 211                 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 212                 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 213                 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 214                 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 215                 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 216                 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 217
 218         switch (state) {
 219         case AMDGPU_IRQ_STATE_DISABLE:
 220                 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
 221                         hub = &adev->vmhub[j];
 222                         for (i = 0; i < 16; i++) {
 223                                 reg = hub->vm_context0_cntl + i;
 224                                 tmp = RREG32(reg);
 225                                 tmp &= ~bits;
 226                                 WREG32(reg, tmp);
 227                         }
 228                 }
 229                 break;
 230         case AMDGPU_IRQ_STATE_ENABLE:
 231                 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
 232                         hub = &adev->vmhub[j];
 233                         for (i = 0; i < 16; i++) {
 234                                 reg = hub->vm_context0_cntl + i;
 235                                 tmp = RREG32(reg);
 236                                 tmp |= bits;
 237                                 WREG32(reg, tmp);
 238                         }
 239                 }
 240         default:
 241                 break;
 242         }
 243
 244         return 0;
 245 }
 246
 247 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
 248                                 struct amdgpu_irq_src *source,
 249                                 struct amdgpu_iv_entry *entry)
 250 {
 251         struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
 252         uint32_t status = 0;
 253         u64 addr;
 254
 255         addr = (u64)entry->src_data[0] << 12;
 256         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 257
 258         if (!amdgpu_sriov_vf(adev)) {
 259                 status = RREG32(hub->vm_l2_pro_fault_status);
 260                 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 261         }
 262
 263         if (printk_ratelimit()) {
 264                 struct amdgpu_task_info task_info = { 0 };
 265
 266                 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 267
 268                 dev_err(adev->dev,
 269                         "[%s] VMC page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d)\n",
 270                         entry->vmid_src ? "mmhub" : "gfxhub",
 271                         entry->src_id, entry->ring_id, entry->vmid,
 272                         entry->pasid, task_info.process_name, task_info.tgid,
 273                         task_info.task_name, task_info.pid);
 274                 dev_err(adev->dev, "  in page starting at address 0x%016llx from %d\n",
 275                         addr, entry->client_id);
 276                 if (!amdgpu_sriov_vf(adev))
 277                         dev_err(adev->dev,
 278                                 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 279                                 status);
 280         }
 281
 282         return 0;
 283 }
 284
 285 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
 286         .set = gmc_v9_0_vm_fault_interrupt_state,
 287         .process = gmc_v9_0_process_interrupt,
 288 };
 289
 290 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
 291 {
 292         adev->gmc.vm_fault.num_types = 1;
 293         adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
 294 }
 295
 296 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
 297                                         uint32_t flush_type)
 298 {
 299         u32 req = 0;
 300
 301         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 302                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
 303         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
 304         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
 305         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
 306         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
 307         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
 308         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
 309         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 310                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
 311
 312         return req;
 313 }
 314
 315 static signed long  amdgpu_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
 316                                                   uint32_t reg0, uint32_t reg1,
 317                                                   uint32_t ref, uint32_t mask)
 318 {
 319         signed long r, cnt = 0;
 320         unsigned long flags;
 321         uint32_t seq;
 322         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 323         struct amdgpu_ring *ring = &kiq->ring;
 324
 325         spin_lock_irqsave(&kiq->ring_lock, flags);
 326
 327         amdgpu_ring_alloc(ring, 32);
 328         amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1,
 329                                             ref, mask);
 330         amdgpu_fence_emit_polling(ring, &seq);
 331         amdgpu_ring_commit(ring);
 332         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 333
 334         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 335
 336         /* don't wait anymore for IRQ context */
 337         if (r < 1 && in_interrupt())
 338                 goto failed_kiq;
 339
 340         might_sleep();
 341
 342         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
 343                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
 344                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 345         }
 346
 347         if (cnt > MAX_KIQ_REG_TRY)
 348                 goto failed_kiq;
 349
 350         return 0;
 351
 352 failed_kiq:
 353         pr_err("failed to invalidate tlb with kiq\n");
 354         return r;
 355 }
 356
 357 /*
 358  * GART
 359  * VMID 0 is the physical GPU addresses as used by the kernel.
 360  * VMIDs 1-15 are used for userspace clients and are handled
 361  * by the amdgpu vm/hsa code.
 362  */
 363
 364 /**
 365  * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
 366  *
 367  * @adev: amdgpu_device pointer
 368  * @vmid: vm instance to flush
 369  * @flush_type: the flush type
 370  *
 371  * Flush the TLB for the requested page table using certain type.
 372  */
 373 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev,
 374                                 uint32_t vmid, uint32_t flush_type)
 375 {
 376         const unsigned eng = 17;
 377         unsigned i, j;
 378         int r;
 379
 380         for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
 381                 struct amdgpu_vmhub *hub = &adev->vmhub[i];
 382                 u32 tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type);
 383
 384                 if (adev->gfx.kiq.ring.sched.ready &&
 385                     (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
 386                     !adev->in_gpu_reset) {
 387                         r = amdgpu_kiq_reg_write_reg_wait(adev, hub->vm_inv_eng0_req + eng,
 388                                 hub->vm_inv_eng0_ack + eng, tmp, 1 << vmid);
 389                         if (!r)
 390                                 continue;
 391                 }
 392
 393                 spin_lock(&adev->gmc.invalidate_lock);
 394
 395                 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
 396
 397                 /* Busy wait for ACK.*/
 398                 for (j = 0; j < 100; j++) {
 399                         tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
 400                         tmp &= 1 << vmid;
 401                         if (tmp)
 402                                 break;
 403                         cpu_relax();
 404                 }
 405                 if (j < 100) {
 406                         spin_unlock(&adev->gmc.invalidate_lock);
 407                         continue;
 408                 }
 409
 410                 /* Wait for ACK with a delay.*/
 411                 for (j = 0; j < adev->usec_timeout; j++) {
 412                         tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
 413                         tmp &= 1 << vmid;
 414                         if (tmp)
 415                                 break;
 416                         udelay(1);
 417                 }
 418                 if (j < adev->usec_timeout) {
 419                         spin_unlock(&adev->gmc.invalidate_lock);
 420                         continue;
 421                 }
 422                 spin_unlock(&adev->gmc.invalidate_lock);
 423                 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
 424         }
 425 }
 426
 427 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 428                                             unsigned vmid, uint64_t pd_addr)
 429 {
 430         struct amdgpu_device *adev = ring->adev;
 431         struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
 432         uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
 433         unsigned eng = ring->vm_inv_eng;
 434
 435         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
 436                               lower_32_bits(pd_addr));
 437
 438         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
 439                               upper_32_bits(pd_addr));
 440
 441         amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
 442                                             hub->vm_inv_eng0_ack + eng,
 443                                             req, 1 << vmid);
 444
 445         return pd_addr;
 446 }
 447
 448 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 449                                         unsigned pasid)
 450 {
 451         struct amdgpu_device *adev = ring->adev;
 452         uint32_t reg;
 453
 454         if (ring->funcs->vmhub == AMDGPU_GFXHUB)
 455                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
 456         else
 457                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
 458
 459         amdgpu_ring_emit_wreg(ring, reg, pasid);
 460 }
 461
 462 /**
 463  * gmc_v9_0_set_pte_pde - update the page tables using MMIO
 464  *
 465  * @adev: amdgpu_device pointer
 466  * @cpu_pt_addr: cpu address of the page table
 467  * @gpu_page_idx: entry in the page table to update
 468  * @addr: dst addr to write into pte/pde
 469  * @flags: access flags
 470  *
 471  * Update the page tables using the CPU.
 472  */
 473 static int gmc_v9_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
 474                                 uint32_t gpu_page_idx, uint64_t addr,
 475                                 uint64_t flags)
 476 {
 477         void __iomem *ptr = (void *)cpu_pt_addr;
 478         uint64_t value;
 479
 480         /*
 481          * PTE format on VEGA 10:
 482          * 63:59 reserved
 483          * 58:57 mtype
 484          * 56 F
 485          * 55 L
 486          * 54 P
 487          * 53 SW
 488          * 52 T
 489          * 50:48 reserved
 490          * 47:12 4k physical page base address
 491          * 11:7 fragment
 492          * 6 write
 493          * 5 read
 494          * 4 exe
 495          * 3 Z
 496          * 2 snooped
 497          * 1 system
 498          * 0 valid
 499          *
 500          * PDE format on VEGA 10:
 501          * 63:59 block fragment size
 502          * 58:55 reserved
 503          * 54 P
 504          * 53:48 reserved
 505          * 47:6 physical base address of PD or PTE
 506          * 5:3 reserved
 507          * 2 C
 508          * 1 system
 509          * 0 valid
 510          */
 511
 512         /*
 513          * The following is for PTE only. GART does not have PDEs.
 514         */
 515         value = addr & 0x0000FFFFFFFFF000ULL;
 516         value |= flags;
 517         writeq(value, ptr + (gpu_page_idx * 8));
 518         return 0;
 519 }
 520
 521 static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
 522                                                 uint32_t flags)
 523
 524 {
 525         uint64_t pte_flag = 0;
 526
 527         if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
 528                 pte_flag |= AMDGPU_PTE_EXECUTABLE;
 529         if (flags & AMDGPU_VM_PAGE_READABLE)
 530                 pte_flag |= AMDGPU_PTE_READABLE;
 531         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 532                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 533
 534         switch (flags & AMDGPU_VM_MTYPE_MASK) {
 535         case AMDGPU_VM_MTYPE_DEFAULT:
 536                 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
 537                 break;
 538         case AMDGPU_VM_MTYPE_NC:
 539                 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
 540                 break;
 541         case AMDGPU_VM_MTYPE_WC:
 542                 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC);
 543                 break;
 544         case AMDGPU_VM_MTYPE_CC:
 545                 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC);
 546                 break;
 547         case AMDGPU_VM_MTYPE_UC:
 548                 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC);
 549                 break;
 550         default:
 551                 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
 552                 break;
 553         }
 554
 555         if (flags & AMDGPU_VM_PAGE_PRT)
 556                 pte_flag |= AMDGPU_PTE_PRT;
 557
 558         return pte_flag;
 559 }
 560
 561 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
 562                                 uint64_t *addr, uint64_t *flags)
 563 {
 564         if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
 565                 *addr = adev->vm_manager.vram_base_offset + *addr -
 566                         adev->gmc.vram_start;
 567         BUG_ON(*addr & 0xFFFF00000000003FULL);
 568
 569         if (!adev->gmc.translate_further)
 570                 return;
 571
 572         if (level == AMDGPU_VM_PDB1) {
 573                 /* Set the block fragment size */
 574                 if (!(*flags & AMDGPU_PDE_PTE))
 575                         *flags |= AMDGPU_PDE_BFS(0x9);
 576
 577         } else if (level == AMDGPU_VM_PDB0) {
 578                 if (*flags & AMDGPU_PDE_PTE)
 579                         *flags &= ~AMDGPU_PDE_PTE;
 580                 else
 581                         *flags |= AMDGPU_PTE_TF;
 582         }
 583 }
 584
 585 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
 586         .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
 587         .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
 588         .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
 589         .set_pte_pde = gmc_v9_0_set_pte_pde,
 590         .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags,
 591         .get_vm_pde = gmc_v9_0_get_vm_pde
 592 };
 593
 594 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
 595 {
 596         adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
 597 }
 598
 599 static int gmc_v9_0_early_init(void *handle)
 600 {
 601         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 602
 603         gmc_v9_0_set_gmc_funcs(adev);
 604         gmc_v9_0_set_irq_funcs(adev);
 605
 606         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
 607         adev->gmc.shared_aperture_end =
 608                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
 609         adev->gmc.private_aperture_start = 0x1000000000000000ULL;
 610         adev->gmc.private_aperture_end =
 611                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
 612
 613         return 0;
 614 }
 615
 616 static int gmc_v9_0_ecc_available(struct amdgpu_device *adev)
 617 {
 618         uint32_t reg_val;
 619         uint32_t reg_addr;
 620         uint32_t field_val;
 621         size_t i;
 622         uint32_t fv2;
 623         size_t lost_sheep;
 624
 625         DRM_DEBUG("ecc: gmc_v9_0_ecc_available()\n");
 626
 627         lost_sheep = 0;
 628         for (i = 0; i < ARRAY_SIZE(ecc_umclocalcap_addrs); ++i) {
 629                 reg_addr = ecc_umclocalcap_addrs[i];
 630                 DRM_DEBUG("ecc: "
 631                           "UMCCH_UmcLocalCap[%zu]: reg_addr: 0x%08x\n",
 632                           i, reg_addr);
 633                 reg_val = RREG32(reg_addr);
 634                 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UmcLocalCap,
 635                                           EccDis);
 636                 DRM_DEBUG("ecc: "
 637                           "reg_val: 0x%08x, "
 638                           "EccDis: 0x%08x, ",
 639                           reg_val, field_val);
 640                 if (field_val) {
 641                         DRM_ERROR("ecc: UmcLocalCap:EccDis is set.\n");
 642                         ++lost_sheep;
 643                 }
 644         }
 645
 646         for (i = 0; i < ARRAY_SIZE(ecc_umcch_umc_config_addrs); ++i) {
 647                 reg_addr = ecc_umcch_umc_config_addrs[i];
 648                 DRM_DEBUG("ecc: "
 649                           "UMCCH0_0_UMC_CONFIG[%zu]: reg_addr: 0x%08x",
 650                           i, reg_addr);
 651                 reg_val = RREG32(reg_addr);
 652                 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UMC_CONFIG,
 653                                           DramReady);
 654                 DRM_DEBUG("ecc: "
 655                           "reg_val: 0x%08x, "
 656                           "DramReady: 0x%08x\n",
 657                           reg_val, field_val);
 658
 659                 if (!field_val) {
 660                         DRM_ERROR("ecc: UMC_CONFIG:DramReady is not set.\n");
 661                         ++lost_sheep;
 662                 }
 663         }
 664
 665         for (i = 0; i < ARRAY_SIZE(ecc_umcch_eccctrl_addrs); ++i) {
 666                 reg_addr = ecc_umcch_eccctrl_addrs[i];
 667                 DRM_DEBUG("ecc: "
 668                           "UMCCH_EccCtrl[%zu]: reg_addr: 0x%08x, ",
 669                           i, reg_addr);
 670                 reg_val = RREG32(reg_addr);
 671                 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
 672                                           WrEccEn);
 673                 fv2 = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
 674                                     RdEccEn);
 675                 DRM_DEBUG("ecc: "
 676                           "reg_val: 0x%08x, "
 677                           "WrEccEn: 0x%08x, "
 678                           "RdEccEn: 0x%08x\n",
 679                           reg_val, field_val, fv2);
 680
 681                 if (!field_val) {
 682                         DRM_DEBUG("ecc: WrEccEn is not set\n");
 683                         ++lost_sheep;
 684                 }
 685                 if (!fv2) {
 686                         DRM_DEBUG("ecc: RdEccEn is not set\n");
 687                         ++lost_sheep;
 688                 }
 689         }
 690
 691         DRM_DEBUG("ecc: lost_sheep: %zu\n", lost_sheep);
 692         return lost_sheep == 0;
 693 }
 694
 695 static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev)
 696 {
 697
 698         /*
 699          * TODO:
 700          * Currently there is a bug where some memory client outside
 701          * of the driver writes to first 8M of VRAM on S3 resume,
 702          * this overrides GART which by default gets placed in first 8M and
 703          * causes VM_FAULTS once GTT is accessed.
 704          * Keep the stolen memory reservation until the while this is not solved.
 705          * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init
 706          */
 707         switch (adev->asic_type) {
 708         case CHIP_VEGA10:
 709                 return true;
 710         case CHIP_RAVEN:
 711         case CHIP_VEGA12:
 712         case CHIP_VEGA20:
 713         default:
 714                 return false;
 715         }
 716 }
 717
 718 static int gmc_v9_0_late_init(void *handle)
 719 {
 720         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 721         /*
 722          * The latest engine allocation on gfx9 is:
 723          * Engine 0, 1: idle
 724          * Engine 2, 3: firmware
 725          * Engine 4~13: amdgpu ring, subject to change when ring number changes
 726          * Engine 14~15: idle
 727          * Engine 16: kfd tlb invalidation
 728          * Engine 17: Gart flushes
 729          */
 730         unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
 731         unsigned i;
 732         int r;
 733
 734         if (!gmc_v9_0_keep_stolen_memory(adev))
 735                 amdgpu_bo_late_init(adev);
 736
 737         for(i = 0; i < adev->num_rings; ++i) {
 738                 struct amdgpu_ring *ring = adev->rings[i];
 739                 unsigned vmhub = ring->funcs->vmhub;
 740
 741                 ring->vm_inv_eng = vm_inv_eng[vmhub]++;
 742                 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n",
 743                          ring->name, ring->vm_inv_eng, ring->funcs->vmhub);
 744         }
 745
 746         /* Engine 16 is used for KFD and 17 for GART flushes */
 747         for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
 748                 BUG_ON(vm_inv_eng[i] > 16);
 749
 750         if (adev->asic_type == CHIP_VEGA10 && !amdgpu_sriov_vf(adev)) {
 751                 r = gmc_v9_0_ecc_available(adev);
 752                 if (r == 1) {
 753                         DRM_INFO("ECC is active.\n");
 754                 } else if (r == 0) {
 755                         DRM_INFO("ECC is not present.\n");
 756                         adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false);
 757                 } else {
 758                         DRM_ERROR("gmc_v9_0_ecc_available() failed. r: %d\n", r);
 759                         return r;
 760                 }
 761         }
 762
 763         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 764 }
 765
 766 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
 767                                         struct amdgpu_gmc *mc)
 768 {
 769         u64 base = 0;
 770         if (!amdgpu_sriov_vf(adev))
 771                 base = mmhub_v1_0_get_fb_location(adev);
 772         /* add the xgmi offset of the physical node */
 773         base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
 774         amdgpu_gmc_vram_location(adev, &adev->gmc, base);
 775         amdgpu_gmc_gart_location(adev, mc);
 776         if (!amdgpu_sriov_vf(adev))
 777                 amdgpu_gmc_agp_location(adev, mc);
 778         /* base offset of vram pages */
 779         adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
 780
 781         /* XXX: add the xgmi offset of the physical node? */
 782         adev->vm_manager.vram_base_offset +=
 783                 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
 784 }
 785
 786 /**
 787  * gmc_v9_0_mc_init - initialize the memory controller driver params
 788  *
 789  * @adev: amdgpu_device pointer
 790  *
 791  * Look up the amount of vram, vram width, and decide how to place
 792  * vram and gart within the GPU's physical address space.
 793  * Returns 0 for success.
 794  */
 795 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
 796 {
 797         int chansize, numchan;
 798         int r;
 799
 800         if (amdgpu_emu_mode != 1)
 801                 adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
 802         if (!adev->gmc.vram_width) {
 803                 /* hbm memory channel size */
 804                 if (adev->flags & AMD_IS_APU)
 805                         chansize = 64;
 806                 else
 807                         chansize = 128;
 808
 809                 numchan = adev->df_funcs->get_hbm_channel_number(adev);
 810                 adev->gmc.vram_width = numchan * chansize;
 811         }
 812
 813         /* size in MB on si */
 814         adev->gmc.mc_vram_size =
 815                 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
 816         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
 817
 818         if (!(adev->flags & AMD_IS_APU)) {
 819                 r = amdgpu_device_resize_fb_bar(adev);
 820                 if (r)
 821                         return r;
 822         }
 823         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 824         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 825
 826 #ifdef CONFIG_X86_64
 827         if (adev->flags & AMD_IS_APU) {
 828                 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev);
 829                 adev->gmc.aper_size = adev->gmc.real_vram_size;
 830         }
 831 #endif
 832         /* In case the PCI BAR is larger than the actual amount of vram */
 833         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 834         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
 835                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 836
 837         /* set the gart size */
 838         if (amdgpu_gart_size == -1) {
 839                 switch (adev->asic_type) {
 840                 case CHIP_VEGA10:  /* all engines support GPUVM */
 841                 case CHIP_VEGA12:  /* all engines support GPUVM */
 842                 case CHIP_VEGA20:
 843                 default:
 844                         adev->gmc.gart_size = 512ULL << 20;
 845                         break;
 846                 case CHIP_RAVEN:   /* DCE SG support */
 847                         adev->gmc.gart_size = 1024ULL << 20;
 848                         break;
 849                 }
 850         } else {
 851                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 852         }
 853
 854         gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
 855
 856         return 0;
 857 }
 858
 859 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
 860 {
 861         int r;
 862
 863         if (adev->gart.bo) {
 864                 WARN(1, "VEGA10 PCIE GART already initialized\n");
 865                 return 0;
 866         }
 867         /* Initialize common gart structure */
 868         r = amdgpu_gart_init(adev);
 869         if (r)
 870                 return r;
 871         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 872         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) |
 873                                  AMDGPU_PTE_EXECUTABLE;
 874         return amdgpu_gart_table_vram_alloc(adev);
 875 }
 876
 877 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
 878 {
 879         u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
 880         unsigned size;
 881
 882         /*
 883          * TODO Remove once GART corruption is resolved
 884          * Check related code in gmc_v9_0_sw_fini
 885          * */
 886         if (gmc_v9_0_keep_stolen_memory(adev))
 887                 return 9 * 1024 * 1024;
 888
 889         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
 890                 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
 891         } else {
 892                 u32 viewport;
 893
 894                 switch (adev->asic_type) {
 895                 case CHIP_RAVEN:
 896                         viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
 897                         size = (REG_GET_FIELD(viewport,
 898                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
 899                                 REG_GET_FIELD(viewport,
 900                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
 901                                 4);
 902                         break;
 903                 case CHIP_VEGA10:
 904                 case CHIP_VEGA12:
 905                 case CHIP_VEGA20:
 906                 default:
 907                         viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
 908                         size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
 909                                 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
 910                                 4);
 911                         break;
 912                 }
 913         }
 914         /* return 0 if the pre-OS buffer uses up most of vram */
 915         if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
 916                 return 0;
 917
 918         return size;
 919 }
 920
 921 static int gmc_v9_0_sw_init(void *handle)
 922 {
 923         int r;
 924         int dma_bits;
 925         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 926
 927         gfxhub_v1_0_init(adev);
 928         mmhub_v1_0_init(adev);
 929
 930         spin_lock_init(&adev->gmc.invalidate_lock);
 931
 932         adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);
 933         switch (adev->asic_type) {
 934         case CHIP_RAVEN:
 935                 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
 936                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
 937                 } else {
 938                         /* vm_size is 128TB + 512GB for legacy 3-level page support */
 939                         amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
 940                         adev->gmc.translate_further =
 941                                 adev->vm_manager.num_level > 1;
 942                 }
 943                 break;
 944         case CHIP_VEGA10:
 945         case CHIP_VEGA12:
 946         case CHIP_VEGA20:
 947                 /*
 948                  * To fulfill 4-level page support,
 949                  * vm size is 256TB (48bit), maximum size of Vega10,
 950                  * block size 512 (9bit)
 951                  */
 952                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
 953                 break;
 954         default:
 955                 break;
 956         }
 957
 958         /* This interrupt is VMC page fault.*/
 959         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
 960                                 &adev->gmc.vm_fault);
 961         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
 962                                 &adev->gmc.vm_fault);
 963
 964         if (r)
 965                 return r;
 966
 967         /* Set the internal MC address mask
 968          * This is the max address of the GPU's
 969          * internal address space.
 970          */
 971         adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
 972
 973         /* set DMA mask + need_dma32 flags.
 974          * PCIE - can handle 44-bits.
 975          * IGP - can handle 44-bits
 976          * PCI - dma32 for legacy pci gart, 44 bits on vega10
 977          */
 978         adev->need_dma32 = false;
 979         dma_bits = adev->need_dma32 ? 32 : 44;
 980         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 981         if (r) {
 982                 adev->need_dma32 = true;
 983                 dma_bits = 32;
 984                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
 985         }
 986         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 987         if (r) {
 988                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 989                 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
 990         }
 991         adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
 992
 993         if (adev->asic_type == CHIP_VEGA20) {
 994                 r = gfxhub_v1_1_get_xgmi_info(adev);
 995                 if (r)
 996                         return r;
 997         }
 998
 999         r = gmc_v9_0_mc_init(adev);
1000         if (r)
1001                 return r;
1002
1003         adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev);
1004
1005         /* Memory manager */
1006         r = amdgpu_bo_init(adev);
1007         if (r)
1008                 return r;
1009
1010         r = gmc_v9_0_gart_init(adev);
1011         if (r)
1012                 return r;
1013
1014         /*
1015          * number of VMs
1016          * VMID 0 is reserved for System
1017          * amdgpu graphics/compute will use VMIDs 1-7
1018          * amdkfd will use VMIDs 8-15
1019          */
1020         adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
1021         adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
1022
1023         amdgpu_vm_manager_init(adev);
1024
1025         return 0;
1026 }
1027
1028 static int gmc_v9_0_sw_fini(void *handle)
1029 {
1030         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1031
1032         amdgpu_gem_force_release(adev);
1033         amdgpu_vm_manager_fini(adev);
1034
1035         if (gmc_v9_0_keep_stolen_memory(adev))
1036                 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
1037
1038         amdgpu_gart_table_vram_free(adev);
1039         amdgpu_bo_fini(adev);
1040         amdgpu_gart_fini(adev);
1041
1042         return 0;
1043 }
1044
1045 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
1046 {
1047
1048         switch (adev->asic_type) {
1049         case CHIP_VEGA10:
1050         case CHIP_VEGA20:
1051                 soc15_program_register_sequence(adev,
1052                                                 golden_settings_mmhub_1_0_0,
1053                                                 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
1054                 soc15_program_register_sequence(adev,
1055                                                 golden_settings_athub_1_0_0,
1056                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1057                 break;
1058         case CHIP_VEGA12:
1059                 break;
1060         case CHIP_RAVEN:
1061                 soc15_program_register_sequence(adev,
1062                                                 golden_settings_athub_1_0_0,
1063                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1064                 break;
1065         default:
1066                 break;
1067         }
1068 }
1069
1070 /**
1071  * gmc_v9_0_gart_enable - gart enable
1072  *
1073  * @adev: amdgpu_device pointer
1074  */
1075 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
1076 {
1077         int r;
1078         bool value;
1079         u32 tmp;
1080
1081         amdgpu_device_program_register_sequence(adev,
1082                                                 golden_settings_vega10_hdp,
1083                                                 ARRAY_SIZE(golden_settings_vega10_hdp));
1084
1085         if (adev->gart.bo == NULL) {
1086                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1087                 return -EINVAL;
1088         }
1089         r = amdgpu_gart_table_vram_pin(adev);
1090         if (r)
1091                 return r;
1092
1093         switch (adev->asic_type) {
1094         case CHIP_RAVEN:
1095                 mmhub_v1_0_update_power_gating(adev, true);
1096                 break;
1097         default:
1098                 break;
1099         }
1100
1101         r = gfxhub_v1_0_gart_enable(adev);
1102         if (r)
1103                 return r;
1104
1105         r = mmhub_v1_0_gart_enable(adev);
1106         if (r)
1107                 return r;
1108
1109         WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
1110
1111         tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
1112         WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
1113
1114         /* After HDP is initialized, flush HDP.*/
1115         adev->nbio_funcs->hdp_flush(adev, NULL);
1116
1117         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
1118                 value = false;
1119         else
1120                 value = true;
1121
1122         gfxhub_v1_0_set_fault_enable_default(adev, value);
1123         mmhub_v1_0_set_fault_enable_default(adev, value);
1124         gmc_v9_0_flush_gpu_tlb(adev, 0, 0);
1125
1126         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1127                  (unsigned)(adev->gmc.gart_size >> 20),
1128                  (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1129         adev->gart.ready = true;
1130         return 0;
1131 }
1132
1133 static int gmc_v9_0_hw_init(void *handle)
1134 {
1135         int r;
1136         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1137
1138         /* The sequence of these two function calls matters.*/
1139         gmc_v9_0_init_golden_registers(adev);
1140
1141         if (adev->mode_info.num_crtc) {
1142                 /* Lockout access through VGA aperture*/
1143                 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
1144
1145                 /* disable VGA render */
1146                 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
1147         }
1148
1149         r = gmc_v9_0_gart_enable(adev);
1150
1151         return r;
1152 }
1153
1154 /**
1155  * gmc_v9_0_gart_disable - gart disable
1156  *
1157  * @adev: amdgpu_device pointer
1158  *
1159  * This disables all VM page table.
1160  */
1161 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1162 {
1163         gfxhub_v1_0_gart_disable(adev);
1164         mmhub_v1_0_gart_disable(adev);
1165         amdgpu_gart_table_vram_unpin(adev);
1166 }
1167
1168 static int gmc_v9_0_hw_fini(void *handle)
1169 {
1170         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1171
1172         if (amdgpu_sriov_vf(adev)) {
1173                 /* full access mode, so don't touch any GMC register */
1174                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1175                 return 0;
1176         }
1177
1178         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1179         gmc_v9_0_gart_disable(adev);
1180
1181         return 0;
1182 }
1183
1184 static int gmc_v9_0_suspend(void *handle)
1185 {
1186         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1187
1188         return gmc_v9_0_hw_fini(adev);
1189 }
1190
1191 static int gmc_v9_0_resume(void *handle)
1192 {
1193         int r;
1194         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1195
1196         r = gmc_v9_0_hw_init(adev);
1197         if (r)
1198                 return r;
1199
1200         amdgpu_vmid_reset_all(adev);
1201
1202         return 0;
1203 }
1204
1205 static bool gmc_v9_0_is_idle(void *handle)
1206 {
1207         /* MC is always ready in GMC v9.*/
1208         return true;
1209 }
1210
1211 static int gmc_v9_0_wait_for_idle(void *handle)
1212 {
1213         /* There is no need to wait for MC idle in GMC v9.*/
1214         return 0;
1215 }
1216
1217 static int gmc_v9_0_soft_reset(void *handle)
1218 {
1219         /* XXX for emulation.*/
1220         return 0;
1221 }
1222
1223 static int gmc_v9_0_set_clockgating_state(void *handle,
1224                                         enum amd_clockgating_state state)
1225 {
1226         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1227
1228         return mmhub_v1_0_set_clockgating(adev, state);
1229 }
1230
1231 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1232 {
1233         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1234
1235         mmhub_v1_0_get_clockgating(adev, flags);
1236 }
1237
1238 static int gmc_v9_0_set_powergating_state(void *handle,
1239                                         enum amd_powergating_state state)
1240 {
1241         return 0;
1242 }
1243
1244 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1245         .name = "gmc_v9_0",
1246         .early_init = gmc_v9_0_early_init,
1247         .late_init = gmc_v9_0_late_init,
1248         .sw_init = gmc_v9_0_sw_init,
1249         .sw_fini = gmc_v9_0_sw_fini,
1250         .hw_init = gmc_v9_0_hw_init,
1251         .hw_fini = gmc_v9_0_hw_fini,
1252         .suspend = gmc_v9_0_suspend,
1253         .resume = gmc_v9_0_resume,
1254         .is_idle = gmc_v9_0_is_idle,
1255         .wait_for_idle = gmc_v9_0_wait_for_idle,
1256         .soft_reset = gmc_v9_0_soft_reset,
1257         .set_clockgating_state = gmc_v9_0_set_clockgating_state,
1258         .set_powergating_state = gmc_v9_0_set_powergating_state,
1259         .get_clockgating_state = gmc_v9_0_get_clockgating_state,
1260 };
1261
1262 const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1263 {
1264         .type = AMD_IP_BLOCK_TYPE_GMC,
1265         .major = 9,
1266         .minor = 0,
1267         .rev = 0,
1268         .funcs = &gmc_v9_0_ip_funcs,
1269 };