drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/pci.h>
  26
  27 #include <drm/drm_cache.h>
  28
  29 #include "amdgpu.h"
  30 #include "gmc_v9_0.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "amdgpu_gem.h"
  33
  34 #include "hdp/hdp_4_0_offset.h"
  35 #include "hdp/hdp_4_0_sh_mask.h"
  36 #include "gc/gc_9_0_sh_mask.h"
  37 #include "dce/dce_12_0_offset.h"
  38 #include "dce/dce_12_0_sh_mask.h"
  39 #include "vega10_enum.h"
  40 #include "mmhub/mmhub_1_0_offset.h"
  41 #include "athub/athub_1_0_offset.h"
  42 #include "oss/osssys_4_0_offset.h"
  43
  44 #include "soc15.h"
  45 #include "soc15_common.h"
  46 #include "umc/umc_6_0_sh_mask.h"
  47
  48 #include "gfxhub_v1_0.h"
  49 #include "mmhub_v1_0.h"
  50 #include "athub_v1_0.h"
  51 #include "gfxhub_v1_1.h"
  52 #include "mmhub_v9_4.h"
  53 #include "umc_v6_1.h"
  54 #include "umc_v6_0.h"
  55
  56 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
  57
  58 #include "amdgpu_ras.h"
  59 #include "amdgpu_xgmi.h"
  60
  61 /* add these here since we already include dce12 headers and these are for DCN */
  62 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x055d
  63 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
  64 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
  65 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
  66 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
  67 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
  68
  69 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
  70 #define AMDGPU_NUM_OF_VMIDS                     8
  71
  72 static const u32 golden_settings_vega10_hdp[] =
  73 {
  74         0xf64, 0x0fffffff, 0x00000000,
  75         0xf65, 0x0fffffff, 0x00000000,
  76         0xf66, 0x0fffffff, 0x00000000,
  77         0xf67, 0x0fffffff, 0x00000000,
  78         0xf68, 0x0fffffff, 0x00000000,
  79         0xf6a, 0x0fffffff, 0x00000000,
  80         0xf6b, 0x0fffffff, 0x00000000,
  81         0xf6c, 0x0fffffff, 0x00000000,
  82         0xf6d, 0x0fffffff, 0x00000000,
  83         0xf6e, 0x0fffffff, 0x00000000,
  84 };
  85
  86 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
  87 {
  88         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
  89         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
  90 };
  91
  92 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
  93 {
  94         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
  95         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
  96 };
  97
  98 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = {
  99         (0x000143c0 + 0x00000000),
 100         (0x000143c0 + 0x00000800),
 101         (0x000143c0 + 0x00001000),
 102         (0x000143c0 + 0x00001800),
 103         (0x000543c0 + 0x00000000),
 104         (0x000543c0 + 0x00000800),
 105         (0x000543c0 + 0x00001000),
 106         (0x000543c0 + 0x00001800),
 107         (0x000943c0 + 0x00000000),
 108         (0x000943c0 + 0x00000800),
 109         (0x000943c0 + 0x00001000),
 110         (0x000943c0 + 0x00001800),
 111         (0x000d43c0 + 0x00000000),
 112         (0x000d43c0 + 0x00000800),
 113         (0x000d43c0 + 0x00001000),
 114         (0x000d43c0 + 0x00001800),
 115         (0x001143c0 + 0x00000000),
 116         (0x001143c0 + 0x00000800),
 117         (0x001143c0 + 0x00001000),
 118         (0x001143c0 + 0x00001800),
 119         (0x001543c0 + 0x00000000),
 120         (0x001543c0 + 0x00000800),
 121         (0x001543c0 + 0x00001000),
 122         (0x001543c0 + 0x00001800),
 123         (0x001943c0 + 0x00000000),
 124         (0x001943c0 + 0x00000800),
 125         (0x001943c0 + 0x00001000),
 126         (0x001943c0 + 0x00001800),
 127         (0x001d43c0 + 0x00000000),
 128         (0x001d43c0 + 0x00000800),
 129         (0x001d43c0 + 0x00001000),
 130         (0x001d43c0 + 0x00001800),
 131 };
 132
 133 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {
 134         (0x000143e0 + 0x00000000),
 135         (0x000143e0 + 0x00000800),
 136         (0x000143e0 + 0x00001000),
 137         (0x000143e0 + 0x00001800),
 138         (0x000543e0 + 0x00000000),
 139         (0x000543e0 + 0x00000800),
 140         (0x000543e0 + 0x00001000),
 141         (0x000543e0 + 0x00001800),
 142         (0x000943e0 + 0x00000000),
 143         (0x000943e0 + 0x00000800),
 144         (0x000943e0 + 0x00001000),
 145         (0x000943e0 + 0x00001800),
 146         (0x000d43e0 + 0x00000000),
 147         (0x000d43e0 + 0x00000800),
 148         (0x000d43e0 + 0x00001000),
 149         (0x000d43e0 + 0x00001800),
 150         (0x001143e0 + 0x00000000),
 151         (0x001143e0 + 0x00000800),
 152         (0x001143e0 + 0x00001000),
 153         (0x001143e0 + 0x00001800),
 154         (0x001543e0 + 0x00000000),
 155         (0x001543e0 + 0x00000800),
 156         (0x001543e0 + 0x00001000),
 157         (0x001543e0 + 0x00001800),
 158         (0x001943e0 + 0x00000000),
 159         (0x001943e0 + 0x00000800),
 160         (0x001943e0 + 0x00001000),
 161         (0x001943e0 + 0x00001800),
 162         (0x001d43e0 + 0x00000000),
 163         (0x001d43e0 + 0x00000800),
 164         (0x001d43e0 + 0x00001000),
 165         (0x001d43e0 + 0x00001800),
 166 };
 167
 168 static const uint32_t ecc_umc_mcumc_status_addrs[] = {
 169         (0x000143c2 + 0x00000000),
 170         (0x000143c2 + 0x00000800),
 171         (0x000143c2 + 0x00001000),
 172         (0x000143c2 + 0x00001800),
 173         (0x000543c2 + 0x00000000),
 174         (0x000543c2 + 0x00000800),
 175         (0x000543c2 + 0x00001000),
 176         (0x000543c2 + 0x00001800),
 177         (0x000943c2 + 0x00000000),
 178         (0x000943c2 + 0x00000800),
 179         (0x000943c2 + 0x00001000),
 180         (0x000943c2 + 0x00001800),
 181         (0x000d43c2 + 0x00000000),
 182         (0x000d43c2 + 0x00000800),
 183         (0x000d43c2 + 0x00001000),
 184         (0x000d43c2 + 0x00001800),
 185         (0x001143c2 + 0x00000000),
 186         (0x001143c2 + 0x00000800),
 187         (0x001143c2 + 0x00001000),
 188         (0x001143c2 + 0x00001800),
 189         (0x001543c2 + 0x00000000),
 190         (0x001543c2 + 0x00000800),
 191         (0x001543c2 + 0x00001000),
 192         (0x001543c2 + 0x00001800),
 193         (0x001943c2 + 0x00000000),
 194         (0x001943c2 + 0x00000800),
 195         (0x001943c2 + 0x00001000),
 196         (0x001943c2 + 0x00001800),
 197         (0x001d43c2 + 0x00000000),
 198         (0x001d43c2 + 0x00000800),
 199         (0x001d43c2 + 0x00001000),
 200         (0x001d43c2 + 0x00001800),
 201 };
 202
 203 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
 204                 struct amdgpu_irq_src *src,
 205                 unsigned type,
 206                 enum amdgpu_interrupt_state state)
 207 {
 208         u32 bits, i, tmp, reg;
 209
 210         /* Devices newer then VEGA10/12 shall have these programming
 211              sequences performed by PSP BL */
 212         if (adev->asic_type >= CHIP_VEGA20)
 213                 return 0;
 214
 215         bits = 0x7f;
 216
 217         switch (state) {
 218         case AMDGPU_IRQ_STATE_DISABLE:
 219                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 220                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 221                         tmp = RREG32(reg);
 222                         tmp &= ~bits;
 223                         WREG32(reg, tmp);
 224                 }
 225                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 226                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 227                         tmp = RREG32(reg);
 228                         tmp &= ~bits;
 229                         WREG32(reg, tmp);
 230                 }
 231                 break;
 232         case AMDGPU_IRQ_STATE_ENABLE:
 233                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 234                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 235                         tmp = RREG32(reg);
 236                         tmp |= bits;
 237                         WREG32(reg, tmp);
 238                 }
 239                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 240                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 241                         tmp = RREG32(reg);
 242                         tmp |= bits;
 243                         WREG32(reg, tmp);
 244                 }
 245                 break;
 246         default:
 247                 break;
 248         }
 249
 250         return 0;
 251 }
 252
 253 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 254                                         struct amdgpu_irq_src *src,
 255                                         unsigned type,
 256                                         enum amdgpu_interrupt_state state)
 257 {
 258         struct amdgpu_vmhub *hub;
 259         u32 tmp, reg, bits, i, j;
 260
 261         bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 262                 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 263                 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 264                 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 265                 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 266                 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 267                 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 268
 269         switch (state) {
 270         case AMDGPU_IRQ_STATE_DISABLE:
 271                 for (j = 0; j < adev->num_vmhubs; j++) {
 272                         hub = &adev->vmhub[j];
 273                         for (i = 0; i < 16; i++) {
 274                                 reg = hub->vm_context0_cntl + i;
 275                                 tmp = RREG32(reg);
 276                                 tmp &= ~bits;
 277                                 WREG32(reg, tmp);
 278                         }
 279                 }
 280                 break;
 281         case AMDGPU_IRQ_STATE_ENABLE:
 282                 for (j = 0; j < adev->num_vmhubs; j++) {
 283                         hub = &adev->vmhub[j];
 284                         for (i = 0; i < 16; i++) {
 285                                 reg = hub->vm_context0_cntl + i;
 286                                 tmp = RREG32(reg);
 287                                 tmp |= bits;
 288                                 WREG32(reg, tmp);
 289                         }
 290                 }
 291         default:
 292                 break;
 293         }
 294
 295         return 0;
 296 }
 297
 298 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
 299                                 struct amdgpu_irq_src *source,
 300                                 struct amdgpu_iv_entry *entry)
 301 {
 302         struct amdgpu_vmhub *hub;
 303         bool retry_fault = !!(entry->src_data[1] & 0x80);
 304         uint32_t status = 0;
 305         u64 addr;
 306         char hub_name[10];
 307
 308         addr = (u64)entry->src_data[0] << 12;
 309         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 310
 311         if (retry_fault && amdgpu_gmc_filter_faults(adev, addr, entry->pasid,
 312                                                     entry->timestamp))
 313                 return 1; /* This also prevents sending it to KFD */
 314
 315         if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
 316                 snprintf(hub_name, sizeof(hub_name), "mmhub0");
 317                 hub = &adev->vmhub[AMDGPU_MMHUB_0];
 318         } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
 319                 snprintf(hub_name, sizeof(hub_name), "mmhub1");
 320                 hub = &adev->vmhub[AMDGPU_MMHUB_1];
 321         } else {
 322                 snprintf(hub_name, sizeof(hub_name), "gfxhub0");
 323                 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 324         }
 325
 326         /* If it's the first fault for this address, process it normally */
 327         if (retry_fault && !in_interrupt() &&
 328             amdgpu_vm_handle_fault(adev, entry->pasid, addr))
 329                 return 1; /* This also prevents sending it to KFD */
 330
 331         if (!amdgpu_sriov_vf(adev)) {
 332                 /*
 333                  * Issue a dummy read to wait for the status register to
 334                  * be updated to avoid reading an incorrect value due to
 335                  * the new fast GRBM interface.
 336                  */
 337                 if (entry->vmid_src == AMDGPU_GFXHUB_0)
 338                         RREG32(hub->vm_l2_pro_fault_status);
 339
 340                 status = RREG32(hub->vm_l2_pro_fault_status);
 341                 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 342         }
 343
 344         if (printk_ratelimit()) {
 345                 struct amdgpu_task_info task_info;
 346
 347                 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
 348                 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 349
 350                 dev_err(adev->dev,
 351                         "[%s] %s page fault (src_id:%u ring:%u vmid:%u "
 352                         "pasid:%u, for process %s pid %d thread %s pid %d)\n",
 353                         hub_name, retry_fault ? "retry" : "no-retry",
 354                         entry->src_id, entry->ring_id, entry->vmid,
 355                         entry->pasid, task_info.process_name, task_info.tgid,
 356                         task_info.task_name, task_info.pid);
 357                 dev_err(adev->dev, "  in page starting at address 0x%016llx from client %d\n",
 358                         addr, entry->client_id);
 359                 if (!amdgpu_sriov_vf(adev)) {
 360                         dev_err(adev->dev,
 361                                 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 362                                 status);
 363                         dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
 364                                 REG_GET_FIELD(status,
 365                                 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
 366                         dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
 367                                 REG_GET_FIELD(status,
 368                                 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
 369                         dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
 370                                 REG_GET_FIELD(status,
 371                                 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
 372                         dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
 373                                 REG_GET_FIELD(status,
 374                                 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
 375                         dev_err(adev->dev, "\t RW: 0x%lx\n",
 376                                 REG_GET_FIELD(status,
 377                                 VM_L2_PROTECTION_FAULT_STATUS, RW));
 378
 379                 }
 380         }
 381
 382         return 0;
 383 }
 384
 385 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
 386         .set = gmc_v9_0_vm_fault_interrupt_state,
 387         .process = gmc_v9_0_process_interrupt,
 388 };
 389
 390
 391 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = {
 392         .set = gmc_v9_0_ecc_interrupt_state,
 393         .process = amdgpu_umc_process_ecc_irq,
 394 };
 395
 396 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
 397 {
 398         adev->gmc.vm_fault.num_types = 1;
 399         adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
 400
 401         if (!amdgpu_sriov_vf(adev)) {
 402                 adev->gmc.ecc_irq.num_types = 1;
 403                 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;
 404         }
 405 }
 406
 407 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
 408                                         uint32_t flush_type)
 409 {
 410         u32 req = 0;
 411
 412         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 413                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
 414         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
 415         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
 416         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
 417         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
 418         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
 419         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
 420         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 421                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
 422
 423         return req;
 424 }
 425
 426 /**
 427  * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
 428  *
 429  * @adev: amdgpu_device pointer
 430  * @vmhub: vmhub type
 431  *
 432  */
 433 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
 434                                        uint32_t vmhub)
 435 {
 436         return ((vmhub == AMDGPU_MMHUB_0 ||
 437                  vmhub == AMDGPU_MMHUB_1) &&
 438                 (!amdgpu_sriov_vf(adev)) &&
 439                 (!(adev->asic_type == CHIP_RAVEN &&
 440                    adev->rev_id < 0x8 &&
 441                    adev->pdev->device == 0x15d8)));
 442 }
 443
 444 /*
 445  * GART
 446  * VMID 0 is the physical GPU addresses as used by the kernel.
 447  * VMIDs 1-15 are used for userspace clients and are handled
 448  * by the amdgpu vm/hsa code.
 449  */
 450
 451 /**
 452  * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
 453  *
 454  * @adev: amdgpu_device pointer
 455  * @vmid: vm instance to flush
 456  * @flush_type: the flush type
 457  *
 458  * Flush the TLB for the requested page table using certain type.
 459  */
 460 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 461                                         uint32_t vmhub, uint32_t flush_type)
 462 {
 463         bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
 464         const unsigned eng = 17;
 465         u32 j, tmp;
 466         struct amdgpu_vmhub *hub;
 467
 468         BUG_ON(vmhub >= adev->num_vmhubs);
 469
 470         hub = &adev->vmhub[vmhub];
 471         tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type);
 472
 473         /* This is necessary for a HW workaround under SRIOV as well
 474          * as GFXOFF under bare metal
 475          */
 476         if (adev->gfx.kiq.ring.sched.ready &&
 477                         (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
 478                         !adev->in_gpu_reset) {
 479                 uint32_t req = hub->vm_inv_eng0_req + eng;
 480                 uint32_t ack = hub->vm_inv_eng0_ack + eng;
 481
 482                 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp,
 483                                 1 << vmid);
 484                 return;
 485         }
 486
 487         spin_lock(&adev->gmc.invalidate_lock);
 488
 489         /*
 490          * It may lose gpuvm invalidate acknowldege state across power-gating
 491          * off cycle, add semaphore acquire before invalidation and semaphore
 492          * release after invalidation to avoid entering power gated state
 493          * to WA the Issue
 494          */
 495
 496         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 497         if (use_semaphore) {
 498                 for (j = 0; j < adev->usec_timeout; j++) {
 499                         /* a read return value of 1 means semaphore acuqire */
 500                         tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
 501                         if (tmp & 0x1)
 502                                 break;
 503                         udelay(1);
 504                 }
 505
 506                 if (j >= adev->usec_timeout)
 507                         DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
 508         }
 509
 510         WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
 511
 512         /*
 513          * Issue a dummy read to wait for the ACK register to be cleared
 514          * to avoid a false ACK due to the new fast GRBM interface.
 515          */
 516         if (vmhub == AMDGPU_GFXHUB_0)
 517                 RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng);
 518
 519         for (j = 0; j < adev->usec_timeout; j++) {
 520                 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
 521                 if (tmp & (1 << vmid))
 522                         break;
 523                 udelay(1);
 524         }
 525
 526         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 527         if (use_semaphore)
 528                 /*
 529                  * add semaphore release after invalidation,
 530                  * write with 0 means semaphore release
 531                  */
 532                 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0);
 533
 534         spin_unlock(&adev->gmc.invalidate_lock);
 535
 536         if (j < adev->usec_timeout)
 537                 return;
 538
 539         DRM_ERROR("Timeout waiting for VM flush ACK!\n");
 540 }
 541
 542 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 543                                             unsigned vmid, uint64_t pd_addr)
 544 {
 545         bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
 546         struct amdgpu_device *adev = ring->adev;
 547         struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
 548         uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
 549         unsigned eng = ring->vm_inv_eng;
 550
 551         /*
 552          * It may lose gpuvm invalidate acknowldege state across power-gating
 553          * off cycle, add semaphore acquire before invalidation and semaphore
 554          * release after invalidation to avoid entering power gated state
 555          * to WA the Issue
 556          */
 557
 558         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 559         if (use_semaphore)
 560                 /* a read return value of 1 means semaphore acuqire */
 561                 amdgpu_ring_emit_reg_wait(ring,
 562                                           hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
 563
 564         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
 565                               lower_32_bits(pd_addr));
 566
 567         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
 568                               upper_32_bits(pd_addr));
 569
 570         amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
 571                                             hub->vm_inv_eng0_ack + eng,
 572                                             req, 1 << vmid);
 573
 574         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 575         if (use_semaphore)
 576                 /*
 577                  * add semaphore release after invalidation,
 578                  * write with 0 means semaphore release
 579                  */
 580                 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + eng, 0);
 581
 582         return pd_addr;
 583 }
 584
 585 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 586                                         unsigned pasid)
 587 {
 588         struct amdgpu_device *adev = ring->adev;
 589         uint32_t reg;
 590
 591         /* Do nothing because there's no lut register for mmhub1. */
 592         if (ring->funcs->vmhub == AMDGPU_MMHUB_1)
 593                 return;
 594
 595         if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
 596                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
 597         else
 598                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
 599
 600         amdgpu_ring_emit_wreg(ring, reg, pasid);
 601 }
 602
 603 /*
 604  * PTE format on VEGA 10:
 605  * 63:59 reserved
 606  * 58:57 mtype
 607  * 56 F
 608  * 55 L
 609  * 54 P
 610  * 53 SW
 611  * 52 T
 612  * 50:48 reserved
 613  * 47:12 4k physical page base address
 614  * 11:7 fragment
 615  * 6 write
 616  * 5 read
 617  * 4 exe
 618  * 3 Z
 619  * 2 snooped
 620  * 1 system
 621  * 0 valid
 622  *
 623  * PDE format on VEGA 10:
 624  * 63:59 block fragment size
 625  * 58:55 reserved
 626  * 54 P
 627  * 53:48 reserved
 628  * 47:6 physical base address of PD or PTE
 629  * 5:3 reserved
 630  * 2 C
 631  * 1 system
 632  * 0 valid
 633  */
 634
 635 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
 636
 637 {
 638         switch (flags) {
 639         case AMDGPU_VM_MTYPE_DEFAULT:
 640                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
 641         case AMDGPU_VM_MTYPE_NC:
 642                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
 643         case AMDGPU_VM_MTYPE_WC:
 644                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC);
 645         case AMDGPU_VM_MTYPE_RW:
 646                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW);
 647         case AMDGPU_VM_MTYPE_CC:
 648                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);
 649         case AMDGPU_VM_MTYPE_UC:
 650                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC);
 651         default:
 652                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
 653         }
 654 }
 655
 656 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
 657                                 uint64_t *addr, uint64_t *flags)
 658 {
 659         if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
 660                 *addr = adev->vm_manager.vram_base_offset + *addr -
 661                         adev->gmc.vram_start;
 662         BUG_ON(*addr & 0xFFFF00000000003FULL);
 663
 664         if (!adev->gmc.translate_further)
 665                 return;
 666
 667         if (level == AMDGPU_VM_PDB1) {
 668                 /* Set the block fragment size */
 669                 if (!(*flags & AMDGPU_PDE_PTE))
 670                         *flags |= AMDGPU_PDE_BFS(0x9);
 671
 672         } else if (level == AMDGPU_VM_PDB0) {
 673                 if (*flags & AMDGPU_PDE_PTE)
 674                         *flags &= ~AMDGPU_PDE_PTE;
 675                 else
 676                         *flags |= AMDGPU_PTE_TF;
 677         }
 678 }
 679
 680 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
 681                                 struct amdgpu_bo_va_mapping *mapping,
 682                                 uint64_t *flags)
 683 {
 684         *flags &= ~AMDGPU_PTE_EXECUTABLE;
 685         *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
 686
 687         *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
 688         *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK;
 689
 690         if (mapping->flags & AMDGPU_PTE_PRT) {
 691                 *flags |= AMDGPU_PTE_PRT;
 692                 *flags &= ~AMDGPU_PTE_VALID;
 693         }
 694
 695         if (adev->asic_type == CHIP_ARCTURUS &&
 696             !(*flags & AMDGPU_PTE_SYSTEM) &&
 697             mapping->bo_va->is_xgmi)
 698                 *flags |= AMDGPU_PTE_SNOOPED;
 699 }
 700
 701 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
 702         .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
 703         .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
 704         .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
 705         .map_mtype = gmc_v9_0_map_mtype,
 706         .get_vm_pde = gmc_v9_0_get_vm_pde,
 707         .get_vm_pte = gmc_v9_0_get_vm_pte
 708 };
 709
 710 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
 711 {
 712         adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
 713 }
 714
 715 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
 716 {
 717         switch (adev->asic_type) {
 718         case CHIP_VEGA10:
 719                 adev->umc.funcs = &umc_v6_0_funcs;
 720                 break;
 721         case CHIP_VEGA20:
 722                 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
 723                 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
 724                 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
 725                 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;
 726                 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
 727                 adev->umc.funcs = &umc_v6_1_funcs;
 728                 break;
 729         case CHIP_ARCTURUS:
 730                 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
 731                 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
 732                 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
 733                 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT;
 734                 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
 735                 adev->umc.funcs = &umc_v6_1_funcs;
 736                 break;
 737         default:
 738                 break;
 739         }
 740 }
 741
 742 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
 743 {
 744         switch (adev->asic_type) {
 745         case CHIP_VEGA20:
 746                 adev->mmhub.funcs = &mmhub_v1_0_funcs;
 747                 break;
 748         case CHIP_ARCTURUS:
 749                 adev->mmhub.funcs = &mmhub_v9_4_funcs;
 750                 break;
 751         default:
 752                 break;
 753         }
 754 }
 755
 756 static int gmc_v9_0_early_init(void *handle)
 757 {
 758         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 759
 760         gmc_v9_0_set_gmc_funcs(adev);
 761         gmc_v9_0_set_irq_funcs(adev);
 762         gmc_v9_0_set_umc_funcs(adev);
 763         gmc_v9_0_set_mmhub_funcs(adev);
 764
 765         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
 766         adev->gmc.shared_aperture_end =
 767                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
 768         adev->gmc.private_aperture_start = 0x1000000000000000ULL;
 769         adev->gmc.private_aperture_end =
 770                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
 771
 772         return 0;
 773 }
 774
 775 static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev)
 776 {
 777
 778         /*
 779          * TODO:
 780          * Currently there is a bug where some memory client outside
 781          * of the driver writes to first 8M of VRAM on S3 resume,
 782          * this overrides GART which by default gets placed in first 8M and
 783          * causes VM_FAULTS once GTT is accessed.
 784          * Keep the stolen memory reservation until the while this is not solved.
 785          * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init
 786          */
 787         switch (adev->asic_type) {
 788         case CHIP_VEGA10:
 789         case CHIP_RAVEN:
 790         case CHIP_ARCTURUS:
 791         case CHIP_RENOIR:
 792                 return true;
 793         case CHIP_VEGA12:
 794         case CHIP_VEGA20:
 795         default:
 796                 return false;
 797         }
 798 }
 799
 800 static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev)
 801 {
 802         struct amdgpu_ring *ring;
 803         unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] =
 804                 {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP,
 805                 GFXHUB_FREE_VM_INV_ENGS_BITMAP};
 806         unsigned i;
 807         unsigned vmhub, inv_eng;
 808
 809         for (i = 0; i < adev->num_rings; ++i) {
 810                 ring = adev->rings[i];
 811                 vmhub = ring->funcs->vmhub;
 812
 813                 inv_eng = ffs(vm_inv_engs[vmhub]);
 814                 if (!inv_eng) {
 815                         dev_err(adev->dev, "no VM inv eng for ring %s\n",
 816                                 ring->name);
 817                         return -EINVAL;
 818                 }
 819
 820                 ring->vm_inv_eng = inv_eng - 1;
 821                 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng);
 822
 823                 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n",
 824                          ring->name, ring->vm_inv_eng, ring->funcs->vmhub);
 825         }
 826
 827         return 0;
 828 }
 829
 830 static int gmc_v9_0_late_init(void *handle)
 831 {
 832         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 833         int r;
 834
 835         if (!gmc_v9_0_keep_stolen_memory(adev))
 836                 amdgpu_bo_late_init(adev);
 837
 838         r = gmc_v9_0_allocate_vm_inv_eng(adev);
 839         if (r)
 840                 return r;
 841         /* Check if ecc is available */
 842         if (!amdgpu_sriov_vf(adev)) {
 843                 switch (adev->asic_type) {
 844                 case CHIP_VEGA10:
 845                 case CHIP_VEGA20:
 846                 case CHIP_ARCTURUS:
 847                         r = amdgpu_atomfirmware_mem_ecc_supported(adev);
 848                         if (!r) {
 849                                 DRM_INFO("ECC is not present.\n");
 850                                 if (adev->df_funcs->enable_ecc_force_par_wr_rmw)
 851                                         adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false);
 852                         } else {
 853                                 DRM_INFO("ECC is active.\n");
 854                         }
 855
 856                         r = amdgpu_atomfirmware_sram_ecc_supported(adev);
 857                         if (!r) {
 858                                 DRM_INFO("SRAM ECC is not present.\n");
 859                         } else {
 860                                 DRM_INFO("SRAM ECC is active.\n");
 861                         }
 862                         break;
 863                 default:
 864                         break;
 865                 }
 866         }
 867
 868         r = amdgpu_gmc_ras_late_init(adev);
 869         if (r)
 870                 return r;
 871
 872         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 873 }
 874
 875 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
 876                                         struct amdgpu_gmc *mc)
 877 {
 878         u64 base = 0;
 879
 880         if (adev->asic_type == CHIP_ARCTURUS)
 881                 base = mmhub_v9_4_get_fb_location(adev);
 882         else if (!amdgpu_sriov_vf(adev))
 883                 base = mmhub_v1_0_get_fb_location(adev);
 884
 885         /* add the xgmi offset of the physical node */
 886         base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
 887         amdgpu_gmc_vram_location(adev, mc, base);
 888         amdgpu_gmc_gart_location(adev, mc);
 889         amdgpu_gmc_agp_location(adev, mc);
 890         /* base offset of vram pages */
 891         adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
 892
 893         /* XXX: add the xgmi offset of the physical node? */
 894         adev->vm_manager.vram_base_offset +=
 895                 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
 896 }
 897
 898 /**
 899  * gmc_v9_0_mc_init - initialize the memory controller driver params
 900  *
 901  * @adev: amdgpu_device pointer
 902  *
 903  * Look up the amount of vram, vram width, and decide how to place
 904  * vram and gart within the GPU's physical address space.
 905  * Returns 0 for success.
 906  */
 907 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
 908 {
 909         int r;
 910
 911         /* size in MB on si */
 912         adev->gmc.mc_vram_size =
 913                 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
 914         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
 915
 916         if (!(adev->flags & AMD_IS_APU)) {
 917                 r = amdgpu_device_resize_fb_bar(adev);
 918                 if (r)
 919                         return r;
 920         }
 921         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 922         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 923
 924 #ifdef CONFIG_X86_64
 925         if (adev->flags & AMD_IS_APU) {
 926                 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev);
 927                 adev->gmc.aper_size = adev->gmc.real_vram_size;
 928         }
 929 #endif
 930         /* In case the PCI BAR is larger than the actual amount of vram */
 931         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 932         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
 933                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 934
 935         /* set the gart size */
 936         if (amdgpu_gart_size == -1) {
 937                 switch (adev->asic_type) {
 938                 case CHIP_VEGA10:  /* all engines support GPUVM */
 939                 case CHIP_VEGA12:  /* all engines support GPUVM */
 940                 case CHIP_VEGA20:
 941                 case CHIP_ARCTURUS:
 942                 default:
 943                         adev->gmc.gart_size = 512ULL << 20;
 944                         break;
 945                 case CHIP_RAVEN:   /* DCE SG support */
 946                 case CHIP_RENOIR:
 947                         adev->gmc.gart_size = 1024ULL << 20;
 948                         break;
 949                 }
 950         } else {
 951                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 952         }
 953
 954         gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
 955
 956         return 0;
 957 }
 958
 959 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
 960 {
 961         int r;
 962
 963         if (adev->gart.bo) {
 964                 WARN(1, "VEGA10 PCIE GART already initialized\n");
 965                 return 0;
 966         }
 967         /* Initialize common gart structure */
 968         r = amdgpu_gart_init(adev);
 969         if (r)
 970                 return r;
 971         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 972         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) |
 973                                  AMDGPU_PTE_EXECUTABLE;
 974         return amdgpu_gart_table_vram_alloc(adev);
 975 }
 976
 977 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
 978 {
 979         u32 d1vga_control;
 980         unsigned size;
 981
 982         /*
 983          * TODO Remove once GART corruption is resolved
 984          * Check related code in gmc_v9_0_sw_fini
 985          * */
 986         if (gmc_v9_0_keep_stolen_memory(adev))
 987                 return 9 * 1024 * 1024;
 988
 989         d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
 990         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
 991                 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
 992         } else {
 993                 u32 viewport;
 994
 995                 switch (adev->asic_type) {
 996                 case CHIP_RAVEN:
 997                 case CHIP_RENOIR:
 998                         viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
 999                         size = (REG_GET_FIELD(viewport,
1000                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1001                                 REG_GET_FIELD(viewport,
1002                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1003                                 4);
1004                         break;
1005                 case CHIP_VEGA10:
1006                 case CHIP_VEGA12:
1007                 case CHIP_VEGA20:
1008                 default:
1009                         viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
1010                         size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1011                                 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1012                                 4);
1013                         break;
1014                 }
1015         }
1016         /* return 0 if the pre-OS buffer uses up most of vram */
1017         if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
1018                 return 0;
1019
1020         return size;
1021 }
1022
1023 static int gmc_v9_0_sw_init(void *handle)
1024 {
1025         int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
1026         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1027
1028         gfxhub_v1_0_init(adev);
1029         if (adev->asic_type == CHIP_ARCTURUS)
1030                 mmhub_v9_4_init(adev);
1031         else
1032                 mmhub_v1_0_init(adev);
1033
1034         spin_lock_init(&adev->gmc.invalidate_lock);
1035
1036         r = amdgpu_atomfirmware_get_vram_info(adev,
1037                 &vram_width, &vram_type, &vram_vendor);
1038         if (amdgpu_sriov_vf(adev))
1039                 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
1040                  * and DF related registers is not readable, seems hardcord is the
1041                  * only way to set the correct vram_width
1042                  */
1043                 adev->gmc.vram_width = 2048;
1044         else if (amdgpu_emu_mode != 1)
1045                 adev->gmc.vram_width = vram_width;
1046
1047         if (!adev->gmc.vram_width) {
1048                 int chansize, numchan;
1049
1050                 /* hbm memory channel size */
1051                 if (adev->flags & AMD_IS_APU)
1052                         chansize = 64;
1053                 else
1054                         chansize = 128;
1055
1056                 numchan = adev->df_funcs->get_hbm_channel_number(adev);
1057                 adev->gmc.vram_width = numchan * chansize;
1058         }
1059
1060         adev->gmc.vram_type = vram_type;
1061         adev->gmc.vram_vendor = vram_vendor;
1062         switch (adev->asic_type) {
1063         case CHIP_RAVEN:
1064                 adev->num_vmhubs = 2;
1065
1066                 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
1067                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1068                 } else {
1069                         /* vm_size is 128TB + 512GB for legacy 3-level page support */
1070                         amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
1071                         adev->gmc.translate_further =
1072                                 adev->vm_manager.num_level > 1;
1073                 }
1074                 break;
1075         case CHIP_VEGA10:
1076         case CHIP_VEGA12:
1077         case CHIP_VEGA20:
1078         case CHIP_RENOIR:
1079                 adev->num_vmhubs = 2;
1080
1081
1082                 /*
1083                  * To fulfill 4-level page support,
1084                  * vm size is 256TB (48bit), maximum size of Vega10,
1085                  * block size 512 (9bit)
1086                  */
1087                 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */
1088                 if (amdgpu_sriov_vf(adev))
1089                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47);
1090                 else
1091                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1092                 break;
1093         case CHIP_ARCTURUS:
1094                 adev->num_vmhubs = 3;
1095
1096                 /* Keep the vm size same with Vega20 */
1097                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1098                 break;
1099         default:
1100                 break;
1101         }
1102
1103         /* This interrupt is VMC page fault.*/
1104         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
1105                                 &adev->gmc.vm_fault);
1106         if (r)
1107                 return r;
1108
1109         if (adev->asic_type == CHIP_ARCTURUS) {
1110                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT,
1111                                         &adev->gmc.vm_fault);
1112                 if (r)
1113                         return r;
1114         }
1115
1116         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
1117                                 &adev->gmc.vm_fault);
1118
1119         if (r)
1120                 return r;
1121
1122         if (!amdgpu_sriov_vf(adev)) {
1123                 /* interrupt sent to DF. */
1124                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
1125                                       &adev->gmc.ecc_irq);
1126                 if (r)
1127                         return r;
1128         }
1129
1130         /* Set the internal MC address mask
1131          * This is the max address of the GPU's
1132          * internal address space.
1133          */
1134         adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
1135
1136         r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
1137         if (r) {
1138                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
1139                 return r;
1140         }
1141         adev->need_swiotlb = drm_need_swiotlb(44);
1142
1143         if (adev->gmc.xgmi.supported) {
1144                 r = gfxhub_v1_1_get_xgmi_info(adev);
1145                 if (r)
1146                         return r;
1147         }
1148
1149         r = gmc_v9_0_mc_init(adev);
1150         if (r)
1151                 return r;
1152
1153         adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev);
1154
1155         /* Memory manager */
1156         r = amdgpu_bo_init(adev);
1157         if (r)
1158                 return r;
1159
1160         r = gmc_v9_0_gart_init(adev);
1161         if (r)
1162                 return r;
1163
1164         /*
1165          * number of VMs
1166          * VMID 0 is reserved for System
1167          * amdgpu graphics/compute will use VMIDs 1-7
1168          * amdkfd will use VMIDs 8-15
1169          */
1170         adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
1171         adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
1172         adev->vm_manager.id_mgr[AMDGPU_MMHUB_1].num_ids = AMDGPU_NUM_OF_VMIDS;
1173
1174         amdgpu_vm_manager_init(adev);
1175
1176         return 0;
1177 }
1178
1179 static int gmc_v9_0_sw_fini(void *handle)
1180 {
1181         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1182         void *stolen_vga_buf;
1183
1184         amdgpu_gmc_ras_fini(adev);
1185         amdgpu_gem_force_release(adev);
1186         amdgpu_vm_manager_fini(adev);
1187
1188         if (gmc_v9_0_keep_stolen_memory(adev))
1189                 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
1190
1191         amdgpu_gart_table_vram_free(adev);
1192         amdgpu_bo_fini(adev);
1193         amdgpu_gart_fini(adev);
1194
1195         return 0;
1196 }
1197
1198 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
1199 {
1200
1201         switch (adev->asic_type) {
1202         case CHIP_VEGA10:
1203                 if (amdgpu_sriov_vf(adev))
1204                         break;
1205                 /* fall through */
1206         case CHIP_VEGA20:
1207                 soc15_program_register_sequence(adev,
1208                                                 golden_settings_mmhub_1_0_0,
1209                                                 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
1210                 soc15_program_register_sequence(adev,
1211                                                 golden_settings_athub_1_0_0,
1212                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1213                 break;
1214         case CHIP_VEGA12:
1215                 break;
1216         case CHIP_RAVEN:
1217                 /* TODO for renoir */
1218                 soc15_program_register_sequence(adev,
1219                                                 golden_settings_athub_1_0_0,
1220                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1221                 break;
1222         default:
1223                 break;
1224         }
1225 }
1226
1227 /**
1228  * gmc_v9_0_gart_enable - gart enable
1229  *
1230  * @adev: amdgpu_device pointer
1231  */
1232 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
1233 {
1234         int r;
1235
1236         if (adev->gart.bo == NULL) {
1237                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1238                 return -EINVAL;
1239         }
1240         r = amdgpu_gart_table_vram_pin(adev);
1241         if (r)
1242                 return r;
1243
1244         r = gfxhub_v1_0_gart_enable(adev);
1245         if (r)
1246                 return r;
1247
1248         if (adev->asic_type == CHIP_ARCTURUS)
1249                 r = mmhub_v9_4_gart_enable(adev);
1250         else
1251                 r = mmhub_v1_0_gart_enable(adev);
1252         if (r)
1253                 return r;
1254
1255         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1256                  (unsigned)(adev->gmc.gart_size >> 20),
1257                  (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1258         adev->gart.ready = true;
1259         return 0;
1260 }
1261
1262 static int gmc_v9_0_hw_init(void *handle)
1263 {
1264         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1265         bool value;
1266         int r, i;
1267         u32 tmp;
1268
1269         /* The sequence of these two function calls matters.*/
1270         gmc_v9_0_init_golden_registers(adev);
1271
1272         if (adev->mode_info.num_crtc) {
1273                 if (adev->asic_type != CHIP_ARCTURUS) {
1274                         /* Lockout access through VGA aperture*/
1275                         WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
1276
1277                         /* disable VGA render */
1278                         WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
1279                 }
1280         }
1281
1282         amdgpu_device_program_register_sequence(adev,
1283                                                 golden_settings_vega10_hdp,
1284                                                 ARRAY_SIZE(golden_settings_vega10_hdp));
1285
1286         switch (adev->asic_type) {
1287         case CHIP_RAVEN:
1288                 /* TODO for renoir */
1289                 mmhub_v1_0_update_power_gating(adev, true);
1290                 break;
1291         case CHIP_ARCTURUS:
1292                 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
1293                 break;
1294         default:
1295                 break;
1296         }
1297
1298         WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
1299
1300         tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
1301         WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
1302
1303         WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
1304         WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
1305
1306         /* After HDP is initialized, flush HDP.*/
1307         adev->nbio.funcs->hdp_flush(adev, NULL);
1308
1309         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
1310                 value = false;
1311         else
1312                 value = true;
1313
1314         if (!amdgpu_sriov_vf(adev)) {
1315                 gfxhub_v1_0_set_fault_enable_default(adev, value);
1316                 if (adev->asic_type == CHIP_ARCTURUS)
1317                         mmhub_v9_4_set_fault_enable_default(adev, value);
1318                 else
1319                         mmhub_v1_0_set_fault_enable_default(adev, value);
1320         }
1321         for (i = 0; i < adev->num_vmhubs; ++i)
1322                 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
1323
1324         if (adev->umc.funcs && adev->umc.funcs->init_registers)
1325                 adev->umc.funcs->init_registers(adev);
1326
1327         r = gmc_v9_0_gart_enable(adev);
1328
1329         return r;
1330 }
1331
1332 /**
1333  * gmc_v9_0_gart_disable - gart disable
1334  *
1335  * @adev: amdgpu_device pointer
1336  *
1337  * This disables all VM page table.
1338  */
1339 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1340 {
1341         gfxhub_v1_0_gart_disable(adev);
1342         if (adev->asic_type == CHIP_ARCTURUS)
1343                 mmhub_v9_4_gart_disable(adev);
1344         else
1345                 mmhub_v1_0_gart_disable(adev);
1346         amdgpu_gart_table_vram_unpin(adev);
1347 }
1348
1349 static int gmc_v9_0_hw_fini(void *handle)
1350 {
1351         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1352
1353         if (amdgpu_sriov_vf(adev)) {
1354                 /* full access mode, so don't touch any GMC register */
1355                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1356                 return 0;
1357         }
1358
1359         amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
1360         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1361         gmc_v9_0_gart_disable(adev);
1362
1363         return 0;
1364 }
1365
1366 static int gmc_v9_0_suspend(void *handle)
1367 {
1368         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1369
1370         return gmc_v9_0_hw_fini(adev);
1371 }
1372
1373 static int gmc_v9_0_resume(void *handle)
1374 {
1375         int r;
1376         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1377
1378         r = gmc_v9_0_hw_init(adev);
1379         if (r)
1380                 return r;
1381
1382         amdgpu_vmid_reset_all(adev);
1383
1384         return 0;
1385 }
1386
1387 static bool gmc_v9_0_is_idle(void *handle)
1388 {
1389         /* MC is always ready in GMC v9.*/
1390         return true;
1391 }
1392
1393 static int gmc_v9_0_wait_for_idle(void *handle)
1394 {
1395         /* There is no need to wait for MC idle in GMC v9.*/
1396         return 0;
1397 }
1398
1399 static int gmc_v9_0_soft_reset(void *handle)
1400 {
1401         /* XXX for emulation.*/
1402         return 0;
1403 }
1404
1405 static int gmc_v9_0_set_clockgating_state(void *handle,
1406                                         enum amd_clockgating_state state)
1407 {
1408         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1409
1410         if (adev->asic_type == CHIP_ARCTURUS)
1411                 mmhub_v9_4_set_clockgating(adev, state);
1412         else
1413                 mmhub_v1_0_set_clockgating(adev, state);
1414
1415         athub_v1_0_set_clockgating(adev, state);
1416
1417         return 0;
1418 }
1419
1420 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1421 {
1422         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1423
1424         if (adev->asic_type == CHIP_ARCTURUS)
1425                 mmhub_v9_4_get_clockgating(adev, flags);
1426         else
1427                 mmhub_v1_0_get_clockgating(adev, flags);
1428
1429         athub_v1_0_get_clockgating(adev, flags);
1430 }
1431
1432 static int gmc_v9_0_set_powergating_state(void *handle,
1433                                         enum amd_powergating_state state)
1434 {
1435         return 0;
1436 }
1437
1438 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1439         .name = "gmc_v9_0",
1440         .early_init = gmc_v9_0_early_init,
1441         .late_init = gmc_v9_0_late_init,
1442         .sw_init = gmc_v9_0_sw_init,
1443         .sw_fini = gmc_v9_0_sw_fini,
1444         .hw_init = gmc_v9_0_hw_init,
1445         .hw_fini = gmc_v9_0_hw_fini,
1446         .suspend = gmc_v9_0_suspend,
1447         .resume = gmc_v9_0_resume,
1448         .is_idle = gmc_v9_0_is_idle,
1449         .wait_for_idle = gmc_v9_0_wait_for_idle,
1450         .soft_reset = gmc_v9_0_soft_reset,
1451         .set_clockgating_state = gmc_v9_0_set_clockgating_state,
1452         .set_powergating_state = gmc_v9_0_set_powergating_state,
1453         .get_clockgating_state = gmc_v9_0_get_clockgating_state,
1454 };
1455
1456 const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1457 {
1458         .type = AMD_IP_BLOCK_TYPE_GMC,
1459         .major = 9,
1460         .minor = 0,
1461         .rev = 0,
1462         .funcs = &gmc_v9_0_ip_funcs,
1463 };