drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "mmhub_v9_4.h"
  25
  26 #include "mmhub/mmhub_9_4_1_offset.h"
  27 #include "mmhub/mmhub_9_4_1_sh_mask.h"
  28 #include "mmhub/mmhub_9_4_1_default.h"
  29 #include "athub/athub_1_0_offset.h"
  30 #include "athub/athub_1_0_sh_mask.h"
  31 #include "vega10_enum.h"
  32
  33 #include "soc15_common.h"
  34
  35 #define MMHUB_NUM_INSTANCES                     2
  36 #define MMHUB_INSTANCE_REGISTER_OFFSET          0x3000
  37
  38 u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev)
  39 {
  40         /* The base should be same b/t 2 mmhubs on Acrturus. Read one here. */
  41         u64 base = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE);
  42         u64 top = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP);
  43
  44         base &= VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
  45         base <<= 24;
  46
  47         top &= VMSHAREDVC0_MC_VM_FB_LOCATION_TOP__FB_TOP_MASK;
  48         top <<= 24;
  49
  50         adev->gmc.fb_start = base;
  51         adev->gmc.fb_end = top;
  52
  53         return base;
  54 }
  55
  56 void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, int hubid,
  57                                 uint32_t vmid, uint64_t value)
  58 {
  59         /* two registers distance between mmVML2VC0_VM_CONTEXT0_* to
  60          * mmVML2VC0_VM_CONTEXT1_*
  61          */
  62         int dist = mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
  63                         - mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
  64
  65         WREG32_SOC15_OFFSET(MMHUB, 0,
  66                             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
  67                             dist * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
  68                             lower_32_bits(value));
  69
  70         WREG32_SOC15_OFFSET(MMHUB, 0,
  71                             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
  72                             dist * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
  73                             upper_32_bits(value));
  74
  75 }
  76
  77 static void mmhub_v9_4_init_gart_aperture_regs(struct amdgpu_device *adev,
  78                                                int hubid)
  79 {
  80         uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
  81
  82         mmhub_v9_4_setup_vm_pt_regs(adev, hubid, 0, pt_base);
  83
  84         WREG32_SOC15_OFFSET(MMHUB, 0,
  85                             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  86                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
  87                             (u32)(adev->gmc.gart_start >> 12));
  88         WREG32_SOC15_OFFSET(MMHUB, 0,
  89                             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  90                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
  91                             (u32)(adev->gmc.gart_start >> 44));
  92
  93         WREG32_SOC15_OFFSET(MMHUB, 0,
  94                             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  95                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
  96                             (u32)(adev->gmc.gart_end >> 12));
  97         WREG32_SOC15_OFFSET(MMHUB, 0,
  98                             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
  99                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 100                             (u32)(adev->gmc.gart_end >> 44));
 101 }
 102
 103 static void mmhub_v9_4_init_system_aperture_regs(struct amdgpu_device *adev,
 104                                                  int hubid)
 105 {
 106         uint64_t value;
 107         uint32_t tmp;
 108
 109         /* Program the AGP BAR */
 110         WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BASE,
 111                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 112                             0);
 113         WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_TOP,
 114                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 115                             adev->gmc.agp_end >> 24);
 116         WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BOT,
 117                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 118                             adev->gmc.agp_start >> 24);
 119
 120         /* Program the system aperture low logical page number. */
 121         WREG32_SOC15_OFFSET(MMHUB, 0,
 122                             mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 123                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 124                             min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 125         WREG32_SOC15_OFFSET(MMHUB, 0,
 126                             mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 127                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 128                             max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 129
 130         /* Set default page address. */
 131         value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
 132                 adev->vm_manager.vram_base_offset;
 133         WREG32_SOC15_OFFSET(MMHUB, 0,
 134                         mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 135                         hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 136                         (u32)(value >> 12));
 137         WREG32_SOC15_OFFSET(MMHUB, 0,
 138                         mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 139                         hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 140                         (u32)(value >> 44));
 141
 142         /* Program "protection fault". */
 143         WREG32_SOC15_OFFSET(MMHUB, 0,
 144                             mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 145                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 146                             (u32)(adev->dummy_page_addr >> 12));
 147         WREG32_SOC15_OFFSET(MMHUB, 0,
 148                             mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 149                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 150                             (u32)((u64)adev->dummy_page_addr >> 44));
 151
 152         tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
 153                                   mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
 154                                   hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
 155         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
 156                             ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 157         WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
 158                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 159 }
 160
 161 static void mmhub_v9_4_init_tlb_regs(struct amdgpu_device *adev, int hubid)
 162 {
 163         uint32_t tmp;
 164
 165         /* Setup TLB control */
 166         tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
 167                            mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 168                            hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
 169
 170         tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 171                             ENABLE_L1_TLB, 1);
 172         tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 173                             SYSTEM_ACCESS_MODE, 3);
 174         tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 175                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 176         tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 177                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 178         tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 179                             ECO_BITS, 0);
 180         tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 181                             MTYPE, MTYPE_UC);/* XXX for emulation. */
 182         tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 183                             ATC_EN, 1);
 184
 185         WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 186                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 187 }
 188
 189 static void mmhub_v9_4_init_cache_regs(struct amdgpu_device *adev, int hubid)
 190 {
 191         uint32_t tmp;
 192
 193         /* Setup L2 cache */
 194         tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
 195                                   hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
 196         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
 197                             ENABLE_L2_CACHE, 1);
 198         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
 199                             ENABLE_L2_FRAGMENT_PROCESSING, 1);
 200         /* XXX for emulation, Refer to closed source code.*/
 201         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
 202                             L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
 203         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
 204                             PDE_FAULT_CLASSIFICATION, 0);
 205         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
 206                             CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 207         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
 208                             IDENTITY_MODE_FRAGMENT_SIZE, 0);
 209         WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
 210                      hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 211
 212         tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2,
 213                                   hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
 214         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,
 215                             INVALIDATE_ALL_L1_TLBS, 1);
 216         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,
 217                             INVALIDATE_L2_CACHE, 1);
 218         WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2,
 219                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 220
 221         tmp = mmVML2PF0_VM_L2_CNTL3_DEFAULT;
 222         if (adev->gmc.translate_further) {
 223                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 12);
 224                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
 225                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 226         } else {
 227                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 9);
 228                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
 229                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 230         }
 231         WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3,
 232                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 233
 234         tmp = mmVML2PF0_VM_L2_CNTL4_DEFAULT;
 235         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,
 236                             VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 237         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,
 238                             VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 239         WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL4,
 240                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 241 }
 242
 243 static void mmhub_v9_4_enable_system_domain(struct amdgpu_device *adev,
 244                                             int hubid)
 245 {
 246         uint32_t tmp;
 247
 248         tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL,
 249                                   hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
 250         tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 251         tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 252         tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL,
 253                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 254         WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL,
 255                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 256 }
 257
 258 static void mmhub_v9_4_disable_identity_aperture(struct amdgpu_device *adev,
 259                                                  int hubid)
 260 {
 261         WREG32_SOC15_OFFSET(MMHUB, 0,
 262                     mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 263                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0XFFFFFFFF);
 264         WREG32_SOC15_OFFSET(MMHUB, 0,
 265                     mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 266                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0x0000000F);
 267
 268         WREG32_SOC15_OFFSET(MMHUB, 0,
 269                     mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
 270                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
 271         WREG32_SOC15_OFFSET(MMHUB, 0,
 272                     mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
 273                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
 274
 275         WREG32_SOC15_OFFSET(MMHUB, 0,
 276                     mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
 277                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
 278         WREG32_SOC15_OFFSET(MMHUB, 0,
 279                     mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
 280                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
 281 }
 282
 283 static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid)
 284 {
 285         uint32_t tmp;
 286         int i;
 287
 288         for (i = 0; i <= 14; i++) {
 289                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
 290                                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i);
 291                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 292                                     ENABLE_CONTEXT, 1);
 293                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 294                                     PAGE_TABLE_DEPTH,
 295                                     adev->vm_manager.num_level);
 296                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 297                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 298                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 299                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 300                                     1);
 301                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 302                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 303                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 304                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 305                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 306                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 307                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 308                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 309                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 310                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 311                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 312                                     PAGE_TABLE_BLOCK_SIZE,
 313                                     adev->vm_manager.block_size - 9);
 314                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 315                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 316                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 317                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
 318                                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i,
 319                                     tmp);
 320                 WREG32_SOC15_OFFSET(MMHUB, 0,
 321                             mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 322                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2, 0);
 323                 WREG32_SOC15_OFFSET(MMHUB, 0,
 324                             mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 325                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2, 0);
 326                 WREG32_SOC15_OFFSET(MMHUB, 0,
 327                                 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 328                                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2,
 329                                 lower_32_bits(adev->vm_manager.max_pfn - 1));
 330                 WREG32_SOC15_OFFSET(MMHUB, 0,
 331                                 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 332                                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2,
 333                                 upper_32_bits(adev->vm_manager.max_pfn - 1));
 334         }
 335 }
 336
 337 static void mmhub_v9_4_program_invalidation(struct amdgpu_device *adev,
 338                                             int hubid)
 339 {
 340         unsigned i;
 341
 342         for (i = 0; i < 18; ++i) {
 343                 WREG32_SOC15_OFFSET(MMHUB, 0,
 344                                 mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 345                                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + 2 * i,
 346                                 0xffffffff);
 347                 WREG32_SOC15_OFFSET(MMHUB, 0,
 348                                 mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 349                                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + 2 * i,
 350                                 0x1f);
 351         }
 352 }
 353
 354 int mmhub_v9_4_gart_enable(struct amdgpu_device *adev)
 355 {
 356         int i;
 357
 358         for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
 359                 if (amdgpu_sriov_vf(adev)) {
 360                         /*
 361                          * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase
 362                          * they are VF copy registers so vbios post doesn't
 363                          * program them, for SRIOV driver need to program them
 364                          */
 365                         WREG32_SOC15_OFFSET(MMHUB, 0,
 366                                      mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE,
 367                                      i * MMHUB_INSTANCE_REGISTER_OFFSET,
 368                                      adev->gmc.vram_start >> 24);
 369                         WREG32_SOC15_OFFSET(MMHUB, 0,
 370                                      mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP,
 371                                      i * MMHUB_INSTANCE_REGISTER_OFFSET,
 372                                      adev->gmc.vram_end >> 24);
 373                 }
 374
 375                 /* GART Enable. */
 376                 mmhub_v9_4_init_gart_aperture_regs(adev, i);
 377                 mmhub_v9_4_init_system_aperture_regs(adev, i);
 378                 mmhub_v9_4_init_tlb_regs(adev, i);
 379                 mmhub_v9_4_init_cache_regs(adev, i);
 380
 381                 mmhub_v9_4_enable_system_domain(adev, i);
 382                 mmhub_v9_4_disable_identity_aperture(adev, i);
 383                 mmhub_v9_4_setup_vmid_config(adev, i);
 384                 mmhub_v9_4_program_invalidation(adev, i);
 385         }
 386
 387         return 0;
 388 }
 389
 390 void mmhub_v9_4_gart_disable(struct amdgpu_device *adev)
 391 {
 392         u32 tmp;
 393         u32 i, j;
 394
 395         for (j = 0; j < MMHUB_NUM_INSTANCES; j++) {
 396                 /* Disable all tables */
 397                 for (i = 0; i < 16; i++)
 398                         WREG32_SOC15_OFFSET(MMHUB, 0,
 399                                             mmVML2VC0_VM_CONTEXT0_CNTL,
 400                                             j * MMHUB_INSTANCE_REGISTER_OFFSET +
 401                                             i, 0);
 402
 403                 /* Setup TLB control */
 404                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
 405                                    mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 406                                    j * MMHUB_INSTANCE_REGISTER_OFFSET);
 407                 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 408                                     ENABLE_L1_TLB, 0);
 409                 tmp = REG_SET_FIELD(tmp,
 410                                     VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 411                                     ENABLE_ADVANCED_DRIVER_MODEL, 0);
 412                 WREG32_SOC15_OFFSET(MMHUB, 0,
 413                                     mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 414                                     j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 415
 416                 /* Setup L2 cache */
 417                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
 418                                           j * MMHUB_INSTANCE_REGISTER_OFFSET);
 419                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
 420                                     ENABLE_L2_CACHE, 0);
 421                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
 422                                     j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 423                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3,
 424                                     j * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
 425         }
 426 }
 427
 428 /**
 429  * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling
 430  *
 431  * @adev: amdgpu_device pointer
 432  * @value: true redirects VM faults to the default page
 433  */
 434 void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev, bool value)
 435 {
 436         u32 tmp;
 437         int i;
 438
 439         for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
 440                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
 441                                           mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 442                                           i * MMHUB_INSTANCE_REGISTER_OFFSET);
 443                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 444                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 445                                     value);
 446                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 447                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT,
 448                                     value);
 449                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 450                                     PDE1_PROTECTION_FAULT_ENABLE_DEFAULT,
 451                                     value);
 452                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 453                                     PDE2_PROTECTION_FAULT_ENABLE_DEFAULT,
 454                                     value);
 455                 tmp = REG_SET_FIELD(tmp,
 456                             VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 457                             TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 458                             value);
 459                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 460                                     NACK_PROTECTION_FAULT_ENABLE_DEFAULT,
 461                                     value);
 462                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 463                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 464                                     value);
 465                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 466                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT,
 467                                     value);
 468                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 469                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT,
 470                                     value);
 471                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 472                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT,
 473                                     value);
 474                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 475                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT,
 476                                     value);
 477                 if (!value) {
 478                         tmp = REG_SET_FIELD(tmp,
 479                                             VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 480                                             CRASH_ON_NO_RETRY_FAULT, 1);
 481                         tmp = REG_SET_FIELD(tmp,
 482                                             VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 483                                             CRASH_ON_RETRY_FAULT, 1);
 484                 }
 485
 486                 WREG32_SOC15_OFFSET(MMHUB, 0,
 487                                     mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 488                                     i * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 489         }
 490 }
 491
 492 void mmhub_v9_4_init(struct amdgpu_device *adev)
 493 {
 494         struct amdgpu_vmhub *hub[MMHUB_NUM_INSTANCES] =
 495                 {&adev->vmhub[AMDGPU_MMHUB_0], &adev->vmhub[AMDGPU_MMHUB_1]};
 496         int i;
 497
 498         for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
 499                 hub[i]->ctx0_ptb_addr_lo32 =
 500                         SOC15_REG_OFFSET(MMHUB, 0,
 501                             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) +
 502                             i * MMHUB_INSTANCE_REGISTER_OFFSET;
 503                 hub[i]->ctx0_ptb_addr_hi32 =
 504                         SOC15_REG_OFFSET(MMHUB, 0,
 505                             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) +
 506                             i * MMHUB_INSTANCE_REGISTER_OFFSET;
 507                 hub[i]->vm_inv_eng0_sem =
 508                         SOC15_REG_OFFSET(MMHUB, 0,
 509                                          mmVML2VC0_VM_INVALIDATE_ENG0_SEM) +
 510                                          i * MMHUB_INSTANCE_REGISTER_OFFSET;
 511                 hub[i]->vm_inv_eng0_req =
 512                         SOC15_REG_OFFSET(MMHUB, 0,
 513                                          mmVML2VC0_VM_INVALIDATE_ENG0_REQ) +
 514                                          i * MMHUB_INSTANCE_REGISTER_OFFSET;
 515                 hub[i]->vm_inv_eng0_ack =
 516                         SOC15_REG_OFFSET(MMHUB, 0,
 517                                          mmVML2VC0_VM_INVALIDATE_ENG0_ACK) +
 518                                          i * MMHUB_INSTANCE_REGISTER_OFFSET;
 519                 hub[i]->vm_context0_cntl =
 520                         SOC15_REG_OFFSET(MMHUB, 0,
 521                                          mmVML2VC0_VM_CONTEXT0_CNTL) +
 522                                          i * MMHUB_INSTANCE_REGISTER_OFFSET;
 523                 hub[i]->vm_l2_pro_fault_status =
 524                         SOC15_REG_OFFSET(MMHUB, 0,
 525                                     mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS) +
 526                                     i * MMHUB_INSTANCE_REGISTER_OFFSET;
 527                 hub[i]->vm_l2_pro_fault_cntl =
 528                         SOC15_REG_OFFSET(MMHUB, 0,
 529                                     mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL) +
 530                                     i * MMHUB_INSTANCE_REGISTER_OFFSET;
 531         }
 532 }
 533
 534 static void mmhub_v9_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 535                                                         bool enable)
 536 {
 537         uint32_t def, data, def1, data1;
 538         int i, j;
 539         int dist = mmDAGB1_CNTL_MISC2 - mmDAGB0_CNTL_MISC2;
 540
 541         for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
 542                 def = data = RREG32_SOC15_OFFSET(MMHUB, 0,
 543                                         mmATCL2_0_ATC_L2_MISC_CG,
 544                                         i * MMHUB_INSTANCE_REGISTER_OFFSET);
 545
 546                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
 547                         data |= ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK;
 548                 else
 549                         data &= ~ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK;
 550
 551                 if (def != data)
 552                         WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
 553                                 i * MMHUB_INSTANCE_REGISTER_OFFSET, data);
 554
 555                 for (j = 0; j < 5; j++) {
 556                         def1 = data1 = RREG32_SOC15_OFFSET(MMHUB, 0,
 557                                         mmDAGB0_CNTL_MISC2,
 558                                         i * MMHUB_INSTANCE_REGISTER_OFFSET +
 559                                         j * dist);
 560                         if (enable &&
 561                             (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
 562                                 data1 &=
 563                                     ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 564                                     DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 565                                     DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 566                                     DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 567                                     DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 568                                     DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 569                         } else {
 570                                 data1 |=
 571                                     (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 572                                     DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 573                                     DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 574                                     DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 575                                     DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 576                                     DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 577                         }
 578
 579                         if (def1 != data1)
 580                                 WREG32_SOC15_OFFSET(MMHUB, 0,
 581                                         mmDAGB0_CNTL_MISC2,
 582                                         i * MMHUB_INSTANCE_REGISTER_OFFSET +
 583                                         j * dist, data1);
 584
 585                         if (i == 1 && j == 3)
 586                                 break;
 587                 }
 588         }
 589 }
 590
 591 static void mmhub_v9_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 592                                                        bool enable)
 593 {
 594         uint32_t def, data;
 595         int i;
 596
 597         for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
 598                 def = data = RREG32_SOC15_OFFSET(MMHUB, 0,
 599                                         mmATCL2_0_ATC_L2_MISC_CG,
 600                                         i * MMHUB_INSTANCE_REGISTER_OFFSET);
 601
 602                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
 603                         data |= ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 604                 else
 605                         data &= ~ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 606
 607                 if (def != data)
 608                         WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
 609                                 i * MMHUB_INSTANCE_REGISTER_OFFSET, data);
 610         }
 611 }
 612
 613 int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
 614                                enum amd_clockgating_state state)
 615 {
 616         if (amdgpu_sriov_vf(adev))
 617                 return 0;
 618
 619         switch (adev->asic_type) {
 620         case CHIP_ARCTURUS:
 621                 mmhub_v9_4_update_medium_grain_clock_gating(adev,
 622                                 state == AMD_CG_STATE_GATE ? true : false);
 623                 mmhub_v9_4_update_medium_grain_light_sleep(adev,
 624                                 state == AMD_CG_STATE_GATE ? true : false);
 625                 break;
 626         default:
 627                 break;
 628         }
 629
 630         return 0;
 631 }
 632
 633 void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 634 {
 635         int data, data1;
 636
 637         if (amdgpu_sriov_vf(adev))
 638                 *flags = 0;
 639
 640         /* AMD_CG_SUPPORT_MC_MGCG */
 641         data = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
 642
 643         data1 = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
 644
 645         if ((data & ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK) &&
 646             !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 647                        DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 648                        DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 649                        DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 650                        DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 651                        DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
 652                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
 653
 654         /* AMD_CG_SUPPORT_MC_LS */
 655         if (data & ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
 656                 *flags |= AMD_CG_SUPPORT_MC_LS;
 657 }