drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_atombios.h"
  25 #include "nbio_v7_4.h"
  26 #include "amdgpu_ras.h"
  27
  28 #include "nbio/nbio_7_4_offset.h"
  29 #include "nbio/nbio_7_4_sh_mask.h"
  30 #include "nbio/nbio_7_4_0_smn.h"
  31 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  32 #include <uapi/linux/kfd_ioctl.h>
  33 #include "amdgpu_ras.h"
  34
  35 #define smnNBIF_MGCG_CTRL_LCLK  0x1013a21c
  36
  37 /*
  38  * These are nbio v7_4_1 registers mask. Temporarily define these here since
  39  * nbio v7_4_1 header is incomplete.
  40  */
  41 #define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK      0x00001000L
  42 #define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK      0x00002000L
  43 #define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK      0x00004000L
  44 #define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK      0x00008000L
  45 #define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK      0x00010000L
  46 #define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK      0x00020000L
  47
  48 #define mmBIF_MMSCH1_DOORBELL_RANGE                     0x01dc
  49 #define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX            2
  50 //BIF_MMSCH1_DOORBELL_RANGE
  51 #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET__SHIFT        0x2
  52 #define BIF_MMSCH1_DOORBELL_RANGE__SIZE__SHIFT          0x10
  53 #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK          0x00000FFCL
  54 #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK            0x001F0000L
  55
  56 static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
  57 {
  58         WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
  59                 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
  60         WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
  61                 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
  62 }
  63
  64 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
  65 {
  66         u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
  67
  68         tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
  69         tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
  70
  71         return tmp;
  72 }
  73
  74 static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable)
  75 {
  76         if (enable)
  77                 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
  78                         BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
  79         else
  80                 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
  81 }
  82
  83 static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev,
  84                                 struct amdgpu_ring *ring)
  85 {
  86         if (!ring || !ring->funcs->emit_wreg)
  87                 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
  88         else
  89                 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
  90 }
  91
  92 static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
  93 {
  94         return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
  95 }
  96
  97 static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
  98                         bool use_doorbell, int doorbell_index, int doorbell_size)
  99 {
 100         u32 reg, doorbell_range;
 101
 102         if (instance < 2)
 103                 reg = instance +
 104                         SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
 105         else
 106                 /*
 107                  * These registers address of SDMA2~7 is not consecutive
 108                  * from SDMA0~1. Need plus 4 dwords offset.
 109                  *
 110                  *   BIF_SDMA0_DOORBELL_RANGE:  0x3bc0
 111                  *   BIF_SDMA1_DOORBELL_RANGE:  0x3bc4
 112                  *   BIF_SDMA2_DOORBELL_RANGE:  0x3bd8
 113                  */
 114                 reg = instance + 0x4 +
 115                         SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
 116
 117         doorbell_range = RREG32(reg);
 118
 119         if (use_doorbell) {
 120                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
 121                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
 122         } else
 123                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
 124
 125         WREG32(reg, doorbell_range);
 126 }
 127
 128 static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
 129                                          int doorbell_index, int instance)
 130 {
 131         u32 reg;
 132         u32 doorbell_range;
 133
 134         if (instance)
 135                 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE);
 136         else
 137                 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
 138
 139         doorbell_range = RREG32(reg);
 140
 141         if (use_doorbell) {
 142                 doorbell_range = REG_SET_FIELD(doorbell_range,
 143                                                BIF_MMSCH0_DOORBELL_RANGE, OFFSET,
 144                                                doorbell_index);
 145                 doorbell_range = REG_SET_FIELD(doorbell_range,
 146                                                BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8);
 147         } else
 148                 doorbell_range = REG_SET_FIELD(doorbell_range,
 149                                                BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0);
 150
 151         WREG32(reg, doorbell_range);
 152 }
 153
 154 static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev,
 155                                                bool enable)
 156 {
 157         WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
 158 }
 159
 160 static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
 161                                                         bool enable)
 162 {
 163         u32 tmp = 0;
 164
 165         if (enable) {
 166                 tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
 167                       REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
 168                       REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
 169
 170                 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW,
 171                              lower_32_bits(adev->doorbell.base));
 172                 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH,
 173                              upper_32_bits(adev->doorbell.base));
 174         }
 175
 176         WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp);
 177 }
 178
 179 static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev,
 180                                         bool use_doorbell, int doorbell_index)
 181 {
 182         u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
 183
 184         if (use_doorbell) {
 185                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
 186                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
 187         } else
 188                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
 189
 190         WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
 191 }
 192
 193
 194 static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 195                                                        bool enable)
 196 {
 197         //TODO: Add support for v7.4
 198 }
 199
 200 static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 201                                                       bool enable)
 202 {
 203         uint32_t def, data;
 204
 205         def = data = RREG32_PCIE(smnPCIE_CNTL2);
 206         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
 207                 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
 208                          PCIE_CNTL2__MST_MEM_LS_EN_MASK |
 209                          PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
 210         } else {
 211                 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
 212                           PCIE_CNTL2__MST_MEM_LS_EN_MASK |
 213                           PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
 214         }
 215
 216         if (def != data)
 217                 WREG32_PCIE(smnPCIE_CNTL2, data);
 218 }
 219
 220 static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev,
 221                                             u32 *flags)
 222 {
 223         int data;
 224
 225         /* AMD_CG_SUPPORT_BIF_MGCG */
 226         data = RREG32_PCIE(smnCPM_CONTROL);
 227         if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
 228                 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
 229
 230         /* AMD_CG_SUPPORT_BIF_LS */
 231         data = RREG32_PCIE(smnPCIE_CNTL2);
 232         if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
 233                 *flags |= AMD_CG_SUPPORT_BIF_LS;
 234 }
 235
 236 static void nbio_v7_4_ih_control(struct amdgpu_device *adev)
 237 {
 238         u32 interrupt_cntl;
 239
 240         /* setup interrupt control */
 241         WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
 242         interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
 243         /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
 244          * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
 245          */
 246         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
 247         /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
 248         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
 249         WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
 250 }
 251
 252 static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev)
 253 {
 254         return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
 255 }
 256
 257 static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev)
 258 {
 259         return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
 260 }
 261
 262 static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev)
 263 {
 264         return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
 265 }
 266
 267 static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev)
 268 {
 269         return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
 270 }
 271
 272 const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = {
 273         .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
 274         .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
 275         .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
 276         .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
 277         .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
 278         .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
 279         .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
 280         .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
 281         .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
 282         .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
 283         .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
 284         .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
 285         .ref_and_mask_sdma2 = GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK,
 286         .ref_and_mask_sdma3 = GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK,
 287         .ref_and_mask_sdma4 = GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK,
 288         .ref_and_mask_sdma5 = GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK,
 289         .ref_and_mask_sdma6 = GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK,
 290         .ref_and_mask_sdma7 = GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK,
 291 };
 292
 293 static void nbio_v7_4_detect_hw_virt(struct amdgpu_device *adev)
 294 {
 295         uint32_t reg;
 296
 297         reg = RREG32_SOC15(NBIO, 0, mmRCC_IOV_FUNC_IDENTIFIER);
 298         if (reg & 1)
 299                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
 300
 301         if (reg & 0x80000000)
 302                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
 303
 304         if (!reg) {
 305                 if (is_virtual_machine())       /* passthrough mode exclus sriov mod */
 306                         adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
 307         }
 308 }
 309
 310 static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
 311 {
 312         uint32_t def, data;
 313
 314         def = data = RREG32_PCIE(smnPCIE_CI_CNTL);
 315         data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1);
 316
 317         if (def != data)
 318                 WREG32_PCIE(smnPCIE_CI_CNTL, data);
 319 }
 320
 321 static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
 322 {
 323         uint32_t bif_doorbell_intr_cntl;
 324
 325         bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
 326         if (REG_GET_FIELD(bif_doorbell_intr_cntl,
 327                 BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) {
 328                 /* driver has to clear the interrupt status when bif ring is disabled */
 329                 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
 330                                                 BIF_DOORBELL_INT_CNTL,
 331                                                 RAS_CNTLR_INTERRUPT_CLEAR, 1);
 332                 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
 333
 334                 amdgpu_ras_global_ras_isr(adev);
 335         }
 336 }
 337
 338 static void nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev)
 339 {
 340         uint32_t bif_doorbell_intr_cntl;
 341
 342         bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
 343         if (REG_GET_FIELD(bif_doorbell_intr_cntl,
 344                 BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) {
 345                 /* driver has to clear the interrupt status when bif ring is disabled */
 346                 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
 347                                                 BIF_DOORBELL_INT_CNTL,
 348                                                 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1);
 349                 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
 350
 351                 amdgpu_ras_global_ras_isr(adev);
 352         }
 353 }
 354
 355
 356 static int nbio_v7_4_set_ras_controller_irq_state(struct amdgpu_device *adev,
 357                                                   struct amdgpu_irq_src *src,
 358                                                   unsigned type,
 359                                                   enum amdgpu_interrupt_state state)
 360 {
 361         /* The ras_controller_irq enablement should be done in psp bl when it
 362          * tries to enable ras feature. Driver only need to set the correct interrupt
 363          * vector for bare-metal and sriov use case respectively
 364          */
 365         uint32_t bif_intr_cntl;
 366
 367         bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
 368         if (state == AMDGPU_IRQ_STATE_ENABLE) {
 369                 /* set interrupt vector select bit to 0 to select
 370                  * vetcor 1 for bare metal case */
 371                 bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,
 372                                               BIF_INTR_CNTL,
 373                                               RAS_INTR_VEC_SEL, 0);
 374                 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
 375         }
 376
 377         return 0;
 378 }
 379
 380 static int nbio_v7_4_process_ras_controller_irq(struct amdgpu_device *adev,
 381                                                 struct amdgpu_irq_src *source,
 382                                                 struct amdgpu_iv_entry *entry)
 383 {
 384         /* By design, the ih cookie for ras_controller_irq should be written
 385          * to BIFring instead of general iv ring. However, due to known bif ring
 386          * hw bug, it has to be disabled. There is no chance the process function
 387          * will be involked. Just left it as a dummy one.
 388          */
 389         return 0;
 390 }
 391
 392 static int nbio_v7_4_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev,
 393                                                        struct amdgpu_irq_src *src,
 394                                                        unsigned type,
 395                                                        enum amdgpu_interrupt_state state)
 396 {
 397         /* The ras_controller_irq enablement should be done in psp bl when it
 398          * tries to enable ras feature. Driver only need to set the correct interrupt
 399          * vector for bare-metal and sriov use case respectively
 400          */
 401         uint32_t bif_intr_cntl;
 402
 403         bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
 404         if (state == AMDGPU_IRQ_STATE_ENABLE) {
 405                 /* set interrupt vector select bit to 0 to select
 406                  * vetcor 1 for bare metal case */
 407                 bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,
 408                                               BIF_INTR_CNTL,
 409                                               RAS_INTR_VEC_SEL, 0);
 410                 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
 411         }
 412
 413         return 0;
 414 }
 415
 416 static int nbio_v7_4_process_err_event_athub_irq(struct amdgpu_device *adev,
 417                                                  struct amdgpu_irq_src *source,
 418                                                  struct amdgpu_iv_entry *entry)
 419 {
 420         /* By design, the ih cookie for err_event_athub_irq should be written
 421          * to BIFring instead of general iv ring. However, due to known bif ring
 422          * hw bug, it has to be disabled. There is no chance the process function
 423          * will be involked. Just left it as a dummy one.
 424          */
 425         return 0;
 426 }
 427
 428 static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_controller_irq_funcs = {
 429         .set = nbio_v7_4_set_ras_controller_irq_state,
 430         .process = nbio_v7_4_process_ras_controller_irq,
 431 };
 432
 433 static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_err_event_athub_irq_funcs = {
 434         .set = nbio_v7_4_set_ras_err_event_athub_irq_state,
 435         .process = nbio_v7_4_process_err_event_athub_irq,
 436 };
 437
 438 static int nbio_v7_4_init_ras_controller_interrupt (struct amdgpu_device *adev)
 439 {
 440         int r;
 441
 442         /* init the irq funcs */
 443         adev->nbio.ras_controller_irq.funcs =
 444                 &nbio_v7_4_ras_controller_irq_funcs;
 445         adev->nbio.ras_controller_irq.num_types = 1;
 446
 447         /* register ras controller interrupt */
 448         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
 449                               NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT,
 450                               &adev->nbio.ras_controller_irq);
 451         if (r)
 452                 return r;
 453
 454         return 0;
 455 }
 456
 457 static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev)
 458 {
 459
 460         int r;
 461
 462         /* init the irq funcs */
 463         adev->nbio.ras_err_event_athub_irq.funcs =
 464                 &nbio_v7_4_ras_err_event_athub_irq_funcs;
 465         adev->nbio.ras_err_event_athub_irq.num_types = 1;
 466
 467         /* register ras err event athub interrupt */
 468         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
 469                               NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT,
 470                               &adev->nbio.ras_err_event_athub_irq);
 471         if (r)
 472                 return r;
 473
 474         return 0;
 475 }
 476
 477 const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
 478         .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
 479         .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
 480         .get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset,
 481         .get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset,
 482         .get_rev_id = nbio_v7_4_get_rev_id,
 483         .mc_access_enable = nbio_v7_4_mc_access_enable,
 484         .hdp_flush = nbio_v7_4_hdp_flush,
 485         .get_memsize = nbio_v7_4_get_memsize,
 486         .sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range,
 487         .vcn_doorbell_range = nbio_v7_4_vcn_doorbell_range,
 488         .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture,
 489         .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture,
 490         .ih_doorbell_range = nbio_v7_4_ih_doorbell_range,
 491         .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating,
 492         .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep,
 493         .get_clockgating_state = nbio_v7_4_get_clockgating_state,
 494         .ih_control = nbio_v7_4_ih_control,
 495         .init_registers = nbio_v7_4_init_registers,
 496         .detect_hw_virt = nbio_v7_4_detect_hw_virt,
 497         .remap_hdp_registers = nbio_v7_4_remap_hdp_registers,
 498         .handle_ras_controller_intr_no_bifring = nbio_v7_4_handle_ras_controller_intr_no_bifring,
 499         .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring,
 500         .init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt,
 501         .init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt,
 502         .ras_late_init = amdgpu_nbio_ras_late_init,
 503 };